AKM AK7744VT

[ASAHI KASEI]
[AK7744]
AK7744VT
24bit 3ch ADC + 24bit 4ch DAC with Audio DSP
1. General Description
The AK7744 is a highly integrated audio processing IC featuring four 24-bit D/A converters, a stereo and monau
ral input 24-bit A/D and on-chip DSP. The four D/A converters with 107dB dynamic range, and A/D with 97dB dyn
amic range provide high quality analog performance. These D/A and A/D support sampling frequencies from 8kHz
to 48kHz. This device also includes 24kbit of SRAM for delayed audio effects. This programmable DSP is optimize
d for audio signal processing. The design allows up to 512 execution lines per audio sample cycle, with multiple fun
ctions per line. The AK7744 can be used to implement complete sound field control, such as surround control, 3D,
parametric equalization, etc. It is packaged in a 64-pin LQFP package.
2. Features
DSP:
-
Word length:
24-bit (Data RAM)
Instruction cycle time: 40ns (512fs, fs=48kHz)
Multiplier: 24 x 16 → 40-bit
Divider:
24 / 24 → 16-bit or 24-bit
ALU:
34-bit arithmetic operation (Overflow margin: 4bit)
24-bit arithmetic and logic operation
Shift+Register: 1, 2, 3, 4, 6, 8 and 15 bits shifted left
1, 2, 3, 4, 8 , 14 and 15 bits shifted right
Other numbers in parentheses are restricted. Provided with indirect shift function
- Program RAM:
512 x 32-bit
- Coefficient RAM:
512 x 16-bit
- Data RAM:
256 x 24-bit
- Offset RAM:
48 x 11-bit
(2048 x 24-bit / 1024 x 24-bit )
- Internal Memory:
24kbit SRAM
- Sampling frequency: 8kHz to 48kHz
- Serial interface port for micro-controller
- Master clock: 512fs
- Master/Slave operation
- Serial signal input port ( 2 ch ): 16/20/24-bit : Output port ( 2 ch ): 24-bit
Input Selector
- Normal stereo : 1 full-differential and 5 single-ended Input
- Interrupt monaural : 1 full-differential and 1 single-ended Input
ADC: 2 channels
- 24-bit 64x Over-sampling delta sigma
- DR, S/N : 97dBA ( Full-differential Input )
- S/(N+D) : 86dB
- Digital HPF (fc = 1Hz)
- Single-ended or Full-differential Input
ADC: 1 channel ( Interrupt input )
- DR, S/N : 97dBA(Full-differential Input)
DAC: 4 channels
- 24-bit 128x Over-sampling advanced multi-bit
- DR, S/N : 107dBA
- S/(N+D) : 92dB
- Full-differential Output
Other
- Power supply:
+3.3V±0.3V
- Operating temperature range: -40°C~85°C
- Package: 64pin LQFP (0.5mm pitch)
<MS0167-E-00>
- 1 -
2002/10
[ASAHI KASEI]
[AK7744]
3. Block diagram
TEST LRCLK BITCLK CLKOUT XTI XTO SMODE
O UTE
TEST LRCLK BITCLK CLKOUT XTI XTO SMODE INIT_RESET
SDOUTA2
CONTROLLER
S_RESET
ADC1
SDOUTA1
AINL-
AINL+
AINL1
AINL2
AINL3
AINL4
AINL5
AINL+
SDINA2
SDINA1
SWA1
RQ
SI
SI
SO
SO
SCLK
SCLK
RDY
RDY
DRDY
AINR-
SDINA1
SDATA1
DSP
AINRAINR+
AINR1
AINR2
AINR3
AINR4
AINR5
AINR+
ISEL1[2:0]
DRDY
JX
S_RESET
AINL-
O UTE
RQ
INIT_RESET
JX
A2IN-
ADC2
SWA2
SDINA2
AINA2IN+
A2IN1
AIN+
SDATA2
ISEL2
VREF
SWD1
SDOUTD1
SDATA
SDIN
SDIN
AOUTL+
AOUTL-
DAC1 AOUTR+
AOUTR-
VCOM
VREFH
AOUTL1+
AOUTL1AOUTR1+
AOUTR1-
SWD2
AOUTL+
AOUTLSDATA DAC2 AOUTR+
AOUTR-
SDOUTD2
SDOUT
AOUTL2+
AOUTL2AOUTR2+
AOUTR2SDOUT
OUTE
24kbit DLRAM
SDOUTD1
OUTE
A
Note)
B
Q
C
SDOUTD2
When Q is L (0), then A connects with C.
* SWA1,SWA2,SWD1,SWD2,ISEL1[2:0],ISEL2
OUTE [Control register]
This block diagram is a simplified illustration of the AK7744; it is not a circuit diagram.
<MS0167-E-00>
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2002/10
[ASAHI KASEI]
[AK7744]
‹ AK7744 DSP Block diagram
CP0,CP1
DP0,DP1
DLP0,DLP1
CRAM
512 X 16
DRAM
256 X 24
DLRAM
2K X 12 or 1K X 24
OFRAM
48 X 11
CMP(Compress & Expand)
CBUS(16bit)
DBUS(24bit)
Micom I/F
Control
MPX24
X
DEC
MPX16
Y
Multiply
16 X 24 -> 40
24bit
40bit
MUL
TMP 8 X 24bit
34bit
A
PRAM
512 X 32
PC
Stack : 1level
DBUS
SHIFT
34bit
Serial I/F
PTMP 24bit X 6(LIFO)
B
ALU1
34bit
Overflow Margin: 4bit
DR0 ∼ 3
24bit
2X24/20/16 bit
ADC1
1X24/20/16 bit
ADC2
2X24/20/16 bit
SDIN
Over Flow Data
Generator
Divider
24 ÷ 24 → 24
<MS0167-E-00>
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2 X 24bit
DAC1
2 X 24bit
DAC2
2 X 24bit
SDOUT
2002/10
[ASAHI KASEI]
[AK7744]
4. Description of Input/Output Pins
AINL-
AINR+
AINRAVDD
VREFH
VCOM
AVSS
AOUTL1+
AOUTL1-
57
56
55
52
50
49
51
AINL+
58
53
AINL5
AINR5
60
54
AINR4
61
59
AINL4
62
63
AINL3
AINR3
64
(1) Pin layout
AOUTR2-
9
(TOP VIEW)
40
BVSS
TEST
10
39
DVSS
INIT_RESET
11
38
DVDD
S_RESET
12
37
RQ
DVSS
13
36
SCLK
DVDD
14
35
SI
XTI
15
34
SO
XTO
16
33
RDY
32
41
DRDY
64pin LQFP
31
8
SDOUTD2
AVDD
AVSS
30
AOUTR2+
SDOUTD1
42
29
7
28
A2IN1
27
NC
SDOUTA1
SDOUTA2
SDOUT
43
26
6
DVDD
A2IN+
25
AOUTL2-
DVSS
44
24
5
SDINA2
A2IN-
23
45
SDINA1
4
22
AINL1
NC
AOUTL2+
SDIN
46
21
3
BITCLK
AINR1
20
AOUTR1-
LRCLK
47
19
2
SMODE
AINL2
18
AOUTR1+
JX
48
17
1
CLKO
AINR2
Note) JX,SDIN,SDINA1,SDINA2 and TEST are pull-down pins.
<MS0167-E-00>
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2002/10
[ASAHI KASEI]
[AK7744]
(2) Pin function
Pin No.
1
2
3
4
5
6
7
8
9
10
Pin name
AINR2
AINL2
AINR1
AINL1
A2INA2IN+
A2IN1
AVDD
AVSS
TEST
11
INIT_RESET
12
S_RESET
13
14
DVSS
DVDD
15
XTI
16
XTO
17
CLKO
18
JX
19
SMODE
20
LRCLK
21
BITCLK
<MS0167-E-00>
I/O
Function
I ADC1 single-ended analog Rch input pin No.2
I ADC1 single-ended analog Lch input pin No.2
I ADC1 single-ended analog Rch input pin No.1
I ADC1 single-ended analog Lch input pin No.1
I ADC2 analog inverted input pin.
I ADC2 analog non-inverted input pin.
I ADC2 single-ended analog input pin.
- Power supply pin for analog section 3.3V (typ)
- Analog ground 0V
- TEST pin
Reset pin ( for initialization )
I Used to input “L” initialize the AK7744 at power-on
Classification
Analog section
Analog
Power Supply
TEST pin
Reset
I System Reset pin.
Digital
- Ground pin for digital section 0.0V
Power Supply
- Power supply pin for digital section 3.3V(Typ).
System clock
Master clock input pin
I Connect a crystal oscillator between this pin and the XTO pin,
or input the external CMOS clock signal XTI pin.
Crystal oscillator output pin
O When a crystal oscillator is used, it should be connected between XTI and
XTO.
When the external clock is used, keep this pin open
System clock
Clock output pin
O Outputs the XTI clock.
Allows the output to be set to "L" by control register setting.
I External condition jump pin (Pulldown)
Condition input
Control
Slave/master mode selector pin
I Set LRCLK and BITCLK to input or output mode.
SMODE="L": Slave mode (These are set to input mode.)
SMODE="H": Master mode (These are set to output mode.)
System clock
LR channel select Clock pin
I/O SMODE="L": Slave mode: Inputs the fs clock.
SMODE="H": Master mode: Outputs the fs clock.
Serial bit clock pin
I/O SMODE="L": Slave mode: Inputs 64 fs or 48 fs clocks.
SMODE="H": Master mode: Outputs 64 fs clocks.
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2002/10
[ASAHI KASEI]
Pin No.
Pin name
22
SDIN
23
SDINA1
24
SDINA2
25
26
27
DVSS
DVDD
SDOUTA1
28
SDOUTA2
29
SDOUT
30
SDOUTD1
31
SDOUTD2
32
33
34
DRDY
RDY
SO
35
SI
36
SCLK
37
38
39
40
RQ
DVDD
DVSS
BVSS
<MS0167-E-00>
[AK7744]
I/O
Function
DSP Serial data input pin
( Pulldown)
I Compatible with MSB/LSB justified 24, 20 and 16 bits.
Classification
Digital section
Serial input data
DSP Serial data input pin
( Pulldown)
I Compatible with MSB/LSB justified 24, 20 and 16 bits.
Allows the selectable input to SDINA1 port of DSP or DAC1 by control
register setting
DSP Serial data input pin
( Pulldown)
I Compatible with MSB/LSB justified 24, 20 and 16 bits.
Allows the selectable input to SDINA2 port of DSP or DAC2 by control
register setting
- Ground pin for digital section
Power supply
- Power supply pin for digital section 3.3V(Typ).
Digital section
O DSP Serial data output pin.
Normally “L” outputs. Allows outputs MSB justified 24-bit data from Serial output data
ADC1 by control register setting.
O DSP Serial data output pin.
Normally “L” outputs. Allows outputs MSB justified 24-bit data from
ADC2 by control register setting.
O DSP Serial data output pin.
Outputs MSB justified 24-bit data.
O DSP Serial data output pin.
Normally “L” outputs. Allows outputs MSB justified 24-bit data to DAC
1 by control register setting.
O DSP Serial data output pin.
Normally “L” outputs. Allows outputs MSB justified 24-bit data to DAC
2 by control register setting.
Microcomputer
O Output data ready pin for Microcomputer interface.
Interface
O Data write ready output pin for Microcomputer interface.
O Serial data output pin for Microcomputer interfaces.
Microcomputer interface serial data input and serial data
I output control pin.
When SI does not use, leave SI=”L”.
Microcomputer interface serial data clock pin.
I When SCLK does not use, leave SCLK=”H”.
Microcomputer interface writes request pin.
I
RQ =”L”: Microcomputer interface enable.
- Power supply pin for digital section 3.3V(Typ).
- Ground pin for digital section
- Silicon substrate potential 0V
- 6 -
Power supply
Power supply
2002/10
[ASAHI KASEI]
[AK7744]
Pin No.
41
42
43
44
45
46
47
48
49
50
51
52
Pin name
AOUTR2AOUTR2+
NC
AOUTL2AOUTL2+
NC
AOUTR1AOUTR1+
AOUTL1AOUTL1+
AVSS
VCOM
I/O
O
O
O
O
O
O
O
O
O
53
VREFH
I
54
55
56
57
58
59
60
61
62
63
64
AVDD
AINRAINR+
AINLAINL+
AINR5
AINL5
AINR4
AINL4
AINR3
AINL3
I
I
I
I
I
I
I
I
I
I
<MS0167-E-00>
Function
DAC2 Rch analog inverted output pin.
DAC2 Rch analog non-inverted output pin.
Non connection pin ( connect with AVSS pin )
DAC2 Lch analog inverted output pin.
DAC2 Lch analog non-inverted output pin.
Non connection pin ( connect with AVSS pin )
DAC1 Rch analog inverted output pin.
DAC1 Rch analog non-inverted output pin.
DAC1 Lch analog inverted output pin.
DAC1 Lch analog non-inverted output pin.
Analog ground 0V
Common voltage
Normally, connect to 0.1uF and 10uF capacitors between this pin and
AVSS. Don’t connect outside cuircuit.)
Analog Reference voltage input pin.
Normally, connect to AVDD (pin 54), and connect 0.1uF and
10uF capacitors between this pin and AVSS.
Power supply pin for analog section 3.3V (typ)
ADC1 Rch analog inverted input pin.
ADC1 Rch analog non-inverted input pin.
ADC1 Lch analog inverted input pin.
ADC1 Lch analog non-inverted input pin.
ADC1 single-ended analog Rch input pin No.5
ADC1 single-ended analog Lch input pin No.5
ADC1 single-ended analog Rch input pin No.4
ADC1 single-ended analog Lch input pin No.4
ADC1 single-ended analog Rch input pin No.3
ADC1 single-ended analog Lch input pin No.3
- 7 -
Classification
Analog section
Power supply
Analog section
Power Supply
Analog section
2002/10
[ASAHI KASEI]
[AK7744]
5. Absolute maximum rating
(AVSS, BVSS, DVSS = 0 V: All voltages indicated are relative to the ground.)
Item
Symbol
min
max
Power supply voltage
Analog(AVDD)
VA
-0.3
4.6
Digital(DVDD)
VD
-0.3
4.6
|AVSS(BVSS)-DVSS|
Note 1)
0.3
∆GND
Input current (except for power supply pin )
IIN
±10
Analog input voltage
AINL+,AINL-,AINR+,AINR-,AINL1,
-0.3
VA+0.3
VINA
AINR1,AINL2,AINR2,AINL3,AINR3,
AINL4,AINR4,AINL5,AINR5,A2IN+,
A2IN-,A2IN1,VREFH
Digital input voltage
VIND
-0.3
VD+0.3
Operating ambient temperature
Ta
-40
85
Storage temperature
Tstg
-65
150
Unit
V
V
V
mA
V
V
°C
°C
Note 1) AVSS(BVSS) should be the same level as DVSS.
WARNING: Operation at or beyond these limits may result in permanent damage of the device.
Normal operation is not guaranteed when these limits are exceeded.
6. Recommended operating conditions
(AVSS, BVSS, DVSS = 0 V: All voltages indicated are relative to the ground.)
Items
Symbol
min
typ
max
Unit
Power supply voltage
AVDD
VA
3.0
3.3
3.6
V
DVDD
VD
3.0
3.3
VA
V
Reference voltage (VREF)
VREFH Note 1)
Note 1)
VRH
VA
V
VREFH normally connects with AVDD.
Note: The analog input and output voltages are proportional to the VREFH voltages.
<MS0167-E-00>
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2002/10
[ASAHI KASEI]
[AK7744]
7. Electric characteristics
(1) Analog characteristics
(Unless otherwise specified, Ta = 25°C; AVDD, DVDD = 3.3V; VREFH = AVDD;
BITCLK = 64 fs; Signal frequency 1 kHz;
Measuring frequency = 20 Hz to 20 kHz @48kHz;
DSP section in the reset state; ADC with all differential inputs)
Parameter
min
typ
max
Resolution
24
ADC1
Section
Dynamic characteristics
S/(N+D)
fs = 48kHz (-1dB)
(Note1)
76
86
Dynamic range fs = 48kHz (A filter) (Note2)
89
97
S/N
fs = 48kHz (A filter)
89
97
Inter-channel isolation (f =1 kHz)
(Note3)
90
120
DC accuracy
Inter-channel gain mismatching
0.1
0.3
Analog input
Input voltage(Differencial)
(Note4)
±1.85
±2.00
±2.15
Input Voltage(Single-ended)
(Note5)
1.85
2.00
2.15
Input impedance
(Note6)
22
33
Resolution
24
ADC2
Section
Dynamic characteristics
S/(N+D)
fs = 48kHz (-1dB)
(Note1)
76
86
Dynamic range fs = 48kHz (A filter) (Note2)
89
97
S/N
fs = 48kHz (A filter)
89
97
Analog input
Input voltage
1.85
2.00
2.15
Input impedance
22
33
Resolution
24
DAC
Section
Dynamic characteristics
S/(N+D)
fs = 48kHz (0dB)
80
92
Dynamic range fs = 48kHz (A filter) (Note2)
99
107
S/N
fs = 48kHz (A filter)
99
107
Inter-channel isolation (f =1 kHz)
(Note7)
90
115
DC accuracy
Inter-channel gain mismatching
(Note7)
0.2
0.5
Analog output
Output voltage (AOUT+)-(AOUT-) (Note8)
3.36
3.66
3.96
Load resistance
5
Note:
Unit
Bits
dB
dB
dB
dB
dB
Vp-p
Vp-p
kΩ
Bits
dB
dB
dB
Vp-p
kΩ
Bits
dB
dB
dB
dB
dB
Vp-p
kΩ
1. In case of the using single-ended input this value does not guarantee.
2. Indicates S/(N+D) when a -60 dB signal is applied.
3. Specified for L and R of each input selector.
4. This applies to AINL+, AINL-, AINR+ , AINR-, A2IN+ and A2IN- pins.
The fullscale (∆AIN = (AIN+) - (AIN-)) can be represented by (±FS = ±(VREFH-AVSS)×(2.0/3.3)).
5. This applies to AINL1,AINR1,AINL2,AINR2,AINL3,AINR3,AINL4,AINR4,AINL5,AINR5 and
A2IN1. The fullscale of single-ended input is (FS=(VREFH-AVSS) × (2.0/3.3)).
6. This applies to AINL1, AINR1, AINL2, AINR2, AINL3, AINR3, AINL4, AINR4, AINL5, AINR5
AINL+,AINL-,AINR+, AINR-,A2IN+,A2IN- and A2IN1.
7. Specified for L and R of each DAC.
8. The full-scale output voltage when VREFH=AVDD.
<MS0167-E-00>
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2002/10
[ASAHI KASEI]
[AK7744]
(2) DC characteristics
(VDD=AVDD=DVDD=3.0~3.6V,Ta=25°C)
Parameter
High level input voltage
Low level input voltage
High level output voltage Iout=-100µA
Low level output voltage Iout=100µA
Input leak current
Note 1)
Input leak current (pull-down) Note 2)
Input leak current (XTI pin)
Symbol
VIH
VIL
VOH
VOL
Iin
Iid
Iix
min
80%VDD
typ
max
20%VDD
VDD-0.5
22
26
0.5
±10
Unit
V
V
V
V
µA
µA
µA
Note:
1. The pull-down and XTI pins are not included.
2. The pull-down pins are JX, SDIN, SDINA1 and SDINA2. The pull-down resistor value is 150kΩ.
3. Regarding the input/output levels in the text, the low level will be represented as "L" or 0, and the high level as
"H" or 1. In principle, "0" and "1" will be used to represent the bus (serial/parallel) such as registers.
(3) Current consumption
(AVDD=DVDD=3.0V~3.6V, Ta=25°C; master clock (XTI)=24.576MHz=512fs[fs=48kHz];
When operating the DAC four channels with 1kHz sinusoidal waves and –1dBFS-scale input to each of ADC 2ch
analog input pins)
Power supply
Parameter
Power supply current
a) AVDD
b) DVDD
c) Total(a+b)
2) INIT_RESET ="L"
Power consumption
1) During operation
a) AVDD
b) DVDD
c) Total(a+b)
2) INIT_RESET ="L"
min
typ
60
40
100
6.0
Note 1)
Note 2)
198
132
330
Note 1)
Note 2)
19.8
max
135
486
Unit
mA
mA
mA
mA
mW
mW
mW
mW
Note:
1) Varies slightly according to the frequency used and contents of the DSP program.
2) This is a reference value when using a crystal oscillator. Since most of the power current during a reset is pulled
from the oscillator section, the value changes slightly depending on the crystal oscillators type and external
circuits used. Therefore this is “reference value”.
<MS0167-E-00>
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2002/10
[ASAHI KASEI]
[AK7744]
(4) Digital filter characteristics
Values described below are design values cited as references.
4-1) ADC Section:
(Ta=25°C; AVDD,DVDD =3.0V~3.6V; fs=48kHz; HPF=off)
parameter
Symbol
min
Pass band
(-0.02dB)
PB
0
(-6.0dB)
0
Stop band
(Note 1)
SB
26.5
Pass band ripple
(Note 2)
PR
Stop band attenuation (Note3,4)
SA
80
Group delay distortion
∆GD
Group delay
(Ts=1/fs)
GD
typ
max
21.768
24.00
±0.005
0
29.3
Unit
kHz
kHz
kHz
dB
dB
us
Ts
Note: : HPF response does not include.
1. The stop band is from 26.5kHz to 3.0455MHz when fs = 48kHz.
2. The pass band is from DC to 21.5kHz from DC when fs = 48kHz.
3. When fs = 48kHz, the analog modulator samples analog input at 3.072MHz. The digital filter does not
attenuate the input signal in the multiple bands (n x 3.072MHz ± 21.99kHz; n=0, 1, 2, 3...) of the sampling
frequency.
4-2) DAC section
(Ta=25°C; AVDD,DVDD =3.0V~3.6V; fs=48kHz)
parameter
Symbol
min
Digital filter
PB
0
Pass band ±0.07dB (Note 1)
(-6.0dB)
Stop band
(Note 1)
SB
26.2
Pass band ripple
PR
Stop band attenuation
SA
47
Group delay
(Note 2)
GD
Digital filter+SCF
Amplitude characteristics
0~20.0kHz
Typ
max
Unit
24.0
21.7
-
15
kHz
kHz
kHz
dB
dB
Ts
±0.5
dB
±0.07
Note:
1. The pass band and stop band frequencies are proportional to "fs" (system sampling rate), and represent
PB=0.4535fs(@-0.06dB) and SB=0.546fs, respectively.
2. This calculated delay time, which occurs in the digital filter, is from setting the 24-bit data of both channels on
input register to the output of analog signal.
<MS0167-E-00>
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2002/10
[ASAHI KASEI]
[AK7744]
(5) Switching characteristics
5-1) System clock
(AVDD=DVDD=3.0V~3.6V,Ta=-40~85°C,CL=20pF)
Parameter
Symbol
min
Master clock (XTI)
a) With a crystal oscillator
512fs: frequency
fMCLK
16.384
1536fs: frequency
fMCLK
22.5792
2048fs: frequency
3072fs: frequency
fMCLK
24.576
b) With a external clock:
40
Duty factor (≤18.432MHz)
45
(>18.432MHz)
512fs: frequency
fMCLK
16
1536fs: frequency
fMCLK
22
2048fs: frequency
3072fs: frequency
fMCLK
24
: High level width
tMCLKH
16
: Low level width
tMCLKL
16
Clock rise time
tCR
Clock fall time
tCF
LRCLK Sampling frequency
1536fs: frequency
2048fs: frequency
3072fs: frequency
Slave mode :clock rise time
Slave mode :clock fall time
typ
max
Unit
24.576
24.576
24.576
24.576
MHz
MHz
24.576
24.576
MHz
50
50
24.576
24.576
60
55
25
25
%
24.576
25
MHz
MHz
6
6
MHz
ns
ns
ns
ns
fs
32
48
49
kHz
fs
fs
fs
14.7
11.025
8
16
12
8
1
16.3
12.2
8.1
6
6
kHz
kHz
kHz
fs
ns
ns
6
6
fs
ns
ns
ns
ns
tLR
tLF
BITCLK
Note 1) fBCLK
Slave mode: High level width
tBCLKH
Slave mode: Low level width
tBCLKL
Slave mode :clock rise time
tBR
Slave mode :clock fall time
tBF
Note 1) 48fs mode can be use only in slave mode.
48
150
150
64
5-2) Reset
(AVDD=DVDD=3.0V~3.6V,Ta=-40~85°C,CL=20pF)
Parameter
Symbol
tRST
INIT_RESET
Note 1)
S_RESET
tRST
min
150
typ
max
150
Unit
ns
ns
Note 1) “L” is acceptable when power is turned on, but ”H” needs a stable master clock input.
<MS0167-E-00>
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2002/10
[ASAHI KASEI]
[AK7744]
5-3) Audio interface
(AVDD=DVDD=3.0V~3.6V,Ta=-40~85°C,CL=20pF)
Parameter
Symbol
Slave mode
BITCLK frequency
fBCLK
BITCLK low level width
tBCLKL
BITCLK high level width
tBCLKH
tBLRD
Delay time from BITCLK"↑" to LRCLK
tLRBD
Delay time from LRCLK to BITCLK "↑"
Delay time from LRCLK to serial data tLRD
output
Delay time from BITCLK to serial data tBSOD
output
Serial data input latch hold time
tBSIDS
Serial data input latch setup time
tBSIDH
Master mode
BITCLK frequency
fBCLK
BITCLK duty factor
tBLRD
Delay time from BITCLK"↑" to LRCLK
tLRBD
Delay time from LRCLK to BITCLK"↑"
Delay time from LRCLK to serial data tLRD
output
Delay time from BITCLK to serial data tBSOD
output
Serial data input latch hold time
tBSIDS
Serial data input latch setup time
tBSIDH
<MS0167-E-00>
- 13 -
min
typ
48
150
150
40
40
64
max
Unit
80
fs
ns
ns
ns
ns
ns
80
ns
40
40
ns
ns
64
50
80
fs
%
ns
ns
ns
80
ns
40
40
40
40
ns
ns
2002/10
[ASAHI KASEI]
[AK7744]
5-4) Microcomputer interface
(AVDD=DVDD=3.0V~3.6V,Ta=-40~85°C,CL=20pF)
Parameter
Symbol
Microcomputer interface signal
tWRF
RQ Fall time
min
typ
max
Unit
8
ns
tWRR
8
ns
SCLK fall time
SCLKrise time
SCLK low level width
SCLK high level width
Microcomputer to AK7744
tSF
tSR
tSCLKL
tSCLKH
8
8
30
30
ns
ns
ns
ns
Time from RESET "↓" to RQ "↓"
tREW
200
ns
Time from RQ "↑" to RESET "↑"
tWRE
200
ns
tWRQH
200
ns
Time from RQ "↓" to SCLK"↓"
tWSC
200
ns
Time from SCLK"↑" to RQ "↑"
tSCW
6×tMCLK
ns
SI latch setup time
SI latch hold time
AK7744 to microcomputer
Time from SCLK"↑" to DRDY"↓"
Time from SI"↑"to DRDY"↓"
SI high level width
Delay time from SCLK"↓" to SO output
AK7744 to microcomputer
(RAM DATA read-out)
SI latch setup time (SI="H")
SI latch setup time (SI="L")
SI latch hold time
Time from SCLK"↓" to SO
AK7744 to microcomputer
(CRC result output) Note 2)
tSIS
tSIH
100
100
ns
ns
RQ Rise time
Note 1)
RQ high level width
tSDR
tSIDR
tSIH
tSOS
tRSISH
tRSISL
tRSIH
tSOD
Delay time from RQ "↑" to SO output
tRSOC
Delay time from RQ "↓" to SO output
tFSOC
3×tMCLK
3×tMCLK
100
ns
ns
ns
ns
100
ns
ns
ns
ns
150
ns
3×tMCLK
30
30
30
50
ns
Note 3)
Note 1) Except for external jump code set at reset state.
Note 2) When a surplus of the serial data D(x) divided by the generated polynomials expression G(x) is
equal to the R(x) then the SO indicates “H”.
Note 3) The Microcontroller should read 50ns before falling the RQ . ( It does not use RUN time. )
<MS0167-E-00>
- 14 -
2002/10
[ASAHI KASEI]
[AK7744]
(6) Timing waveform
6-1) System clock
1/fMCLK
1/fMCLK
tMCLK=1/fMCL
XTI
VIH
VIL
tCR
tMCLKH
tCF
tMCLKL
1/fs
1/fs
VIH
LRCLK
VIL
tLR
1/fBCLK
1/fBCLK
tLF
tBCLK=1/fBCLK
VIH
BITCLK
VIL
tBCLKH
tBCL K
tBR
tBF
6-2)Reset signal
INIT_RESET
tRST
S_RESET
VIL
<MS0167-E-00>
- 15 -
2002/10
[ASAHI KASEI]
[AK7744]
6-3) Audio interface
LRCLK
50%DVDD
tBLRD
tLRBD
BITCLK
50%DVDD
tLRD
tBSOD
SDOUT
SDOUTA1,SDOUTA2,
SDOUTD1,SDOUTD2
50%DVDD
tBSIDS
SDIN
SDINA1,SDINA2
<MS0167-E-00>
tBSIDH
50%DVDD
- 16 -
2002/10
[ASAHI KASEI]
[AK7744]
6-4) Microcomputer interface
* Microcomputer interface signals
RQ
tWR
tWR
tSF
VIH
VIL
tSR
VIH
VIL
SCLK
tSCLKL
tSCLKH
* Microcomputer to AK7744
tWRE
tREW
50%DVDD
S_RESET
RQ
50%DVDD
tWRQH
50%DVDD
SCLK
tSCW
tWSC
tWSC
tSCW
SI
50%DVDD
tSIS
tSIH
NOTE : Timing for RUN state is the same except that RESET is set to an "H"
RESET represents system reset in normal use.
<MS0167-E-00>
- 17 -
2002/10
[ASAHI KASEI]
[AK7744]
* AK7744 to Microcomputer (DBUS data)
1) DBUS data in case of 24-bit data output.
DVDD
50%DVDD
DVSS
S_RESET
RQ
DVDD
50%DVDD
DVSS
SI
50%DVDD
DVSS
DRDY
SCLK
50%DVDD
tSDR
50%DVDD
tSOS
50%DVDD
SO
2) DBUS data less than 24 bits data output ( in case of using SI )
DVDD
50%DVDD
DVSS
S_RESET
RQ
tSIH
SI
DVDD
50%DVDD
DVSS
50%DVDD
DRDY
tSIDR
SCLK
50%DVDD
50%DVDD
tSOS
SO
50%DVDD
* AK7744 to Microcomputer ( RAM DATA Read-out )
<MS0167-E-00>
- 18 -
2002/10
[ASAHI KASEI]
[AK7744]
50%DVDD
DVSS
S_RESET
50%DVDD
DVSS
tRSISL
RQ
SI
50%DVDD
tRSIS
tRSIH
SCLK
50%DVDD
SO
50%DVDD
tSOD
* AK7744 to Microcomputer ( RAM DATA Read-out ) (CRC Check : the surplus of {D(x)/G(x)}=R(x))
RQ
50%DVD
tRSOC
tFSOC
SO
<MS0167-E-00>
50%DVD
- 19 -
2002/10
[ASAHI KASEI]
[AK7744]
8. Function Description
(1) Various setting
1-1) SMODE : slave and master mode selector pin
Sets LRCLK and BITCLK to either inputs or outputs.
a) Slave mode :SMODE="L"
LRCLK(1fs) and BITCLK (64fs or 48fs ) become inputs.
b) Master mode: SMODE="H"
LRCLK (1fs) and BITCLK (64fs) become outputs.
Note) SMODE pin is to be fixed “L” or “H”. Therefore, after release an initial reset ( INIT_RESET =”L”→”H”)
SMODE must change during the system reset state ( S_RESET ="L") . This is especiallty critical in slave mode, as
phase matching between internal and external clocks begins when a system reset occurs (See (8.(4)) Resetting). DO
NOT CHANGE SMODE during runtime, as this will cause an error.
(2) Control registers
The control registers can be set via the microcomputer interface or the control pins. These registers consist of 4
addresses and each register is 8-bits. For the value to be written in the control registers see the microcomputer
interface description. The following describes the control register map.
TEST: for TEST (input 0,X: it ignore input data, but should input
0).
Command Code
Write
Name
D7
D6
D5
D3
D4
D2
D1
D0
Default
Read
60h
70h
CONT0
CFS1
CFS0
DIF
DIF1
DIF0
DISCK
SELCKO
X
00h
64h
74h
CONT1
DATARAM
RM
BANK
CMP_N
SS[1]
SS[0]
TEST
X
00h
68h
78h
CONT2
SWA2
SWA1
SWD2
SWD1
PSDA2
OUTE
TEST
X
00h
6Ch
7Ch
CONT3
ISEL2
ISEL1[2]
ISEL1[1]
ISEL1[0]
PSAD2
PSAD1
TEST
X
00h
1. CONT0 can be set only at system reset ( S_RESET ="L").
2. CONT1~2 should be set at system reset ( S_RESET ="L" ), otherwise some noise can come out.
3. The input selector (CONT3) can be changed “on the fly”. However it must change synchronously with the
initialization of the ADC’s digital interface. For example: ADC1, the input selector (CONT3: ISEL1[2:0]) and
CONT3:PSAD1=1 should change at the same time. After CONT3:PSAD1=0, then the ADC1 digital interface
can be initialized. When changing CONT3 on the fly, some noise will occur, so an external mute circuit after the
DAC output should be used. ADC2 can also cause some noise.
4. Default setting is the same value as an initial reset ( INIT_RESET =”L” ).
<MS0167-E-00>
- 20 -
2002/10
[ASAHI KASEI]
[AK7744]
2-1) CONT0 : clock and interface selector
This register is enabled only at system reset state ( S_RESET =”L”).
Command Code
Write
Read
60h
70h
Name
CONT0
D7
D6
D5
D4
D3
D2
D1
D0
Default
CFS1
CFS0
DIF
DIF1
DIF0
DISCK
SELCKO
X
00h
c D7,D6:CFS1 CFS0 Master clock select
Mode
1
2
3
4
CFS1(D7) CFS0(D6) Enable fs []: Master clock
Note) It can use only as following frequency.
0
0
512fs(fs=48kHz[24.576MHz],44.1kHz[22.5792MHz],32kHz[16.384MHz])
0
1
1536fs(fs=16kHz[24.576MHz],14.7kHz[22.5792MHZ])
1
0
2048fs(fs=12kHz[24.576MHz],11.025kHz[22.5792MHz])
1
1
3072fs(fs=8kHz[24.576MHz])
d D5:DIF Audio interface selector
0:AKM method
1: I2S compatible ( In this case, all input / output pins are I2S compatible.)
e D4,D3:DIF1,DIF0 SDIN Input mode selector
Mode
D4
D3
1
0
0
MSB justified (24bit)
2
0
1
LSB justified (24bit)
3
1
0
LSB justified (20bit)
4
1
1
LSB justified (16bit)
Note) When D5= 1, the state is I2S compatible independently of mode setting. In this case, set D4 and D3 to Mod
e 1.
f D2:DISCK LRCLK,BITCLKOutput control
0: Normal Operation
1: In MASTER mode, this setting can fix BITCLK=”L” and LRCLK=”H”.
(Note In case of I 2 S
compatible setting, it become LRCLK=”L”.) This setting is available only when using the AK7744’s analog
inputs and analog outputs. When this mode is selected, SDIN and SDOUT are not available.
g D1:SELCKO CLKO Output selector.
0:CLKO outputs the same frequency as XTI.
1:CLKO outputs “L” level.
Note) When CLKO=”1”, after setting CONT0 (when the last clock of SCLK rise up) CLKO will change its
frequency.
h D0: Always 0
Note) Underlined settings of c~g = default setting.
<MS0167-E-00>
- 21 -
2002/10
[ASAHI KASEI]
[AK7744]
2-2) CONT1: RAM control
Command Code
Write
Read
64h
74h
Name
CONT1
D7
D6
D5
D4
D3
D2
D1
D0
Default
DATARAM
RM
BANK
CMP_N
SS[1]
SS[0]
TEST
X
00h
c D7:DATARAM DATARAM addressing mode selector
0:Ring addressing mode
1:Linear addressing mode
DATARAM has 256-word x 24-bit and has 2 addressing pointers (DP0, DP1).
In Ring addressing mode: Starting address increments by 1 every sampling period.
In Linear addressing mode: Starting address is always the same, DP0 = 00h and DP1 = 80h.
d D6:RM: Depress bit mode
0: SIGN bit
1: Random data
When it selects Compress & Depress mode (D3:CMP_N = 0), this bit decides depressed LSB bits.
e D5:BANK DLRAM Setting
0:24bit 1kword
1:12bit 2kword
f D3:CMP_N 12-bitDLRAM Compress & Depress selector
When BANK[D5]=1 is selected, this register can set up ON or OFF of its compress/depress function.
0: Compress & Depress function ON
When it writes to DLRAM the DBUS data is compressed to 12-bit and when it read from DLRAM, the data.
is depressed to 16-bit.
1: Compress & Depress function OFF
It always writes to DLRAM MSB 12-bit of DBUS data and it reads from the MSB 12-bit of DLRAM and ad
d to 000h for LSB bits.
g D2,D1:SS[1:0] DLRAM setting of sampling timing.
Mode
D2
D1
RAM mode
0
0
0
Update every sampling time
1
0
1
Update every 2 sampling time
2
1
0
Update every 4 sampling time
3
1
1
Update every 8 sampling time
Note) When the mode 1,2 or 3 is selected, it comes out aliasing.
h D0: Input always 0
Note) Underlined settings of c~g = default setting.
<MS0167-E-00>
- 22 -
2002/10
[ASAHI KASEI]
[AK7744]
2-3) CONT2 : DA,DSP control
Command Code
Write
Read
68h
78h
Name
CONT2
D7
D6
D5
D4
D3
D2
D1
D0
Default
SWA2
SWA1
SWD2
SWD1
PSDA2
OUTE
TEST
X
00h
c D7:SWA2 internal path setting (see p.2 Block diagram)
0:Normal operation (SDINA2 of DSP is input from ADC2)
1:SDINA2 pin connects with SDINA2 of DSP block. Its format is same as SDIN.
d D6:SWA1 internal path setting (see p.2 Block diagram)
0:Normal operation (SDINA1 of DSP is input from ADC1)
1:SDINA1 pin connects with SDINA2 of DSP block. Its format is same as SDIN.
e D5:SWD2 internal path setting (see p.2 Block diagram)
0:Normal operation (SDOUTD2 of DSP outputs to DAC2)
1:SDINA2 pin connects with SDATA of DAC2. Its format is 24bit MSB first or I2S.
f D4:SWD1 internal path setting (see p.2 Block diagram)
0:Normal operation (SDOUTD1 of DSP outputs to DAC1)
1:SDINA1 pin connects with SDATA of DAC1. Its format is 24bit MSB first or I2S.
g D3:PSDA2 DA2 power save control
0:Normal operation
1:DA2 power save
In the case of not using DA2, set this value to “1” and DA2 will RESET.
This can be useful for reducing power consumption.
When changing to normal operation, set this value to “0” at system reset.
h D2:OUTE Output enable ( see Block-diagram)
0:Normal operation (SDOUTA1,SDOUTA2,SDOUTD1,SDOUTD2=”L”)
1: SDOUTA1,SDOUTA2,SDOUTD1 and SDOUTD2 are enable to output.
i D1:TEST
0:Normal operation
1:Test mode (Do NOT use this mode)
j : Always input 0
Note): Underlined settings of c~g = default setting.
<MS0167-E-00>
- 23 -
2002/10
[ASAHI KASEI]
[AK7744]
2-4) CONT3: ADC control
Command Code
Write
Read
6Ch
7Ch
Name
CONT3
D7
D6
D5
D4
D3
D2
D1
D0
Default
ISEL2
ISEL1[2]
ISEL1[1]
ISEL1[0]
PSAD2
PSAD1
TEST
X
00h
c D7: ISEL2 ADC2 Analog input selector setting
0:A2IN-,A2IN+
1:A2IN1
d D6,D5,D4:ISEL1[2:0] ADC1 Analog input selector setting
ISEL1[2](D6)
ISEL1[1](D5)
ISEL1[0](D4)
Analog input pin
0
0
0
AINL-,AINL+,AINR-,AINR+
0
0
1
AINL1,AINR1
0
1
0
AINL2,AINR2
0
1
1
AINL3,AINR3
1
0
0
AINL4,AINR4
1
0
1
AINL5,AINR5
e D3:PSAD2 ADC2 power save
0:Normal operation
1:ADC2 power save
In the case of not using ADC2, set this value to “1” and ADC2 will be in RESET.
This is useful for reducing power consumption.
The digital output signals of ADC2 will 00000h.
When changing to normal operation, set this value to “0” at system reset.
f D2:PSAD1 ADC1 power save
0:Normal operation
1:ADC1 power save
In the case of not using ADC1, set this value to “1” and ADC1 will be in RESET.
This is useful for reducing power consumption.
The digital output signals of ADC1 will 00000h.
When changing to normal operation, set this value to “0” at system reset.
g D1:TEST
0:Normal operation
1:TESTmode (Do NOT use this mode )
h D0: Always input 0
Note) Un Underlined settings of c~g = default setting.
<MS0167-E-00>
- 24 -
2002/10
[ASAHI KASEI]
[AK7744]
(3) Power supply startup sequence
Turn on the power and reset the AK7744 by setting the INIT_RESET = "L" and S_RESET = "L". The VREF
(Analog reference level) of the AK7744 is set and its control registers are initialized by setting the INIT_RESET =
"H". The time for the VREF to become stable depends on the external capacitance on the VCOM pin. For example,
connecting a 10uF and a 0.1uF capacitor takes about 300ms before VREF is stable. Additional capacitance will
increase this time, and this rise time is the MINIMUM amount of time for a stable VREF. You can guarantee a stable
VREF by waiting longer than this minimum time after INIT_RESET ="H" to S_RESET ="H” (ADC and DAC
start to work.).
Normally, INIT_RESET sequence is executed when power is applied to the device.
Note 1): Set INIT_RESET = "H" after setting the oscillation when a crystal oscillator is used.
This setting time may differ depending on the crystal oscillator and its external circuit.
NOTE: Do not stop the system clock (slave mode: XTI, LRCLK, BITCLK, master mode: XTI) except when
S_RESET = "L". If these clock signals are not supplied, excess current will flow due to dynamic logic that is
used internally, and an operation failure may result.
Don’t set S_RESET ="H" during INIT_RESET ="L", or else the the crystal oscillator will stop or become
unstable.
AVDD
DVDD
INIT_RESET
S_RESET
Power OFF
When a crystal oscillator is
After VREF is stable, then rise
used, ensure stable oscillation
up S_RESET. It will take
in this period.
300ms(reference)
Fig. Power supply startup sequence
<MS0167-E-00>
- 25 -
2002/10
[ASAHI KASEI]
[AK7744]
(4) Resetting
The AK7744 has two reset pins: INIT_RESET and S_RESET .
The INIT_RESET pin is used to set up VREF and initialize the AK7744, as shown in "Power supply startup
sequence section 3)."
The system is reset when S_RESET =”L”. (Description of "reset" is for "system reset".)
During a system reset, a program write operation is normally performed (except for write operation during
running).
During the system reset phase, the ADC and DAC sections are also reset. (The digital section of ADC output is
MSB first 00000h and the analog section of DAC output is AVDD/2). However, VREF will be active, LRCLK and
BITCLK in the master mode will be inactive
The system reset is released by setting S_RESET to "H", whichl activates the internal counter. This counter
generates LRCLK and BITCLK in the master mode: however, a problem may occur when a clock signal is generated.
When the system reset is released in slave mode, internal timing will be actuated in synchronization with rising edge
"Ç" of LRCLK (when the standard input format is used). Timing between the external and internal clocks is adjusted
at this time. If the phase difference in LRCLK and internal timing is within about -1/16 to 1/16 of the input sampling
cycle (1/fs) during the operation, the operation is performed with internal timing remaining unchanged. If the phase
difference exceeds the above range, the phase is adjusted by synchronizing the "Ç" of LRCLK (when the standard
input format is used). This prevents synchronization failure with the external circuit. For some time after returning to
the normal state after loss of synchronization, normal data will not be valid. It should change the frequency of clock,
SMODE or Analog input selector, while the system is in reset.
When S_RESET is set to “H”, the reset state is cancelled, and an internal DRAM clear is executed on the rising
edge of LRCLK. It takes 8Fs (167usec at fs=48kHz) to clear the internal DRAM.
The ADC section can output 516-LRCLK after its internal counter has started. (The internal counter starts at the first
rising edge of LRCLK in master mode. In slave mode, it starts 2 LRCLKs after the release of system reset. )
The AK7744 performs normal operation when S_RESET is set to "H".
When INIT_RESET or S_RESET changes, the status of the DAC section also changes to Power down or
Release mode, and it causes a click noise on the output. In this case, the SMUTE function is not effective; an external
mute circuit is necessary to avoid any click noise.
<MS0167-E-00>
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2002/10
[ASAHI KASEI]
[AK7744]
(5) System clock
The required system clock is XTI (384fs/512fs), LRCLK (fs) and BITCLK (64 fs) in the slave mode, and is XTI
(384 fs/512 fs) in the master mode. LRCLK corresponds to the standard digital audio rate (32 kHz, 44.1 kHz, and
48 kHz).
Fs
32.0kHz
44.1kHz
48.0kHz
XTI(Master Clock)
512fs
384fs
16.3840MHz
12.2880MHz
22.5792MHz
16.9344MHz
24.576MHz
18.4320MHz
BITCLK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
5-1) Master clock (XTI pin)
The master clock is obtained by connecting a crystal oscillator between the XTI pin and XTO pin or by inputting an
external clock into the XTI pin while the XTO pin is left open.
5-2) Slave mode
The required system clock is XTI, LRCLK (1 fs) and BITCLK (48/64 fs).
The master clock (XTI) and LRCLK must be synchronized, but the phase is not critical.
5-3) Master mode
The required system clock is XTI (384fs/512fs). When the master clock (XTI) is input, LRCLK (1 fs) and BITCLK
(64 fs) will be outputted from the internal counter synchronized with the XTI. LRCLK and BITCLK will not be
active during initial reset ( INIT_RESET ="L") and system reset ( S_RESET ="L").
<MS0167-E-00>
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2002/10
[ASAHI KASEI]
[AK7744]
(6) Audio data interface (internal connection mode )
The serial audio data pins SDIN,SDINA1,SDINA2,SDOUT,SDOUTA1,SDOUTA2,SDOUTD1 and SDOUTD2 are
interfaced with the external system, using LRCLK and BITCLK. The ports SDINA1, SDINA2, SDOUTA1,
SDOUTA2, SDOUTD1 and SDOUTD2 are not normally used. These ports are controlled via registers. ( See the
block diagram on page.2 and the control register setting section at page 28.)
The data format is MSB-first 2's complement. Normally, the input/output format, in addition to the standard format
used by AKM, can be changed to the I2S compatible mode by setting the control register “CONT0 DIF (D5) to 1”.
(In this case, all input/output audio data pin interface are in the I2S compatible mode.)
The input SDIN,SDINA1 and SDINA2 formats are MSB justified 24-bit at initialization. Setting the control registers
CONT0: DIF1 (D4), DIF0(D3) will cause these ports to be compatible with LSB justified 24-bit, 20-bit and 16-bit.
(SDINA is fixed at 24-bit MSB justified only.) (Note: CONT0 DIF(D5)=0). However, individual setting of SDIN,
SDINA1 and SDINA2 is not allowed. The output SDOUT, SDOUTA1, SDOUTA2, SDOUTD1 and SDOUTD2
are fixed at 24-bit MSB justified only.
In slave mode BITCLK corresponds to not only 64fs but also 48fs. 64fs is the recommended mode. Following form
ats describe 64fs examples.
6-1) Standard input format (DIF = 0: default set value)
a) Mode 1 (DIF1, DIF0 = 0,0: default set value)
LRCLK
Right ch
Left ch
BITCLK
10 9 8 7 6
31 30 29
SDIN,SDINA1,
SDINA2
M 22 21
5 4 3 2
10 9 8 7 6
1 0 31 30 29
M 22 21
2 1 L
5 4 3 2
1 0
2 1 L
M : MSB, L : LSB
* When you want to input the MSB-justified 20-bit data into SDIN, SDINA input four "0" following the LSB.
b) Mode 2, Mode 3, Mode 4
LRCLK
Right ch
Left ch
BITCLK
31 30
SDIN,SDINA1,
SDINA2
Don't Care
23 22 21 20 19 18 17 16 15
1
0
Don't Care
M 22 21 20 19 18 17 16 15
1
L
23 22 21 20 19 18 17 16 15
1
0 31 30
M 22 21 20 19 18 17 16 15
1
L
SDIN,SDINA1
SDINA2
Don't Care
M 18 17 16 15
1
L
Don't Care
M 18 17 16 15
1
L
SDIN,SDINA1
SDINA2
Don't Care
M
1
L
Don't Care
M
1
L
M : MSB, L : LSB
SDIN,SDINA1,SDINA2
SDIN,SDINA1,SDINA2
SDIN,SDINA1,SDINA2
<MS0167-E-00>
Mode2 : (DIF1,DIF0)=(0,1) LSB justified 24-bit
Mode3 : (DIF1,DIF0)=(1,0) LSB justified 20-bit
Mode4 : (DIF1,DIF0)=(1,1) LSB justified 16-bit
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2002/10
[ASAHI KASEI]
[AK7744]
6-2) I2S compatible input format (DIF=1)
LRCLK
Left ch
Right ch
BITCLK
9 8 7
31 30 29 28
SDIN,SDINA1
SDINA2
2
M 22 21
6
5 4
3 2 1 0 31 30 29 28
1 L
9 8 7 6 5 4 3 2
2
M 22 21
1 0
1 L
M : MSB, L : LSB
Mode 1: (DIF1(D4), DIF0(D3)) = (0, 0) must be set.
6-3) Standard output format (DIF=0: default set value)
LRCLK
Right ch
Left ch
BITCLK
SDOUT
SDOUTA1
SDOUTA2
SDOUTD1
SDOUTD2
31 30 29
10 9 8 7
M 22 21
2
6 5 4
3 2 1 0 31 30 29
1 L
M 22 21
10 9 8 7 6 5 4 3 2 1 0
2
1 L
M : MSB, L : LSB
6-4) I2S compatible output format (DIF=1)
LRCLK
Left ch
Right ch
BITCLK
31 30 29 28
SDOUT
SDOUTA1
SDOUTA2
SDOUTD1
SDOUTD2
<MS0167-E-00>
M 22 21
9 8 7
2
6
5 4
3 2 1 0 31 30 29 28
1 L
M 22 21
9 8 7
2
6
5 4
3 2 1 0
1 L
M : MSB, L : LSB
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2002/10
[ASAHI KASEI]
[AK7744]
(7) Interface with microcomputer
The microcomputer interface uses 6 control pins; RQ (ReQuest Bar), SCLK (Serial data input Clock), SI (Serial
data Input), SO (Serial data Output), RDY (ReaDY) and DRDY (Data ReaDY).
In the AK7744, two types of operations are provided; writing and reading during the reset phase (namely, system
reset) and R/W during the run phase.
During the reset phase, writing of the control register, program RAM, coefficient RAM, offset RAM, external
conditional jump code, and reading of the program RAM, coefficient RAM and offset RAM, are enabled.
During the run phase, writing of coefficient RAM, offset RAM and external conditional jump code, and reading of
data on the DBUS (data bus) from the SO, are enabled. Its data is MSB first serial I/O.
When the AK7744 needs to transfer data to the microcomputer, it starts by RQ going “L” expects reading of data
on the DBUS. The AK7744 reads SI data at the rising point of SCLK, and outputs to SO at the falling point of SCLK.
The AK7744 accepts first data as command then address data or some kinds of data input / output starts.
When RQ changes to “H”, one command has finished. New command requests must set RQ to “L” again. For
DBUS data reads, leave RQ =”H”. (It does not need command code input.)
When it needs to clear the output buffer (MICR), the SI pin uses for control. (In this case, it is necessary to protect
against a noise as SCLK.)
Command code table is as follow.
Conditions Code name
for use
RESET
CONT0
phase
CONT1
CONT2
CONT3
PRAM
CRAM
OFRAM
External condition jump
CRC check (R(x))
RUN
CRAM rewrite preparation
phase
CRAM rewrite
OFRAM rewrite preparation
OFRAM rewrite
External condition jump
CRC check (R(x))
Command code list
Remark:
Command code
WRITE
READ
60h
70h
For the function of each bit,
See the description of Control
64h
74h
Registers.
68h
78h
6Ch
7Ch
C0h
C1h
A0h
A1h
90h
91h
C4h
B6h
D6h
A8h
It needs to do before CRAM rewrite
A4h
98h
It needs to do before OFRAM rewrite
94h
C4h
Same code as RESET
B6h
D6h
Same code as RESET
NOTE: Do not send other than the above command codes. Otherwise an operation error may occur.
If there is no communication with the microcomputer, set the SCLK to "H” and the SI to "L" for use.
<MS0167-E-00>
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2002/10
[ASAHI KASEI]
[AK7744]
7-1) Write during reset phase
7-1-a) Control register write (during reset phase)
The data comprises a set of 2 bytes used to perform control register write operations (during reset phase). When all
data has been entered, the new data is sent at the rising edge of the 16th count of SCLK.
Data transfer procedure
c Command code
60h,64h,68h,6Ch
d Control data
(D7 D6 D5 D4 D3 D2 D1 D0)
For the function of each bit, see the description of Control registers, (section 2).
S_RESET
RQ
SCLK
SI
60h
64h
D7 ***D1 D0
D7 ***D1 D0
SO
Note) It must be set always 0 to D0.
Control Registers write operation
<MS0167-E-00>
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2002/10
[ASAHI KASEI]
[AK7744]
7-1-b) Program RAM writes (during reset phase)
Program RAM write operations are performed during the reset phase using 7-bytes of data. When all data have been
transferred, the RDY terminal is set to "L". Upon completion of writing into the PRAM, RDY returns “H” to allow
the next data bit input. When writing to sequential addresses, input the data without a command code or address. To
write discontinuous data, shift the RQ terminal from "H" to "L" again and then input the command code, address and
data in that order.
Data transfer procedure
c Command code C0h
d Address upper
e Address lower
f Data
g Data
h Data
i Data
(1 1 0 0
(0 0 0 0
(A7 . . . .
(D31 . . .
(D23 . . .
(D15 . . .
(D7 . . .
0 0 0 0)
0 0 0 A8)
. . . A0)
. . . D24)
. . . D16)
. . . D8)
. . . D0)
S_RESET
RQ
SCLK
SI
11000000
0000000
A7 ****A1A0
D31***** D0
D31***** D0
RDY
SO
Input of continuous address data into PRAM
S_RESET
RQ
SCLK
SI
11000000 0000000A8 A7**A1A0 D31***D0
11000000 0000000A8 A7**A1A0
RDY
SO
Input of discontinuous address data into PRAM
<MS0167-E-00>
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2002/10
[ASAHI KASEI]
[AK7744]
7-1-c) Coefficient RAM write (during reset phase)
5 bytes of data are used to perform coefficient RAM write operations (during reset phase). When all data has been
transferred, the RDY terminal goes to "H". Upon completion of writing into the CRAM, it goes to "H" to allow the
next data to be input. When writing to sequential addresses, input the data as shown below. To write discontinuous
data, transition the RQ terminal from "H" to "L" and then input the command code, address and data.
Data transfer procedure
c Command code A0h
d Address upper
e Address lower
f Data
g Data
(1 0 1 0 0 0 0 0)
( 0 0 0 0 0 0 0 A8)
(A7 . . . . . . . A0)
(D15 . . . . . . D8)
(D7 . . . . . . D0)
S_RESET
RQ
SCLK
SI
10100000
0000000 A8
A7****A1A0
D15****D0
D15****D0
RDY
SO
Input of continuous address data into CRAM
S_RESET
RQ
SCLK
SI
10100000 0000000 A8 A7***A1A0 D15****D0
10100000 0000000 A8 A7***A1A0 D15*
RDY
SO
Input of discontinuous address data into CRAM
<MS0167-E-00>
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[ASAHI KASEI]
[AK7744]
7-1-d) Offset RAM write (during reset phase)
5 bytes of data are used to perform offset RAM write operations (during reset phase). When all data has been
transferred, the RDY terminal goes to "H". Upon completion of writing into the OFRAM, it goes to "H" to allow the
next data to be input. When writing to sequential addresses, input the data without a command code or address. To
write discontinuous data, shift the RQ terminal from "H" to "L" and then input the command code, address and data
in that order.
Data transfer procedure
c Command code 90h
d Address
e Data
f Data
g Data
(1 0 0 1 0 0
( 0 0 A5 A4 .. .
(0 0 0 0 0 0
(0 0 0 D12 D11 *
(D7 . . . . .
0 0)
. A0 )
0 0)
* . D8 )
. D0 )
S_RESET
RQ
SCLK
SI
10010000
00A5****A0
00000000
00000D10* D8 D7****D1D0
RDY
SO
Input of data into OFRAM
<MS0167-E-00>
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2002/10
[ASAHI KASEI]
[AK7744]
7-1-e) External conditional jump code write (during reset phase)
Two bytes of data are used to perform offset is external conditional jump operations. The data can be entered during
both the reset and operation phases, and the input data are set to the specified register at the leading edge of the
LRCLK. When all data bits have been transferred, the RDY terminal goes to "L". Upon write completion, it goes to
"H". A jump command will be executed if there is any one agreement between "1" of each bit of external condition
code 8 bits (soft set) plus 1 bit (hard set) at the external input terminal JX and "1" of each bit of the IFCON field. The
data during the reset phase can be written only before release of the reset, after all data has been transferred. RQ
Transition from "L" to "H" in the write operation during the reset phase must be executed after three LRCLK in the
slave mode or one LRCLK in master mode, respectively, from the trailing edge of the LRCLK after release of the
reset. Then the RDY goes to "H" after capturing the rise of the next LRCLK. A write operation from the
microcomputer is disabled until the RDY goes to "H". The IFCON field provides external conditions written on the
program. It resets to 00h by INIT_RESET =”L”, however, it remains previous condition even S_RESET =”L”.
Note: It should be noted that the LRCLK phase is inverted in the I2S-compatible state.
7
0 JX
External condition code „„„„„„„„†
Ç
Check if there is any one agreement between the bit specified in IFCON and
"1" in the external condition code
16
È
8
IFCON field ‹‹‹‹‹‹‹‹
Data transfer procedure
c Command code
C4h ( 1 1 0 0 0 1 0 0)
d Code data
(D7 . . . . . D0)
S_RESET
SCLK
SI
11000100 D7 **** D0
SO
RQ
LRCLK
RDY
L ch
R ch
2LRCLK(max)
Timing for external conditional jump write operation (during reset phase)
<MS0167-E-00>
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2002/10
[ASAHI KASEI]
[AK7744]
7-2) Read during reset phase
7-2-a) Control register data read (during reset phase)
To read data written into the control registers, input the command code and 16 bits of SCLK. After the input
command code, the data of D7 to D1 outputs from SO is synchronized with the falling edge of SCLK. D0 is invalid,
so please ignore this bit.
Data transfer procedure
c Command code
70h,74h,78h,7Ch
S_RESET
RQ
SCLK
SI
SO
70h (example)
74h (example)
D7 **** D1
D7 **** D1
Reading of Control Register data
<MS0167-E-00>
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2002/10
[ASAHI KASEI]
[AK7744]
7-2-b) Program RAM read (during reset phase)
To read data written into PRAM, input the command code and the address you want to read out. After that,
set SI to "H" and SCLK to "L". The data is then clocked out from SO in synchronization with the falling edge of
SCLK. (Ignore the RDY operation that will occur in this case.)
If there are continuous addresses to be read, repeat the above procedure starting from the step where SI is set to "H".
Data transfer procedure
cCommand code input C1h ( 1 1 0 0 0 0 0 1 )
dRead address input MSB ( 0 0 0 0 0 0 0 A8)
eRead address input LSB
(A7 . . . . A0)
S_RESET
RQ
SCLK
SI
11000001
0000000 A8 A7 **** A1 A0
D31 **** D0
SO
D31 **** D0
RDY
Reading of PRAM data
<MS0167-E-00>
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2002/10
[ASAHI KASEI]
[AK7744]
7-2-c) CRAM data read (during reset phase)
To read out the written coefficient data, input the command code and the address you want to read out. After
that, set SI to "H" and SCLK to "L”. The data is clocked out from SO in synchronization with the falling edge of
SCLK. If there are continuous addresses to be read, repeat the above procedure starting from the step where SI is set
to "H".
Data transfer procedure
c Command code A1h
d Address upper
e Address lower
(1 0 1 0 0 0 0 1)
( 0 . . . . . . A8)
(A7 . . . . . . A0)
S_RESET
RQ
SCLK
SI
10100001
0000000A8
A7 **** A1A0
D15 **** D0
SO
D15 **** D0
RDY
Reading of CRAM data
<MS0167-E-00>
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2002/10
[ASAHI KASEI]
[AK7744]
7-2-d) OFRAM data read (during reset phase)
The written offset data can be read out during the reset phase. To read it, input the command code and the address
you want to read. After that, set SI to "H" and SCLK to "L". This completes preparation for outputting the data. Then
set SI to "L", and the data is clocked out in synchronization with the falling edge of SCLK. If there are continuous
addresses to be read, repeat the above procedure starting from the step where SI is set to “H”.
Data transfer procedure
c Command code
d Address
91h ( 1 0 0 0 1 0 0 0 1 )
( 0 0 A5 . . . . A0)
S_RESET
RQ
SCLK
SI
SO
10010001
00 A5 **** A0
D10 *** D1 D0
D10 *** D1 D0
D10*** D1 D0
RDY
Reading of OFRAM data
<MS0167-E-00>
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2002/10
[ASAHI KASEI]
[AK7744]
7-3) Write during RUN phase
7-3-a) CRAM rewrite preparation and write (during RUN phase)
This function is used to rewrite CRAM (coefficient RAM) during program execution. After inputting the
command code, you can input a maximum of 16 data bytes of a continuous address you want to rewrite, then input the
write command code and rewrite the leading address. Every time the RAM address to be rewritten is specified, the
contents of RAM are rewritten. The following is an example to show how five data bytes from address "10" of the
coefficient RAM are rewritten:
Coefficient RAM execution address
7 8 9 10 11 13 16 11 12 13 14 15
È È
È È È
Rewrite position
} } Ç
} } }
Note that address "13" is not executed until address "12" is rewritten.
Data transfer procedure
* Preparation for rewrite c Command code A8h ( 1 0 1 0 1 0 0 0 )
d Data
( D15 . . . . D8 )
e Data
( D7 . . . . . D0 )
* Rewrite
c Command code A4h ( 1 0 1 0 0 1 0 0 )
d Address upper
( 0 0 0 0 0 0 0 A8 )
e Address lower
(A7 . . . . A0 )
S_RESET
RQ
SCLK
SI
10101000 D15 **** D0
10100100 A15 **** A0
AL
max 200ns
RDY
SO
Longer of (16-n) x 2 MCL
K
(n: number of data) and AL
RDYLG
Note: The RDY signal will go to high within the maximum of two LRCLKs if the
RDYLG width is programmed to ensure a new address to be rewritten within one
li
l
CRAM rewriting preparation and writing
<MS0167-E-00>
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2002/10
[ASAHI KASEI]
[AK7744]
7-3-b) OFRAM rewrite preparation and write (during RUN phase)
This function is used to rewrite OFRAM (offset RAM) during program execution. After inputting the
command code, you can input a maximum of 16 data bytes of a continuous address you want to rewrite.
Then input the write command code and rewrite the leading address. Every time the RAM address to be rewritten is
specified, the contents of RAM are rewritten. The following is an example to show how five data bytes from address
"10" of the coefficient RAM are rewritten:
Offset RAM execution address 7 8 9 10 11 13 16 11 12 13 14 15
È È
È È È
Rewrite position
} } Ç
} } }
Note that address "13" is not executed until address "12" is rewritten.
Data transfer procedure
* Preparation for rewrite c Command code 98h ( 1 0 0 0 1 1 0 0 0 )
d Data
(D23 . . . . . . D16)
e Data
(D15 . . . . . . D8 )
f Data
( D7 . . . . . . D0 )
* Rewrite
c Command code 94h ( 1 0 0 0 1 0 1 0 0 )
d Address
( 0 0 A5A4 . . . A0)
S_RESET
RQ
SCLK
SI
10011000 D23 **** D0
10010100 00 A5***A0
AL
max 200ns
RDY
(Longer of (16-n) x 2 MCLK
(n: number of data) and AL
RDYLG
SO
Note: The RDY signal will go to high within the maximum of two LRCLKs if the RDYLG
width is programmed to ensure a new address to be rewritten within one sampling cycle.
OFRAM rewriting preparation and writing
<MS0167-E-00>
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[ASAHI KASEI]
[AK7744]
7-3-c) External conditional jump code rewrite (during RUN phase)
Two data bytes are used to write an external conditional jump code. Data can be input during both the reset
and operation phases, and input data is set to the specified register at the rising edge of LRCLK. When all data has
been transferred, the RDY terminal goes to "L". Upon completion of writing, it goes to "H". A jump command will be
executed if there is any one agreement between each bit of the 8-bit external condition code and "1"of each bit of the
IFCON field. A write operation from the microcomputer is disabled until RDY goes to "H".
Note: The LRCLK phase is inverted in the I2S-compatible state.
Data transfer procedure
c Command code
C4h ( 1 1 0 0 0 1 0 0 )
d Code data
(D7 . . . . . D0)
S_RESET
SCLK
SI
11000100
D7 *** D0
SO
RQ
L ch R ch
LRCLK
RDY
max 2LRCLK
max0.25LRCLK
External condition jump write timing (during RUN phase)
<MS0167-E-00>
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[ASAHI KASEI]
[AK7744]
7-4) Read-out during RUN phase (SO output )
SO outputs data on DBUS (data bus) of the DSP section. Data is set when @MICR the DST field specifies. Setting
of data allows DRDY to go to "H", and data is output synchronized with the falling edge of SCLK. When SI goes to
"H", DRDY goes to "L" to wait for the next command. Once DRDY goes to "H", the data of the last @MICR
command immediately before DRDY goes to "H" will be held until SI goes to "H", and subsequent commands will
be rejected. A maximum of 24 bits are output from SO. After the required number of data (not exceeding 24 bits) is
taken out by SCLK, setting SI to “H” can output the next data.
S_RESET
RQ
SI
@MICR
Data1
Data2
DRDY
SCLK
SO
DM Data1
DLSB
DM Data2
DLSB
SO read (during RUN phase)
(8) ADC section high-pass filter
The AK7744 incorporates a digital high-pass filter (HPF) for canceling DC offset in the ADC. The HPF
cut-off frequency is about 1 Hz (fs = 48 kHz). This cut-off frequency is proportional to the sampling frequency (fs).
Cut-off frequency
<MS0167-E-00>
48kHz
0.93Hz
44.1kHz
0.86Hz
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32kHz
0.62Hz
2002/10
[ASAHI KASEI]
[AK7744]
5) Simple error check for communication
The AK7744 has a simple CRC error check function.
(Note: Its main purpose is checking against the noise effects during ata writes from microprocessor to the AK7744.
This check CANNOT guarantee 100% error detection on the AK7744, because this CRC (cyclic redundancy
check) is before writing internal AK7744’s RAM or its register.
Explanation:
* Serial data(X): Input SI data from RQ fall to rise up.
* Generator polynomial G(x) =x16+x12+x5+1 (X.25 of CCITT standard order of hexadecimal is 11021h).
* The rest of D(x) divides by G(x) is R(x).
This division is using exclusive-or instead of subtraction during this calculation.
It makes good 16-bit zero data after translated serial data D(X) and the rest R(X) of
this division comes out 16bit data.
In order to do simple error check is as following:
1) Use the command code B6h and write the R(x) (the rest result of serial data D(x) divided by G(x)).
2) Then use the command code D6h and read out R(x) to check whether the R(x) is correct or not. (Unless this read
out, CRC check itself works.)
3) If the result of the rest D(x) divided by G(x) is equal to R(x), SO outputs “H” from the next rising edge of RQ
to falling edge of RQ . (However, SO read out from micro-controller is prior to this signal. Refrain from a
runtime read out while doing CRC check.) If R(x) is not equal to the result, it outputs “L”.
4) If you want to check other serial data, then repeat action form 1) to 3).
Note) In the case of detecting CRC error in runtime “CRAM rewrite” (A4h) or “OFRAM rewrite“(94h), the
possibility of writing data to the wrong address exists.
* Specific order of data translates.
1) Write the register
The rest R(x) data writing is using 3-byte/unit (24bit)
Data translate order.
cCommand code
B6h
dUpper 8bit of R(x) (D15 * * * * * * D8)
eLower 8bit of R(x) ( D7 * * * * * * D0)
2) Read out the register
The rest R(x) data reading out is 3-byte/unit (24bit)
Data translate order
cCommand code
D6h
dUpper 8bit of R(x) (D15 * * * * * * D8)
eLower 8bit of R(x) ( D7 * * * * * * D0)
<MS0167-E-00>
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2002/10
[ASAHI KASEI]
[AK7744]
R(x)
RQ
SCLK
SI
B6h
D15 *** D0
D6h
SO
D15 *** D0
Example: Control register writing, reading
3) CRC Check
D(x)
RQ
SCLK
SI
10100000
0000000A8
A7***A1 A0
D15*** D0
10100000
0000000A8 A7***A1 A0
SO
The rest(D(x)/G(x))=R(x)
The rest of D(x)/G(x)=R(x) CRC Check example.
4) Example of the R(x) made from D(x).
Examples
1
2
3
<MS0167-E-00>
D(X)
D6ABCDh
D2A5A5h
A855557777AAAA0000FFFFh
R(X)
1E51h
0C30h
2297h
- 45 -
2002/10
[ASAHI KASEI]
[AK7744]
9. System Design
(1) Connection example
Digital +3.3V
0.1u 0.1u 0.1u
10u
14,26,38
DVDD
22,23,24
20
21
Rd
Cd
16
Cd
15
SDIN,SDINA1,SDINA2
SMODE
19
DRDY
32
LRCLK
SO
34
BITCLK
RDY
33
37
RQ
XTO
SI
SCLK
17
Analog INT+
6
Analog INT-
5
Analog INT1
7
Analog Lch+
58
Analog Lch-
57
Analog Rch+
56
Analog Rch-
55
4
Analog 1L
3
Analog 1R
Analog 2L
2
Analog 2R
1
Analog 3L
64
Analog 3R
63
Analog 4L
62
Analog 4R
61
Analog 5L
60
Analog 5R
59
51
Analog +3.3V
10u
54
A2IN+
AK7744
JX
INIT_RESET
S_RESET
A2IN-
I/F
35
36
18
11
RESET
12
CONTROL
A2IN1
AINL+
AINL-
AVSS
AINR+
AINR-
AVDD
9
Analog +3.3V
8
0.1u
10u
0.1u
10u
AINL1
AINR1
VCOM
52
AINL2
AINR2
SDOUT
AINL3
30
AINR3
AINL4
AOUTL1+ 50
AINR4
AOUTL1-
49
AINL5
AOUTR1+ 48
AINR5
AOUTR1-
AVSS
LPF
1R
AOUTL2+ 45
LPF
44
AOUTR2+ 42
AOUTR2-
VREFH
1L
47
AOUTL2-
AVDD
LPF
41
2L
LPF
2R
0.1u
13,25,39
<MS0167-E-00>
CLKO
0.1u
53
10u
XTI
Micom
BVSS
40
DVSS
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[ASAHI KASEI]
[AK7744]
(2) Peripheral circuit
1) Ground and power supply
A To minimize digital noise coupling, AVDD and DVDD should be individually de-coupled at the AK7744.
System analog power is supplied to AVDD. Generally, the power supply and ground wires must be connected
separately for the analog and digital sections. Connect them at a position close to the power source on the PC board.
Decoupling capacitors and small ceramic capacitors should be connected as close as possible to the AK7744
2) Reference voltage
The input voltage difference between the VREFH pin and the AVSS pin determines the full scale of analog input,
while the potential difference between the VREFH pin and the AVSS pin determines the full scale of the analog
output. Normally, connect AVDD to VREFH, and connect 0.1µF ceramic capacitors from them to AVSS. To shut out
high frequency noise, connect a 0.1µF ceramic capacitor in parallel with an appropriate 10µF electrolytic capacitor
between this pin and AVSS. The ceramic capacitor in particular should be connected as close as possible to the pin.
To avoid coupling to the AK7744, digital signals and clock signals should be kept away as far as possible from the
VREFH pin.
VCOM is used as the common voltage of the analog signal.To shut out high frequency noise, connect a 0.1µF
ceramic capacitor in parallel with an appropriate 10µF electrolytic capacitor between this pin and AVSS. The
ceramic capacitor should be connected as close as possible to the pin. Do not lead current from the VCOM pin.
3) Analog input
Analog input signals are applied to the modulator through the differential input pins or single-ended pins of
each channel selected by the input selector. When using the differential inputs, this voltage is equal to the differential
voltage between AIN+ and AIN- (∆VAIN=(AIN+)-(AIN-)), and the input range is ±FS= ±(VREFH-AVSS)×(2.0/3.3).
When VREFH = 3.3V and AVSS = 0V, the input range is within ±2.0Vpp. When using single-ended inputs, this input
range is FS = (VREFH-AVSS)×(2.0/3.3). When VREFH = 3.3V and AVSS = 0V, the input range is within 2.0Vpp
the output code format is given in terms of 2's complements.
The analog source voltage to the AK7744 is +3.3V(Typ.). Voltage of AVDD+0.3V or more, voltage of
AVSS-0.3V or less, and current of 10 mA or more must not be applied to analog input pins
(AINL+,AINL-,AINR+,AINR-,AINL1,AINR1,AINL2,AINR2,AINL3,AINR3,AINL4,AINR4,AINL5,AINR5,
A2IN+,A2IN-,A2IN1,VREFH) Excessive current will damage the internal protection circuit and will cause
latch-up, thereby damaging the IC. Accordingly, if the surrounding analog circuit voltage is ±15 V, the analog input
pins must be protected from high-voltage signals.
10k
Signal
10k
+10V
22u
+
10k
2.00Vpp
10k
+
+
+
NJM5532D
-10V
AIN+
4.7u
+
Vop = VA+ = 3.3V
4.7u
AIN2.00Vpp
Fig. 1 Example of input buffer circuit (differential input)
<MS0167-E-00>
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[ASAHI KASEI]
[AK7744]
10k
Signal
10k
+10V
22u
+
10k
2.00Vp p
10k
+
+
+
NJM5532D
AIN
4.7u
-10V
Vop = VA+ = 3.3V
Fig. 2 Example of input buffer circuit (single ended input)
An analog signal can be applied to the AK7744 is single ended mode. In this case, apply the analog signal
(the full scale is 2.0Vpp when the internal reference voltage is used). However, use of a low saturated operational a
mplifier is recommended if the operational amplifier is driven by the 3.3-volt power supply.
4) Analog output
5 .1 k
1 .8 3 Vp p
AOUT-
33u
+
5 .1 k
390
6 .8 n
AINAOUT+
33u
+
6 .8 n
5 .1 k
1 .8 3 Vp p
3 .6 6 Vp
Vop
+
390
5 .1 k
750p
22u
+
220
AOUT
NJM5532D
10k
750p
Fig.3 Example of output LPF circuit
The analog outputs are full differential outputs and nominally ±1.83Vpp (typ @ VRDAH=3.3V) centered in the internal
common voltage about (AVDD/2). The differential outputs are summed externally, VAOUT=(AOUT+)-(AOUT-)
between AOUT+ and AOUT-.
If the summing gain is 1, the output range is VAOUT = 3.66Vpp(typ@ VRDAH=3.3V). The bias voltage of external
summing circuit is supplied externally.
The input data format is 2’s complement. The output voltage is a positive full scale for 7FFFFFH(@24bit) and a negative
full scale for 800000H(@24bit). The ideal AOUT is 0V for 000000H(@24bit).
The internal switched-capacitor filter and external LPF attenuate the noise generated by the delta-sigma modulator
beyond the audio passband.
Differential outputs can eliminate few mV+AVDD/2 DC offset on analog outputs with capacitors.
Fig.3 shows the example of external op-amp circuit summing the differential outputs.
5) Connection to digital circuit
To minimize the noise resulting from the digital circuit, connect low voltage logic to the digital output. The
applicable logic family includes the 74LV, 74LV-A, 74ALVC and 74AVC series.
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[ASAHI KASEI]
[AK7744]
10. Package
z
64pin LQFP
(Unit : mm)
12.0±0.3
Max 1.70
10.0
1.40
0.10±0.10
12.0±0.3
49
33
32
48
64
17
16
1
0.5
0.21±0.05
0.17±0.05
0.10 M
1.0
0°~10°
0.45 ±0.2
0.10
z
Material & Lead finish
Package:
Lead-frame:
Lead-finish
<MS0167-E-00>
Epoxy
Copper
Soldering (Not include lead) plate
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[ASAHI KASEI]
[AK7744]
11. Marking
AKM
AK7744VT
XXXXXXX
1)
2)
3)
4)
Pin #1 indication
Date Code: XXXXXXX(7 digits)
Marking Code: AK7744VT
Asahi Kasei Logo
IMPORTANT NOTICE
z
z
z
z
z
These products and their specifications are subject to change without notice. Before
considering any use or application, consult the Asahi Kasei Microsystems Co.,
Ltd.(AKM) sales office or authorized distributor concerning their current status.
AKM assumes no liability for infringement of any patent, intellectual property, or other
right in the application or use of any information contained herein.
Any export of these products, or devices or systems containing them, may require an
export license or other official approval under the law and regulations of the country of
export pertaining to customs and tariffs, currency exchange, or strategic materials.
AKM products are neither intended nor authorized for use as critical components in any
safety, life support, or other hazard related device or system, and AKM assumes no
responsibility relating to any such use, except with the express written consent of the
Representative Director of AKM. As used here:
(a): A hazard related device or system is one designed or intended for life support or
maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other
fields, in which its failure to function or perform may reasonably be expected to result in
loss of life or in significant injury or damage to person or property.
(b): A critical component is one whose failure to function or perform may reasonably be
expected to result, whether directly or indirectly, in the loss of the safety or effectiveness
of the device or system containing it, and which must therefore meet very high standards
of performance and reliability.
It is the responsibility of the buyer or distributor of an AKM product who distributes,
disposes of, or otherwise places the product with a third party to notify that party in
advance of the above content and conditions, and the buyer or distributor agrees to
assume any and all responsibility and liability for and hold AKM harmless from any and
all claims arising from the use of said product in the absence of such notification.
<MS0167-E-00>
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