Integrated Circuits Inc. aIVR341N APLUS MAKE YOUR PRODUCTION A-PLUS Data Sheet aIVR341N – 341 sec APLUS INTEGRATED CIRCUITS INC. Address: 3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei, Taiwan 115, R.O.C. (115)台北市南港區成功路一段 32 號 3 樓之 10. Sales E-mail: [email protected] TEL: 886-2-2782-9266 FAX: 886-2-2782-9255 WEBSITE : http: //www.aplusinc.com.tw 2 Support E-mail: [email protected] SEP 15, 2011 Integrated Circuits Inc. aIVR341N FEATURES Standard CMOS process. Embedded EPROM. Embedded 8-bit MCU. 341sec voice duration at 6 KHz sampling with 4-bit ADPCM compression. Combination of voice building blocks to extend playback duration. Table entries are available for voice block combinations. User selectable PCM or ADPCM data compress. Voice Group Trigger Options: Edge / Level; Hold / Un-hold; Retrigger / Non-retrigger. Programmable I/Os, Timer Interrupt and Watch Dog Timer. Built-in oscillator with fixed Rosc, software control sampling frequency 2.4V – 3.6V single power supply and < 5uA low stand-by current. PWM Vout1 and Vout2 drive speaker directly. D/A COUT with ramp-up ramp-down option to drive speaker through an external BJT. Volume control. Maximum 9-bit resolution. Internal Power-up reset circuit built-in; RSTB provides external controlled reset to the chip. DESCRIPTION Aplus’ aIVR341N is a 8-bit MCU based Voice chip. It is fabricated with Standard CMOS process with embedded voice storage memory. It can store 341sec voice message with 4-bit ADPCM compression at 6KHz sampling rate. 8-bit PCM is also available as user selectable option to improve sound quality. There are upto fifteen programmable I/O pins. Key trigger and Parallel CPU trigger mode can be configured according to different application requirement. User selectable triggering and output signal options provide maximum flexibility to various applications. Built-in resistor controlled oscillator, 9-bit resolution current mode D/A output and PWM direct speaker driving minimize the number of external components. Volume control for both DAC and VOUT output is available. 3 SEP 15, 2011 Integrated Circuits Inc. aIVR341N PIN CONFIGURATION PIN DESCRIPTIONS Pin Names VOUT1 VOUT2_COUT VSS VSSA Description PWM output to drive speaker directly PWM output or COUT DAC output select by programmable option Power Ground Analog Power Ground OSC Oscillator input VDD Positive Power Supply VDDA VPP Analog Positive Power Supply Positive Power for EPROM programming, NC during voice playback PB0~PB3 Programmable I/O port B PC0~PC3 Programmable I/O port C PD0~PD2 Programmable I/O port D PE0~PE3 Programmable I/O port E RSTB Reset pin, Low active; Note: PB, PC, PD and PE ports are software programmable I/O pins that can be set to different configurations such as pure input, input with pull-up, input with pull-down and output. The programmable I/O pins set up will take effect immediately after chip RESET is applied. Pins for memory programming are: VDD, VDDA, VSS, VSSA, VPP, PB0, PB1, OSC, VOUT2 and RSTB. 4 SEP 15, 2011 Integrated Circuits Inc. aIVR341N BLOCK DIAGRAM OSC VDD, VDDA, VPP Oscillator MEMORY VSS, VSSA Clock Tree Generator PB0 ~ 3 PC0 ~ 3 PD0 ~ 2 PE0 ~ 3 8-bit MCU I/O PWM Driver & DAC VOUT1 VOUT2_ COUT ABSOLUTE MAXIMUM RATINGS Symbol Rating Unit VDD - VSS -0.5 ~ +4.0 V VIN VSS - 0.3<VIN<VDD + 0.3 V VOUT VSS <VOUT<VDD V T (Operating): 0 ~ +85 ℃ T (Junction) -40 ~ +125 ℃ T (Storage) -55 ~ +125 ℃ 5 SEP 15, 2011 Integrated Circuits Inc. aIVR341N DC CHARACTERISTICS ( TA = 0 to 70℃, VDD = 3.0V, VSS = 0V ) Symbol Parameter Min. Typ. Max. Unit VDD Operating Voltage 2.2 3.0 3.6 V ISB Standby current 1 5 µA I/O properly terminated IOP Operating current 7 mA I/O properly terminated VIH "H" Input Voltage 2.5 3.0 3.5 V VDD=3.0V VIL "L" Input Voltage -0.3 0 0.5 V VDD=3.0V IVOUTL_N VOUT low O/P Current (Normal Volume) 130 mA Vout=1.0V IVOUTL_H VOUT low O/P Current (High Volume) 200 mA Vout=1.0V IVOUTH_N VOUT high O/P Current (Normal Volume) -130 mA Vout=2.0V IVOUTH_H VOUT high O/P Current (High Volume) -200 mA Vout=2.0V ICO COUT O/P Current -2 mA Data = 80h IOH O/P High Current -10 mA VOH=2.5V IOL O/P Low Current 17 mA VOL=0.3V RNVOUT VOUT pull-down resistance 100K Ω VOUT pin set to internal pull-down RNPIO Programmable IO pin pull-down resistance 1M Ω PBx, PCx, PDx set to internal pull-down RUPIO Programmable IO pin pull-up resistance 3.3K 4.7K Ω PBx, PCx, PDx set to internal pull-up ∆Fs/Fs Frequency stability -3 +3 % ∆Fc/Fc Chip to chip Frequency Variation -5 6 +5 % Conditions VDD = 3V +/- 0.4V Also apply to lot to lot variation SEP 15, 2011 Integrated Circuits Inc. aIVR341N TYPICAL APPLICATIONS Rp=1ohm R1 1M C2, 0.1uF VDDA VDD ROSC=220K C1, 0.1uF OSC VOUT1 PB0 PB1 PB2 3.3V SP VOUT2_ COUT PB3 Rrst = 4.7K RSTB VSS, VSSA Crst = 0.1uF Note: 1. PB0 to PB2 are set to input; PB3 is set to output 2. C1 and C2 must be connected directly on the VDD, VDDA and VSS, VSSA pins of the chip 3. R1 is optional for fast discharge of C1, C2 and Crst when power off. Using 3.3V Battery Direct Drive Speaker Rp=1ohm HT7335 C2, 0.1uF ROSC=220K VDDA VDD 8Ω 1/4W Speaker C1, 0.1uF OSC 4.5V VOUT2_ COUT PB0 PB1 PB2 Tr Rb 4.7K RSTB VSS, VSSA 0.1uF Note : PB0 to PB2 are set to input C1 and C2 must be connected directly on the VDD/VDDA and VSS/VSSA pins Output driving of HT LDO: HT7133 (30mA, 3.3V) HT7536 (100mA, 3.6V) HT7335 (250mA, 3.5V) Using 4.5V Battery with COUT speaker drive 7 SEP 15, 2011 Integrated Circuits Inc. aIVR341N VIN=+5V Rp=1ohm VOUT=+3.5V HT7335 C1, 0.1uF C2, 0.1uF 8Ω 1/4W Speaker VDDA VDD 4.7K ROSC 220K OSC MCU Addr[0] Addr[1] Addr[2] PB0 PB1 PB2 PB3 IO0 VOUT2_ COUT Tr Rb RSTB 0.1uF VSS, VSSA Note : PB0 to PB2 set to internal pull-up Addr[0] to [2] are open drain output drive 5V CPU Control with COUT Note for COUT speaker drive: 1. C1 and C2 must be connected as close to the VDD/VDDA and VSS/VSSA pins as possible. 2. Rb is base resistor from 120 Ohm to 390 Ohm depends on value of VDD and transistor gain. 3. Tr is an NPN transistor with beta larger than 150, e.g. 8050D. 4. Rosc = 220K Ohm with Vdd=3.0V can support sampling rate up to 14KHz. 8 SEP 15, 2011 Integrated Circuits Inc. aIVR341N Bonding Diagrams Note: Substrate must be connected to VSS 9 SEP 15, 2011