TI TPS54327DDA

TPS54327
www.ti.com
SLVSAG1 – NOVEMBER 2010
3-A OUTPUT SINGLE SYNCHRONOUS STEP DOWN SWITCHER
WITH INTEGRATED FET (SWIFTTM )
Check for Samples: TPS54327
FEATURES
1
•
23
•
•
•
•
•
•
•
•
•
•
D-CAP2™ Mode Enables Fast Transient
Response
Low Output Ripple and Allows Ceramic Output
Capacitor
Wide VIN Input Voltage Range: 4.5 V to 18 V
Output Voltage Range: 0.76 V to 7.0 V
Highly Efficient Integrated FET’s Optimized
for Lower Duty Cycle Applications
– 100 mΩ (High Side) and 70 mΩ (Low Side)
High Efficiency, less than 10 mA at shutdown
High Initial Bandgap Reference Accuracy
Adjustable Soft Start
Pre-Biased Soft Start
700-kHz Switching Frequency (fSW)
Cycle By Cycle Over Current Limit
APPLICATIONS
•
DESCRIPTION
The TPS54327 is an adaptive on-time D-CAP2™
mode synchronous buck converter. TheTPS54327
enables system designers to complete the suite of
various end equipment’s power bus regulators with a
cost effective, low component count, low standby
current solution. The main control loop for the
TPS54327 uses the D-CAP2™ mode control which
provides a fast transient response with no external
compensation components. The TPS54327 also has
a proprietary circuit that enables the device to adopt
to both low equivalent series resistance (ESR) output
capacitors, such as POSCAP or SP-CAP, and
ultra-low ESR ceramic capacitors. The device
operates from 4.5-V to 18-V VIN input. The output
voltage can be programmed between 0.76 V and 7 V.
The device also features an adjustable soft start time.
The TPS54327 is available in the 8-pin DDA
package, and designed to operate from –40°C to
85°C.
Wide Range of Applications for Low Voltage
System
– Digital TV Power Supply
– High Definition Blu-ray Disc™ Players
– Networking Home Terminal
– Digital Set Top Box (STB)
Vout (50 mV/div)
Iout (2A/div)
100 ms/div
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D-CAP2 is a trademark of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TPS54327
SLVSAG1 – NOVEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–45°C to 85°C
(1)
(2)
(3)
(3)
ORDERABLE PART NUMBER
TPS54327DDA
DDA
TRANSPORT
MEDIA
PIN
Tube
8
TPS54327DDAR
Tape and Reel
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
All package options have Cu NIPDAU lead/ball finish.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
Input voltage range
Output voltage range
MAX
VIN, EN
–0.3
20
V
VBST
–0.3
26
V
VBST (10 ns transient)
–0.3
28
V
VBST (vs SW)
–0.3
6.5
V
VFB, SS
–0.3
6.5
V
SW
–2
20
V
SW (10 ns transient)
–3
22
V
VREG5
–0.3
6.5
V
GND
–0.3
0.3
V
–0.2
0.2
V
2
kV
Voltage from GND to thermal pad, Vdiff
Electrostatic discharge
UNIT
MIN
Human Body Model (HBM)
Charged Device Model (CDM)
500
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
THERMAL METRIC (1)
TPS54327
DDA (8 PINS)
qJA
Junction-to-ambient thermal resistance
42.1
qJCtop
Junction-to-case (top) thermal resistance
50.9
qJB
Junction-to-board thermal resistance
31.8
yJT
Junction-to-top characterization parameter
yJB
Junction-to-board characterization parameter
13.5
qJCbot
Junction-to-case (bottom) thermal resistance
7.1
(1)
5
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54327
TPS54327
www.ti.com
SLVSAG1 – NOVEMBER 2010
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
VIN
MIN
MAX
4.5
18
VBST
–0.1
24
VBST (10 ns transient)
-.0.1
27
VBST(vs SW)
–0.1
5.7
SS
–0.1
5.7
EN
–0.1
18
VFB
–0.1
5.5
SW
–1.8
18
Supply input voltage range
VI
Input voltage range
SW (10 ns transient)
UNIT
V
V
–3
21
GND
–0.1
0.1
–0.1
5.7
V
VO
Output voltage range
VREG5
IO
Output Current range
IVREG5
0
10
mA
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
150
°C
TYP
MAX
UNIT
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SUPPLY CURRENT
IVIN
Operating - non-switching supply current
VIN current, TA = 25°C, EN = 5 V,
VFB = 0.8 V
800
1200
mA
IVINSDN
Shutdown supply current
VIN current, TA = 25°C, EN = 0 V
1.8
10
mA
LOGIC THRESHOLD
VENH
EN high-level input voltage
EN
VENL
EN low-level input voltage
EN
2
V
0.45
V
765
781
mV
0
±0.1
mA
5.5
5.7
V
25
mV
100
mV
VFB VOLTAGE AND DISCHARGE RESISTANCE
VFBTH
VFB threshold voltage
TA = 25°C, VO = 1.05 V, continuous mode
IVFB
VFB input current
VFB = 0.8 V, TA = 25°C
749
VREG5 OUTPUT
VVREG5
VREG5 output voltage
TA = 25°C, 6.0 V < VIN < 18 V,
0 < IVREG5 < 5 mA
VLN5
Line regulation
6 V < VIN < 18 V, IVREG5 = 5 mA
VLD5
Load regulation
0 mA < IVREG5 < 5 mA
IVREG5
Output current
VIN = 6 V, VREG5 = 4.0 V, TA = 25°C
RDS(on)h
High side switch resistance
25°C, VBST - SW = 5.5 V
RDS(on)l
Low side switch resistance
25°C
5.2
60
mA
100
mΩ
70
mΩ
MOSFET
CURRENT LIMIT
Iocl
(1)
Current limit
L out = 1.5 mH (1), TA = -20ºC to 85ºC
3.5
4.2
5.7
A
Not production tested.
3
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54327
TPS54327
SLVSAG1 – NOVEMBER 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THERMAL SHUTDOWN
TSDN
Thermal shutdown threshold
Shutdown temperature
Hysteresis
(2)
165
(2)
°C
30
ON-TIME TIMER CONTROL
tON
On time
VIN = 12 V, VO = 1.05 V
150
ns
tOFF(MIN)
Minimum off time
TA = 25°C, VFB = 0.7 V
260
310
ns
1.4
2.0
2.6
mA
SOFT START
ISSC
SS charge current
VSS = 0 V
ISSD
SS discharge current
VSS = 0.5 V
0.05
0.1
Wake up VREG5 voltage
3.45
3.75
4.05
Hysteresis VREG5 voltage
0.19
0.32
0.45
mA
UVLO
UVLO
(2)
UVLO threshold
V
Not production tested.
4
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54327
TPS54327
www.ti.com
SLVSAG1 – NOVEMBER 2010
DEVICE INFORMATION
DDA PACKAGE
(TOP VIEW)
1
EN
2
VFB
3
VREG5
4
SS
TPS54327
(DDA)
Exposed
Thermal Pad
VIN
8
VBST
7
SW
6
GND
5
PIN FUNCTIONS
PIN
NAME
NO.
DESCRIPTION
EN
1
Enable input control. Active high.
VFB
2
Converter feedback input. Connect to output voltage with feedback resistor divider.
VREG5
3
5.5 V power supply output. A capacitor (typical 1 µF) should be connected to GND. VREG5 is not active
when EN is low.
SS
4
Soft-start control. An external capacitor should be connected to GND.
GND
5
Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB returns to GND at
a single point.
SW
6
Enable control input. EN is active high and must be pulled up to enable the device.
VBST
7
Supply input for the high-side FET gate drive circuit. Connect 0.1µF capacitor between VBST and SW
pins. An internal diode is connected between VREG5 and VBST.
VIN
8
Input voltage supply pin.
Exposed Thermal
Pad
Back side
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected to
GND.
5
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54327
TPS54327
SLVSAG1 – NOVEMBER 2010
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
EN
1
EN
VIN
Logic
VIN
8
VREG5
Control Logic
Ref
+
SS
+ PWM
7
1 shot
VFB
SW
VO
6
-
2
VBST
XCON
ON
VREG5
VREG5
Ceramic
Capacitor
3
SGND
SS
SS
4
5
Softstart
GND
PGND
SGND
+
OCP
-
SW
PGND
VIN
UVLO
VREG5
UVLO
REF
TSD
Protection
Logic
Ref
6
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54327
TPS54327
www.ti.com
SLVSAG1 – NOVEMBER 2010
OVERVIEW
The TPS54327 is a 3-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It
operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output
capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low
ESR output capacitors including ceramic and special polymer types.
DETAILED DESCRIPTION
PWM Operation
The main control loop of the TPS54327 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need
for ESR induced output ripple from D-CAP2™ mode control.
PWM Frequency and Adaptive On-Time Control
TPS54327 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54327 runs with a pseudo-constant frequency of 700 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage, therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
Soft Start and Pre-Biased Soft Start
The soft start function is adjustable. When the EN pin becomes high, 2-mA current begins charging the capacitor
which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up.
The equation for the slow start time is shown in Equation 1. VFB voltage is 0.765 V and SS pin source current is
2 mA.
t
SS
(ms) =
C6(nF) x V
REF = C6(nF) x 0.765
I (mA)
2
SS
(1)
The TPS54327 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting
the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a
cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.
This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and
ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to
normal mode operation.
Current Protection
The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,
Vout, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. The TPS54327 constantly
monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.
If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented
per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the
voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching
7
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54327
TPS54327
SLVSAG1 – NOVEMBER 2010
www.ti.com
cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in
the same manner. If the over current condition exists for 7 consecutive switching cycles, the internal OCL
threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the
switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the
higher value.
There are some important considerations for this type of over-current protection. The load current one half of the
peak-to-peak inductor current higher than the over-current threshold. Also when the current is being limited, the
output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. This may cause the output voltage to fall. When the over current condition is removed, the output
voltage will return to the regulated value. This protection is non-latching.
UVLO Protection
Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower
than UVLO threshold voltage, the TPS54327 is shut off. This is protection is non-latching.
Thermal Shutdown
TPS54327 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C),
the device is shut off. This is non-latch protection.
8
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54327
TPS54327
www.ti.com
SLVSAG1 – NOVEMBER 2010
TYPICAL CHARACTERISTICS
1200
10.0
8.0
IVINSDN - Supply Current - µA
IVIN - Supply Current - µA
1000
800
600
400
6.0
4.0
2.0
200
0
-50
0
50
100
Tj - Junction Temperature - °C
0
-50
150
Figure 1. VIN CURRENT vs JUNCTION TEMPERATURE
0
50
100
Tj - Junction Temperature - °C
150
Figure 2. VIN SHUTDOWN CURRENT vs JUNCTION
TEMPERATURE
100
1.08
VIN = 18 V
90
80
VO - Output Voltage - V
EN - Input Current - mA
1.07
70
60
50
40
30
VIN = 18 V
VIN = 12 V
VIN = 5 V
1.06
1.05
20
10
1.04
0
0
2
4
6
8
10
12
14
EN - Input Voltage - V
16
18
20
Figure 3. EN CURRENT vs EN VOLTAGE
0
0.5
1
1.5
2
IO - Output Current - A
2.5
3
Figure 4. 1.05-V OUTPUT VOLTAGE vs OUTPUT CURRENT
1.08
Vout (50 mV/div)
VO - Output Voltage - V
1.07
IO = 0 A
1.06
Iout (2 A/div)
IO = 1 A
1.05
100 ms/div
1.04
0
5
10
VI - Input Voltage - V
15
20
Figure 5. 1.05-V OUTPUT VOLTAGE vs INPUT VOLTAGE
Figure 6. 1.05-V, 50-mA to 2-A LOAD TRANSIENT
RESPONSE
9
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54327
TPS54327
SLVSAG1 – NOVEMBER 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
100
VO = 3.3 V
90
Efficiency - %
EN (10 V/div)
VREG5 (5 V/div)
Vout (0.5 V/div)
VO = 2.5 V
80
VO = 1.8 V
70
60
50
1 ms/div)
40
0
Figure 7. START-UP WAVE FORM
2
3
IO - Output Current - A
4
Figure 8. EFFICIENCY vs OUTPUT CURRENT
900
900
IO = 1 A
850
fs - Switching Frequency - kHz
850
fs - Switching Frequency - kHz
1
800
VO = 3.3 V
750
700
VO = 1.8 V
650
600
VO = 1.05 V
550
800
VO = 1.8 V
750
700
650
600
500
450
450
5
10
VIN - Input Voltage - V
15
20
Figure 9. SWITCHING FREQUENCY vs INPUT VOLTAGE
VO = 1.05 V
VO (10 mV/div)
400
0
0.5
1
1.5
2
IO - Output Current - A
2.5
3
Figure 10. SWITCHING FREQUENCY vs OUTPUT
CURRENT
VO = 1.05 V
SW (5 V/div)
VO = 1.05 V
550
500
400
0
VO = 3.3 V
VIN (50 mV/div)
SW (5 V/div)
Figure 11. VOLTAGE RIPPLE AT OUTPUT (IO = 2 A)
Figure 12. VOLTAGE RIPPLE AT INPUT (IO = 2 A)
10
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54327
TPS54327
www.ti.com
SLVSAG1 – NOVEMBER 2010
DESIGN GUIDE
Step By Step Design Procedure
To
•
•
•
•
•
begin the design process, you must know a few application parameters:
Input voltage range
Output voltage
Output current
Output voltage ripple
Input voltage ripple
Figure 13. Shows the schematic diagram for this design example.
Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 2 to calculate VOUT.
To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more
susceptible to noise and voltage errors from the VFB input current will be more noticeable.
æ
ö
R1÷
V
= 0.765 x çç1 +
÷
OUT
çè
R2 ÷ø
(2)
Output Filter Selection
The output filter used with the TPS54327 is an LC circuit. This LC filter has double pole at:
F =
P
2p L
1
OUT
x COUT
(3)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS54327. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a -40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that
reduces the gain roll off to -20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 3 is located below the high frequency zero but close enough that the phase boost provided be the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 1
11
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54327
TPS54327
SLVSAG1 – NOVEMBER 2010
www.ti.com
Table 1. Recommended Component Values
Output Voltage (V)
R1 (kΩ)
R2 (kΩ)
L1 (µH)
C8 + C9 (µF)
1
6.81
22.1
C4 (pF)
1.5
22 - 68
1.05
8.25
22.1
1.5
22 - 68
1.2
12.7
22.1
1.5
22 - 68
1.8
30.1
22.1
5 - 22
2.2
22 - 68
2.5
49.9
22.1
5 - 22
2.2
22 - 68
3.3
73.2
22.1
5 - 22
2.2
22 - 68
5
124
22.1
5 - 22
3.3
22 - 68
6.5
165
22.1
5 - 22
3.3
22 - 68
Since the DC gain is dependent on the output voltage, the required inductor value will increase as the output
voltage increases. For higher output voltages above 1.8 V, additional phase boost can be achieved by adding a
feed forward capacitor (C4) in parallel with R1
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4,
Equation 5 and Equation 6. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 700 kHz for
fSW.
Use 700 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS
current of Equation 6.
- VOUT
V
V
OUT x IN(max)
I
=
IPP
V
L x f
IN(max)
O
SW
I
lpp
I
=I +
Ipeak
O
=
I
Lo(RMS)
(4)
2
I
2
O
(5)
+
1
2
I
12 IPP
(6)
For this design example, the calculated peak current is 3.47 A and the calculated RMS current is 3.01 A. The
inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating of 11
A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54327 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 22uF to 68uF. Use Equation 7 to
determine the required RMS current rating for the output capacitor.
I
Co(RMS)
=
VOUT x (VIN - VOUT )
12 x VIN x LO x fSW
(7)
For this design two TDK C3216X5R0J226M 22uF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is .271A and each output capacitor is rated for 4A.
Input Capacitor Selection
The TPS54327 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10 mF is recommended for the decoupling capacitor. An additional 0.1 µF
capacitor from pin 14 to ground is recommended to improve the stability of the over-current limit function. The
capacitor voltage rating needs to be greater than the maximum input voltage.
Bootstrap Capacitor Selection
A 0.1 µF. ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is
recommended to use a ceramic capacitor.
VREG5 Capacitor Selection
A 1-µF. ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is
recommended to use a ceramic capacitor.
12
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54327
TPS54327
www.ti.com
SLVSAG1 – NOVEMBER 2010
THERMAL INFORMATION
This 8-pin DDA package incorporates an exposed thermal pad that is designed to be directly to an external
heartsick. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be
used as a heartsick. In addition, through the use of thermal vias, the thermal pad can be attached directly to the
appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a
special heartsick structure designed into the PCB. This design optimizes the heat transfer from the integrated
circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, refer to Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No.
SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.
The exposed thermal pad dimensions for this package are shown in the following illustration.
Figure 14. Thermal Pad Dimensions (Top View)
13
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54327
TPS54327
SLVSAG1 – NOVEMBER 2010
www.ti.com
LAYOUT CONSIDERATIONS
1. Keep the input switching current loop as small as possible.
2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin of the device.
3. Keep analog and non-switching components away from switching components.
4. Make a single point connection from the signal ground to power ground.
5. Do not allow switching current to flow under the device.
6. Keep the pattern lines for VIN and PGND broad.
7. Exposed pad of device must be connected to PGND with solder.
8. VREG5 capacitor should be placed near the device, and connected PGND.
9. Output capacitor should be connected to a broad pattern of the PGND.
10. Voltage feedback loop should be as short as possible, and preferably with ground shield.
11. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to SGND.
12. Providing sufficient via is preferable for VIN, SW and PGND connection.
13. PCB pattern for VIN, SW, and PGND should be as broad as possible.
14. VIN Capacitor should be placed as near as possible to the device.
VIN
FEEDBACK
RESISTORS
TO ENABLE
CONTROL
BIAS
CAP
VIN
INPUT
BYPASS
CAPACITOR
VIN
HIGH FREQENCY
BYPASS
CAPACITOR
EN
VIN
VFB
VBST
VREG5
SW
SS
GND
BOOST
CAPACITOR
OUTPUT
INDUCTOR
SLOW
START
CAP
Connection to
POWER GROUND
on internal or
bottom layer
ANALOG
GROUND
TRACE
EXPOSED
THERMAL PAD
AREA
VOUT
OUTPUT
FILTER
CAPACITOR
POWER GROUND
VIA to Ground Plane
Figure 15. PCB Layout
14
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54327
PACKAGE OPTION ADDENDUM
www.ti.com
4-Dec-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
TPS54327DDA
ACTIVE
SO PowerPAD
DDA
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
TPS54327DDAR
ACTIVE
SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Dec-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS54327DDAR
Package Package Pins
Type Drawing
SO
Power
PAD
DDA
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Dec-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS54327DDAR
SO PowerPAD
DDA
8
2500
346.0
346.0
29.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DLP® Products
www.dlp.com
Communications and
Telecom
www.ti.com/communications
DSP
dsp.ti.com
Computers and
Peripherals
www.ti.com/computers
Clocks and Timers
www.ti.com/clocks
Consumer Electronics
www.ti.com/consumer-apps
Interface
interface.ti.com
Energy
www.ti.com/energy
Logic
logic.ti.com
Industrial
www.ti.com/industrial
Power Mgmt
power.ti.com
Medical
www.ti.com/medical
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
RFID
www.ti-rfid.com
Space, Avionics &
Defense
www.ti.com/space-avionics-defense
RF/IF and ZigBee® Solutions www.ti.com/lprf
Video and Imaging
www.ti.com/video
Wireless
www.ti.com/wireless-apps
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2010, Texas Instruments Incorporated