DEM-PCM1704 EVALUATION FIXTURE ® FEATURES DESCRIPTION ● INCLUDES TWO PCM1704s, A DF1704 8X INTERPOLATION FILTER, I/V CONVERTERS AND DAC POST FILTERS The DEM-PCM1704 is a complete evaluation fixture for the PCM1704 24-bit sign-magnitude digital-toanalog converter and the DF1704 8X interpolation filter. It includes a demonstration board, PC interface cable, and software for controlling the DF1704 filter. ● REQUIRES ±5V SUPPLIES FOR THE PCM1704 DACs, UP TO ±18V SUPPLIES FOR THE OP AMPS, AND A SINGLE +5V SUPPLY FOR THE DIGITAL SECTION The demonstration board includes all necessary power supply and interface connectors. A socket is provided for accommodating the DEM-DIR1700 demo board. Analog signal conditioning circuitry for the DAC outputs is also included. ● 28-PIN DIP SOCKET FOR DEM-DIR1700 DIGITAL AUDIO RECEIVER ADAPTOR BOARD ● INTERFACE CABLE FOR INTERFACING TO A PC PARALLEL PORT(1) ● DEMONSTRATION SOFTWARE FOR PROGRAMMING DF1704 INTERNAL REGISTERS(1) International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1998 Burr-Brown Corporation LI-528 Printed in U.S.A. October, 1998 BLOCK DIAGRAM CND1 Control +5V CN1 ±5V VCC CN2 PCM1704 DEM-DIR1700 CND2 ±VA VCC DAC OPA627 OPA2134 I/V LPF OPA627 OPA2134 I/V LPF PJ2 Right DF1704 Socket Header Digital Filter Header CN3 PCM1704 DAC UD2 PJ1 Left DEM-PCM1704 Digital Section DAC Section HARDWARE DESCRIPTION Switches DIP switch SW0 is used to set up the data format for the two PCM1704 DACs. Table I shows the function of the DIP switch settings. This section describes the hardware components of the DEM-PCM1704 demonstration board. DAC SECTION The DAC section of the demonstration board includes two PCM1704Us, two OPA627s used as current-to-voltage (I/V) converters, and a OPA2134 dual op amp used to provide second-order lowpass filters for the right and left audio channels. Connectors are provided for power supplies and interfacing to the digital section or an external digital host. SW0 FUNCTION SETTINGS 20-BIT INVL INVR Selects Data Word Length Selects Phase for Left Channel DAC Selects Phase for Right Channel DAC H = 24 Bits, L = 20 Bits H = Normal, L = Inverted H = Normal, L = Inverted TABLE I. DAC Data Format Configuration. DIGITAL SECTION The digital section of the DEM-PCM1704 demonstration board includes the DF1704 digital filter, DIP switches for configuring the filter, a connector for the PC interface cable and digital power supply, and a header for the input data interface. A socket is provided for the DEM-DIR1700 digital audio receiver adaptor board so that clocks and data can be derived from a standard S/PDIF input source. Connectors Connector CN1 is used to provide power to the PCM1704 DACs. +VCC should be set for +5VDC, and –VCC should be set for –5VDC. Connector CN2 is used to provide power to the OPA627 and OPA2134 op amps. +VA is typically set for +15VDC (maximum is +18VDC), while –VCC is typically set to –15VDC (maximum is –18VDC). The GND pins on connectors CN1 and CN2 are connected to the analog ground plane of the DAC section. CN3 is used to connect the audio interface of the digital section to the PCM1704 DACs. Normally, jumpers should be installed for BCK, WDCK, DOL, DOR, and GND. However, if the user desires to bypass the circuitry of the digital section and drive the DACs directly from another signal source, this can be accomplished through this connector. Connectors Connector CND1 is used to provide the +5V digital power supply and ground connections. It is also used to provide connection with an external host when using the DF1704 digital filter in Software control mode. The PC interface cable which accompanies the DEM-PCM1704 kit can be used to provide the connection with a PC parallel (or printer) port to control the MC, MD, ML, and RST signals. The cable also includes two banana plugs for connection to an external +5V supply. RCA jacks PJ1 and PJ2 provide the left and right audio channel outputs. They provide straight forward connection to measurement and commercial audio equipment. Connector CND2 is used to provide the audio input data interface. CND2 can be connected to an external source, or ® DEM-PCM1704 2 it can be configured to function with the DEM-DIR1700 adaptor board, which plugs into socket UD2. The DEMDIR1700 adaptor board includes Burr-Brown’s DIR1700 digital audio receiver. This module can be used to connect to an S/PDIF or optical audio interface used by measurement and commercial audio equipment, such as CD and DVD players. Table III shows the operation of DIP switch SW2 in Hardware mode. SW2 settings are ignored in Software mode. SW2 DESCRIPTION I2S Input Data Format Controls IW0 IW1 Switches DIP switches SW1 and SW2 are used to set the configuration of the DF1704 digital filter. The DF1704 can be controlled using Hardware or Software modes, which is determined by the logic state of the MODE switch. Table II shows the operation of DIP switch SW1. SW1 DESCRIPTION ML (RESV) Software Mode: Control Port Word Clock Signal—set switch to H Hardware Mode: Reserved, Not Used MC (LRIP) Software Mode: Control Port Bit Clock—set switch to H Hardware Mode: LRCIN Polarity LRIP = H, then H = Left Channel, L = Right Channel LRIP = L, then H = Right Channel, L = Left Channel MD (CKO) Software Mode: Control Port Data—set switch to H Hardware Mode: CLKO Output Frequency CKO = H, then CLKO frequency = XTI/2 CKO = L, then CLKO frequency = XTI RST I2S L L L L H H IW1 L L H H L L IW0 L H L H L H INPUT FORMAT 16-Bit, Standard, MSB-First, Right-Justified 20-Bit, Standard, MSB-First, Right-Justified 24-Bit, Standard, MSB-First, Right-Justified 24-Bit, MS-First, Right-Justified 16-Bit, I2S 24-Bit, I2S SRO Digital Filter Roll-Off: H = Slow, L = Sharp OW0 Output Data Format Controls OW1 OW1 OW0 OUTPUT FORMAT L L 16-Bit, MSB-First L H 18-Bit, MSB-First H L 20-Bit, MSB-First H H 24-Bit, MSB-First SF0 Sample Rate Selection for De-Emphasis Control SF1 SF1 L L H H DEM Digital De-Emphasis: H = On, L = Off SF0 L H L H SAMPLING RATE 44.1kHz Reserved 48kHz 32kHz TABLE III. SW2 Operation (Hardware mode only). Reset: H = Normal Operation; L = Reset Operation MODE Mode Control: H = Software Mode, L = Hardware Mode MUTE Mute Control (ignored in Software mode) H = Mute Off—Normal Operation; L = Mute On SCHEMATICS Figure 1 shows the circuit connections for the digital section of the demonstration board. Figure 2 shows the circuit diagram for the DAC Section of the demonstration board. TABLE II. SW1 Operation (Hardware mode descriptions of dual mode pins shown in parentheses). The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 DEM-PCM1704 FIGURE 1. ® DEM-PCM1704 4 +VDD 7 22 C7 10µF + Audio Receiver Adaptor Board UD2 DEM-DIR1700 NC = No Connection 8 21 XTI CLKO DATA 19 BCK 12 26 LRCK CND2 11 Unmounted C6 22pF C5 22pF SW1 ML XTAL MC I2S IW0 3 4 MD/CKD MC/LRIP ML/RESV RST 11 12 13 14 SW1 MODE CLKO 9 10 VSS XTO XTI 8 7 6 IW1 BCKIN 2 5 DIN 1 RST MUTE MD MODE SW2 I2S ML MC UD1 DF1704 MD + CND1 C4 100µF GND RST +VDD MUTE 15 DEM 16 SF0 17 SF1 18 OW0 19 OW1 20 NC 21 VDD 22 DOR 23 DOL 24 WCKO 25 BCKO 26 SR0 27 LRCIN 28 IW1 DW1 SF1 DEM IW0 SR0 OW0 SF0 +VDD C3 0.1µF +VDD C2 10µF + C1 0.1µF CN3 +VDD GND DOR DOL WDCK BCK Digital Section DAC Section FIGURE 2. DAC Section. 5 DEM-PCM1704 ® L H 20-Bit INVL C3 4.7pF C4 4.7pF SW0 INVR INVL 20-Bit DAC Section CN3 Digital Section + + –VCC C10 4.7pF C11 4.7pF + + 20-Bit INVERT WCLK NC NC –VDD DGND +VDD DATA BCLK +VCC NC BPO DC AGND IOUT SERVO DC AGND REF DC NC –VCC UA2 PCM1704U –VCC DATA BCLK REF DC NC NC –VDD SERVO DC DGND AGND +VDD AGND WCLK IOUT NC NC 20-Bit BPO DC INVERT +VCC UA1 PCM1704U C1 4.7pF + C8 4.7pF + C14 100pF + C7 100pF + C13 47pF + C12 47pF + C6 47pF + C5 47pF + C9 4.7pF + C2 4.7pF + + – + – +VCC 4 CF2 47pF UA4 OPA627AP 3 2 4 RF2 2.5kΩ UA3 OPA627AP 3 2 CF1 47pF RF1 2.5kΩ –VCC + 7 + 7 C22 4.7pF 6 C16 4.7pF 6 + C21 4.7pF C15 4.7pF + R4 4.7kΩ R1 4.7kΩ R2 2kΩ R5 2kΩ C23 2200pF R6 4.7kΩ C19 2200pF R3 4.7kΩ + – + – UA5B 1/2 OPA2134A 5 6 C24 560pF UA5A 1/2 OPA2134A 2 C20 560pF 1 7 C18 4.7pF + 8 4 C17 4.7pF + +VA R8 100Ω R7 100Ω –VA PJ2 Rch Out PJ1 Lch Out