DF1706 49% FPO DF1 706 www.ti.com Stereo, 24-Bit, 192kHz 8x Oversampling Digital Interpolation Filter ● SYSTEM CLOCK: 128fS, 192fS, 256fS, 384fS, 512fS, 768fS ● ON-CHIP CRYSTAL OSCILLATOR ● PROGRAMMABLE FUNCTIONS: Hardware or Software Control Modes Sharp or Slow Roll-Off Filter Response Soft Mute Digital De-Emphasis Independent Left/Right Digital Attenuation ● +3.3V SINGLE-SUPPLY OPERATION ● SMALL SSOP-28 PACKAGE FEATURES ● COMPANION DIGITAL FILTER FOR THE PCM1704 24-BIT AUDIO DAC ● HIGH PERFORMANCE FILTER: Stopband Attenuation: –115dB Passband Ripple: ±0.00005dB ● AUDIO INTERFACE: Input Data Formats: Standard, LeftJustified, and I2S Input Word Length: 16, 20, or 24 Bits Output Word Length: 16, 18, 20, or 24 Bits Sampling Frequency: 32kHz to 192kHz DESCRIPTION selectable filter response, de-emphasis, attenuation, and input/output data formats. DIN Serial Input I/F (OW1) (OW0) The DF1706 is the ideal companion for Texas Instruments’s PCM1704 24-bit audio Digital-to-Analog (D/A) converter. This combination allows for the construction of very high-performance audio systems and components. (IW1) (I2S) BCKIN LRCIN (IW0) The DF1706 is a high performance, stereo, 8X oversampling digital interpolation filter designed for high-end consumer and professional audio applications. The DF1706 supports 24-bit, 192kHz operation and features user-programmable functions, including BCKO 8X Oversampling Digital Filter with Function Controller WCKO Output I/F DOL DOR x4 MD/CKO MC/LRIP ML/RESV MODE Mode Control I/F SCK (MUTE) RST (DEM) Crystal/OSC (SF0) (SF1) (SRO) Copyright © 2001, Texas Instruments Incorporated XTI XTO SBAS182 Power Supply CLKO VDD DGND Printed in U.S.A. January, 2001 SPECIFICATIONS All specifications at TA = +25°C, VDD = 3.3V, fS = 44.1kHz, system clock = 256fS/384fS, 16-bit data, unless otherwise noted. DF1706E PARAMETER CONDITIONS MIN RESOLUTION INPUT DATA FORMAT Audio Data Interface Format Audio Data Bit Length Audio Data Format Sampling Frequency System Clock Frequency(1) UNITS Bits Standard , Left-Justified , I2S 16, 20, 24 Selectable MSB First, Binary Two’s Complement 32 192 128/192/256/384/512/768 fS kHz fS Right-Justified 16, 20, 24 Selectable MSB First, Binary Two’s Complement DIGITAL INPUT/OUTPUT Input Logic Level: VIH VIL Output Logic Level: VOH VOL CMOS Compatible 0.7VDD 0.3VDD IOH = 2mA IOL = 4mA tR tF DIGITAL FILTER PERFORMANCE Filter Characteristics 1 (Sharp Roll-Off) Passband 2.4 1.0 20% to 80% VDD, 20pF 80% to 20% VDD, 20pF 20pF Load 4 3 50 ±0.00005dB –3dB Stopband Passband Ripple Stopband Attenuation Filter Characteristics 2 (Slow Roll-Off) Passband Ripple 0.454 0.493 ±0.00005 Stopband = 0.546fS –115 ±0.0001dB –3dB 0.254 0.460 ±0.004 3.6 45 149 VDC mA mW +85 +125 °C °C °C ±0.0001 –100 45.125/fS IDD TEMPERATURE RANGE Operation Storage Thermal Resistance, θJA VDD VDD = 3.3V VDD = 3.3V 3.0 3.3 30 99 –25 –55 SSOP-28 100 fS fS fS dB dB fS fS fS dB dB sec dB 0.732 Stopband = 0.748fS V V V V ns ns % 0.546 Stopband Passband Ripple Stopband Attenuation Delay Time De-Emphasis Error POWER-SUPPLY REQUIREMENTS Voltage Range Supply Current Power Dissipation MAX 24 OUTPUT DATA FORMAT Audio Data Interface Format Audio Data Bit Length Audio Data Format CLKO AC CHARACTERISTICS(2) Rise Time Fall Time Duty Cycle(2) TYP NOTES: (1) Refer to Table I. (2) Crystal resonator used. 2 DF1706 SBAS182 PIN CONFIGURATION PIN ASSIGNMENTS Top View SSOP PIN NAME I/O DESCRIPTION 1 2 3 4 5 6 7 8 9 10 DIN BCKIN I2S IW0 IW1 XTI XTO DGND CLKO MODE IN IN IN IN IN IN OUT — OUT IN Serial Audio Data Input(1) Bit Clock Input for Serial Audio Data(1) Input Audio Data Format Select(2, 4) Input Audio Data Word Select(2, 4) Input Audio Data Word Select(2, 4) Oscillator Input /External Clock Input Oscillator Output Digital Ground Buffered System Clock Output Mode Control Select (HIGH: Software Mode, LOW: Hardware Mode)(3) Mode Control, Data/Half External Clock Frequency Select(3, 5) Mode Control, Clock/Polarity of LRCIN Select(3, 5) Mode Control, Latch Clock/Reserve(3, 5) Reset, Active LOW. When this pin is LOW the DF and modulators are held in reset.(3) Mute Control, Active LOW(4) De-Emphasis Control(2, 4) Sampling Rate Select for De-emphasis(2, 4) Sampling Rate Select for De-emphasis(2, 4) Output Audio Data Word Select(2, 4) Output Audio Data Word Select(2, 4) Oversampling Ratio Control. When this pin is set HIGH, the ratio is 4 times. Digital Power, +3.3V R-Channel, Serial Audio Data Output L-Channel, Serial Audio Data Output Word Clock Output for Serial Audio Data Output Bit Clock Output for Serial Audio Data Output Filter Response Select (2, 4) L/R Clock Input (fS)(1) DIN 1 28 LRCIN BCKIN 2 27 SRO I 2S 3 26 BCKO IW0 4 25 WCKO 11 MD/CKO IN IW1 5 24 DOL XTI 6 23 DOR 12 13 14 MC/LRIP ML/RESV RST IN IN IN 22 VDD 15 16 17 18 19 20 21 MUTE DEM SF0 SF1 OW0 OW1 x4 IN IN IN IN IN IN IN 22 23 24 25 26 27 28 VDD DOR DOL WCKO BCKO SRO LRCIN — OUT OUT OUT OUT IN IN DF1706E XTO 7 DGND 8 21 x4 CLKO 9 20 OW1 MODE 10 19 OW0 MD/CKO 11 18 SF1 MC/LRIP 12 17 SF0 ML/RSV 13 16 DEM RST 14 15 MUTE NOTES: (1) Pins 1, 2, 28—Schmitt-Trigger input without pull-up and -down resistor. (2) Pins 3-5, 16-21, 27—Schmitt-Trigger input without pull-up and -down resistor. (3) Pins 10-15—Schmitt-Trigger input without pull-up and -down resistor. (4) Pins 3-5, 15-20, 27—these pins are invalid when MODE (pin 10) is HIGH. (5) Pins 11-13—these pins have different functions corresponding to MODE (pin 10) HIGH/LOW. ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS Supply Voltage .................................................................................. +4.0V Digital Input Voltage .............................................................. –0.2V to 4.5V Input Current (any pins except supplies) ........................................ ±10mA Operating Temperature Range ......................................... –25°C to +85°C Ambient Storage Temperature ....................................... –40°C to +125°C Junction Temperature ................................................................... +150°C Lead Temperature (soldering, 5s) ................................................. +260°C Package Temperature (IR reflow, Peak, 10s) ................................ +235°C This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT DF1706E " PACKAGE PACKAGE DRAWING NUMBER SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER(1) TRANSPORT MEDIA SSOP-28 324 –25°C to +85°C DF1706E " " " " DF1706E DF1706E/2K Rails Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “DF1706E/2K” will get a single 2000-piece Tape and Reel. DF1706 SBAS182 3 TYPICAL PERFORMANCE CURVES At TA = +25°C, VDD = ±3.3V, fS = 44.1kHz, System Clock = 256fS/384fS, 16-bit data, unless otherwise noted. DIGITAL FILTER (DE-EMPHASIS OFF, fS = 44.1kHz) PASSBAND RIPPLE (Sharp Roll-Off) 0.00010 0 0.00008 –20 0.00006 –40 Attenuation (dB) Attenuation (dB) FREQUENCY RESPONSE (Sharp Roll-Off) 20 –60 –80 –100 –120 –140 0.00004 0.00002 0 –0.00002 –0.00004 –160 –0.00006 –180 –0.00008 –0.00010 –200 0 1 2 3 4 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Frequency (fS) Frequency (fS) TRANSITION CHARACTERISTIC (Slow Roll Off) FREQUENCY RESPONSE (Slow Roll Off) 0 0 –20 –60 Attenuation (dB) Attenuation (dB) –40 –80 –100 –120 –140 –5 –10 –160 –180 –15 –200 0 1 2 3 0 4 0.1 0.2 0.3 0.4 0.5 0.6 0.7 12 14 Frequency (fS) Frequency (fS) DE-EMPHASIS AND DE-EMPHASIS ERROR DE-EMPHASIS (fS = 32kHz) 0 DE-EMPHASIS ERROR (fS = 32kHz) 0.010 0.008 0.006 –2 Error (dB) Level (dB) 0.004 –4 –6 0.002 0 –0.002 –0.004 –0.006 –8 –0.008 –0.010 –10 0 2 4 6 8 Frequency (kHz) 4 10 12 14 0 2 4 6 8 10 Frequency (kHz) DF1706 SBAS182 TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, VDD = ±3.3V, fS = 44.1kHz, System Clock = 256fS/384fS, 16-bit data, unless otherwise noted. DE-EMPHASIS (fS = 44.1kHz) 0 DE-EMPHASIS ERROR (fS = 44.1kHz) 0.010 0.008 –2 0.006 Error (dB) Level (dB) 0.004 –4 –6 0.002 0 –0.002 –0.004 –0.006 –8 –0.008 –0.010 –10 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 Frequency (kHz) DE-EMPHASIS (fS = 48kHz) 0 8 10 12 14 16 18 20 Frequency (kHz) DE-EMPHASIS ERROR (fS = 48kHz) 0.010 0.008 0.006 –2 Error (dB) Level (dB) 0.004 –4 –6 0.002 0 –0.002 –0.004 –0.006 –8 –0.008 –0.010 –10 0 2 4 6 8 10 12 14 Frequency (kHz) DF1706 SBAS182 16 18 20 22 0 2 4 6 8 10 12 14 16 18 20 22 Frequency (kHz) 5 SYSTEM CLOCK REQUIREMENTS tSCKH The system clock of the DF1706 can be supplied by either an external clock signal at XTI (pin 6), or by the on-chip crystal oscillator. The system clock rate must run at 128fS, 192fS, 256fS, 384fS, 512fS, or 768fS, where fS is the audio sampling rate. When a 128fS or 192fS system clock is applied to DF1706, the Over-Sampling Ratio (OSR) of the DF1706's digital filter should be four times instead of eight times. The OSR can be selected by the x4 pin (pin 21) in hardware mode or x4 bit on MODE 2 register in software mode. HIGH 2.0V System Clock 0.8V LOW tSCKL SYMBOL tSCKH tSCKL PARAMETERS MIN System Clock Pulse Width HIGH System Clock Pulse Width LOW 12 12 MAX UNITS ns(1) ns(1) NOTE: (1) For fS = 96kHz and SCK = 256fS, tSCKIH = 14ns (min) tSCKIL = 14ns (min) For fS ≠ 96kHz and SCK = 256fS, tSCKIH = 20ns (min) tSCKIL = 20ns (min) It should be noted that a 768fS system clock cannot be used when fS is larger than 48kHz. Both 128fS and 192fS system clock can be used when fS is larger than 96kHz. In addition, the on-chip crystal oscillator is limited to a maximum frequency of 24.0MHz. Table I shows the typical system clock frequencies for selected sample rates. FIGURE 1. System Clock Timing. RESET The DF1706 has both an internal power-on reset circuit and a reset pin, RST (pin 14), for providing an external reset signal. The internal power-on reset is performed automatically when power is applied to the DF1706, as shown in Figure 2. The RST pin can be used to synchronize the DF1706 with a system reset signal, as shown in Figure 3. During the power-on reset period (1024 system clocks), the outputs of BCKO, DOL, and DOR are forced LOW and the output of WCKO is forced HIGH. For an external forced reset, the outputs of BCKO, DOL, and DOR are forced LOW and the output of WCKO is forced HIGH during the initialization period (1024 system clocks), which occurs after the LOW-toHIGH transition of the RST pin (see Figure 3). The DF1706 includes a system clock detection circuit that determines the system clock rate in use. The circuit compares the system clock input (XTI) frequency with the LRCIN input rate to determine the system clock multiplier. Ideally, LRCIN and BCKIN should be derived from the system clock to ensure proper synchronization. If the phase difference between the system clock and LRCIN is larger than ±4 bit clock (BCKIN) periods, the synchronization of the system and LRCIN clocks will be performed automatically by the DF1706. Timing requirements for the system clock input are shown in Figure 1. SYSTEM CLOCK FREQUENCY (MHz) SAMPLING RATE FREQUENCY (fS)256fS 128fS 192fS 256fS 384fS 512fS 768fS 32kHz 44.1kHz 48kHz 88.2kHz 96kHz 176.4kHz 192kHz N/A N/A N/A N/A N/A 22.5792(2) 24.576(1)(2) N/A N/A N/A N/A N/A 33.8688(1)(2) 36.864(1)(2) 8.192 11.2896 12.288 22.5792(1) 24.576 N/A N/A 12.288 16.934 18.432 33.8688(1) 36.864(1) N/A N/A 16.384 22.5792 24.576(1) N/A N/A N/A N/A 24.576(1) 33.8688(1) 36.864(1) N/A N/A N/A N/A NOTES: (1) Crystal oscillator frequency using internal oscillator is not covered at frequency larger than 24.0MHz. (2) x4 (pin 21) should be set to HIGH. TABLE I. Typical System Clock Frequencies. 2.8V VCC/VDD 2.5V 1.8V Reset Reset Removal Internal Reset 1024 system clocks System Clock FIGURE 2. Internal Power-On Reset Timing. 6 DF1706 SBAS182 External Reset Reset Reset Removal Internal Reset 1024 system clocks System Clock FIGURE 3. External Forces Reset Timing. AUDIO INPUT INTERFACE The audio input interface is comprised of BCKIN (pin 2), LRCIN (pin 28), and DIN (pin 1). BCKIN is the input bit clock, which is used to clock data applied at DIN into the DF1706’s input serial interface. Input data at DIN is clocked into the DF1706 on the rising edge of BCKIN. The left/right clock, LRCIN, is used as a word latch for the audio input data. BCKIN can run at 32fS, 48fS, or 64fS, where fS is the audio sample frequency. LRCIN is run at the fS rate. Figures 4 (a) through (c) show the input data formats, which are selected by hardware or software controls. See Figure 5 for the audio input interface timing requirements. (a) Standard Data Format; L-Channel = HIGH, R-Channel = LOW 1/fS Lch Rch LRCIN BCKIN AUDIO DATA WORD = 16-BIT DIN 14 15 16 1 MSB AUDIO DATA WORD = 20-BIT DIN 18 19 20 1 22 23 24 1 1 15 16 2 LSB 19 20 2 MSB AUDIO DATA WORD = 24-BIT DIN 15 16 2 1 19 20 2 LSB 23 24 2 MSB 1 23 24 2 LSB MSB LSB (b) Left-Justified Format; L-Channel = HIGH, R-Channel = LOW 1/fS Lch Rch LRCIN BCKIN AUDIO DATA WORD = 24-BIT DIN 1 2 22 3 MSB 23 24 1 2 LSB 22 3 MSB 23 24 1 2 3 LSB (c) I2S Data Format (Philips Format); L-Channel = LOW, R-Channel = HIGH 1/fS Lch LRCIN Rch BCKIN AUDIO DATA WORD = 16-BIT DIN 1 2 1 2 MSB AUDIO DATA WORD = 24-BIT DIN 15 16 2 1 2 LSB 15 16 MSB 23 24 MSB 1 LSB 2 1 2 LSB 23 24 MSB 1 LSB FIGURE 4. Audio Data Input Formats. DF1706 SBAS182 7 AUDIO OUTPUT INTERFACE The audio output interface includes BCKO (pin 26), WCKO (pin 25), DOL (pin 24), and DOR (pin 23). BCKO is the output bit clock and is used to clock data into an audio D/A converter, such as the PCM1704. DOL and DOR are the left and right audio data outputs. WCKO is the output word clock and is used to latch audio data words into an audio D/A converter. WCKO runs at a fixed rate of 8fS (8x oversampling) for all system clock rates. BCKO is fixed at 256fS for system clock rates of 256fS or 512fS. BCKO is fixed at 192fS for system clock rates of 384fS or 768fS. The output data format used by the DF1706 for DOL and DOR is Binary Two’s Complement, MSB-first, right-justified audio data. Figures 6(a), (b), (c), and (d) show the output data formats for the DF1706. See Figure 7 the audio output timing. LRCKIN 50% of VDD tBCH tBCL tLB BCKIN 50% of VDD tBL tBCY 50% of VDD DIN tDS BCKIN Pulse Cycle Time tBCY 82ns (min) BCKIN Pulse Width LOW tBCL 35ns (min) BCKIN Pulse Width HIGH tBCH 35ns (min) BCKIN Rising Edge to LRCIN Edge tBL 10ns (min) LRCIN Edge to BCK Rising Edge tLB 10ns (min) DIN Set-up Time tDS 10ns (min) DIN Hold Time tDH 10ns (min) tDH FIGURE 5. Audio Input Interface Timing. (a) SYSTEM CLOCK: 256/512fS 1/8fS WCKO BCKO AUDIO DATA WORD = 16-BIT DOR 14 15 16 DOL 1 15 16 2 MSB AUDIO DATA WORD = 18-BIT DOR 16 17 18 DOL 1 LSB 17 18 2 MSB AUDIO DATA WORD = 20-BIT DOR 18 19 20 DOL 1 LSB 19 20 2 MSB AUDIO DATA WORD = 24-BIT DOR 22 23 24 DOL 1 LSB 23 24 2 MSB (b) SYSTEM CLOCK: 384/768fS LSB 1/8fS WCKO BCKO AUDIO DATA WORD = 16-BIT DOR 14 15 16 DOL 1 MSB AUDIO DATA WORD = 18-BIT DOR 16 17 18 DOL 1 2 MSB AUDIO DATA WORD = 20-BIT DOR 18 19 20 DOL AUDIO DATA WORD = 24-BIT DOR 22 23 24 DOL 15 16 2 1 17 18 LSB 19 20 2 MSB 1 LSB LSB 23 24 2 MSB 1 2 LSB FIGURE 6. Audio Output Data Format. 8 DF1706 SBAS182 (a) SYSTEM CLOCK: 128fS 1/4fS WCKO BCKO AUDIO DATA WORD = 16-BIT DOR 14 15 16 DOL 1 15 16 2 MSB AUDIO DATA WORD = 18-BIT DOR 16 17 18 DOL 1 LSB 17 18 2 MSB AUDIO DATA WORD = 20-BIT DOR 18 19 20 DOL 1 LSB 19 20 2 MSB AUDIO DATA WORD = 24-BIT DOR 22 23 24 DOL 1 LSB 23 24 2 MSB (b) SYSTEM CLOCK: 192fS LSB 1/4fS WCKO BCKO AUDIO DATA WORD = 16-BIT DOR 14 15 16 DOL 1 MSB AUDIO DATA WORD = 18-BIT DOR 16 17 18 DOL 1 LSB 17 18 2 MSB AUDIO DATA WORD = 20-BIT DOR 18 19 20 DOL AUDIO DATA WORD = 24-BIT DOR 22 23 24 DOL 15 16 2 1 LSB 19 20 2 MSB 1 LSB 23 24 2 MSB 1 2 LSB (Cont.) FIGURE 6. Audio Output Data Format. MODE CONTROL The DF1706 may be configured using either software or hardware control. The selection is made using the MODE input (pin 10). See Table II for MODE selection. MODE SETTING MODE CONTROL SELECTION MODE = H MODE = L Software Mode Hardware Mode TABLE II. MODE Selection. tWCKP PARAMETERS WCKO 0.5VDD tBCKH tBCKL 0.5VDD tBCKP tCKDO DOL, R tBCKP 0.5VDD MIN TYP MAX UNITS 1/96fS, 1/128fS, 1/192fS, 1/256fS, 10 20 ns (fS = 192kHz, 128fS) 14 30 ns (other fS, 256/384/512/768fS) 20 100 ns –5 5 ns 5 ns BCKO Pulse Width HIGH/LOW (fS = 192kHz, 192fS) tCKWK BCKO SYMBOL BCKO Period tBCKH/tBCKL Delay Time BCKO Falling Edge to WCKO Valid tCKWK WCKO Period tWCKP Delay Time BCKO Falling Edge to DOL, R Valid 1/4fS, 1/8fS tCKDO –5 Rising Time of All Signals tR 7 ns Falling Time of All Signals tF 7 ns NOTE: (1) Rising and falling time is measured from 10% to 90% of IN/OUT signal swing. (2) Load capacitance of all signals are 20pF. FIGURE 7. Audio Data Output Timing. DF1706 SBAS182 9 Programmable Functions The DF1706 includes a number of programmable features, with most being accessible from either Hardware or Software mode. Table III summarizes the user-programmable functions for both modes of operation. SOFTWARE (MODE = H) HARDWARE (MODE = L) RESET DEFAULT (Software Mode) Input Data Format Selection O O Standard Format Input Word Length Selection O O 16 Bits Output Word Length Selection O O 16 Bits LRCIN Polarity Selection O O Left/Right = High/Low FUNCTION PIN NAME PIN NUMBER DESCRIPTION RSV 13 Reserved, Not Used LRIP 12 LRCIN Polarity LRIP = H: LRCIN= H = Left Channel, LRCIN= L = Right Channel LRIP = L: LRCIN= L = Left Channel, LRCIN = H = Right Channel CKO 11 CLKO Output Frequency CKO = H: CLKO Frequency = XTI/2 CKO = L: CLKO Frequency = XTI MUTE 15 Soft Mute Control: H = Mute Off, L = Mute On I2S IW0 IW1 3 4 5 Input Data Format Controls I2S L L L L H H IW1 L L H H L L IW0 L H L H L H INPUT FORMAT 16-Bit, Standard, MSB-First, Right-Justified 20-Bit, Standard, MSB-First, Right-Justified 24-Bit, Standard, MSB-First, Right-Justified 24-Bit, MSB-First, Left-Justified 16-Bit, I2S 24-Bit, I2S Digital De-Emphasis O O OFF Over Sample Ratio Control O O 8x Soft Mute O O OFF Digital Attenuation O X 0dB, Independent L/R SRO 27 Digital Filter Roll-Off: H = Slow, L = Sharp Sample Rate for De-Emphasis Function O O 44.1 kHz OW0 OW1 19 20 Output Data Word Length Controls Filter Roll-Off Selection O O Sharp Roll-Off Selected CLKO Output-Frequency Selection O O Same As XTI Input OW1 OW0 L L L H H L H H Legend: O = User Programmable, X = Not Available. OUTPUT FORMAT 16-Bit, MSB-First 18-Bit, MSB-First 20-Bit, MSB-First 24-Bit, MSB-First TABLE III. User-Programmable Functions for Software and Hardware Mode. SF0 SF1 Hardware Mode Controls With MODE = L, the DF1706 may be configured by utilizing several user-programmable pins. The following is a brief summary of the pin functions. Table IV provides more details on setting the hardware mode controls. DEM 16 Digital De-Emphasis: H = On, L = Off x4 21 Oversampling Rate Control: H = 4fS, L = 8fS Pins I2S, IW0, and IW1 are used to select the audio data input format and word length. Pins OW0 and OW1 are used to select the output data word length. The DEM pin is used to enable and disable the digital deemphasis function. De-emphasis is only available for 32kHz, 44.1kHz, and 48kHz sample rates. Pins SF0 and SF1 are used to select the sample rate for the de-emphasis function. The SRO pin is used to select the digital filter response, either sharp or slow roll-off. Generally, sharp roll-off filter is used. The MUTE pin is used to enable or disable the soft mute function. The CKO pin is used to select the clock frequency seen at the CLKO pin, either XTI or XTI ÷ 2. The LRIP pin is used to select the polarity used for the audio input left/right clock, LRCIN. The x4 pin is used to control the over sampling ratio of the internal digital filter, either a 8x or 4x. For instance, when fs is 192kHz or 176.4kHz, the over sampling ratio should be 4x. 10 17 18 Sample Rate Selection for the Digital De-Emphasis Control SF1 L L H H SF0 L H L H SAMPLING RATE 44.1kHz Reserved, Not Used 48kHz 32kHz TABLE IV. Hardware Mode Controls. Finally, the RESV pin is not used by the current DF1706 design, but is reserved for future use. Software Mode Controls With MODE = H, the DF1706 may be configured by programming four internal registers in software mode. ML (pin 13), MC (pin 12), and MD (pin 11) make up the 3-wire software control port, and may be controlled using DSP or microcontroller general purpose I/O pins, or a serial port. Table V provides an overview of the internal registers, labeled MODE0 through MODE3 (see Table V). See Figures 8 through 10 for more details regarding the control port data format and timing requirements. The data format for the control port is 16-bit, MSB-first, with Bit B15 being the MSB. Register Addressing A[1:0], bits B10 and B9 of the 16-bit control data word, are used to indicate the register address to be written to by the current control port write cycle. See Table VI for how to address the internal registers using bits A[1:0] of registers MODE0 through MODE3. DF1706 SBAS182 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 MODE0 res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0 MODE1 res res res res res A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 MODE2 res res res res res A1 A0 res res OW1 OW0 IW1 IW0 x4 DEM MUT MODE3 res res res res res A1 A0 res SF1 SF0 CKO res SRO ATC LRP I2S FIGURE 8. Internal Mode Control Registers. ML MC MD B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 FIGURE 9. Software Interface Format. tMLL tMHH ML(1) 0.5VDD tMCH tMLH tMCL tMLS 0.5VDD MC(2) tMCY LSB MD tMDS 0.5VDD tMDH MC Pulse Cycle Time tMCY 100ns (min) MC Pulse Width LOW tMCL 40ns (min) MC Pulse Width HIGH tMCH 40ns (min) MD Hold Time tMDH 10ns (min) MD Set-Up Time tMDS 10ns (min) ML LOW Level Time tMLL 40ns ML HIGH Level Time tMHH 40ns ML Hold Time(1) tMLH 20ns (min) ML Set-Up Time(2) tMLS 20ns (min) NOTES: (1) ML rising edge to the next MC rising edge. (2) MC rising edge for LSB to ML rising edge. FIGURE 10. Software Interface Timing Requirements. REGISTER NAME BIT NAME DESCRIPTION MODE0 AL[7:0] LDL A[1:0] res Attenuation Data for the Left Channel Attenuation Load Control for the Left Channel Register Address Reserved MODE1 AR[7:0] LDL A[1:0] res Attenuation Data for the Right Channel Attenuation Load Control for the Right Channel Register Address Reserved MODE2 MUT DEM x4 IW[1:0] OW[1:0] A[1:0] res Soft Mute Control Digital De-Emphasis Control Oversampling Rate Control Input Data Format and Word Length Output Data Word Length Register Address Reserved MODE3 I2S LRP ATC SRO CKO SF[1:0] A[1:0] res Input Data Format (I2S or Standard/Left-Justified) LRCIN Polarity Attenuator Control, Dependent or Independent Digital Filter Roll-Off Selection (sharp or slow) CLKO Frequency Selection (XTI or XTI ÷ 2) Sample Rate Selection for De-Emphasis Function Register Address Reserved A1 A0 REGISTER SELECTED 0 0 MODE0 0 1 MODE1 1 0 MODE2 1 1 MODE3 TABLE VI. Internal Register Addressing. NOTE: All reserved bits should be programmed to 0. TABLE V. Internal Register Mapping. DF1706 SBAS182 11 MODE0 Register The MODE0 register is used to set the attenuation data for the left output channel, or DOL (pin 24). When ATC = 1 (Bit B2 of Register MODE3 = 1), the left channel attenuation data AL[7:0] is used for both the left and right channel attenuators. When ATC = 0, (Bit B2 of Register MODE3 = 0), left channel attenuation data is taken from AL[7:0] of register MODE0, and right channel attenuation data is taken from AR[7:0] of register MODE1. AL[7:0] Left Channel Attenuator Data, where AL7 is the MSB and AL0 is the LSB. Attenuation Level is given by: programmed data in bits AL[7:0] of register MODE0. When LDR = 0, the right channel output data remains at its previously programmed level. MODE2 Register The MODE2 register is used to program various functions: MUT When MUT = 0, Soft Mute is ON for both left and right channels. When MUT = 1, Soft Mute is OFF for both left and right channels. DEM LDL DATA DATA DATA DATA = = = = FFH, ATTEN = –0dB FEH, ATTEN = –0.5dB 01H, ATTEN = –127.5dB 00H, ATTEN = infinity = Mute Left Channel Attenuation Data Load Control. This bit is used to simultaneously set attenuation levels of both the left and right channels. IW[1:0] When LDL = 1, the left channel output level is set by the data in AL[7:0]. The right channel output level is set by the data in AL[7:0], or the most recently programmed data in bits AR[7:0] of register MODE1. When LDL = 0, the left channel output data remains at its previously programmed level. MODE1 Register The MODE1 register is used to set the attenuation data for the right output channel, or DOR (pin 23). When ATC = 1 (Bit B2 of Register MODE3 = 1), the left channel attenuation data AL[7:0] of register MODE0 is used for both the left and right channel attenuators. When ATC = 0, (Bit B2 of Register MODE3 = 0), left channel attenuation data is taken from AL[7:0] of register MODE0, and right channel attenuation data is taken from AR[7:0] of register MODE1. AR[7:0] Right Channel Attenuator Data, where AR7 is the MSB and AR0 is the LSB. Attenuation Level is given by: ATTEN = 0.5 • (DATA – 255)dB For For For For LDR DATA DATA DATA DATA = = = = FFH, ATTEN = –0dB FEH, ATTEN = –0.5dB 01H, ATTEN = –127.5dB 00H, ATTEN = infinity = Mute Right Channel Attenuation Data Load Control. This bit is used to simultaneously set attenuation levels of both the left and right channels. When LDR = 1, the right channel output level is set by the data in AR[7:0], or by the data in bits AL[7:0] of register MODE0. The left channel output level is set to the most recently 12 Digital De-Emphasis Function. When DEM = 0, de-emphasis is OFF. When DEM = 1, de-emphasis is ON. x4 Oversampling Rate Selection When x4 = 0, 8fS Sampling Rate Operation When x4 = 1, 4fS Sampling Rate Operation ATTEN = 0.5 • (DATA – 255)dB For For For For Soft Mute Function. OW[1:0] Input Data Format and Word Length. I2 S IW1 IW0 Description 0 0 0 16-Bit Data, Standard Format (MSB-First, Right-Justified) 0 0 1 20-Bit Data, Standard Format 0 1 0 24-Bit Data, Standard Format 0 1 1 24-Bit Data, MSB-First, Left-Justified 1 0 0 16-Bit Data, I2S Format 1 0 1 24-Bit Data, I2S format 1 1 0 Reserved 1 1 1 Reserved Output Data Word Length. OW1 OW0 Description 0 0 1 1 16-Bit 18-Bit 20-Bit 24-Bit 0 1 0 1 Data, Data, Data, Data, MSB-First MSB-First MSB-First MSB-First MODE3 Register The MODE3 register is used to program various functions. I2 S Input Data Format. When I2S = 0, standard or left-justified formats are enabled. When I2S = 1, the I2S formats are enabled. LRP LRCIN Polarity Selection. When LRP = 0, left channel is HIGH and right channel is LOW. When LRP = 1, left channel is LOW and right channel is HIGH. DF1706 SBAS182 ATC Attenuator Control. This bit is used to determine whether the Left and Right channel attenuators operate with independent data, or use common data (the Left channel data in bits AL[7:0] of register MODE0). When ATC = 0, the Left and Right channel attenuator data is independent. When ATC = 1, the Left and Right channel attenuators use common data. SRO Digital Filter Roll-Off Selection. When SRO = 0, sharp roll-off is selected. When SRO = 1, slow roll-off is selected. CKO CLKO Output Frequency Selection. When CKO = 0, the CLKO frequency is the same as the clock at the XTI input. When CKO =1, the CLKO frequency is half of the XTI input clock frequency. SF[1:0] Sampling Frequency Selection for the De-Emphasis Function. SF1 SF0 Description 0 0 1 1 44.1 kHz Reserved 48 kHz 32 kHz 0 1 0 1 APPLICATIONS INFORMATION PCB LAYOUT GUIDELINES In order to obtain the specified performance from the DF1706 and its associated D/A converters, proper printed circuit board layout is essential. Figure 11 shows two approaches for obtaining the best audio performance. Figure 11(a) shows a standard, mixed signal layout scheme. The board is divided into digital and analog sections, each with its own ground. The ground areas should be put on a split-plane, separate from the routing and power layers. The DF1706 and all digital circuitry should be placed over the digital section, while the audio D/A converter(s) and analog circuitry should be located over the analog section of the board. A common connection between the digital and analog grounds is required and is done at a single point as shown. DF1706 SBAS182 For Figure 11(a), digital signals should be routed from the DF1706 to the audio D/A converter(s) using short, direct connections to reduce the amount of radiated high-frequency energy. If necessary, series resistors may be placed in the clock and data signal paths to reduce or eliminate any overshoot or undershoot present on these signals. A value of 50Ω to 100Ω is recommended as a starting point, but the designer should experiment with the resistor values in order to obtain the best results. Figure 11(b) shows an improved method for high-performance, mixed signal board layout. This method adds digital isolation between the DF1706 and the audio D/A converter(s), and provides complete isolation between the digital and analog sections of the board. The ISO150 dual digital coupler provides excellent isolation, and operates at speeds up to 80Mbps. POWER SUPPLIES AND BYPASSING The DF1706 requires a single +5V power supply for operation. The power supply should be bypassed by a 10µF and 0.1µF parallel capacitor combination. The capacitors should be placed as close as possible to VDD (pin 22). Aluminum electrolytics or tantalum capacitors can be used for the 10µF value, while ceramics may be used for the 0.1µF value. BASIC CIRCUIT CONNECTIONS See Figures 12 and 13 for basic circuit connections of the DF1706. Figure 12 shows connections for Hardware mode controls, while Figure 13 shows connections for Software mode controls. Notice the placement of C1 and C2 in both figures, as they are physically close to the DF1706. TYPICAL APPLICATIONS The DF1706 will typically be used in high performance audio equipment, in conjunction with high performance audio D/A converters. Figure 14 shows a typical application circuit example, employing the DF1706, a digital audio receiver, and two PCM1704 24-bit, 192kHz audio D/A converter(s). 13 (a) Layout Without Isolation Digital Power Supplies Common Ground Connection Analog Power Supplies WCKO BCKO DAC DOL DOR DF1706 DAC Digital Section Analog Section Split Ground Plane (b) Layout With Isolation Digital Power Supplies Analog Power Supplies WCKO BCKO ISO150 DAC DOL DOR DF1706 ISO150 Digital Section DAC Analog Section = DGND Split Ground Plane = AGND FIGURE 11. PCB Layout Model. 14 DF1706 SBAS182 DF1706 Audio Data and Clock Source 22pF XTAL 1 DIN 2 BCKIN 3 I2S BCKO 26 4 IW0 WCKO 25 5 IW1 DOL 24 6 XTI DOR 23 7 XTO VDD 22 8 VSS 9 CLKO OW1 20 10 MODE OW0 19 LRCIN 28 SRO 27 D/A Converters or Digital Couplers C1 0.1µF 22pF (optional) C2 10µF +3.3V x4 21 11 MD/CKO SF1 18 12 MC/LRIP SF0 17 13 ML/RESV DEM 16 14 RST Digital Logic or Manual Controls + MUTE 15 7 7 = DGND NOTE: Do not allow pins 3-5, 11-20, and 27 to float. These pins should be manually connected to VDD or DGND (hardwired, switch, jumper) or actively driven by logic. FIGURE 12. Basic Circuit Connections, Hardware Control. DF1706 Audio Data and Clock Source 22pF XTAL 1 DIN 2 BCKIN 3 I2S BCKO 26 4 IWO WCKO 25 5 IW1 DOL 24 6 XTI DOR 23 7 XTO VDD 22 8 VSS 9 CLKO OW1 20 10 MODE OW0 19 22pF (optional) +3.3V Controller or Logic LRCIN 28 SRO 27 x4 21 11 MD SF1 18 12 MC SF0 17 13 ML DEM 16 14 RST D/A Converters or Digital Couplers C1 0.1µF + +5V C2 10µF MUTE 15 = DGND FIGURE 13. Basic Circuit Connection, Software Control. DF1706 SBAS182 15 DIGITAL SECTION WORD CLOCK ANALOG SECTION DF1706 Digital Audio Input Digital Audio Receiver DATA 1 BIT CLOCK +3.3V Host Interface BCLK BCKIN SRO 27 WCLK 3 I2S BCKO 26 DATA 4 IWO WCKO 25 5 IW1 DOL 24 6 XTI DOR 23 7 XTO VDD 22 8 VSS 9 CLKO OW1 20 10 MODE OW0 19 11 MD SF1 18 12 MC SF0 17 13 ML Post Filter Left Channel Out I/V Post Filter Right Channel Out PCM1704 DATA D/A Converter DEM 16 MUTE 15 10µF = DGND I/V BCLK WCLK System Reset D/A Converter x4 21 14 RST +5V PCM1704 LRCIN 28 2 SYSTEM CLOCK Micro Controller or Logic DIN + 0.1µF +5V FIGURE 14. DF1706 Typical Application Circuit. 16 DF1706 SBAS182 PACKAGE OPTION ADDENDUM www.ti.com 3-Oct-2003 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY DF1706E ACTIVE SSOP DB 28 47 DF1706E/2K ACTIVE SSOP DB 28 2000 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. 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