CS1600 Low-cost PFC Controller for Electronic Ballasts Features & Description Description Lowest PFC System Cost for Electronic Ballasts CS1600 is a high-performance Variable Frequency Discontinuous Conduction Mode (VF - DCM), active Power Factor Correction (PFC) controller, optimized to deliver the lowest PFC system cost for electronic ballast applications. Variable Frequency Discontinuous Conduction Mode Improved Efficiency Due to Variable Switching Frequency A variable ON time / variable frequency algorithm is used to achieve near unity power factor. This algorithm spreads the EMI frequency spectrum, which reduces the conducted EMI filtering requirements. The feedback loop is closed through an integrated compensation network within the IC, eliminating the need for additional external components. Protection features such as overvoltage, overcurrent, overpower, open- and short-circuit protection, overtemperature, and brownout help protect the device during abnormal transient conditions. EMI Signature Reduction from Digital Noise Shaping Integrated Feedback Compensation Overvoltage Protection with Hysteresis Overpower Protection with Shutdown UVLO with Wide Hysteresis Thermal Shutdown with Hysteresis Pin Assignments NC 1 8 NC STBY 2 7 VDD IAC 3 6 GD FB 4 5 GND 8-lead SOIC D5 L1 R1a BR1 RAC R2a CS1600 1 C1 AC Mains R1c 3 +12V BR1 Advance Product Information Cirrus Logic, Inc. http://www.cirrus.com RFB BR1 R1b BR1 D6 7 C2 8 R2b NC STBY IAC FB VDD NC GD GND C3a Clink 2 R2c 4 C3b 6 R3 Q1 5 This document contains information for a product under development. Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 2010 (All Rights Reserved) JUL ‘10 DS904A7 CS1600 1. PIN DESCRIPTIONS NC 1 8 NC STBY 2 7 VDD IAC 3 6 GD FB 4 5 GND Table 1. Pin Descriptions Pin Name Pin # I/O Description NC 1, 8 - No Connect — Connect these pins to VDD to prevent any leakage path that could arise from leaving them unterminated. STBY 2 IN Standby — This is an active-low pin. Shorting this pin to GND disables PFC switching. The input has a pull-up resistor and should be driven with an open-collector device. Leave this pin unterminated when not in use. IN Rectified Line Voltage Sense — The IAC pin is used to sense the rectified line voltage. This signal, in conjunction with the signal on the FB pin, is used in the Power Factor Correction (PFC) algorithm A filter capacitor of up to 2.2 nF may be added between this pin and VDD to provide noise immunity. IAC FB 4 IN Feedback Voltage Sense — The FB pin is used to sense the output voltage of the PFC stage. This signal, in conjunction with the signal on the IAC pin, is used in the Power Factor Correction (PFC) algorithm. A filter capacitor of up to 2.2 nF may be added between this pin and VDD to provide noise immunity. GND 5 – Ground — GND is a common reference for all the functional blocks in this device. GD 6 OUT Gate Drive — GD is the output of the device with a source capability of 0.5 A and a current sink capacity of 1 A. VDD 2 3 7 IN IC Supply Voltage — VDD is the input used to provide bias to the device. This pin has an internal shunt to ground. An external bias needs to be applied for steadystate operation. A low-ESR ceramic decoupling capacitor at this pin is recommended for reliable operation of this device. DS904A7 CS1600 2. CHARACTERISTICS AND SPECIFICATIONS 2.1 Absolute Maximum Ratings Pin Symbol Parameter Value Unit Vz V 7 VDD IC Supply 2,3,4 VIN Input Voltage -0.5 to VDD V 3,4 IIN Input Current 50 mA 6 VGD Gate Drive Voltage -0.3 to VDD V 6 IGD Gate Drive Current -1.0 / +0.5 A 1,2,3,4,5,6,8 ESD Human Body Model 2000 V 1,2,3,4,5,6,8 ESD Machine Model 200 V 1,2,3,4,5,6,8 ESD Charged Device Model 500 V - PD Total Power Dissipation at 50° C2 600 mW - TJ Junction Temperature Operating Range -40 to +125 ºC - TStg Storage Temperature Range -65 to +150 ºC Voltage1 Notes: 1. The CS1600 has an internal shunt regulator that controls the nominal operating voltage on the VDD pin. 2. 2.2 Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation at the rate of 50 mW / ºC for variation over temperature. Electrical Characteristics Recommended operating conditions (unless otherwise specified): TA = TJ = -40º to +125º C, VDD = 10 to 15 V, GND = 0 V. Typical values are at TA = 25º C. Parameter Condition Symbol Min Typ Max Unit VDD Turn-on Threshold Voltage VDD increasing Vth(St) 8.4 8.8 9.3 V VDD Turn-off Threshold Voltage VDD decreasing Vth(Stp) 7.1 7.4 7.9 V VHys - 1.3 - V IDD = 20 mA VZ 17.0 17.9 18.5 V Start-up Supply Current VDD < Vth(St) IST - 68 80 μA Standby Supply Current STBY < 0.8V ISB - 80 112 μA CL = 1nF, fsw(max) = 70 kHz IDD - 1.7 1.9 mA Maximum Operating Frequency3,4 Normal mode, VDD = 13 V fSW(max) 62 66 70 kHz Minimum Operating Frequency3,4 Normal mode, VDD = 13 V fSW(min) 20 22 23 kHz Minimum Duty Cycle VDD = 13 V, STBY < 0.8 V tDC_min - - 0 % Maximum Duty Cycle3,4 VDD = 13 V Dmax 64 66 68 % Minimum On Time VDD = 13 V ton_min 0.45 0.5 0.55 μs Output Source Resistance IGD = 100 mA, VDD = 13 V ROH - 9 - Ω Output Sink Resistance IGD = -200 mA, VDD = 13 V ROL - 6 - Ω CL = 1 nF, VDD = 13 V tr - 32 60 ns VDD Supply Voltage UVLO Hysteresis Zener Voltage Supply Current Section Operating Supply Current PFC Gate Drive Section Rise Time DS904A7 3 CS1600 Parameter Condition Fall Time Symbol Min Typ Max Unit CL = 1 nF, VDD = 13 V tf - 15 30 ns Output Voltage Low IGD = -200 mA,VDD = 13 V VOL - 0.9 1.3 v Output Voltage High IGD = 100 mA,VDD = 13 V VOH 11.3 11.8 - v 125 129 135 120 - 136 Feedback and Protection 3, 7 25º C Reference Current -40º to +125º C Overvoltage Protection Threshold Recovery from Overvoltage Protection Iref 25º C 104 108 111 -40º to +125º C 101 - 113 25º C 98 101 105 -40º to +125º C 94 - 105 μA % % Start-up Mode Start Threshold 25º C 83 85 87 Normal Mode Start Threshold 25º C 97 99 101 Recovery from Undervoltage 25º C - 10 - % 123 125 127 % Overpower Protection Hysteresis 4 GDRV turns off, 25º C % of full load as defined by Eq. 3 - 5 - % Input Brownout Protection Threshold Vout = 460V, GDRV turns off, 25º C VBP(th) 79 85 93 Vrms Input Brownout Recovery Threshold Vout = 460V, GDRV turns on, 25º C VBR 91 97 104 Vrms Thermal Shutdown Threshold 3 TSD 130 143 155 ºC Thermal Shutdown Hysteresis TSD(Hy) - 9 - ºC VDD – 0.8 - 0.8 - V Overpower Protection Threshold 4 % Thermal Protection STBY Input Logic Threshold 5 2.3 Thermal Characteristics Symbol Parameter Value Unit RθJA Thermal Resistance (Junction to Ambient)6. 159 ºC / W RθJC Thermal Resistance (Junction to Case)6. 39 ºC / W 3. 4. 5. 6. 7. 4 Low High Specifications guaranteed by design & characterization. Specifications measured as an instantaneous quantity NOT as a time-averaged quantity. STBY is designed to be driven by an open-collector device. The input is internally pulled up with a 600 kΩ resistor. The package thermal impedance is calculated in accordance with JESD 51. Based upon input voltage 120 to 277 VAC and an output voltage (Vout) of 460 V, with boost inductance of 380 μH, output capacitance of 23.5 μF, and VDD of 13 V. DS904A7 CS1600 3. TYPICAL ELECTRICAL PERFORMANCE 3.5 13 CL = 1 nF fSW(max) = 70 kHz 3 12 TA = 25 °C 2.5 VDD (V) IDD (mA) 11 2 10 1.5 9 1 Startup 8 0.5 UVLO Rising Falling 7 -50 0 0 2 4 6 8 10 12 14 16 18 20 VDD (V) 50 TEMP (o C) 100 150 Figure 2. Start-up & UVLO vs. Temperature 2 19 1.5 18.5 IDD = 20 mA VZ (V) UVLO Hysteresis (V) Figure 1. UVLO Characteristics 0 1 0.5 18 17.5 0 17 -50 0 50 TEMP ( o C) 100 Figure 3. UVLO Hysteresis vs. Temperature DS904A7 150 -50 0 50 100 150 TEMP ( oC) Figure 4. VDD Zener Voltage vs. Temperature 5 CS1600 1.8 14 Operating 12 VDD = 13 V CL = 1 nF fSW(max) = 70 kHz 1.4 1.2 Source 10 Zout (Ohm) Supply Current (mA) 1.6 1.0 0.8 6 0.6 VDD = 13 V Isource = 100 mA Isink = 200 mA Sink 4 0.4 0.2 2 Start-up 0 -50 Standby Start-up Standby 0 50 TEMP ( o C) 100 150 Figure 5. Supply Current (ISB, IST, IDD) vs. Temperature 6 8 0 -60 -40 -20 0 20 40 60 80 100 120 Gate Resistor (ROH, ROL) Temp (oC) 140 Figure 6. Gate Resistance (ROH, ROL) vs. Temperature DS904A7 CS1600 4. INTRODUCTION The CS1600 is a digitally controlled Power Factor Correction (PFC) controller that operates in the Variable Frequency Discontinuous Conduction Mode (VF - DCM). The CS1600 uses a proprietary digital algorithm to optimize control of the power switch to deliver highly efficient performance for electronic ballast applications. With this control scheme, the total number of external components needed is minimized in comparison to conventional control techniques, thus reducing the overall system cost. Figure 7 below. Digital control is achieved by constantly monitoring two voltages – the PFC output voltage (Vlink) at pin FB and the rectified AC line voltage (Vrect) at pin IAC. This is done by measuring the currents that flow into the respective pins. These currents are then fed to the inputs of two analog-to-digital converters (ADCs) and are compared against an internal target current, Iref. 20 The digital outputs of the two ADCs are then processed in a control algorithm which determines the behavior of the CS1600 during start-up, normal operation, and under fault conditions such as brownout, overvoltage, overcurrent, overpower, and over-temperature. Details of operation during these conditions are discussed in later sections of this document. Some of the key features of the CS1600 are as follows: • Discontinuous Conduction Mode with Continuously Variable Switching Frequency The PFC switching frequency is varied every switching cycle. This allows for a spread spectrum which minimizes the conducted EMI peaks at any given frequency, thereby minimizing the size and cost of the EMI filter required at the front-end. During start-up, the control algorithm limits the maximum ON time and adjusts the frequency to avoid inductor saturation and provides a near-trapezoidal envelope for the input current during every half cycle. During normal operation, as the line voltage changes over half of a line cycle, the frequency varies approximately 2:1 as shown in DS904A7 120 Switching Frequency (% of Max) 100 % of Max 80 60 Line Voltage (% of Max) 40 0 0 45 90 135 180 Rectified Line Voltage Phase (Deg.) Figure 7. Switching Frequency vs. Phase Angle Maximum power transfer occurs at the peak of the AC line voltage, at which time, the frequency reaches its maximum value. Switching losses are minimized during periods of low power transfer by switching at lower frequencies near the zero-crossing of the AC line. This switching frequency profile helps reduce total BOM cost through savings in the size of the boost inductor and the EMI filter components, while at the same time, improving overall system efficiency. • Integrated Feedback Control No external feedback compensation components are required for the CS1600. The internal digital control engine self-compensates the feedback error signal using an adaptive control algorithm. • Protection Features The CS1600 provides various protection features such as undervoltage, overcurrent, overpower, open and short circuit protection and brownout. It also provides the user with the option of using the STBY pin to disable switching of the device. 7 CS1600 4.1 PFC Implementation The PFC switching frequency profile over the line period has been discussed in detail in Section 4. In addition, the digital control algorithm tracks changes the AC input and operates in different frequency bands at different line voltages as illustrated in Figure 8 and Figure 9 below. CRM mode near the peaks of the input line, in order to enable maximum power delivery, as illustrated in Figure 10 below. DCM Quasi CRM DCM Quasi CRM DCM ILB fSW [kHz] 100 Burst Mode Max fSW 70 Figure 10. DCM and quasi-CRM Operation with CS1600 4.1.1 Start-up Mode vs. Normal Mode CS1600 operates in two discrete states: 35 Min fSW 5% 50% Start-up mode: 100% PO [W] Figure 8. Switching Frequency vs. Output Power Vin < 165 VAC During this start-up phase of operation, the switching frequency could be significantly lower than the normal operating frequency, and the input current waveform is forced into following a trapezoidal envelope in phase with the line voltage, to maximize energy transfer. The ON time and the switching frequency of the IC ensure that peak currents are kept controlled to prevent saturation of the boost inductor during this period. fSW [kHz] Burst Mode 60 Max fSW 48 When the output voltage of the PFC stage, Vlink, is <90% of its nominal value, the device operates in the start-up mode. It continues operating in this mode till the nominal Vlink voltage is reached. The start-up algorithm provides an ON time which is varied in proportion to the sensed rectified voltage, while changing the switching frequency to provide maximum power. Normal mode: 5% 50% 100% PO [W] Figure 9. Switching Frequency vs. Output Power Vin > 165 VAC The CS1600 primarily operates in the DCM mode with a properly sized inductor. However, it will move into a quasi- Once Vlink reaches its nominal value, the chip operates in the normal mode. Here, the frequency follows the profile shown in Figure 7, and the ON time is varied to achieve PFC. Any drop in Vlink to below its undervoltage threshold, as defined in Section 2.2. Electrical Characteristics re-triggers the start-up mode of operation. A simplified illustration of operation in these two modes is shown below in Figure 11. 100% 90% Normal Mode Startup Mode Min fSW Startup Mode 24 Normal Mode t [ms] Figure 11. Start-up and Normal Modes 8 DS904A7 CS1600 4.1.2 Burst Mode Iref = Target Reference current used for feedback In addition to the start-up mode and normal mode of operation, the controller enters the burst mode of operation when the estimated output power (PO) is < 5% of its nominal value. During this stage, the PFC driver is disabled intermittently over a full line cycle period, as shown in Figure 12. The period of time for which the PFC drive is disabled depends on the level of loading present.. Vlink RFB IFB VDD 7 RIFB 15k PO [W] FB 5% Burst Mode Active ADC 4 Figure 13. Output Feedback Vlink t [ms] Vin [V] PFC Disable Vin IFB RFB FET Vgs VDD 7 RIFB 15k t [ms] FB ADC 4 Figure 12. Burst Mode of Operation 4.2 Input Feedforward and Output Regulation Figure 14. Input Feedforward The CS1600 continuously monitors the rectified AC line and the PFC output voltage through sense resistors tied to the IAC and the FB pins to monitor the voltages, scaled as currents. The rectified AC line sense resistor RAC needs to be the same size of the resistor RFB used for current feedback from the PFC output voltage. These currents are effectively compared against an internal reference current to provide adaptive PFC control. The resistor values are calculated as follows: V link – V DD R FB = ----------------------------I ref [Eq.1] R AC = R FB [Eq.2] RFB = Feedback resistor used to sense the PFC output voltage RAC = Feedforward resistor used to sense the rectified line voltage VDD = IC Supply Voltage DS904A7 Protection Features 4.3.1 Overvoltage Protection If the PFC output voltage, Vlink, exceeds the overvoltage threshold, as scaled by the current monitored by the sense resistors, the CS1600 provides protection by disabling the gate drive. A nominal hysteresis is provided to allow the system to recover from the fault condition, before switching is resumed. 4.3.2 Overcurrent Protection The CS1600’s digital controller algorithm limits the ON time of the Power MOSFET by the following equation: where Vlink= PFC Output Voltage 4.3 0.001126 T on ≤ ------------------------V rect Where Ton is the max time that the power MOSFET is turned on and Vrect is the rectified line voltage. In the event of a sudden line surge or sporadic, high dv/dt line voltages, this equation may not limit the ON time appropriately. For this type of line disturbance, additional protection mechanisms, such as fusible resistors, fast-blow fuses, or other current-limiting devices, are recommended. 9 CS1600 4.3.3 Overpower Protection The nominal output power is estimated internally by the CS1600 from the following equation 2 V link – ( V in ( min ) × 2 ) Po = α × η × ( V in ( min ) ) × --------------------------------------------------------2 × f max × L B × V link [Eq.3] where Po = rated output power of the system η = efficiency of the boost converter = estimated as 100% by the internal PFC algorithm Vin(min) = minimum RMS line voltage for operation Vlink = PFC output voltage fmax = maximum switching frequency LB = boost inductor used in the application V link V link – -------------- × 90V × 2 V 400V 90V link α = -------------- × -------------------- × --------------------------------------------------------------------400V V in ( min ) V link – V in ( min ) × 2 for the output voltage, drops to 49% of its nominal value. Detection of brownout for a period of 56 ms disables the gate drive. The device continues to monitor the input voltage while in this condition. The CS1600 exits the brownout mode when the input current scales up to, and stays above 56.4% of its nominal value for a period of 56 ms. To minimize false detects, the brownout detection circuit increases the brownout detection time by a factor of 1.6 mS/V for every volt differential between the minimum operating voltage and the brownout threshold, following half of a line cycle of exceeding the brownout threshold. The following diagram illustrates the brownout sequence whereby the CS1600 enters standby, and upon recovery from brownout, enters normal operation.. TBrownout Brownout Thresholds Upper Lower 2 Start Timer Enter Standby Start Timer Operation estimated to be at power levels higher than that calculated by Eq. 3 above is tracked by the IC as an overpower condition. During this phase, the PFC output voltage, Vlink, is reduced and will continue to decrease as the power draw increases. When Vlink reaches its undervoltage threshold, it goes into the start-up mode as explained in section 4.1.1. 4.3.6 At this point, the overpower protection timer is activated. If this condition continues to exist for 112 ms, the gate drive is disabled for a period of about 3 seconds. This “hiccup” mode of operation continues until the fault is removed. 4.4 If a value of the boost inductor other than that obtained from Eq. 3 above is used, the total output power capability as well as the thresholds for the different operating conditions will scale accordingly. 4.3.4 Open/short circuit protection 56 ms 56 ms Figure 15. Brownout Over-temperature Protection Over-temperature protection is activated and PFC switching is disabled when the die temperature of the device exceeds 125°C. There is a hysteresis of about 30°C before resumption of normal operation. Standby (STBY) Function The standby (STBY) pin may be used as a means to force the CS1600 into a non-operating, low-power state. The STBY input should be driven by an open-collector/open-drain device. Internal to the pin, there is a pull-up resistor connected to the VDD pin as shown in Figure 16. A filter capacitance of about 1000 pF is recommended while this pin is being used. CAP The CS1600 protects the system in case the feedforward resistor tied to the IAC pin or the feedback resistor tied to the FB pin is open or shorted to ground. A fault seen on the resistor going into the FB pin would imply no current being fed into the pin, which would trigger the Vlink undervoltage algorithm as described in Section 4.3.1. A fault detected on the IAC pin would trigger the brownout condition discussed in Section 4.3.5 below. 4.3.5 Brownout Protection Brownout occurs when the current representing the rectified input voltage, nominally 100% of the reference current used 10 Exit Standby 600 kΩ STBY CS1600 <1 nF See Text GND Figure 16. STBY Pin Connection DS904A7 CS1600 5. FLUORESCENT BALLAST APPLICATION EXAMPLE The following section gives an example for a front-end PFC stage design for an electronic ballast application. The equations that follow may be used as guidelines for any other requirements using the CS1600. D5 L1 R1a BR1 RAC R2a RFB BR1 CS1600 R1b 1 R1c C1 AC Mains 3 +12V BR1 D6 7 C2 BR1 8 R2b NC STBY IAC FB VDD NC GD GND C3a Clink 2 R2c 4 C3b 6 R3 Q1 5 Figure 17. CS1600 Basic Application Circuit 5.1 Component Selection Guidelines The following design example is for a wide-input-voltage fluorescent ballast application using 2 T5 lamps in series for a total nominal power of 108W.The target specifications for the PFC portion of the design, assuming a 94% efficient second stage, are as follows: 5.1.1 108 VAC Vin(max) 305 VAC Vlink 460 V Po 115 W η 95% IAC and IFB Sense Resistors The rectified line voltage, VAC, and the output voltage of the PFC boost converter, Vlink, are scaled as currents by using sense resistors, whose values are estimated based on the equations below: V link – V dd [Eq.4] R FB = ---------------------------I ref R FB = 3.45MΩ DS904A7 [Eq.5] R AC = 3.45MΩ where Vin(min) 460 – 12 R FB = --------------------------–6 130 × 10 R AC = R FB RFB = Feedback resistor used to reflect the PFC output voltage RAC = Feedforward resistor used to reflect the rectified line voltage Vlink= PFC Output Voltage VDD = IC Supply Voltage Iref = Target reference current used for feedback 1% or lower tolerance resistors are recommended to maximize the tightly toleranced system behavior provided by the unique digital controller in the CS1600. Resistors may be separated into two or more series elements if voltage breakdown and/or regulatory compliance is of concern. 5.1.2 PFC Input Filter Capacitor For a typical 115 W PFC output stage required to power up a 108 W fluorescent ballast, an input filter capacitance of 0.33 μF is recommended. Capacitor tolerances and the value of the EMI filter capacitor need to be considered when selecting the value of the capacitor to be used in this application. 11 CS1600 5.1.3 PFC Boost Inductor Equation 3 can be rewritten to calculate the PFC boost Inductor, LB, as follows: V link 2 V link – -------------- × 90V × 2 V 400V 90V link α = -------------- × -------------------- × --------------------------------------------------------------------- [Eq.6] 400V V in ( min ) V link – V in ( min ) × 2 V link 2 V link – -------------- × 90V × 2 V 400V 90V link -------------------------------------------------------------------- = 0.937 ------------------------------α = × × 400V V in ( min ) – V in ( min ) × 2 V link 2 V link – ( V in ( min ) × 2 ) L B = α × η × ( V in ( min ) ) × --------------------------------------------------------2 × f max × P O × V link The minimum RMS current rating, IFET(rms), required for the FET is calculated as follows: PO [Eq.9] I FET ( rms ) = -----------------------------V in ( min ) × η 115 I LB ( rms ) = ---------------------------108 × 0.95 I LB ( rms ) = 1.12A 5.1.5 PFC Diode The PFC diode peak current is equal to the inductor peak current: [Eq.6] I D ( pk ) = I LB ( pk ) 2 ( 460 – 108 × 2 ) L B = 0.937 × 0.95× 108 × --------------------------------------------------------------= 431μH 3 2 × 70 × 10 × 115 × 460 I D ( pk ) = 3.17 A The PFC diode average current is calculated as follows: PO I D ( avg ) = ----------V link The RMS current rating for the inductor can be estimated as follows: PO I LB ( rms ) = -----------------------------V in ( min ) × η I LB ( rms ) [Eq.7] I D ( avg ) = 0.25 A 5.1.6 I LB ( rms ) = 1.12A The peak inductor current, ILB(pk), may be estimated using the following equation: I LB ( pk ) [Eq.8] 4 × 115 = ----------------------------------------0.95 × 108 × 2 I LB ( pk ) = 3.17 A Inductor tolerances should be considered when estimating the peak currents present in the application. The internal control algorithm of the controller dictates that the peak inductor current seen in the application could be as high as a pre-defined threshold of 0.001984 times the inverse of the inductor, which in this example amounts to 4.72 A. Care needs to be taken to ensure that the saturation current rating of the PFC boost inductor factors in this threshold used for the protection schemes. 5.1.4 PFC MOSFET The peak voltage stress on the PFC MOSFET is a diode drop above the output voltage. Accounting for leakage spikes, for the 460 V output application, a 600 V FET is recommended. The FET should be able to handle the same peak current as that seen through the inductor. This would amount to 3.17 A. 12 [Eq.11] 115 I D ( avg ) = ---------460 115 = ---------------------------108 × 0.95 4 × PO I LB ( pk ) = -------------------------------------------η × V in ( min ) × 2 [Eq.10] PFC Output Capacitor The output capacitor needs to be designed to meet the voltage ripple and hold-up time requirements. In the case of a costsensitive ballast application, the hold-up requirement is not a key requirement. The CS1600 has been designed to operate with a low output capacitance of approximately 0.2 μF per watt of output power. For this specific application: 0.2μF C out = ---------------- × 115W = 23μF W The 120 Hz ripple on the output capacitor may be estimated using the following equation: PO ΔV link ( rip ) = -----------------------------------------------------------------------2π × f line ( min ) × V link × C out [Eq.12] 115 = ------------------------------------------------2π × 45 × 460 × 23 = 40.2V where Cout = Output Capacitance value Po = Output Power fline(min) = Minimum Line Frequency Vlink = PFC Output Voltage ΔVlink = Peak-Peak Voltage Ripple on the PFC Output DS904A7 CS1600 The voltage rating on the capacitor needs to account for the operation of the device before it hits the overvoltage protection threshold. This is typically 105% of nominal value, which is DS904A7 483 V. With the ripple voltage factored in, 22 μF of capacitance rated at 500 V would suffice for this application. 13 CS1600 5.2 Bill of Materials (for Application Example shown in Figure 17) Designator R1a 1.5 MΩ R1b 1.5 MΩ R1c 1.5 MΩ R2a 1.5 MΩ R2b 1.5 MΩ R2c 1.5 MΩ R3 24.9Ω C1 0.47μF C2 4.7μF C3a C3b BR1 14 Value Description/Part Number 23.5μF 2 47μF, 250V caps in series 4A, 600V Bridge diode - GBU4J-BP D5 1 A, 600 1N4005 D6 3A, 600V MURS360 L1 420μH (max) Premier Magnetics TSD-2798 Renco RLCS-1002 Q1 9A, 600V FCP9N60N CS1600 - CS1600-FSZ DS904A7 CS1600 5.3 Summary of Equations Eq. # Equation 1, 4 V link – V DD R FB = ----------------------------I ref 2, 5 3, 6 R AC = R FB 2 V link – ( V in ( min ) × 2 ) P O = α × η × ( V in ( min ) ) × --------------------------------------------------------2 × f max × L B × V link 7 PO I LB ( rms ) = -----------------------------V in ( min ) × η 8 4 × PO I LB ( pk ) = -------------------------------------------η × V in ( min ) × 2 9 PO I FET ( rms ) = -----------------------------V in ( min ) × η 10 I D ( pk ) = I LB ( pk ) 11 PO I D ( avg ) = ----------V link 12 PO C out = --------------------------------------------------------------------------------------2π × f line ( min ) × V link × ΔV link ( rip ) DS904A7 15 CS1600 6. PACKAGE DRAWING 8L SOIC (150 MIL BODY) PACKAGE DRAWING E H 1 b c D SEATING PLANE ∝ A L e A1 INCHES DIM A A1 B C D E e H L ∝ MIN 0.053 0.004 0.013 0.007 0.189 0.150 0.040 0.228 0.016 0° MAX 0.069 0.010 0.020 0.010 0.197 0.157 0.060 0.244 0.050 8° MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.02 1.52 5.80 6.20 0.40 1.27 0° 8° JEDEC # : MS-012 16 DS904A7 CS1600 7. ORDERING INFORMATION Part # Temperature Range Package Description CS1600-FSZ -40 °C to +125 °C 8-lead SOIC, Lead (Pb) Free 8. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number Peak Reflow Temp MSL Ratinga Max Floor Lifeb CS1600-FSZ 260 °C 2 365 Days a. MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. b. Stored at 30 °C, 60% relative humidity. DS904A7 17 CS1600 9. REVISION HISTORY Revision Date Changes A1 OCT 2009 Initial Advance Information release. A2 MAR 2010 Revised feature list, product description and parametric table to reflect the C0 version of silicon. A3 MAR 2010 Revised to reflect the update in switching frequency and variation of frequency over line. A4 APR 2010 Revised parametric table and equations to reflect the C1 version of silicon. A5 MAY 2010 Updated with additional test bench data for EP level. A6 JUN 2010 Added RθJA and RθJC in electrical specifications section. A7 JUL 2010 Updated operating supply current, overpower protection recovery, output capacitance calculation. Added Figure 6. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com IMPORTANT NOTICE “Advance” product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. 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