ICS83052I Integrated Circuit Systems, Inc. 2:1, SINGLE-ENDED MULTIPLEXER TABLE 1. PIN DESCRIPTIONS Number Name 1 VDDO Power Type Description Output supply pin. 2 GND Power 3, 6 CLK1, CLK0 Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. Power supply ground. 4 VDD Power 5 OE Input 7 SEL0 Input 8 Q Output Core supply pin. Output enable. When LOW, outputs are in HIGH impedance state. Pullup When HIGH, outputs are active. LVCMOS / LVTTL interface levels. Clock select input. See Control Input Function Table. Pulldown LVCMOS / LVTTL interface levels. Single-ended clock output. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Test Conditions Minimum Typical Maximum Units Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ 18 pF Power Dissipation Capacitance (per output) VDDO = 3.465V CPD VDDO = 2.625V 19 pF VDDO = 1.89V 19 pF 15 Ω Output Impedance ROUT TABLE 3. CONTROL INPUT FUNCTION TABLE Control Inputs SEL0 0 1 83052AGI Input Selected to Q CLK0 CLK1 www.icst.com/products/hiperclocks.html 2 REV. A AUGUST 2, 2005 ICS83052I Integrated Circuit Systems, Inc. 2:1, SINGLE-ENDED MULTIPLEXER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 101.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 3.3V±5%, 2.5V±5% OR 1.8V±5%,TA = -40°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VDD Core Supply Voltage Test Conditions 3.135 3.3 3.465 V 3.135 3.3 3.465 V VDDO Output Supply Voltage 2.375 2. 5 2.625 V 1.6 1.8 2.0 V IDD Power Supply Current 40 mA IDDO Output Supply Current 5 mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V±5%, VDDO = 2.5V±5% OR 1.8V±5%, TA = -40°C TO 85°C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 2.375 2. 5 2.625 V 2.375 2. 5 2.625 V 1.6 1.8 2.0 V VDDO Output Supply Voltage IDD Power Supply Current 36 µA IDDO Output Supply Current 5 µA 83052AGI www.icst.com/products/hiperclocks.html 3 REV. A AUGUST 2, 2005 ICS83052I Integrated Circuit Systems, Inc. 2:1, SINGLE-ENDED MULTIPLEXER TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C Symbol VIH VIL IIH IIL VOH VOL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK0, CLK1, SEL0 OE CLK0, CLK1, SEL0 OE Output HighVoltage Output Low Voltage Test Conditions Minimum Maximum Units VDD = 3.3V ± 5% 2 Typical VDD + 0.3 V VDD = 2.5V ± 5% 1.7 VDD + 0.3 V VDD = 3.3V ± 5% -0.3 0.8 V VDD = 2.5V ± 5% -0.3 0.7 V VDD = 3.3V or 2.5V ± 5% 150 µA VDD = 3.3V or 2.5V ± 5% 5 µA VDD = 3.3V or 2.5V ± 5% -5 µA VDD = 3.3V or 2.5V ± 5% -150 µA VDDO = 3.3V ± 5%; NOTE 1 2.6 V VDDO = 2.5V ± 5%; NOTE 1 1.8 V VDDO = 1.8V ± 5%; NOTE 1 VDD - 0.3 V VDDO = 3.3V ± 5%; NOTE 1 0.5 V VDDO = 2.5V ± 5%; NOTE 1 0.45 V VDDO = 1.8V ± 5%; NOTE 1 0.35 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams. TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 4 tpLH tpHL t sk(i) t sk(pp) Test Conditions tR / tF Par t-to-Par t Skew; NOTE 2, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 Output Rise/Fall Time odc Output Duty Cycle t jit 155.52MHz, Integration Range: 12kHz - 20MHz 20% to 80% Minimum Typical Maximum Units 250 MHz 2.0 2.4 2.7 ns 2.0 2.5 2.9 ns 36 160 ps 490 ps 0.18 200 700 ps 45 55 % 45 MUXISOLATION MUX Isolation NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: Driving only one input clock. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 83052AGI www.icst.com/products/hiperclocks.html 4 ps dB REV. A AUGUST 2, 2005 ICS83052I Integrated Circuit Systems, Inc. 2:1, SINGLE-ENDED MULTIPLEXER TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 4 tpLH tpHL t sk(i) t sk(pp) Test Conditions tR / tF Par t-to-Par t Skew; NOTE 2, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 Output Rise/Fall Time odc Output Duty Cycle tjit Minimum 155.52MHz, Integration Range: 12kHz - 20MHz 20% to 80% Typical Maximum Units 250 MHz 2.3 2.6 2. 9 ns 2.3 2.6 2. 9 ns 23 106 ps 350 ps 0.14 ps 30 0 700 ps 46 54 % 45 MUXISOLATION MUX Isolation NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: Driving only one input clock. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. dB TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V ± 5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 4 tpLH tpHL t sk(i) t sk(pp) Test Conditions Typical Maximum Units 250 MHz 2.3 3.1 3.9 ns 2.3 3.1 3.9 ns 19 tR / tF Par t-to-Par t Skew; NOTE 2, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 Output Rise/Fall Time odc Output Duty Cycle t j it Minimum 155.52MHz, Integration Range: 12kHz - 20MHz 20% to 80% www.icst.com/products/hiperclocks.html 5 ps ps 0.16 ps 35 0 850 46 54 45 MUXISOLATION MUX Isolation NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: Driving only one input clock. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 83052AGI 66 350 ps % dB REV. A AUGUST 2, 2005 ICS83052I Integrated Circuit Systems, Inc. 2:1, SINGLE-ENDED MULTIPLEXER TABLE 5D. AC CHARACTERISTICS, VDD = VDDO = 2.5V ± 5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 4 tpLH tpHL t sk(i) t sk(pp) Test Conditions tR / tF Par t-to-Par t Skew; NOTE 2, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 Output Rise/Fall Time odc Output Duty Cycle t jit Minimum Typical Maximum Units 250 MHz 2.2 2.7 3.2 ns 2.2 2.7 3.2 ns 28 155.52MHz, Integration Range: 12kHz - 20MHz 20% to 80% 123 ps 400 ps 0.22 ps 30 0 700 45 55 45 MUXISOLATION MUX Isolation NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: Driving only one input clock. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. ps % dB TABLE 5E. AC CHARACTERISTICS, VDD = 2.5V ± 5%, VDDO = 1.8V ± 5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 4 tpLH tpHL t sk(i) t sk(pp) Test Conditions tR / tF Par t-to-Par t Skew; NOTE 2, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 3 Output Rise/Fall Time odc Output Duty Cycle t j it 155.52MHz, Integration Range: 12kHz - 20MHz 20% to 80% Minimum Typical Maximum Units 250 MHz 2.1 3.1 4.1 ns 2.1 3.1 4.2 ns 19 73 ps 350 ps 0.19 35 0 85 0 45 55 45 MUXISOLATION MUX Isolation NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: Driving only one input clock. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 83052AGI www.icst.com/products/hiperclocks.html 6 ps ps % dB REV. A AUGUST 2, 2005 ICS83052I Integrated Circuit Systems, Inc. 2:1, SINGLE-ENDED MULTIPLEXER ADDITIVE PHASE JITTER the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 -10 Additive Phase Jitter (Random) -20 at 155.52MHz (12kHz - 20MHz) = 0.18ps (typical) -30 -40 -50 SSB PHASE NOISE dBc/HZ -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated 83052AGI above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. www.icst.com/products/hiperclocks.html 7 REV. A AUGUST 2, 2005 ICS83052I Integrated Circuit Systems, Inc. 2:1, SINGLE-ENDED MULTIPLEXER PARAMETER MEASUREMENT INFORMATION 1.65V±5% 1.25V±5% SCOPE VDD, VDDO LVCMOS SCOPE VDD, VDDO Qx Qx LVCMOS GND GND -1.65V±5% -1.25V±5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 2.05V±5% 2.4±5% 1.25V±5% SCOPE V DD VDDO LVCMOS SCOPE V DD VDDO Qx Qx LVCMOS GND GND -0.9V±5% -1.25V±5% 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 1.6V±5% 0.9V±5% 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 0.9V±5% Part 1 SCOPE VDD VDDO LVCMOS Qx V DDO 2 Qx Part 2 GND Qy V DDO 2 tsk(pp) -0.9V±5% 2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 83052AGI PART-TO-PART SKEW www.icst.com/products/hiperclocks.html 8 REV. A AUGUST 2, 2005 ICS83052I Integrated Circuit Systems, Inc. 2:1, SINGLE-ENDED MULTIPLEXER VDD CLK0, CLK1 80% 80% tR tF 2 VDDO Clock Outputs 2 tpLH Q PROPAGATION DELAY 20% 20% OUTPUT RISE/FALL TIME CLKx V DDO 2 Q Q t PW tPD1 t odc = PERIOD t PW x 100% t PERIOD CLKy Q tPD2 tsk(i) = ⏐tPD1 – tPD1⏐ INPUT SKEW 83052AGI OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD www.icst.com/products/hiperclocks.html 9 REV. A AUGUST 2, 2005 ICS83052I Integrated Circuit Systems, Inc. 2:1, SINGLE-ENDED MULTIPLEXER APPLICATION INFORMATION RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W TRANSISTOR COUNT The transistor count for ICS83052I is: 967 83052AGI www.icst.com/products/hiperclocks.html 10 REV. A AUGUST 2, 2005 ICS83052I Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX 2:1, SINGLE-ENDED MULTIPLEXER FOR 8 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 8 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 83052AGI www.icst.com/products/hiperclocks.html 11 REV. A AUGUST 2, 2005 ICS83052I Integrated Circuit Systems, Inc. 2:1, SINGLE-ENDED MULTIPLEXER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS83052AGI 052AI 8 lead TSSOP tube -40°C to 85°C ICS83052AGIT 052AI 8 lead TSSOP 2500 tape & reel -40°C to 85°C ICS83052AGILF TBD 8 lead "Lead-Free" TSSOP tube -40°C to 85°C ICS83052AGILFT TB D 8 lead "Lead-Free" TSSOP 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83052AGI www.icst.com/products/hiperclocks.html 12 REV. A AUGUST 2, 2005 WWW.ALLDATASHEET.COM Copyright © Each Manufacturing Company. All Datasheets cannot be modified without permission. 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