DS90LV047A www.ti.com SNLS044C – MAY 2000 – REVISED APRIL 2013 DS90LV047A 3V LVDS Quad CMOS Differential Line Driver Check for Samples: DS90LV047A FEATURES DESCRIPTION • • • • • • • • • • The DS90LV047A is a quad CMOS flow-through differential line driver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. 1 2 • • • >400 Mbps (200 MHz) Switching Rates Flow-Through Pinout Simplifies PCB Layout 300 ps Typical Differential Skew 400 ps Maximum Differential Skew 1.7 ns Maximum Propagation Delay 3.3V Power Supply Design ±350 mV Differential Signaling Low Power Dissipation (13mW at 3.3V Static) Interoperable with Existing 5V LVDS Receivers High impedance on LVDS Outputs on Power Down Conforms to TIA/EIA-644 LVDS Standard Industrial Operating Temperature Range (−40°C to +85°C) Available in Surface Mount (SOIC) and Low Profile TSSOP Package The DS90LV047A accepts low voltage TTL/CMOS input levels and translates them to low voltage (350 mV) differential output signals. In addition, the driver supports a TRI-STATE function that may be used to disable the output stage, disabling the load current, and thus dropping the device to an ultra low idle power state of 13 mW typical. The DS90LV047A has a flow-through pinout for easy PCB layout. The EN and EN* inputs are ANDed together and control the TRI-STATE outputs. The enables are common to all four drivers. The DS90LV047A and companion line receiver (DS90LV048A) provide a new alternative to high power psuedo-ECL devices for high speed point-to-point interface applications. Connection Diagram Figure 1. Order Number DS90LV047ATM, DS90LV047ATMTC D0016A, PW0016A Packages Truth Table ENABLES INPUT OUTPUTS EN EN* DIN DOUT+ DOUT− H L or Open L L H H H L X Z Z All other combinations of ENABLE inputs 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2013, Texas Instruments Incorporated DS90LV047A SNLS044C – MAY 2000 – REVISED APRIL 2013 www.ti.com Functional Diagram These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) −0.3V to +4V Supply Voltage (VCC) Input Voltage (DIN) −0.3V to (VCC + 0.3V) Enable Input Voltage (EN, EN*) −0.3V to (VCC + 0.3V) −0.3V to +3.9V Output Voltage (DOUT+, DOUT−) Short Circuit Duration (DOUT+, DOUT−) Continuous D0016A Package Maximum Package Power Dissipation @ +25°C 1088 mW PW0016A Package 866 mW Derate D0016A Package 8.5 mW/°C above +25°C Derate PW0016A Package 6.9 mW/°C above +25°C −65°C to +150°C Storage Temperature Range Lead Temperature Range Soldering (4 sec.) +260°C (HBM, 1.5 kΩ, 100 pF) ≥ 10 kV Maximum Junction Temperature ESD Rating (2) (1) (2) +150°C (EIAJ, 0 Ω, 200 pF) ≥ 1200 V “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the devices should be operated at these limits. Electrical Characteristics specifies conditions of device operation. ESD Ratings: HBM (1.5 kΩ, 100 pF) ≥ 10 kV EIAJ (0 Ω, 200 pF) ≥ 1200 V Recommended Operating Conditions Min Typ Max Supply Voltage (VCC) +3.0 +3.3 +3.6 V Operating Free Air Temperature (TA) −40 +25 +85 °C 2 Submit Documentation Feedback Units Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90LV047A DS90LV047A www.ti.com SNLS044C – MAY 2000 – REVISED APRIL 2013 Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified (1) (2) (3) Symbol Parameter Conditions VOD1 Differential Output Voltage ΔVOD1 Change in Magnitude of VOD1 for Complementary Output States VOS Offset Voltage ΔVOS Change in Magnitude of VOS for Complementary Output States VOH Output High Voltage VOL Output Low Voltage VIH Input High Voltage VIL Input Low Voltage IIH Input High Current VIN = VCC or 2.5V IIL Input Low Current VIN = GND or 0.4V VCL Input Clamp Voltage ICL = −18 mA IOS Output Short Circuit Current (4) ENABLED, DIN = VCC, DOUT+ = 0V or DIN = GND, DOUT− = 0V IOSD Differential Output Short Circuit Current (4) ENABLED, VOD = 0V IOFF Power-off Leakage VOUT = 0V or 3.6V, VCC = 0V or Open IOZ Output TRI-STATE Current EN = 0.8V and EN* = 2.0V VOUT = 0V or VCC ICC No Load Supply current Drivers Enabled DIN = VCC or GND ICCL Loaded Supply Current Drivers Enabled ICCZ No Load Supply Current Drivers Disabled (1) (2) (3) (4) RL = 100Ω (Figure 2) Pin Min Typ Max DOUT− DOUT+ 250 310 450 mV 1 35 |mV| 1.17 1.375 V 1 25 |mV| 1.33 1.6 V 1.125 0.90 DIN, EN, EN* Units 1.02 V 2.0 VCC GND 0.8 V 2 +10 μA −10 −2 +10 μA −1.5 −0.8 −4.2 −9.0 mA −4.2 −9.0 mA −20 ±1 +20 μA −10 ±1 +10 μA 4.0 8.0 mA RL = 100Ω All Channels, DIN = VCC or GND (all inputs) 20 30 mA DIN = VCC or GND, EN = GND, EN* = VCC 2.2 6.0 mA −10 DOUT− DOUT+ VCC V V Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except: VOD1 and ΔVOD1. All typicals are given for: VCC = +3.3V, TA = +25°C. The DS90LV047A is a current mode device and only functions within datasheet specifications when a resistive load is applied to the driver outputs typical range is (90Ω to 110Ω). Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90LV047A 3 DS90LV047A SNLS044C – MAY 2000 – REVISED APRIL 2013 www.ti.com Switching Characteristics VCC = +3.3V ± 10%, TA = −40°C to +85°C (1) (2) (3) Symbol Parameter Conditions RL = 100Ω, CL = 15 pF (Figure 3 and Figure 4) Min Typ Max Units 0.5 0.9 1.7 ns 0.5 1.2 1.7 ns tPHLD Differential Propagation Delay High to Low tPLHD Differential Propagation Delay Low to High tSKD1 Differential Pulse Skew |tPHLD − tPLHD| (4) 0 0.3 0.4 ns tSKD2 Channel-to-Channel Skew (5) 0 0.4 0.5 ns tSKD3 Differential Part to Part Skew (6) 0 1.0 ns tSKD4 Differential Part to Part Skew (7) 0 1.2 ns tTLH Rise Time 0.5 1.5 ns tTHL Fall Time 0.5 1.5 ns tPHZ Disable Time High to Z 2 5 ns tPLZ Disable Time Low to Z 2 5 ns tPZH Enable Time Z to High 3 7 ns tPZL Enable Time Z to Low 3 7 fMAX Maximum Operating Frequency (8) (1) (2) (3) (4) (5) (6) (7) (8) RL = 100Ω, CL = 15 pF (Figure 5 and Figure 6) 200 250 ns MHz All typicals are given for: VCC = +3.3V, TA = +25°C. Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr ≤ 1 ns, and tf ≤ 1 ns. CL includes probe and jig capacitance. tSKD1 |tPHLD − tPLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. tSKD2 is the Differential Channel-to-Channel Skew of any event on the same device. tSKD3, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay. fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0V to 3V. Output Criteria: duty cycle = 45%/55%, VOD > 250mV, all channels switching. Parameter Measurement Information Figure 2. Driver VOD and VOS Test Circuit Figure 3. Driver Propagation Delay and Transition Time Test Circuit 4 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90LV047A DS90LV047A www.ti.com SNLS044C – MAY 2000 – REVISED APRIL 2013 Parameter Measurement Information (continued) Figure 4. Driver Propagation Delay and Transition Time Waveforms Figure 5. Driver TRI-STATE Delay Test Circuit Figure 6. Driver TRI-STATE Delay Waveform Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90LV047A 5 DS90LV047A SNLS044C – MAY 2000 – REVISED APRIL 2013 www.ti.com Typical Application Figure 7. Point-to-Point Application APPLICATION INFORMATION General application guidelines and hints for LVDS drivers and receivers may be found in the following application notes: LVDS Owner's Manual (lit #550062-001), AN808, AN977, AN971, AN916, AN805, AN903. LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 7. This configuration provides a clean signaling environment for the fast edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic differential impedance of the media is in the range of 100Ω. A termination resistor of 100Ω (selected to match the media), and is located as close to the receiver input pins as possible. The termination resistor converts the driver output current (current mode) into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. The DS90LV047A differential line driver is a balanced current source design. A current mode driver, generally speaking has a high output impedance and supplies a constant current for a range of loads (a voltage mode driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in one direction to produce a logic state and in the other direction to produce the other logic state. The output current is typically 3.1 mA, a minimum of 2.5 mA, and a maximum of 4.5 mA. The current mode driver requires (as discussed above) that a resistive termination be employed to terminate the signal and to complete the loop as shown in Figure 7. AC or unterminated configurations are not allowed. The 3.1 mA loop current will develop a differential voltage of 310mV across the 100Ω termination resistor which the receiver detects with a 250mV minimum differential noise margin, (driven signal minus receiver threshold (250mV – 100mV = 150mV)). The signal is centered around +1.2V (Driver Offset, VOS) with respect to ground as shown in Figure 8. Note that the steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage (VOD) and is typically 620mV. The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver increases exponentially in most case between 20 MHz–50 MHz. This is due to the overlap current that flows between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed current between its output without any substantial overlap current. This is similar to some ECL and PECL devices, but without the heavy static ICC requirements of the ECL/PECL designs. LVDS requires > 80% less current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing RS-422 drivers. The TRI-STATE function allows the driver outputs to be disabled, thus obtaining an even lower power state when the transmission of data is not required. The DS90LV047A has a flow-through pinout that allows for easy PCB layout. The LVDS signals on one side of the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and the receiver as well as allowing the trace lines to be close together to couple noise as common-mode. Noise isolation is achieved with the LVDS signals on one side of the device and the TTL signals on the other side. 6 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90LV047A DS90LV047A www.ti.com SNLS044C – MAY 2000 – REVISED APRIL 2013 POWER DECOUPLING RECOMMENDATIONS Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended) 0.1μF and 0.001μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple vias should be used to connect the decoupling capacitors to the power planes. A 10μF (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply and ground. PC BOARD CONSIDERATIONS Use at least 4 PCB layers (top to bottom); LVDS signals, ground, power, TTL signals. Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s). Keep drivers and receivers as close to the (LVDS port side) connectors as possible. DIFFERENTIAL TRACES Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as common-mode. In fact, we have seen that differential signals which are 1mm apart radiate far less noise than traces 3mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI will result. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match differential impedance and provide isolation for the differential lines. Minimize the number or vias and other discontinuities on the line. Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels. Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. Minor violations at connection points are allowable. TERMINATION Use a termination resistor which best matches the differential impedance or your transmission line. The resistor should be between 90Ω and 130Ω. Remember that the current mode outputs need the termination resistor to generate the differential voltage. LVDS will not work without resistor termination. Typically, connecting a single resistor across the pair at the receiver end will suffice. Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination to the receiver inputs should be minimized. The distance between the termination resistor and the receiver should be < 10mm (12mm MAX). PROBING LVDS TRANSMISSION LINES Always use high impedance (> 100kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz) scope. Improper probing will give deceiving results. CABLES AND CONNECTORS, GENERAL COMMENTS When choosing cable and connectors for LVDS it is important to remember: Use controlled impedance media. The cables and connectors you use should have a matched differential impedance of about 100Ω. They should not introduce major impedance discontinuities. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90LV047A 7 DS90LV047A SNLS044C – MAY 2000 – REVISED APRIL 2013 www.ti.com Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax.) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by the receiver. For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M ≤ d ≤ 10M, CAT 3 (category 3) twisted pair cable works well, is readily available and relatively inexpensive. LVDS FAIL-SAFE This section addresses the common concern of fail-safe biasing of LVDS interconnects, specifically looking at the DS90LV047A driver outputs and the DS90LV048A receiver inputs. The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. The receiver's internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs. 1. Open Input Pins. The DS90LV048A is a quad receiver device, and if an application requires only 1, 2 or 3 receivers, the unused channel(s) inputs should be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by internal high value pull up and pull down resistors to set the output to a HIGH state. This internal circuitry will ensure a HIGH, stable output state for open inputs. 2. Terminated Input. If the DS90LV047A driver is disconnected (cable unplugged), or if the DS90LV047A driver is in a TRI-STATE or power-off condition, the receiver output will again be in a HIGH state, even with the end of cable 100Ω termination resistor across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable picks up more than 10mV of differential noise, the receiver may see the noise as a valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced interconnect should be used. Twisted pair cable will offer better balance than flat ribbon cable. 3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V differential input voltage, the receiver output will remain in a HIGH state. Shorted input fail-safe is not supported across the common-mode range of the device (GND to 2.4V). It is only supported with inputs shorted and no external common-mode voltage applied. External lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the presence of higher noise levels. The pull up and pull down resistors should be in the 5kΩ to 15kΩ range to minimize loading and waveform distortion to the driver. The common-mode bias point should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry. Figure 8. Driver Output Levels 8 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90LV047A DS90LV047A www.ti.com SNLS044C – MAY 2000 – REVISED APRIL 2013 PIN DESCRIPTIONS Pin No. Name Description 2, 3, 6, 7 DIN 10, 11, 14, 15 DOUT+ Driver input pin, TTL/CMOS compatible Non-inverting driver output pin, LVDS levels 9, 12, 13, 16 DOUT− Inverting driver output pin, LVDS levels 1 EN Driver enable pin: When EN is low, the driver is disabled. When EN is high and EN* is low or open, the driver is enabled. If both EN and EN* are open circuit, then the driver is disabled. 8 EN* Driver enable pin: When EN* is high, the driver is disabled. When EN* is low or open and EN is high, the driver is enabled. If both EN and EN* are open circuit, then the driver is disabled. 4 VCC Power supply pin, +3.3V ± 0.3V 5 GND Ground pin Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90LV047A 9 DS90LV047A SNLS044C – MAY 2000 – REVISED APRIL 2013 www.ti.com Typical Performance Curves 10 Figure 9. Output High Voltage vs Power Supply Voltage Figure 10. Output Low Voltage vs Power Supply Voltage Figure 11. Output Short Circuit Current vs Power Supply Voltage Figure 12. Output TRI-STATE Current vs Power Supply Voltage Figure 13. Differential Output Voltage vs Power Supply Voltage Figure 14. Differential Output Voltage vs Load Resistor Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90LV047A DS90LV047A www.ti.com SNLS044C – MAY 2000 – REVISED APRIL 2013 Typical Performance Curves (continued) Figure 15. Offset Voltage vs Power Suppy Voltage Figure 16. Power Supply Current vs Frequency Figure 17. Power Supply Current vs Power Supply Voltage Figure 18. Power Supply Current vs Ambient Temperature Figure 19. Differential Propagation Delay vs Power Supply Voltage Figure 20. Differential Propagation Delay vs Ambient Temperature Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90LV047A 11 DS90LV047A SNLS044C – MAY 2000 – REVISED APRIL 2013 www.ti.com Typical Performance Curves (continued) Figure 21. Differential Skew vs Power Supply Voltage Figure 22. Differential Skew vs Ambient Temperature Figure 23. Transition Time vs Power Supply Voltage Figure 24. Transition Time vs Ambient Temperature Figure 25. Data Rate vs Cable Length 12 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90LV047A DS90LV047A www.ti.com SNLS044C – MAY 2000 – REVISED APRIL 2013 Data Rate vs Cable Length Graph Test Procedure A pseudo-random bit sequence (PRBS) of 29−1 bits was programmed into a function generator (Tektronix HFS9009) and connected to the driver inputs via 50Ω cables and SMB connectors. An oscilloscope (Tektronix 11801B) was used to probe the resulting eye pattern, measured differentially at the input to the receiver. A 100Ω resistor was used to terminate the pair at the far end of the cable. The measurements were taken at the far end of the cable, at the receiver"s input, and used for the jitter analysis for this graph (Figure 25). The frequency of the input signal was increased until the measured jitter (ttcs) equaled 20% with respect to the unit interval (ttui) for the particular cable length under test. Twenty percent jitter is a reasonable place to start with many system designs. The data used was NRZ. Jitter was measured at the 0V differential voltage of the differential eye pattern. The cables used were LG UTP 4 pair 24 gauge CAT 5 cables. The DS90LV047A and DS90LV048A were tested using the new LVDS Flow-Evaluation Board LVDS47/48PCB which is available in the LVDS47/48EVK evaluation kit. The curve shows very good typical performance that can be used as a design guideline for data rate vs cable length. Increasing the jitter percentage increases the curve respectively, allowing the device to transmit faster over longer cable lengths. This relaxes the jitter tolerance of the system allowing more jitter into the system, which could reduce the reliability and efficiency of the system. Alternatively, decreasing the jitter percentage will have the opposite effect on the system. The area under the curve is considered the safe operating area based on the above signal quality criteria. For more information on eye pattern testing, please see TI Application Note AN-808. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90LV047A 13 DS90LV047A SNLS044C – MAY 2000 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision B (April 2013) to Revision C • 14 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 13 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: DS90LV047A PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DS90LV047ATM NRND SOIC D 16 48 TBD Call TI Call TI -40 to 85 DS90LV047A TM DS90LV047ATM/NOPB ACTIVE SOIC D 16 48 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS90LV047A TM DS90LV047ATMTC NRND TSSOP PW 16 92 TBD Call TI Call TI -40 to 85 DS90LV 047AT DS90LV047ATMTC/NOPB ACTIVE TSSOP PW 16 92 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS90LV 047AT DS90LV047ATMTCX NRND TSSOP PW 16 2500 TBD Call TI Call TI -40 to 85 DS90LV 047AT DS90LV047ATMTCX/NOPB ACTIVE TSSOP PW 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS90LV 047AT DS90LV047ATMX/NOPB ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS90LV047A TM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS90LV047ATMTCX TSSOP PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 DS90LV047ATMX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90LV047ATMTCX TSSOP PW 16 2500 367.0 367.0 35.0 DS90LV047ATMX/NOPB SOIC D 16 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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