DS90LV032AQML DS90LV032AQML 3V LVDS Quad CMOS Differential Line Receiver Literature Number: SNLS205 DS90LV032AQML 3V LVDS Quad CMOS Differential Line Receiver General Description Features The DS90LV032A is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The DS90LV032A accepts low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The receiver supports a TRI-STATE® function that may be used to multiplex outputs. The DS90LV032A and companion LVDS line driver (eg. DS90LV031A) provide a new alternative to high power PECL/ ECL devices for high speed point-to-point interface applications. In addition, the DS90LV032A provides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present. ■ ■ ■ ■ ■ ■ ■ ■ ■ Low chip to chip skew Low differential skew High impedance LVDS inputs with power-off Low power dissipation Accepts small swing (330 mV) differential signal levels. Compatible with ANSI/TIA/EIA-644 Operating temperature range (-55°C to +85°C) Pin compatible with DS90C032A and DS26C32A. Typical Rise/Fall time is 350pS. Ordering Information NS Part Number SMD Part Number DS90LV032AW-QML 5962–9865201QFA NS Package Number W16A DS90LV032AWGQML 5962–9865201QXA WG16A DS90LV032AW-MLS W16A DS90LV032AWGMLS WG16A DS90LV032 MDS (Note 10) Connection Diagram Package Description 16LD Ceramic Flatpack 16LD Ceramic SOIC 16LD Ceramic Flatpack 16LD Ceramic SOIC BARE DIE Functional Diagram Dual-in-Line Pictured 20163901 See NS Package Number W16A or WG16A 20163902 TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2011 Texas Instruments Incorporated 201639 www.ti.com DS90LV032AQML 3V LVDS Quad CMOS Differential Line Receiver November 15, 2011 DS90LV032AQML Absolute Maximum Ratings (Note 1) Supply Voltage (VCC) Input Voltage (RI+, RI−) Enable Input Voltage (En, En*) Output Voltage (RO) Storage Temperature Range −0.3V to +4V −0.3V to +3.9V −0.3V to (VCC + 0.3V) −0.3V to (VCC + 0.3V) −65°C ≤ TA ≤ +150°C +260°C Lead Temperature Range (Soldering 4 sec.) Maximum Package Power Dissipation @ +25°C (Note 2) W Package WG Package Thermal Resistance 845 mW 845 mW θJA W Package WG Package 148°C/W 148°C/W θJC W Package WG Package Maximum Junction Temperature ESD Rating (Note 3) 21°C/W 21°C/W +150°C 4.5 KV Recommended Operating Conditions Min +3.15 Gnd −55 Supply Voltage (VCC) Receiver Input Voltage Operating Free Air Temperature (TA) Max +3.45 +3.0 +85 Unit V V °C Quality Conformance Inspection Mil-Std-883, Method 5005 - Group A www.ti.com Subgroup Description Temp °C 1 Static tests at +25 2 Static tests at +125 3 Static tests at -55 4 Dynamic tests at +25 5 Dynamic tests at +125 6 Dynamic tests at -55 7 Functional tests at +25 8A Functional tests at +125 8B Functional tests at -55 9 Switching tests at +25 10 Switching tests at +125 11 Switching tests at -55 12 Settling time at +25 13 Settling time at +125 14 Settling time at -55 2 DC Parameters The following conditions apply, unless otherwise specified. Over supply voltage range of 3.15V to 3.45V and operating temperature of −55°C to +85°C. Symbol Parameter Conditions Notes Min -100 VTL Differential Input Low Threshold VCM = +1.2V (Note 4) VTh Differential Input High Threshold VCM = +1.2V (Note 4) VCMR Common Mode Voltage Range VID = 200mV peak to peak (Note 4), (Note 6) II Input Current VOH Output High Voltage Subgroups mV 1, 2, 3 mV 1, 2, 3 2.3 V 1, 2, 3 VCC = 3.45V or 0V, VI = 2.8V or 0V ±10 µA 1, 2, 3 VCC = 0V, VI = 3.45V ±20 µA 1, 2, 3 0.1 IOH = -0.4 mA, VID = 200mV 2.7 V 1, 2, 3 IOH = -0.4 mA, Inputs Open 2.7 V 1, 2, 3 Output Low Voltage IOL = 2 mA, VID = -200mV IOS Output Short Circuit Current Enabled, VO = 0V IOZ Output TRI-STATE Current Disabled, VO = 0V or VCC VIH Input High Voltage VIL Input Low Voltage IL Input Current VI = VCC or 0V, Other Input = VCC or Gnd VCl Input Clamp Voltage ICl = -18mA ICC No Load Supply Current Receivers Enabled En, En* = VCC or Gnd, Inputs Open No Load Supply Current Receivers Disabled Units 100 VOL ICCZ Max 0.25 V 1, 2, 3 (Note 8) -15 -120 mA 1, 2, 3 ±10 µA 1, 2, 3 (Note 9) 2.0 VCC V 1, 2, 3 (Note 9) Gnd 0.8 V 1, 2, 3 ±10 µA 1, 2, 3 -1.5 V 1, 2, 3 15 mA 1, 2, 3 En, En* = 2.4 or 0.5, Inputs Open 15 mA 1, 2, 3 En = Gnd, En* = VCC , Inputs Open 5.0 mA 1, 2, 3 AC Parameters The following conditions apply, unless otherwise specified. AC: VCC = 3.15 / 3.3 / 3.45V, CL = 20pF Symbol Parameter Conditions Notes Min Max Units Subgroups tPHLD Differential Propagation Delay High to Low VID = 200mV, Input pulse = 1.1V to 1.3V, VI = 1.2V (0V differential) to VO = 1/2 VCC Fig 1 & 2 0.5 3.5 ns 9, 10, 11 tPLHD Differential Propagation Delay Low to High VID = 200mV, Input pulse = 1.1V to 1.3V, VI = 1.2V (0V differential) to VO = 1/2 VCC Fig 1 & 2 0.5 3.5 ns 9, 10, 11 tSkD Differential Skew |tPHLD - tPLHD| CL = 20pF, VID = 200mV Fig 1 & 2 1.5 ns 9, 10, 11 tSk1 Channel to Channel Skew CL = 20pF, VID = 200mV (Note 7) 1.75 ns 9, 10, 11 tSk2 Chip to Chip Skew CL = 20pF, VID = 200mV (Note 5) 3.0 ns 9, 10, 11 tPLZ Disable Time Low to Z Input pulse = 0V to 3.0V, VI = 1.5V, VO = VOL+0.5V, Fig 3 & 4 12 ns 9, 10, 11 RL= 1kΩ. 3 www.ti.com DS90LV032AQML DS90LV032A Electrical Characteristics DS90LV032AQML Symbol Parameter Conditions tPHZ Disable Time High to Z Input pulse = 0V to 3.0V, VI = 1.5V, VO = VOH-0.5V, tPZH Enable Time Z to High Input pulse = 0V to 3.0V, VI = 1.5V, VO = 50%, Max Units Subgroups Fig 3 & 4 12 ns 9, 10, 11 Fig 3 & 4 20 ns 9, 10, 11 Fig 3 & 4 20 ns 9, 10, 11 Notes Min RL = 1kΩ. RL = 1kΩ. tPZL Enable Time Z to Low Input pulse = 0V to 3.0V, VI = 1.5V, VO = 50%, RL = 1kΩ. Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: Derate @ 6.8mW/°C Note 3: Human body model, 1.5 kΩ in series with 100 pF. Note 4: Tested during VOH/VOL tests by applying appropriate voltage levels to the input pins of the device under test. Note 5: Chip to chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays. Note 6: The VCMR range is reduced for larger VID. Example: if VID = 400mV, the VCMR is 0.2V to 2.2V. The fail-safe condition with inputs shorted is valid over a common-mode range of 0V to 2.3V. A VID up to VCC − 0V may be applied to the RIN+/ RI− inputs with the Common-Mode voltage set to VCC/2. Propagation delay and Differential Pulse skew decrease when VID is increased from 200mV to 400mV. Skew specifications apply for 200mV ≤ VID ≤ 800mV over the commonmode range . Note 7: Channel-to-Channel Skew, is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any event on the inputs. Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed maximum junction temperature. Note 9: Tested during IOZ tests by applying appropriate threshold voltage levels to the En and En* pins. Note 10: FOR ADDITIONAL DIE INFORMATION, PLEASE VISIT THE HI REL WEB SITE AT: www.national.com/analog/space/level_die Parameter Measurement Information 20163903 FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit 20163904 FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms www.ti.com 4 DS90LV032AQML 20163905 CL includes load and test jig capacitance. S1 = VCC for tPZL, and tPLZ measurements. S1 = Gnd for tPZH and tPHZ measurements. FIGURE 3. Receiver TRI-STATE Delay Test Circuit 20163906 FIGURE 4. Receiver TRI-STATE Delay Waveforms Typical Performance Characteristics 20163909 20163908 FIGURE 6. Typical Common-Mode Range variation with respect to amplitude of differential input FIGURE 5. ICC vs Frequency, four channels switching 5 www.ti.com DS90LV032AQML 20163910 20163911 FIGURE 7. Typical Pulse Skew variation versus commonmode voltage FIGURE 8. Variation in High to Low Propagation Delay versus VCM 20163912 FIGURE 9. Variation in Low to High Propagation Delay versus VCM Typical Application Balanced System 20163907 FIGURE 10. Point-to-Point Application www.ti.com 6 General application guidelines and hints for LVDS drivers and receivers may be found in the following application notes: www.national.com/lvds. LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 10. This configuration provides a clean signaling environment for the fast edge rates of the drivers . The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to the receiver input pins as possible. The termination resistor converts the driver output (current mode) into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. The DS90LV032A differential line receiver is capable of detecting signals as low as 100 mV, over a ±1V common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting may be the result of a ground potential difference between the driver's ground reference and the receiver's ground reference, the common-mode effects of coupled noise, or a combination of the two. Both receiver input pins have a recommended operating input voltage range of 0V to +2.4V (measured from each pin to ground), exceeding these limits may turn on the ESD protection circuitry which will clamp the bus voltages. TERMINATION Use a resistor which best matches the differential impedance of your transmission line. The resistor should be between 90Ω and 130Ω. Remember that the current mode outputs need the termination resistor to generate the differential voltage. LVDS will not work without resistor termination. Typically, connect a single resistor across the pair at the receiver end. Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination to the receiver inputs should be minimized. The distance between the termination resistor and the receiver should be <10mm (12mm MAX) PROBING LVDS TRANSMISSION LINES Always use high impedance (> 100kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz) scope. Improper probing will give deceiving results. POWER DECOUPLING RECOMMENDATIONS Bypass capacitors must be used on power pins. High frequency ceramic (surface mount is recommended) 0.1μF in parallel with 0.01μF, in parallel with 0.001μF at the power supply pin as well as scattered capacitors over the printed circuit board. Multiple vias should be used to connect the decoupling capacitors to the power planes A 10μF (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board. CABLES AND CONNECTORS, GENERAL COMMENTS When choosing cable and connectors for LVDS it is important to remember: Use controlled impedance media. The cables and connectors you use should have a matched differential impedance of about 100Ω. They should not introduce major impedance discontinuities. Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax.) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation as common-mode (not differential mode) noise which is rejected by the receiver. For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M ≤ d ≤ 10M, CAT 3 (category 3) twisted pair cable works well, is readily available and relatively inexpensive. PC BOARD CONSIDERATIONS Use at least 4 PCB layers (top to bottom); LVDS signals, ground, power, TTL signals. Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s). Keep drivers and receivers as close to the (LVDS port side) connectors as possible. DIFFERENTIAL TRACES Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as common-mode. Lab experiments show that differential signals which are 1mm apart radiate far less noise than traces 3mm apart since magnetic field cancellation is much better with the closer traces. Plus, FAIL-SAFE FEATURE The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. The receiver's internal fail-safe circuitry is designed to source/ sink a small amount of current, providing fail-safe protection 7 www.ti.com DS90LV032AQML noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI will result. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match differential impedance and provide isolation for the differential lines. Minimize the number of vias and other discontinuities on the line. Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels. Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. Minor violations at connection points are allowable. Applications Information DS90LV032AQML (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs. 1. Open Input Pins. The DS90LV032A is a quad receiver device, and if an application requires only 1, 2 or 3 receivers, the unused channel(s) inputs should be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by internal high value pull up and pull down resistors to set the output to a HIGH state. This internal circuitry will guarantee a HIGH, stable output state for open inputs. 2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a TRI-STATE or poweroff condition, the receiver output will again be in a HIGH state, even with the end of cable 100Ω termination resistor across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable picks up more than 10mV of differential noise, the receiver may see the noise as a valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced interconnect should be used. Twisted pair cable will offer better balance than flat ribbon cable. 3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V differential input voltage, the receiver output will remain in a HIGH state. Shorted input fail-safe is not supported across the common-mode range of the device (GND to 2.4V). It is only supported with inputs shorted and no external common-mode voltage applied. External lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the presence of higher noise levels. The pull up and pull down resistors should be in the 5kΩ to 15kΩ range to minimize loading and waveform distortion to the driver. The common-mode bias point should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry. The footprint of the DS90LV032A is the same as the industry standard 26LS32 Quad Differential (RS-422) Receiver. Pin Descriptions Pin No. Name 2, 6, Description RI+ Non-inverting receiver input pin RI− Inverting receiver input pin RO Receiver output pin 4 En Active high enable pin, OR-ed with En* 12 En* Active low enable pin, OR-ed with En 16 VCC Power supply pin, +3.3V ± 0.3V 8 Gnd Ground pin 10, 14 1, 7, 9, 15 3, 5, 11, 13 Truth Table INPUTS OUTPUT En ENABLES En* RI+ − RI− RO L H X Z VID ≥ 0.1V H VID ≤ −0.1V L Full Fail-safe Open/Short or Terminated H All other combinations of enable inputs www.ti.com 8 Released 15–Nov-2011 Revision Section Originator A New Release, Corporate format L. Lytle B Ordering Information, Quality Conformance Inspection, AC Parameters, Applications Information 9 K. Kruckmeyer Changes 1 MDS data sheet converted into one Corp. data sheet format. MNDS90LV032A-X Rev 0D0 will be archived. Addeded Part Numbers DS90LV032AWGMLS and DS90LV032AWMLS along with DS90LV032 MDS and associated footnote reference to Ordering Information. Added missing '+' sign on the Temp's for 25 and 125 deg C from QCI section. For AC Parameters changed units from nS to ns, changed 1K to 1k and added Fig 1, 2, 3 and 4 as needed for notes. Added Note 10 for die sales. For Application Information change minor typo errors under several sections. Revision A will be archived. www.ti.com DS90LV032AQML Revision History Section DS90LV032AQML Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Ceramic Flatpack NS Package Number W16A 16-Lead Ceramic SOIC NS Package Number WG16A www.ti.com 10 DS90LV032AQML Notes 11 www.ti.com DS90LV032AQML 3V LVDS Quad CMOS Differential Line Receiver Notes TI/NATIONAL INTERIM IMPORTANT NOTICE Texas Instruments has purchased National Semiconductor. As of Monday, September 26th, and until further notice, products sold or advertised under the National Semiconductor name or logo, and information, support and interactions concerning such products, remain subject to the preexisting National Semiconductor standard terms and conditions of sale, terms of use of website, and Notices (and/or terms previously agreed in writing with National Semiconductor, where applicable) and are not subject to any differing terms and notices applicable to other TI components, sales or websites. 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