LM3401 www.ti.com SNVS516C – AUGUST 2007 – REVISED MAY 2013 LM3401 Hysteretic PFET Controller for High Power LED Drive Check for Samples: LM3401 FEATURES DESCRIPTION • • • • • • The LM3401 is a switching controller designed to provide constant current to high power LEDs. The LM3401 drives an external P-MOSFET switch for step-down (Buck) regulators. The LM3401 delivers constant current within ±6% accuracy to a wide variety and number of series connected LEDs. Output current is adjusted with an external current sensing resistor to drive high power LEDs in excess of 1A. 1 2 • • • • Hysteretic Control for Speed and Simplicity Input Operating Range of 4.5V-35V 1.5MHz Maximum Switching Frequency Low 200mV Reference Voltage Programmable Current Limit High speed CMOS Compatible Enable/Dimming Adjustable Hysteresis Input UVLO No output Capacitor Required 8-pin VSSOP Package For improved accuracy and efficiency, the LM3401 features dual-side hysteresis, very low reference voltage, and short propagation delay. A cycle by cycle current limit provides protection against over current and short circuit failures. Additional features include adjustable hysteresis and a CMOS compatible input pin for PWM dimming. APPLICATIONS • • LED Driver Battery Charger TYPICAL APPLICATION CIRCUIT VIN = 4.5V to 35V R3 VIN ILIM C1 HG Q1 HYS CS D1 GND SNS DIM LM3401 L1 LED current R2 R1 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2013, Texas Instruments Incorporated LM3401 SNVS516C – AUGUST 2007 – REVISED MAY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. CONNECTION DIAGRAM CS 1 8 ILIM DIM 2 7 VIN SNS 3 6 HG HYS 4 5 GND Figure 1. Top View 8-Lead VSSOP See DGK Package PIN DESCRIPTIONS 2 Pin # Pin Name Description 1 CS Current sense pin. Connect to the PFET drain 2 DIM Dimming input pin. When DIM is low, the HG drive is off. Can be connected to a logic level PWM signal 3 SNS Current feedback pin – to LED cathode. Connect a resistor from this pin to ground to set the DC LED current 4 HYS Hysteresis adjust pin. Connect a resistor from this pin to GND to set the hysteresis window 5 GND Ground pin 6 HG Gate drive output. Connect to the PFET gate 7 VIN Power supply input 8 ILIM Current limit adjust pin. Connect a resistor from this pin to the PFET source to set the current limit threshold Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3401 LM3401 www.ti.com SNVS516C – AUGUST 2007 – REVISED MAY 2013 ABSOLUTE MAXIMUM RATINGS (1) If Military/Aerospace specified devices are required, contact the Texas Instruments Semiconductor Sales Office/ Distributors for availability and specifications. VALUE / UNIT VIN -0.3V to 36V CS -2.0V to 36V SNS -0.3V to 8V ILIM -0.3V to 36V DIM -0.3V to 36V HYS -0.3V to 4V Storage Temperature -65°C to +150°C Lead Temperature Vapor Phase (60sec) 215°C Infrared (15sec) 220°C ESD Rating Human Body Model (1) (2) (2) 2.5kV Absolute Maximum Ratings indicate limits beyond which damage may occur to the device. Operating Ratings indicate conditions for which the device is intended to be functional, but do not include specific performance limits. For specified specifications, see Electrical Characteristics. The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. RECOMMENDED OPERATING CONDITIONS (1) VALUE / UNIT VIN 4.5V to 35V Junction Temperature Range -40°C to +125°C Thermal Resistance θJA (2) Power Dissispation (1) (2) 151°C/W (2) 0.66W Absolute Maximum Ratings indicate limits beyond which damage may occur to the device. Operating Ratings indicate conditions for which the device is intended to be functional, but do not include specific performance limits. For specified specifications, see Electrical Characteristics. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ_MAX, the junction-to-ambient thermal resistance, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PD_MAX = (TJ_MAX - TA)/θJA. The maximum power dissipation of 0.66W is determined using TA = 25°C, θJA = 151°C/W, and TJ_MAX = 125°C. θJA will vary with board size and copper area. The θJA spec is based on a JEDEC standard 4-layer board. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3401 3 LM3401 SNVS516C – AUGUST 2007 – REVISED MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS Specifications in standard type are for TJ = 25°C only, and limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Unless otherwise stated, VIN = 24V. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only (1). Symbol Parameter Conditions Min Typ Max 200 212 Units SYSTEM VREF ΔVREF / ΔVIN IQ IHYS Reference Voltage 188 Line regulation Operating VIN Current 5V < VIN < 35V (2) HYS pin = 50 mV to 500 mV SNS Comparator Hysteresis Multiplier HYS pin = 250 mV TDLY SNS Comparator to HG Delay SNS rising TDIM DIM to HG Delay DIM rising IILIM ILIM Pin Sink Current VCL_OFF Current Limit Comparator Offset VZC Zero Cross Comparator Threshold VDIM DIM Threshold Voltage Measured at CS pin ISNS mA 15 20 25 µA 0.168 0.20 0.224 - 46 80 ns 69 120 ns 4 5.5 8 µA -10 0 +10 mV -70 -130 -200 mV 1.85 2.0 2.25 Hysteresis UVLO mV mV/V 1.05 Hysteresis Pin Source Current SNSHYS_MU 0.002 286 V mV SNS pin Bias Current VSNS = 200 mV 300 780 nA UVLO threshold Vin rising 4.3 4.48 V Hysteresis 0.5 V DRIVER Ton_min RHG IHG VHG (1) (2) 4 Minimum on-time Gate Drive Resistance Driver Output Current HG on voltage 150 ns Source Current = 100 mA 5.3 Ω Sink Current = 100 mA 10.5 Ω Source, HG = VIN -2.5V 0.41 A Sink, HG = VIN -2.5V 0.33 Referenced to VIN, steady state voltage -4.2 -4.7 A -5.5 V All room temperature limits are 100% production tested. All limits at temperature extremes are specified through correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). IQ specifies the current into the VIN pin and applies to non-switching operation. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3401 LM3401 www.ti.com SNVS516C – AUGUST 2007 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified, VIN = 24V, TA = 25°C. VREF vs Temperature HYS Current vs VIN 0.205 20.85 20.6 HYS CURRENT (PA) VREF (V) 0.203 0.201 0.199 20.35 20.1 19.85 0.197 0.195 -50 19.6 0 -25 25 50 75 100 125 0 5 10 TEMPERATURE (qC) 15 20 25 30 35 INPUT VOLTAGE (V) Figure 2. Figure 3. HYS Multiplier vs Temperature Startup Waveforms 0.23 ILED 100 mA/Div HYS MULTIPLIER 0.22 0.21 VIN 5V/Div 500 mV 0.20 0.19 50 mV 0.18 0.17 -50 VCS 10V/Div -25 0 25 50 75 100 4 Ps/DIV 125 TEMPERATURE (qC) Figure 4. Figure 5. HYS Current vs Temperature 21 5.8 20.6 HYS CURRENT (PA) ILIM SINK CURRENT (PA) ILIM Sink Current vs Temperature 6.0 5.6 5.4 5.2 5.0 -50 20.2 19.8 19.4 -25 0 25 50 75 100 19 -50 125 -25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (qC) Figure 6. Figure 7. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3401 5 LM3401 SNVS516C – AUGUST 2007 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified, VIN = 24V, TA = 25°C. UVLO Threshold vs Temperature SNS to HG Propagation Delay vs VIN 70 4.50 TURN-ON 60 DELAY TIME (ns) INPUT VOLTAGE (V) 4.30 4.10 TURN-OFF 3.90 3.70 50 40 30 3.50 3.30 -50 -25 0 25 50 75 100 20 125 0 5 10 15 20 25 30 TEMPERATURE (°C) INPUT VOLTAGE (V) Figure 8. Figure 9. Line Transient Response 35 40 Initial HG Voltage vs Input Voltage 8.0 180 pF 6.5 ILED 100 mA/Div VIN_HG (V) 470 pF VIN 10V/Div 5.0 1000 pF 3.5 2.0 20 Ps/DIV 0 5 10 15 20 25 30 35 INPUT VOLTAGE (V) Figure 10. Figure 11. 350 mA Efficiency 700 mA and 1A Efficiency 100 100 95 2 series (700 mA) 95 3 series 90 EFFICIENCY (%) EFFICIENCY (%) 90 85 2 series 80 1 series 75 70 80 1 series (1A) 75 70 65 65 60 60 0 5 10 15 20 25 30 35 INPUT VOLTAGE (V) 0 5 10 15 20 25 30 35 INPUT VOLTAGE (V) Figure 12. 6 1 series (700 mA) 85 Figure 13. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3401 LM3401 www.ti.com SNVS516C – AUGUST 2007 – REVISED MAY 2013 BLOCK DIAGRAM VIN on UVLO VDD regulator -0.13V Q Q S DIM R HG GND - + + CS SNS + ILIM ILIM X 0.2 20 PA + - VREF 200 mV 5.5 PA HYS Figure 14. Block Diagram Operational Description HYSTERETIC CONTROL The LM3401 is a step-down DC-DC controller designed to provide a constant current source for driving a high power LED string. The LM3401 uses comparator-based voltage mode hysteretic control for a simple and stable design. Hysteretic control does not utilize an internal oscillator, but relies on output conditions to directly control switching. The LM3401 controls LED current within the adjustable hysteresis window by monitoring peak and valley voltage at the SNS pin. A dual sided hysteresis window is used to optimize accuracy. Regulated LED current flows to ground through a sense resistor at the SNS pin. The voltage generated at the SNS pin is compared to the 200 mV internal reference. When the SNS voltage falls below the reference voltage minus hysteresis, the output of the hysteretic comparator goes low. This results in the driver output, HG, pulling the gate of the PFET low and turning on the PFET. With the PFET on, LED current ramps up through the PFET and the inductor. As the LED current increases, the SNS voltage reaches its upper threshold (reference voltage plus hysteresis). This forces the output of the comparator and HG to go high, which turns the PFET off. When the PFET turns off, current flows through the catch diode, and LED and inductor current ramp down. When the SNS voltage falls to its lower threshold, the cycle repeats. The resulting LED current, SNS, and switch node waveforms are shown in Figure 15. ILED 100 mA/Div VSNS 100 mV/Div VCS 10V/Div 400 ns/DIV Figure 15. Hysteretic Switching Waveforms Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3401 7 LM3401 SNVS516C – AUGUST 2007 – REVISED MAY 2013 www.ti.com OUTPUT CURRENT SETTING The LED average current is programmed using a resistor between SNS and GND, shown as R1 in the typical application schematic. The SNS resistor (RSNS) can be calculated as follows: RSNS = VSNS ILED (1) Where VSNS is 200 mV typically, and ILED is the DC average LED current. The sense resistor power rating must be higher than its power dissipation. The required power rating can be calculated (in Watts) as follows: WRSNS = VSNS x ILED (2) When selecting a sense resistor, thermal de-rating must also be taken into consideration. While RSNS sets the DC LED current, the AC peak LED current will be higher than the DC setting. This peak current must not be greater than the maximum peak current rating of the LED, ILED_max. Peak LED current can be calculated from the equation below: ILED_PK = ILED + ILED_RIP 2 (3) The LED ripple current, ILED_RIP, is described below in the Hysteresis Adjust section. HYSTERESIS ADJUST Adjustable hysteresis (via the HYS pin) provides direct control over the LED ripple current. The HYS pin also gives some control over the switching frequency. Although the hysteresis value can be set after the inductor is selected, a preliminary value must be set in order to begin the frequency calculation. The hysteresis window must be set small enough to keep the peak LED current below its maximum rating, ILED_max. The maximum SNS pin hysteresis can be calculated as shown: SNSHYS_MAX = (ILED_max - ILED) x RSNS (4) Any SNSHYS value between 10mV and this maximum is acceptable. The SNSHYS value is set with a single resistor from the HYS pin to GND, shown as R2 in the typical application schematic. The HYS pin voltage, VHYS, is internally multiplied by SNSHYS_MU (0.2 typical) to generate the hysteresis at the SNS pin, SNSHYS. The hysteresis setting resistor can be determined from the following equation: R2 = SNSHYS x 5 20 PA (5) Where 20 µA is the typical HYS source current, and SNSHYS is the resulting SNS pin hysteresis voltage. The hysteresis voltage can be set within a range of 10 mV to 100 mV (50 mV to 500 mV at the HYS pin). The SNSHYS value defines both the upper and lower threshold of the SNS pin. For example, with a VHYS setting of 100 mV, SNSHYS will be 20 mV. Therefore, the total hysteretic window will be 40 mV, or 20 mV above and 20mV below the 200 mV reference voltage. This directly correlates to peak-to-peak inductor and LED ripple current, approximated by the following equation: ILED_RIP = SNSHYS x 2 RSNS (6) If LED ripple current is a design priority, the preliminary R2 value can be determined using a target LED ripple current as shown: R2 = ILED_RIP x RSNS x 5 40 PA (7) A more precise equation for ripple current is given in the Inductor Selection section. Once an inductor is selected the more precise equation should be used to determine the actual ripple current and LED peak current. Larger hysteresis values will result in lower switching frequency and higher ripple current for a given inductor. Typical examples are shown in Figure 16 below. 8 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3401 LM3401 www.ti.com SNVS516C – AUGUST 2007 – REVISED MAY 2013 1800 1800 22 PH freq 1500 22 PH rip 1200 1200 68 PH freq 900 900 600 600 RIPPLE CURRENT (mA) FREQUENCY (kHz) 1500 300 300 68 PH rip 0 0 110 50 175 255 340 425 505 VHYS (mV) Figure 16. Switching Frequency and Ripple Current vs Hysteresis SWITCHING FREQUENCY Although hysteretic control is a simple control method, the switching frequency depends on application conditions and components. If the inductance, input voltage, or LED forward voltage is changed, there will be a change in the switching frequency. Therefore, care must be taken to select components which will provide the desired frequency range. Usually, the best approach is to determine a nominal switching frequency for the application and then select the inductor accordingly. Once the inductor is selected, VHYS can be adjusted to set the frequency range more precisely. This design process usually involves a few iterations to select appropriate standard values that will result in the desired frequency and ripple current. Switching frequency can be approximately calculated using the formula: fSW = D 2 x SNSHYS x L RSNS x (VIN - VANODE) + (2 x delay) (8) Where D is the duty cycle, defined as (VOUT + VDIODE) / VIN, VANODE is 200 mV plus the sum of LED forward voltages, and delay is the sum of the LM3401 propagation delay time and the PFET delay time. The LM3401 propagation delay is 46 ns typically (See the Propagation Delay curve). Alternately, the inductor value can be calculated from a known frequency by re-arranging the same equation: D - (2 x delay) x RSNS x (VIN - VANODE) fSW L= 2 x SNSHYS (9) Switching frequency for a typical application is shown in Figure 17 along with the calculated frequency. 1500 = calculated value 1250 FREQUENCY (kHz) 22 PH 1000 750 500 68 PH 250 0 0 5 10 15 20 25 30 35 INPUT VOLTAGE (V) Figure 17. Frequency vs Input Voltage Maximum switching frequency will typically occur around the input voltage which corresponds to 25% duty cycle. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3401 9 LM3401 SNVS516C – AUGUST 2007 – REVISED MAY 2013 www.ti.com If the input voltage falls below the forward voltage of the LED string, the LM3401 will operate at 100% duty cycle. In this state, the anode voltage will be equal to the input voltage and LED current is determined by the v-i curve of the LED. At 100% duty cycle, LED current will be continuous with a maximum value equal to the ILED_PK level set at the HYS pin. In some applications, maximum operating frequency will be limited by the minimum on-time as shown in the following equation: ton = D fSW (10) When the on-time reaches minimum (150 ns typical) due to increasing input voltage, the frequency will be reduced in order to maintain the proper duty cycle. INDUCTOR SELECTION The most important parameters for the inductor are the inductance and the current rating. The LM3401 operates over a wide frequency range and can use a wide range of inductance values. Once an inductance value is determined from the frequency equation, the maximum operating current must be verified. Although peak-to-peak ripple current is controlled by the hysteresis value, there is some variation due to propagation delay. This means that the inductance has a direct effect on LED current line regulation. In general, a larger inductor will result in lower frequency and better line regulation. The actual peak-to-peak inductor current can be calculated as follows: ILED_RIP = IL_RIP = 2 x SNSHYS RSNS + (VIN - VANODE) x 2 x delay L (11) Use the maximum value of Vin to determine the worst case ILED_RIP value. This value should be used to determine the peak current, ILED_PK, shown in the Output Current Setting section. Since the LM3401 can operate at 100% duty cycle, the inductor must be rated to handle ILED_PK continuously. RIPPLE REDUCTION CAPACITOR The typical application schematic shown on the front page is the simplest application of the LM3401. In this schematic, inductor current is equal to LED current. Therefore, the equations for ripple current apply to both LED ripple and inductor ripple. However, LED ripple current can be reduced without altering the inductor current by using a bypass capacitor placed in parallel with the LED string (shown as C2 in the Figure 24 schematic). This allows larger hysteresis values to be used while significantly reducing ripple current in the LED string. Figure 18 below shows this effect: inductor ripple current is unaffected while LED ripple current is dramatically reduced. ILED 50 mA /Div IL 50 mA/Div VCS 20V/Div 400 ns/DIV Figure 18. LED Ripple Current Reduction with a 1 µF Ripple Reduction Capacitor If a ripple reduction capacitor is used, the equation for SNSHYS_MAX only applies for 100% duty operation. 10 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3401 LM3401 www.ti.com SNVS516C – AUGUST 2007 – REVISED MAY 2013 LED average DC current and peak inductor current are not affected by the ripple reduction capacitor. However, LED peak current is reduced and switching frequency may shift slightly. Any type of capacitor can be used, provided the working voltage rating is sufficient. In general, higher capacitance and lower ESR will provide more ripple reduction; a typical value greater than 100 nF is recommended. Smaller capacitance values will be less effective, and large ESR values may actually increase LED ripple current. Despite its effectiveness to smooth LED ripple current, there are two notable disadvantages to using a ripple reduction capacitor. First, when used, care must be taken to avoid shorting the LED anode to ground. If this occurs, the capacitor will force a large negative voltage spike at the SNS pin which could damage the IC. Second, this capacitor will limit the maximum PWM dimming frequency because it takes some additional time to charge and discharge. Additionally, ceramic capacitors can generate audible noise due to fast voltage changes during dimming. To reduce audible noise, use the smallest possible case size, use dimming frequencies below 500 Hz, or use a non-ceramic ripple reduction capacitor. A small bypass capacitor, in the range of 100 pF to 200 pF can also be used to reduce high frequency switching noise. This is recommended in higher current applications, where switching noise can adversely affect the SNS or DIM pins. A small capacitor for noise reduction will have little to no effect on the LED ripple current or dimming but may help solve potential EMI problems. HG AND PFET SELECTION When switching, the HG pin swings from VIN (off state) to 4.7V below VIN (typical). As long as the DIM pin is high and the SNS pin is below the upper threshold, HG will stay low, driving the PFET on. The PFET should be selected based on the maximum Drain-Source voltage (VDS), Drain current rating (Id), maximum Gate-Source voltage (VGS), on-resistance (RDS(on)), and Gate capacitance. The voltage across the PFET in the off state is equal to the sum of the input voltage and the diode forward voltage. The VDS must therefore be selected to provide some margin beyond this voltage. Since the peak current through the PFET is equal to the peak current through the inductor, Id must be rated higher than the maximum ILED_PK. The LM3401 is capable of 100% duty cycle, therefore, the PFET drain current should be rated to handle ILED_PK continuously. In this case there is no ripple, so IPK = IAVE. Although the typical HG voltage is VIN - 4.7V, this voltage can go much lower during the initial PFET turn-on time. How far HG swings at turn-on depends on several factors including the gate capacitance, on-time, and input voltage. As shown in the Typical Performance Characteristics, the initial HG voltage swing increases with decreasing PFET gate capacitance. Therefore, A PFET must be selected with a maximum VGS rating larger than the initial HG voltage. Conversely, when driving PFETs with larger gate capacitance, the initial HG voltage will be lower. In some cases, a low VGS threshold PFET may be required to ensure complete turn-on. Use the Typical Performance curve as a guideline to selecting a proper PFET. Note that HG will eventually settle around the typical voltage of VIN - 4.7V regardless of the PFET gate capacitance. HG has an absolute minimum voltage of 1.2V typically. When the input voltage is below approximately 6V, this minimum limit causes a reduction in drive voltage. At 5V input, for example, HG will swing to 1.2V (or a gate drive voltage of -3.8V). This may not be sufficient to drive some PFETs, and at this reduced HG voltage, RDS(on) is likely to increase and trigger current limit. Therefore, a low VGS threshold PFET is also recommended for lower input voltage applications. The power loss in the PFET consists of switching losses and conducting losses. Although switching losses are difficult to precisely calculate, the equations below can be used to estimate total power dissipation, which is the sum of PDCOND and PDSW. PDFET_COND = RDS(on) x ILED2 x D (12) fSW x ILED x VIN x (Pon + Poff) PDFET_SW = 2 (13) Where Pon = PFET turn-on time, Poff = PFET turn-off time, and D is the duty cycle. A value of 10 ns to 50 ns is typical for ton and toff. Longer PFET on and off times will degrade both efficiency and accuracy. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3401 11 LM3401 SNVS516C – AUGUST 2007 – REVISED MAY 2013 www.ti.com Increasing RDS(on) will increase power losses and degrade efficiency. FET RDS(on) has a positive temperature coefficient. At 125°C, the RDS(on) may be as much as 150% higher than the value at 25°C. The Gate capacitance of the PFET has a direct impact on both PFET transition time and the power dissipation in the LM3401. Most of the power dissipated in the LM3401 is used to drive the PFET switch. This power can be calculated as follows: The average amount of gate driver current required during switching (IG) is: IG = Qg x fSW (14) Where Qg is the PFET gate charge. And the total power dissipated in the IC is: PD = (Iq x VIN) + (IG x 4.7V) (15) Where Iq is typically 1.05 mA and 4.7V is the typical HG voltage. Maximum power dissipation within the LM3401 is limited by ambient temperature. Use the following equation to determine maximum allowable power dissipation, or maximum allowable ambient temperature: PDmax = (125°C ± Ta_max) TJA (16) Where θJA is the typical thermal resistance of 151°C/W. In general, keeping the gate capacitance below 2000 pF is recommended to keep propagation delay, switching losses, and power losses low. PFETs with very fast rise times may cause excessive ringing at the HG node when combined with the inductance of a long HG trace. To reduce this ringing, a small resistor can be added between HG and the PFET gate. A typical value of 10Ω is usually sufficient. CURRENT LIMIT OPERATION The LM3401 current limit monitors inductor current at each switching cycle. Current is sensed across the RDS(on) of the PFET at the CS pin. When the PFET current exceeds the current limit threshold, HG is turned off and the current limit latch is set. In current limit mode, the PFET is held off until the inductor current falls to near zero. IL 500 PA /Div VCS 10V/Div 10 Ps/DIV Figure 19. Typical Current Limit Operation The current limit threshold is adjusted with a setting resistor, shown as R3 in the typical application schematic, connected from ILIM to the VIN node of the PFET. An internal 5.5 µA (typical) current sink at the ILIM pin creates a voltage across the setting resistor. This voltage is compared to the sensed voltage at the CS pin. Current limit is activated and latched when the voltage at the CS pin drops below the voltage at the ILIM pin. The current limit setting resistor, R3, can be calculated from the equation below. The minimum current limit occurs at maximum RDS(on) and minimum IILIM value. R3 = ILIM_PK x RDS(on) 4 PA (17) Where 4 µA is the minimum IILIM value and ILIM_PK is the peak inductor current limit threshold. ILIM_PK should be set somewhat higher than the maximum LED current, ILED_PK, to avoid false current limit triggering. The temperature variation of the PFET RDS(on) will result in an equivalent variation in current limit. To ensure that current limit is not falsely triggered, use the highest RDS(on) value over the temperature range to set the R3 value. 12 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3401 LM3401 www.ti.com SNVS516C – AUGUST 2007 – REVISED MAY 2013 When current limit is activated, the HG driver remains off until the CS voltage rises to -130 mV (typical). This ensures that inductor current is close to 0A when the current limit latch is released. The actual minimum inductor current will depend on the catch diode forward voltage characteristic, which determines the CS pin negative voltage. Although the LM3401 monitors voltage at the CS pin to reset the current limit, there is also a minimum off time of typically 3 µs. When current limit is triggered, HG will be turned off for at least this amount of time, regardless of the inductor current. The current limit comparator imposes typically 150 ns of blanking time at the beginning of each switching cycle. This ensures that the PFET is fully on and any switch node ringing has dissipated when the current is sensed. However a slower PFET may not fully turn on within the blanking time. In this case, the current limit threshold must be increased or a faster PFET must be used. Because the current limit comparator has a limited differential voltage capability, a maximum of 1MΩ is recommended for R3. PWM DIMMING The DIM pin is a CMOS compatible input for a PWM (Pulse Width Modulation) dimming signal. PWM dimming adjusts LED brightness by varying the duty cycle, which varies the average LED current. This type of dimming is recommended, because LED peak current remains constant regardless of brightness, which results in more predictable LED color and performance as compared to analog dimming. Figure 20 shows a typical PWM dimming waveform. When DIM is high (above 2V typically) the LM3401 operates normally and the LED string will be driven at the set current. When pulled low, DIM will disable HG and switching will stop. The PFET will remain off as long as DIM is low. When the LM3401 is powered up or enabled with the DIM pin, the LED current will very rapidly increase to its set point. There is minimal delay time between a DIM logic change and HG switching. Also, because the LM3401 requires no output capacitor, minimal time is required to ramp-up the LED current. This allows for low duty cycle, high frequency PWM dimming signals to be used. A dimming frequency greater than 100 Hz is recommended to avoid visible flicker. The LM3401 is capable of PWM dimming frequencies up to 10 kHz with a duty cycle between 1 and 100%. Any DIM signal pulse width longer than 100 ns can be used. In most cases, the maximum dimming frequency is limited by the inductor size and input voltage to anode voltage ratio. Less inductance and higher VIN/VANODE ratios will allow the inductor and LED current to increase faster, thus allowing for a faster PWM frequency, or lower dimming duty cycle. ILED 200 mA/Div VCS 20V/Div DIM 2V/Div 2 Ps/DIV Figure 20. Typical PWM DIM Signal and LED Current L = 22 µH DIM is a high impedance pin, which is somewhat sensitive to noise. If there is excessive switching noise at the DIM pin, a small bypass filter capacitor can be used. See the Ripple Reduction Capacitor section. VIN can also be used for PWM dimming when a logic signal is not available. In this mode of operation DIM should be connected to VIN through a 10 kΩ resistor. There is typically 10 us of startup delay time when using VIN for dimming. Depending on the application, this delay limits the maximum dimming frequency to typically several hundred Hz. Higher dimming frequency and lower dimming duty cycle can be achieved by using a FET switch in parallel with the LED string. This is shown in Figure 21 below. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3401 13 LM3401 SNVS516C – AUGUST 2007 – REVISED MAY 2013 www.ti.com L1 DIM signal to SNS R1 Figure 21. Parallel FET Dimming When the FET switches on, inductor current flows through the FET and the regulated average inductor current is unchanged. Using this method, inductor current rise time does not limit the dimming frequency. A ripple reduction capacitor should not be used with the parallel FET dimming method since it significantly slows the LED current rise time. However, a small noise filter capacitor can be used. INPUT CAPACITOR SELECTION An input bypass capacitor is required between VIN and ground. The input capacitor prevents large voltage transients at the input and provides the instantaneous current when the PFET turns on. The important parameters for the input capacitor are the voltage rating and the RMS current rating. Follow the manufacturer’s recommended voltage de-rating. RMS current can be calculated with the equation below. The highest RMS current will occur around 50% duty cycle. Irms = ILED x VANODE VANODE x 1VIN VIN (18) A ceramic input capacitor must be placed close to the drain of the PFET. This minimizes the trace inductance between VIN and the PFET, which is a source of switching noise. If the input capacitor is not properly located, switching noise can cause current limit and stability problems. CATCH DIODE SELECTION The catch diode provides the current path to the LED string during the PFET off-time and must be rated higher than the average current through the diode, which can be calculated as shown: IDIODE = ILED x (1-D) (19) The peak reverse voltage across the catch diode is approximately equal to the input voltage. Therefore, the diode’s peak reverse voltage rating should be larger than the maximum input voltage, plus some safety margin. A Schottky diode is recommended because its low forward voltage maximizes efficiency. For high temperature applications, diode leakage current may become significant and require a higher reverse voltage rating or a low leakage diode to achieve acceptable performance. LED CURRENT ACCURACY The total accuracy of average LED current is affected by several factors, both internal and external to the LM3401. Total static accuracy is the part-to-part variation and can be calculated from the equation below: ILED_Acc% = RSNS%2 + VSNS%2 (20) Where the worst case VSNS% is ±6%, and RSNS% is the sense resistor accuracy. Because these factors are not correlated, the RSS (root-sum-square) method of calculation is used. The LED current will also show some variation with input voltage. This is primarily due to propagation delay and the dynamic resistance of the LED. In longer on-time operation, the error due to dynamic resistance tends to dominate, while at shorter on-time, the propagation delay will dominate. These two effects counteract each other, resulting in typical regulation curves similar to those shown in Figure 22. A larger inductor will reduce the error due to propagation delay and will result in better overall line regulation. 14 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3401 LM3401 www.ti.com SNVS516C – AUGUST 2007 – REVISED MAY 2013 LED AVERAGE CURRENT (mA) 395 100% Duty 385 375 50 % Duty 365 33 PH 68 PH 355 100 PH 345 335 5 10 15 20 25 30 35 INPUT VOLTAGE (V) Figure 22. LED DC current line regulation LED Vf = 7.0V For most applications, the average LED current will be the highest at the maximum input voltage and lowest at a duty cycle somewhat greater than 50%. The maximum LED current variation can be estimated as: ILED_reg (A) = (VIN_max ± VIN_60%) x delay 2xL (21) Where VIN_60% is the input voltage corresponding to a duty cycle of 60%. Since the actual input voltage where minimum LED current occurs varies with the application, this is an approximation. As the duty cycle approaches 100%, the average LED current will approach ILED_PK. The average LED current will be the highest at the point that 100% duty cycle is reached. In the case that 100% duty cycle can occur, maximum LED current variation is calculated as: ILED_var_100% (A) = SNSHYS RSNS (22) PCB LAYOUT PCB layout is very important in all switching regulator designs. Poor layout can cause EMI problems, excess switching noise, and improper device operation. The following key points should be followed to ensure a quality layout. Traces carrying large AC currents should be as wide and short as possible to minimize trace inductance. These areas, shown as darker regions in Figure 23, are: • VIN between the input capacitor and PFET • GND between the input capacitor and catch diode • The switch node As shown in Figure 23, place the input capacitor ground as close as possible to the anode of the catch diode. The VIN side of the input capacitor should be placed close to the top of the PFET. The CS node (the node connecting the catch diode cathode, inductor, and PFET source) should be kept as small as possible. This node is one of the main sources for radiated EMI. The SNS and HYS pins are sensitive to noise. Be sure to route the SNS trace away from the inductor and the switch node, which are sources of noise. The SNS and HYS resistors should be placed close to their respective pins and grounded close to the GND pin. An isolated ground area shown as SGND in Figure 23 is recommended for the SNS, HYS, and GND pin connections. The two ground areas, GND and SGND, should be connected on an inner or bottom layer. This connection is shown as two vias in Figure 23. A large, continuous ground plane can also be used, as long as the input capacitor and catch diode ground area is somewhat isolated. The HG trace should be kept as short as possible to minimize inductance and gate ringing (See HG and PFET selection section). Finally, for accurate current limit sensing, the CS pin and ILIM resistor connections should be made at the PFET pads, via separate traces. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3401 15 LM3401 SNVS516C – AUGUST 2007 – REVISED MAY 2013 www.ti.com LED+ GND CS IC SGND VIN Figure 23. Example PCB Layout DESIGN EXAMPLE VIN = 18V to 35V VIN C1 2.2 PF 50V ILIM R3 46k DIM HG LM3401 HYS CS GND SNS Q1 40V 1.8A L1 D1 40V 33 PH 1A R2 5.6k 1% * Optional Component C2* 1 PF 50V + 690 mA ± 5% R1 290 m 1% 0.25W Figure 24. Example Circuit The following design example is intended to illustrate the step-by-step design process described in the previous sections. The example refers to the circuit in Figure 24, and the results are summaized in Table 1. The resulting circuit will drive a string of 2 Luxeon V Star LEDs at 700 mA from an input voltage between 18V and 35V. The example LEDs have a maximum DC current rating of 700 mA, a forward voltage of 5.4V to 8.3V, and a maximum peak current rating of 1.0A. First, set the LED DC current with R1: R1 = 200 mV = 286 m: 700 mA (23) And the required wattage is: WRSNS = 700 mA2 x 0.286 = 140 mW (24) Select a standard value of 290 mΩ, 1/4W resistor, which will result in a 690 mA LED DC current. To keep the peak LED current below ILED_MAX, the maximum hysteresis is determined by: SNSHYS_MAX = (1.0A - .690A) x 0.29Ω = 90 mV (25) Which gives a maximum R2 value of: R2 = 90 mV x 5 = 22.48 k: 20 PA (26) Next, a preferred switching frequency of 1 MHz is selected for this example. 16 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3401 LM3401 www.ti.com SNVS516C – AUGUST 2007 – REVISED MAY 2013 Since this is a relatively high switching frequency, a low starting point of 25 mV is selected for the comparator hysteresis to maintain good line regulation. This will allow a larger inductor at the same operating frequency and is well below the calculated maximum. Set a preliminary hysteresis value with R2: 25 mV x 5 = 6.25 k: 20 PA R2 = (27) For 1 MHz switching frequency and 25 mV hysteresis, inductance can be calculated. Because frequency varies with input voltage and LED forward voltage, for this calculation, assume typical values of 24V and 13.6V respectively, and a PFET delay time of 15 ns. 0.60 -(2 x 60 ns) x [0.29 x (24V - 13.8V)] 1 MHz L= = 29.6 PH 2 x 25 mV (28) Select a value of 33 µH and the hysteresis can be adjusted downward by re-arranging the same frequency equation: 0.60 -(2 x 60 ns) x [0.29 x (24V - 13.8V)] 1 MHz SNSHYS = = 22.4 mV 2 x 33 PH (29) This gives a new R2 value of 5.6k. This will result in a typical operating frequency of 1 MHz at 24VIN. Next, it must be verified that the peak LED current is within the maximum allowed. For now, the design is created without using a ripple reduction capacitor. Therefore, LED ripple current is equal to inductor ripple current. Maximum LED ripple current is calculated as: ILED_RIP = 2 x 22.4 mV 0.29: + (35V ± 11V) x 2 x 60 ns 33 PH = 227 mA (30) Note that the maximum input voltage and minimum anode voltage were used for this worst case calculation. Now peak LED current can be determined: ILED_PK = 690 mA + 227 mA = 804 mA 2 (31) This confirms that the component selections will keep LED peak current below the maximum LED rating. Notice if a ripple reduction capacitor is chosen, the peak inductor current is still 804mA, but the LED peak current is reduced. Therefore, the inductor must be rated for a DC current greater than 804 mA. Now that the inductor value has been selected and verified, the operating frequency range can be determined. Lowest operating frequency occurs at minimum input voltage and maximum anode voltage. For this example the values are 18V minimum input and 16.8V maximum anode voltage (200 mV SNS voltage plus the maximum LED forward voltages) and calculate: fSW = 0.96 2 x 22.4 mV x 33 PH 0.29: x (18V ± 16.8V) = 219 kHz + (2 x 60 ns) (32) At duty cycles close to 100% (96% in this case) the frequency equation becomes less accurate. Actual switching frequency will typically be lower than the calculated value. To estimate maximum operating frequency, calculate using a VIN which corresponds to a duty cycle of 25%. In this particular example, 25% duty cycle would occur above 35VIN (VIN = (VOUT + VDIODE)/0.25 = 69.9V), therefore maximum frequency will occur at the maximum input voltage corresponding to a duty cycle of 50% (D = (VOUT + VDIODE)/35V = 0.50): fSW = 0.50 2 x 22.4 mV x 33 PH + (2 x 60 ns) 0.29: x (35V ± 16.8V) = 1.25 MHz (33) Using the equation in the Switching Frequency section, it can be verified that this maximum frequency is within the minimum on-time limited frequency (and below the maximum operating frequency). The maximum frequency calculation is only an estimate, the actual maximum should be verified on the bench. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3401 17 LM3401 SNVS516C – AUGUST 2007 – REVISED MAY 2013 www.ti.com The next step is to select a PFET. The critical PFET parameters must meet the minimum circuit requirements of 35V input, 804 mA DC current, and adequate gate drive voltage rating. Therefore, select a PFET with the following ratings: • 40V maximum VDS • –20V maximum VGS • 1.8A continuous Id • 130mohm maximum RDS(on) Typically the PFET may be only sourcing 690 mA for about 50% duty cycle. However, at minimum input voltage the duty cycle will increase close to 100%. Therefore, the PFET Id rating should be based on its continuous, not pulsed, current capability. Now the power dissipation should be verified. Assume the selected PFET has a gate capacitance of 200 pF, which is within recommendation, and a gate charge of 15 nC. Maximum frequency and input voltage are used for a worst case calculation: IG = 15 nC x 1.25 MHz = 18.75 mA PD = (1.05 mA x 35V) + (18.75 mA x 4.7V) = 0.125W Ta_max = 125°C - (151°C/W x 0.125W) = 106°C (34) With the selected components, the maximum ambient temperature is above 100°C, sufficient for most applications. Note that this limit applies to the IC only and depends on the pcb type and size. Lower ambient temperature limits may apply to the PFET and other components. Now the current limit threshold is set with R3 at 0.95A, which is 120% of the maximum peak current. The worst case RDS(on) value at 125°C is used, which is 150% of nominal, and the worst case ILIM pin sink current. R3 = 0.95A x 195 m: = 46.3 k: 4 PA (35) The typical current limit threshold will be higher than 1A and can be determined by using typical values for RDS(on) and ILIM sink current. The PFET, inductor, and catch diode must be able to handle this current for short periods of time. The next component is the input capacitor, C1. A low ESR ceramic capacitor must be used and properly located on the PCB. For this design, the capacitor working voltage must be rated to at least 40V, and 50V is recommended. A 2.2 µF input capacitor should be sufficient, assuming a good PCB layout. The worst case input RMS current is calculated below 50% at duty cycle: Irms = 690 mA x 13.8V x 1 - 13.8V = 345 mA 27.6V 27.6V (36) It must be verified that the selected input capacitor can tolerate this current. An additional bulk capacitor placed at the input voltage connection is also recommended. Next, select D1, the catch diode. A Schottky diode should be used. The reverse voltage rating must be greater than 35V and the average forward current rating must be greater than: IDIODE = 690 mA x (1 - 0.31) = 480 mA (37) This calculation assumes the minimum duty cycle, which is maximum input voltage and minimum anode voltage. The diode must also be able to handle peak currents as high as the current limit threshold for short periods. We select a 1A diode to ensure adequate capability over temperature. If desired, a ripple reduction capacitor can be added at C2 to reduce the LED ripple current. A minimum starting value of 100 nF is recommended for C2, and a value of 1 µF will work well in most applications. In case of an open LED failure, the ripple reduction capacitor must be rated to the maximum input voltage of 35V. If C2 is used, LED ripple current is reduced and the calculated maximum R2 value no longer applies as a limit. Finally, check the accuracy. The static accuracy is calculated below using a 1% sense resistor. ILED_Acc% = 2 2 0.01 + 0.06 = 6.1% (38) To estimate line regulation, maximum input voltage and 60% duty cycle input voltage is used. For this example 60% duty cycle occurs at (13.6V + 0.2V)/0.60 or 23V input. ILED_reg = 18 (35V ± 23V) x 60 ns 2 x 33 PH = 11 mA (39) Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3401 LM3401 www.ti.com SNVS516C – AUGUST 2007 – REVISED MAY 2013 This is the estimated amount of LED current variation over the input voltage range. If the minimum input voltage was below 17V, the LED current variation would be calculated using the 100% duty cycle equation. Table 1. Design Example Summary Parameter Value Result Comment R1 290 mΩ 690 mA DC 1% R2 5.6 kΩ ±22.4 mV hysteresis VHYS = 112 mV(adjustable) L1 33 µH, >804 mA fsw - 1MHz typical 219 kHz min Iripple - 227 mA p-p worst case ILED_PK - 804 mA worst case PFET 40V, 1.8A, 130 mΩ adjustable R3 46 kΩ 0.95A minimum peak current limit C1 2.2 µF, 50V ceramic >345 mA rms D1 40V, 1A Schottky Accuracy ±6.1% ±42 mA max variation Regulation 1.6% 11 mA variation Ta_max 108°C C2 1.0 µF, 50V part-to-part vs VIN worst case LED ripple reduction optional Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3401 19 LM3401 SNVS516C – AUGUST 2007 – REVISED MAY 2013 www.ti.com REVISION HISTORY Changes from Revision B (May 2013) to Revision C • 20 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 19 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM3401 PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM3401MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN | Call TI Level-1-260C-UNLIM -40 to 125 SNHB LM3401MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SNHB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM3401MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM3401MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM3401MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM3401MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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