VISHAY AN805

AN805
Vishay Siliconix
PWM Optimized Power MOSFETs
for Low-Voltage DC/DC Conversion
Designers of low-voltage dc-to-dc converters have two main
concerns: reducing size and reducing losses. As a way of reducing
size, designers are increasing switching frequencies. But the result
has been reduced converter efficiency. To minimize losses,
MOSFET manufacturers have generally focused on lowering
on-resistance. But the results have not been optimal for dc-to-dc
conversion designs, since gate charge and switching speed issues
have been largely ignored. The dominant losses associated with
MOSFETs were once conduction losses, but this is no longer the
case.
[ ] The value of the parameter before the parenthesis is dependent
on the parameter within the parenthesis.
Drain
IRMS
Crss
RG
Vishay Siliconix’s new family of PWM optimized MOSFETs has
been designed to give the highest efficiency available for a given
on-resistance in switching applications such as dc-to-dc
conversion. These new devices provide a very low gate charge
per unit of on-resistance, in addition to fast switching times. The
result is reduced gate drive and crossover losses, allowing
designers of dc-to-dc converters to simultaneously reduce the
design footprint and increase efficiency.
Source
FIGURE 1.
where:
A simplistic model of power loss in a MOSFET used in a dc-to-dc
converter (Figure 1) can be calculated if we know the RMS, the
current through the MOSFET, the duty cycle, the gate voltage, and
the rDS(on) of the MOSFET. This model can then be used to
compare the efficiency of designs using Vishay Siliconix’s new
PWM optimized MOSFETs versus conventional and low-threshold
power MOSFETs.
I2RMS
rDS(on)
VGS
[TJ]
D
Qg
f
P I 2RMS r DS(on)
D Q
g V
GS
VGS T J
Using Equation 1 we can obtain a plot of power loss (gate loss +
rDS(on) loss) as a function of gate voltage at varying switching
frequencies (Figure 2). [1]
VGS f (Watts) Eq1
Technology Comparison: 1 MHz Power Loss
0
30
0.6
20
0.4
10
0.2
0
0
1
2
3
4
5
6
7
0
V GS
FIGURE 2. Power loss for PWM optimized Si6801 p-channel
MOSFET as a function of VGS and switching
frequency.
Document Number: 70649
January 1997
50
40
Loss (mW)
0.8
Conduction + Gate Charge
10
40
r DS(on) ( )
20
Power Loss (mW)
Gate Charge (nC)
30
Generic MOSFET model with body diode omitted.
The RMS current in the MOSFET (A)
On-resistance of the device for a given drive voltage
and junction temperature.
The peak driver gate voltage for the MOSFET (V)
Junction temperature of the MOSFET
Duty factor of the MOSFET (Ratio of on time to off
time)
Total gate charge for the MOSFET at a given gate
voltage (C)
Frequency of MOSFET switching (Hz)
Si6801 Power Loss, QG, rDS VGS
40
rDS(on)
Ciss
MOSFET Losses
The equation that defines the losses associated only with
on-resistance and the gate drive is:
Coss
Gate
30
20
10
1
2
3
4
5
6
7
V GS
FIGURE 3. Gate losses and on-resistance losses for PWM
optimized power MOSFET (Si6801DQ) versus
conventional (Si6542DQ) and low-threshold
(Si6552DQ) power MOSFETs.
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AN805
Vishay Siliconix
Figure 2 shows the respective contribution of on-resistance and
gate charge to overall losses for the p-channel Si6801DQ at three
different switching frequencies. At low gate-source voltages, the
rDS(on) of the MOSFET is high and therefore on-resistance losses
dominate. At higher gate-source voltages, on-resistance becomes
almost a constant and the gate charge losses controlled by Qg
dominate. Gate losses increase with the switching frequency,
causing a narrowing in the optimum gate voltage. Therefore, the
optimum drive voltage will be at a level which is just enough to take
the rDS(on) into its constant region, but no further. Typically, this
drive voltage is between 3 and 5 V, which is what most controller
ICs provide.
The PWM Optimized MOSFET in a Real Application
The PWM optimized power MOSFET is best viewed in the context
of a real application. In the example used here, the Si6801DQ is
paired with the Si9160BQ switching regulator IC to create a
synchronous boost converter for cellular telephones with the
following specifications:
Input voltage:
2.7 V to 5 V (single-cell lithium ion battery is
2.7 V to 4.2 V)
Output voltage:
5V
Output current:
1 A maximum
Gate drive voltage: 4.5 V
Control scheme: Constant frequency voltage mode control
Switching frequency:
Varied by RC value from 300 kHz to
1.8 MHz
Figure 3 compares the power losses, at a switching frequency of 1
MHz, of Vishay Siliconix’s PWM optimized Si6801DQ, a
conventional power MOSFET (Si6542DQ), and a low-threshold
power MOSFET (Si6552DQ).
Power losses for the PWM optimized MOSFET at gate drives
between 2.5 and 5.5 V are significantly lower than both
conventional and low-threshold MOSFETs, making the optimized
device the obvious choice for all switching applications.[7.]
1-Cell
LiIon
D1
LS4148
All results shown are with VIN = 3.6 V, VOUT = 5 V, IOUT = 600 mA, f
= 1 MHz unless otherwise stated.
ML
ML
C1
C2
10 mF 10 mF
D2
LS4148
4.7 mH
R5
100 k
1
D
2 1
S
3 1
S
4 1
G1
SYNC
1
C2
0.1 mF
2
3
R4
2.2 K
C3
0.1 mF
R2, 270 W
R1
10 k
C6
C4
22 pF 0.1 mF
C10
0.1 mF
Si9160
C10
0.33 mF
C5
0.1 mF
R3
2.2 k
4
5
6
7
8
VDD
VS
NC
DR
DMAX/SS
DS
COMP
PGND
FB
UVLOSET
NI
COSC
VREF
ROSC
GND
ENABLE
8
D2
7
S2
6
S2
5
G2
Si6801
16
15
14
13
12
11
10
R9
100 W
9
R6
12 k
C11
36 pF
R10
3.6 k
C9
0.1 mF
C8
5600 pF
R11
1.2 k
ML
C3
10 mF
ML
C4
10 mF
FIGURE 4. Si9160 Boost converter test circuit used to compare MOSFET technologies.
7.
Neither Figure 2 nor Figure 3 is intended for exacting power loss calculations. These figures should only be used as a comparative measure for various MOSFET technologies.
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Document Number: 70649
January 1997
AN805
Vishay Siliconix
The following complementary n- and p-channel MOSFETs, all
LITTLE FOOT TSSOP-8 devices, represent the three
technologies under test:
PWM optimized MOSFET Si6801DQ
Conventional MOSFET . . . . . . . . . . Si6542DQ
Low-threshold MOSFET . . . . . . . . . . Si6552DQ
Figure 4 shows test circuit used.
PWM Optimized MOSFET Performance
Reducing gate charge is one way in which PWM optimized
MOSFETs cut power losses. In a real application, another
component of power loss is crossover losses. These are also
minimized by the PWM optimized power MOSFET design, and
are discussed in detail in Appendix A.
Figure 5 shows oscillograms of the boost converter switching
waveform using the three different types of power MOSFETs.
Document Number: 70649
January 1997
The switching speeds are 4 ns for the Si6801DQ PWM optimized
MOSFET and 11 ns for the conventional MOSFET. The Si6801DQ
provides a nearly threefold improvement and thus lower losses. In
addition to the increase in basic switching speed, notice that the
PWM optimized MOSFET does not exhibit a large characteristic
step in the voltage waveform. This step is due to the feedback
capacitance from drain to gate of the MOSFET or “Miller”
capacitance (Crss in Figure 1) being charged when the drain
voltage is lower than the gate voltage during a switching transition
from an OFF state to an ON state. Effectively the gate voltage is
“stalled” while the Miller capacitance is charged, and this is
reflected in the voltage waveform from drain to source. This is
obviously an unwanted characteristic and has largely been
eliminated with PWM optimized MOSFET technology.
A final component that affects the switching speed of a MOSFET is
the effective gate resistance (RG in Figure 1). The effective gate
resistance defines how fast the MOSFET capacitance can be
charged. It is therefore one of the dominant factors in determining
how fast a MOSFET will switch. Vishay Siliconix’s PWM optimized
MOSFETs provide a minimum effective gate resistance.
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AN805
Vishay Siliconix
N-Channel Turn On 5 ns/dv
N-Channel Turn Off 5 ns/dv
Si6801
Si6801
High-Frequency
MOSFET
Technology
4 ns
3 ns
Si6542
Si6542
Conventional
MOSFET
Technology
11 ns
Si6552
FIGURE 5.
10 ns
Switching speed comparison between high-frequency, conventional, and low-threshold power MOSFETs.
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Si6552
Low-Threshold
MOSFET
Technology
14 ns
11 ns
Document Number: 70649
January 1997
AN805
Vishay Siliconix
A power MOSFET is made up of many single MOSFET cells
arranged in a parallel combination. In an ideal MOSFET all the
cells will turn on together when activated by a gate signal, and a
minimum switching time transition will be obtained. This does not
happen in a conventional MOSFET layout because the gate signal
has to propagate across the silicon in a turn-on “wave,” where the
cells nearest the gate bus turn on first with the outer cells following.
The PWM optimized MOSFET has symmetrical gate bussing, and
its bonding and layout structures minimize the turn-on “wave,” thus
increasing the switching speed of the device.
Efficiency
How much extra efficiency does the PWM optimized MOSFET
provide? A comparison of the efficiency of the synchronous boost
converter (Figure 4) using three different MOSFET technologies
shows that an improvement on the order of 5% can be made if an
optimized device is used.
h%
Figures 6, 7, and 8 show efficiency at switching frequencies
ranging from 300 kHz to 1.8 MHz, while Figure 9 summarizes the
efficiencies of the three technologies against switching frequency
at an output current of 400 mA. For all the results shown, the input
voltage for the synchronous boost converter was 3.6 V, with an
output voltage of 5 V.
The PWM optimized MOSFET surpasses all other technologies
while maintaining the highest efficiencies over the broadest load
ranges at all switching frequencies. The conventional MOSFET
technology provides the same breadth of efficiency but at a
reduced value. The low- threshold technology is clearly unsuited to
switching at higher switching frequencies with a gate voltage of
4.5 V.
As summarized in Table 1, at all switching frequencies the PWM
optimized MOSFET technology gives superior performance, both
in highest peak efficiencies and over the broadest load range,
making it the ideal choice for most low-voltage dc-to-dc designs.
100.00
100.00
90.00
90.00
80.00
h%
70.00
h % 6801 300 kHz
80.00
70.00
h % 6801 1 kHz
h % 6542 300 kHz
h % 6542 1 kHz
h % 6552 300 kHz
60.00
0.0
200.0
h % 6552 1 kHz
400.0 600.0
800.0
1000.0
60.00
0.0
200.0
Output Current 0 to 1000 mA
400.0 600.0
800.0
1000.0
Output Current 0 to 1000mA
FIGURE 6. Efficiency comparison between high-frequency,
conventional, and low-threshold MOSFETs at a
switching frequency of 300 kHz.
FIGURE 7. Efficiency comparison between high-frequency,
conventional and low-threshold MOSFETs at a
switching frequency of 300 kHz
100
100.00
95
90.00
h%
90
h%
80.00
85
80
70.00
h % 6801 1.8 MHz
h % 6801 400 mA
75
h % 6542 400 mA
h % 6542 1.8 MHz
60.00
0.0
h % 6552 1.8 MHz
200.0
400.0 600.0
800.0
1000.0
Output Current 0 to 1000mA
FIGURE 8. Efficiency comparison between high-frequency,
conventional, and low-threshold MOSFETs at a
switching frequency of 1.8 MHz.
Document Number: 70649
January 1997
h % 6552 400 mA
70
0
500
1000
1500
2000
Switching Frequency (kHz)
FIGURE 9. Efficiency vs. switching frequency comparing the
PWM optimized MOSFET technology with
conventional and low-threshold technologies
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Vishay Siliconix
Type of
MOSFET
Typical On-Resistance
at 4.5 V (m)
Specific
Gate Charge
Normalized Gate Charge
per 100 m (nc)
PWM Optimized
120
1.7
1.4
Conventional
100
4.0
4.0
Low- Threshold
73
16.0
22.0
Figure of Merit for the PWM Optimized MOSFET
Technology
Normalized gate charge serves as a quick figure of merit for
comparing the high-frequency, conventional, and low-threshold
MOSFETs. This was calculated by normalizing the on-resistance
and gate charge of the n-channel MOSFET to 100 m:
have a lower gate charge per unit ohm, making it a lot easier and
more efficient to implement a given drive scheme.
All N-Channel or
N- and P-Control IC,
eg.,
Si9140, Si9145
Similar performance advantages will be seen for the p-channel
process as well.
FIGURE 10. All n-channel synchronous buck converter.
Application Areas
Ideal applications for Vishay Siliconix’s PWM optimized MOSFETs
include mobile communication equipment and other hand-held
battery-operated systems, where dc-to-dc converters are
becoming essential, and any other application where small size
and high efficiency are design criteria. A good example is the
demonstration board used as an example in this application note.
The Si9160BQ and Si6801DQ chip set is targeted for the cellular
phone market where single-cell lithium ion batteries are becoming
more popular and high-efficiency boost converters are required.
The buck converter in notebook computers is another key
application for Vishay Siliconix’s PWM optimized MOSFETs. Most
buck converter controller ICs today support synchronous
operation and require all n-channel MOSFETs. A typical
synchronous buck converter is shown in Figure 10.
FIGURE 11. Implementation for synchronous rectification in a
resonant reset forward converter.
Conclusions
Vishay Siliconix’s PWM optimized MOSFET technology goes
beyond the traditional improvements in on-resistance that have
been the standard benchmark for MOSFETs. This technology
addresses gate, crossover and conduction losses giving the
dc-to-dc converter designer several valuable advantages,
including faster switching times, lower gate losses, and higher
overall converter efficiency with a minimum footprint.
References
In addition to non-isolated buck and boost topologies,
Vishay Siliconix’s PWM optimized MOSFETs are also very useful
in the application of synchronous rectification for isolated
converters (Figure 11). The replacement of Schottky diodes with
MOSFETs on the output of isolated topologies is becoming more
popular and even a necessity as output voltages drop below the
3-V level. This makes Schottky diodes impractical for efficiency
reasons. The biggest disadvantage to MOSFETs in isolated
synchronous rectification is that MOSFETs have to be driven and
Schottkies don’t. Vishay Siliconix’s PWM optimized MOSFETs
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Spice Analysis of low loss control/Power MOSFET Chip set for
High Frequency DC-DC Converter Design. Jeff Berwick,
John Huang, Wayne Grabowski and Richard K. Williams.
Siliconix Inc. Charles Hymowitz and Steve Sandler. Intusoft Inc.
HFPC Power Conversion, September 1996 Proceedings.
Jerry Fennel, “DO Cross Talk”, Advance Power Supplies, Bishop’s
Stortford, England.
Andrew Cowell, Si9160 Boost
Communications, May 1996.
Converter
for
Mobile
Document Number: 70649
January 1997
AN805
Vishay Siliconix
Power loss due to crossover or switching transition loss can be calculated from the generic expression below
ƪ ŕ
P S + f tts 1
ts1
V DS
ŕV
ƫ
ts2
I D dt ) ts 2
0
I D dt
DS
0
From this equation we can define the crossover losses generically for both resistive and clamped inductive loads.
Resistive Cross over Losses
Vdd
Vdd / RL
Vds
RL
Ids
ts1
ts2
Power
Dissipation
Vds . Ids (ts1 + ts2) f
P=
6
Clamped Inductive Cross over Losses
Vdd
Id1
ts2
Vds
RL
+
–
Ids
ts1
ts2
Power
Dissipation
Vds (Id1 . ts1 + Id2 . ts2) f
P=
2
Document Number: 70649
January 1997
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