SN54HC646, SN74HC646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS150B – DECEMBER 1982 – REVISED MAY 1997 D Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data True Data Paths High-Current 3-State Outputs Can Drive up to 15 LSTTL Loads Package Options Include Plastic Small-Outline (DW) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs SN54HC646 . . . JT OR W PACKAGE SN74HC646 . . . DW OR NT PACKAGE (TOP VIEW) CLKAB SAB DIR A1 A2 A3 A4 A5 A6 A7 A8 GND description The ’HC646 consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental busmanagement functions that can be performed with the ’HC646. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE is active (low). In the isolation mode (OE high), A data may be stored in one register and /or B data may be stored in the other register. 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC CLKBA SBA OE B1 B2 B3 B4 B5 B6 B7 B8 DIR SAB CLKAB NC VCC CLKBA SBA SN54HC646 . . . FK PACKAGE (TOP VIEW) A1 A2 A3 NC A4 A5 A6 5 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 4 11 3 19 12 13 14 15 16 17 18 A7 A8 GND NC B8 Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either or both registers. 1 OE B1 B2 NC B3 B4 B5 B7 B6 D D D D NC – No internal connection When an output function is disabled, the input function is still enabled and can be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. The SN54HC646 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74HC646 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54HC646, SN74HC646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS 21 OE L 3 DIR L 1 23 CLKAB CLKBA X X 2 SAB X BUS B BUS A BUS A BUS B SCLS150B – DECEMBER 1982 – REVISED MAY 1997 22 SBA L 21 OE L 3 DIR H 3 DIR X X X 1 23 CLKAB CLKBA X ↑ X ↑ ↑ ↑ 2 SAB X X X 22 SBA X X X 21 OE L L 22 SBA X BUS B 3 DIR L H STORAGE FROM A, B, OR A AND B 1 CLKAB X H or L 23 CLKBA H or L X 2 SAB X H TRANSFER STORED DATA TO A AND/OR B Pin numbers shown are for the DW, JT, NT, and W packages. Figure 1. Bus-Management Functions 2 2 SAB L BUS A BUS A 21 OE X X H 23 CLKBA X REAL-TIME TRANSFER BUS A TO BUS B BUS B REAL-TIME TRANSFER BUS B TO BUS A 1 CLKAB X POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 22 SBA H X SN54HC646, SN74HC646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS150B – DECEMBER 1982 – REVISED MAY 1997 FUNCTION TABLE INPUTS DATA I/O OPERATION OR FUNCTION OE DIR CLKAB CLKBA SAB SBA A1– A8 B1– B8 X X ↑ X X X Input Unspecified† Input Store A, B unspecified† Store B, A unspecified† X X X ↑ X X Unspecified† H X ↑ ↑ X X Input Input Store A and B data H X H or L H or L X X Input disabled Input disabled Isolation, hold storage L L X X X L Output Input Real-time B data to A bus L L X H or L X H Output Input Stored B data to A bus L H X X L X Input Output Real-time A data to B bus L H H or L X H X Input Output Stored A data to B bus † The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions are always enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs. logic symbol‡ OE DIR CLKBA SBA CLKAB SAB A1 21 3 23 22 1 2 G3 3 EN1 [BA] 3 EN2 [AB] C4 G5 C6 G7 ≥1 4 1 7 1 A3 A4 A5 A6 A7 A8 20 B1 5 1 6D A2 4D 5 ≥1 2 7 5 19 6 18 7 17 8 16 9 15 10 14 11 13 B2 B3 B4 B5 B6 B7 B8 ‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, NT, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54HC646, SN74HC646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS150B – DECEMBER 1982 – REVISED MAY 1997 logic diagram (positive logic) OE DIR CLKBA SBA CLKAB SAB 21 3 23 22 1 2 One of Eight Channels 1D C1 A1 4 20 B1 1D C1 To Seven Other Channels Pin numbers shown are for the DW, JT, NT, and W packages. absolute maximum ratings over operating free-air temperature range† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54HC646, SN74HC646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS150B – DECEMBER 1982 – REVISED MAY 1997 recommended operating conditions SN54HC646 VCC VIH Supply voltage VCC = 2 V VCC = 4.5 V High-level input voltage VCC = 6 V VCC = 2 V VIL VI VO Low-level input voltage Input voltage Output voltage Input transition (rise and fall) time TA Operating free-air temperature NOM MAX 2 5 6 VCC = 2 V VCC = 4.5 V VCC = 6 V MIN NOM MAX 2 5 6 1.5 1.5 3.15 3.15 4.2 VCC = 4.5 V VCC = 6 V tt SN74HC646 MIN UNIT V V 4.2 0 0.5 0 0.5 0 1.35 0 1.35 0 1.8 0 1.8 0 0 0 VCC VCC 0 VCC VCC 0 1000 0 1000 0 500 0 500 0 400 0 400 –55 125 –40 85 V V V ns °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH TEST CONDITIONS IOZ ICC Ci A or B SN54HC646 MIN MAX SN74HC646 MIN MAX UNIT 2V 1.9 1.998 1.9 1.9 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 IOH = –6 mA IOH = –7.8 mA 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 5.34 2V 0.002 0.1 0.1 0.1 IOL = 20 µA 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 VI = VCC or 0 6V ±0.1 ±100 ±1000 ±1000 nA VO = VCC or 0 VI = VCC or 0, 6V ±0.01 ±0.5 ±10 ±5 µA 8 160 80 µA 10 10 10 pF IOL = 6 mA IOL = 7.8 mA II TA = 25°C TYP MAX 4.5 V VI = VIH or VIL Control inputs MIN IOH = –20 µA VI = VIH or VIL VOL VCC IO = 0 Control inputs 6V 2 V to 6 V 3 V V PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54HC646, SN74HC646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS150B – DECEMBER 1982 – REVISED MAY 1997 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock tw tsu th Clock frequency Pulse duration, CLKBA or CLKAB high or low Setup time, A before CLKAB↑ ↑ or B before CLKBA↑ ↑ Hold time, A after CLKAB↑ ↑ or B after CLKBA↑ ↑ TA = 25°C MIN MAX POST OFFICE BOX 655303 SN74HC646 MIN MAX MIN MAX 2V 0 6 0 4.3 0 5.5 4.5 V 0 31 0 22 0 27 6V 0 36 0 25 0 31 2V 80 115 95 4.5 V 16 23 19 6V 14 20 16 2V 100 150 125 4.5 V 20 30 25 6V 17 26 21 2V 5 5 5 4.5 V 5 5 5 6V 5 5 5 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 SN54HC646 • DALLAS, TEXAS 75265 UNIT MHz ns ns ns SN54HC646, SN74HC646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS150B – DECEMBER 1982 – REVISED MAY 1997 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) fmax CLKBA or CLKAB tpd A or B SBA or SAB† ten tdis ten tdis OE OE DIR DIR tt A or B B or A A or B A or B A or B A or B A or B Any VCC MIN TA = 25°C TYP MAX SN54HC646 MIN MAX SN74HC646 MIN 2V 6 11 4.4 5.5 4.5 V 31 54 22 27 6V 36 64 25 31 MAX UNIT MHz 2V 65 180 270 225 4.5 V 18 36 54 45 6V 14 31 46 38 2V 50 135 205 170 4.5 V 14 27 41 34 6V 11 23 35 29 2V 70 190 285 240 4.5 V 20 38 57 48 6V 16 32 48 41 2V 85 245 370 305 4.5 V 25 49 74 61 6V 20 42 63 52 2V 85 245 370 305 4.5 V 25 49 74 61 6V 20 42 63 52 2V 80 245 370 305 4.5 V 25 49 74 61 6V 20 42 63 52 2V 80 245 370 305 4.5 V 25 49 74 61 6V 20 42 63 52 2V 28 60 90 75 4.5 V 8 12 18 15 6V 6 10 15 13 ns ns ns ns ns ns † These parameters are measured with the internal output state of the storage register opposite that of the bus input. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54HC646, SN74HC646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS150B – DECEMBER 1982 – REVISED MAY 1997 switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) CLKBA or CLKAB tpd A or B A or B B or A SBA or SAB† A or B OE A or B ten DIR A or B tt Any VCC MIN TA = 25°C TYP MAX SN54HC646 MIN MAX SN74HC646 MIN MAX 2V 90 265 400 330 4.5 V 24 53 80 66 6V 20 46 68 57 2V 70 220 335 280 4.5 V 20 44 67 56 6V 15 38 57 49 2V 80 275 415 345 4.5 V 24 55 83 69 6V 20 47 70 60 2V 113 330 500 410 4.5 V 33 66 100 82 6V 27 57 85 71 2V 113 330 500 410 4.5 V 33 66 100 82 6V 27 57 85 71 2V 45 210 315 265 4.5 V 17 42 63 53 6V 13 36 53 † These parameters are measured with the internal output state of the storage register opposite that of the bus input. UNIT ns ns ns 43 operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP 50 UNIT pF SN54HC646, SN74HC646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS150B – DECEMBER 1982 – REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test CL (see Note A) PARAMETER S1 Test Point tPZH ten RL 1 kΩ tPZL tPHZ tdis S2 RL 1 kΩ Data Input VCC 50% 10% 50% 50% 0V In-Phase Output 50% 10% tPHL 90% 90% tr tPHL Out-ofPhase Output 90% tf Closed Closed Open Open Open VCC th 90% 90% VCC 50% 10% 0 V tf 50% 10% Output Control (Low-Level Enabling) VCC 50% 50% 0V tPZL VOH 50% 10% V OL tf Output Waveform 1 (See Note B) tPLZ ≈ VCC ≈ VCC 50% 10% VOL tPZH tPLH 50% 10% Open VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES VCC tPLH Open tr VOLTAGE WAVEFORMS PULSE DURATIONS 50% Closed 0V 0V Input Closed tsu 0V 50% Open 50% 50% tw Low-Level Pulse 50 pF or 150 pF 50 pF or 150 pF –– Reference Input VCC S2 50 pF LOAD CIRCUIT 50% S1 tPLZ tpd or tt High-Level Pulse CL 90% VOH VOL Output Waveform 2 (See Note B) tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES 50% 90% VOH ≈0V tPHZ VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured when the input duty cycle is 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated