SN54AHCT594, SN74AHCT594 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS417F – JUNE 1998 – REVISED NOVEMBER 2002 D D 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER RCLR RCLK SRCLK SRCLR QH′ SN54AHCT594 . . . FK PACKAGE (TOP VIEW) QC QB description/ordering information The ’AHCT594 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks and direct overriding clear (SRCLR, RCLR) inputs are provided on both the shift and storage registers. A serial (QH′) output is provided for cascading purposes. QD QE NC QF QG 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 QH Both the shift register (SRCLK) and storage register (RCLK) clocks are positive edge triggered. If both clocks are connected together, the shift register always is one count pulse ahead of the storage register. 4 SER RCLR NC RCLK SRCLK SRCLR D QB QC QD QE QF QG QH GND NC VCC QA D SN54AHCT594 . . . J OR W PACKAGE SN74AHCT594 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) Inputs Are TTL-Voltage Compatible 8-Bit Serial-In, Parallel-Out Shift Registers With Storage Independent Direct Overriding Clears on Shift and Storage Registers Independent Clocks for Both Shift and Storage Registers Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) GND NC Q H′ D D NC – No internal connection ORDERING INFORMATION PDIP – N –55°C to 125°C TOP-SIDE MARKING Tube SN74AHCT594N Tube SN74AHCT594D Tape and reel SN74AHCT594DR SOP – NS Tape and reel SN74AHCT594NSR AHCT594 SSOP – DB Tape and reel SN74AHCT594DBR HB594 TSSOP – PW Tape and reel SN74AHCT594PWR HB594 CDIP – J Tube SNJ54AHCT594J SNJ54AHCT594J CFP – W Tube SNJ54AHCT594W SNJ54AHCT594W LCCC – FK Tube SNJ54AHCT594FK SNJ54AHCT594FK SOIC – D –40°C 40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA SN74AHCT594N AHCT594 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54AHCT594, SN74AHCT594 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS417F – JUNE 1998 – REVISED NOVEMBER 2002 FUNCTION TABLE INPUTS 2 FUNCTION SER SRCLK SRCLR RCLK RCLR X X L X X Shift register is cleared. L ↑ H X X First stage of shift register goes low. Other stages store the data of previous stage, respectively. H ↑ H X X First stage of shift register goes high. Other stages store the data of previous stage, respectively. L ↓ H X X Shift-register state is not changed. X X X X L Storage register is cleared. X X X ↑ H Shift-register data is stored in the storage register. X X X ↓ H Storage-register state is not changed. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54AHCT594, SN74AHCT594 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS417F – JUNE 1998 – REVISED NOVEMBER 2002 logic diagram (positive logic) 13 RCLR 12 RCLK 10 SRCLR SRCLK SER 11 14 1D Q C1 R 2D Q C2 R 2D Q C2 R 2D Q C2 R 2D Q C2 R 2D Q C2 R 2D Q C2 R 2D Q C2 R R 3D Q C3 15 R 3D Q C3 1 R 3D Q C3 2 R 3D Q C3 3 R 3D Q C3 4 R 3D Q C3 5 R 3D Q C3 6 R 3D Q C3 7 QA QB QC QD QE QF QG QH 9 QH′ Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54AHCT594, SN74AHCT594 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS417F – JUNE 1998 – REVISED NOVEMBER 2002 timing diagram SRCLK SER RCLK SRCLR RCLR ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ QA QB QC QD QE QF QG QH QH’ 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54AHCT594, SN74AHCT594 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS417F – JUNE 1998 – REVISED NOVEMBER 2002 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54AHCT594 SN74AHCT594 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 V Input voltage 0 5.5 0 5.5 V VO IOH Output voltage 0 0 VCC –8 V High-level output current VCC –8 IOL Dt/Dv Low-level output current 8 8 mA 20 20 ns/V High-level input voltage 2 2 0.8 Input transition rise or fall rate V V mA TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54AHCT594, SN74AHCT594 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS417F – JUNE 1998 – REVISED NOVEMBER 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VOH IOH = –50 mA IOH = –8 mA 45V 4.5 VOL IOL = 50 mA IOL = 8 mA 45V 4.5 II ICC VI = 5.5 V or GND VI = VCC or GND, IO = 0 5.5 V ∆ICC† One input at 3.4 V, Other inputs at VCC or GND 5.5 V Ci VI = VCC or GND MIN 4.4 TA = 25°C TYP MAX 4.5 3.94 0 V to 5.5 V 5V SN54AHCT594 MIN SN74AHCT594 MAX MIN 4.4 4.4 3.8 3.8 MAX UNIT V 0.1 0.1 0.1 0.36 0.44 0.44 ±0.1 ±1* ±1 mA 2 20 20 mA 2 2.2 2.2 mA 10 pF 2 10 V * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. † This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC. timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw tsu Pulse duration Setup time RCLK or SRCLK high or low SN54AHCT594 MIN MAX SN74AHCT594 MIN 5 5.5 5.5 RCLR or SRCLR low 5.2 5.5 5.5 SER before SRCLK↑ 3 3 3 SRCLK↑ before RCLK↑‡ 5 5 5 SRCLR low before RCLK↑ 5 5 5 SRCLR high (inactive) before SRCLK↑ 2.9 3.3 3.3 RCLR high (inactive) before RCLK↑ 3.4 3.8 3.8 MAX UNIT ns ns th Hold time SER after SRCLK↑ 2 2 2 ns ‡ This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54AHCT594, SN74AHCT594 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS417F – JUNE 1998 – REVISED NOVEMBER 2002 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax TA = 25°C TYP MAX SN54AHCT594 SN74AHCT594 LOAD CAPACITANCE MIN CL = 15 pF 135* 170* 115* 115 CL = 50 pF 120 140 95 95 tPLH tPHL RCLK QH QA–Q CL = 15 pF tPLH tPHL SRCLK QH′ CL = 15 pF tPHL RCLR QA–QH SRCLR MIN MAX MIN MAX UNIT MHz 3.3* 6.2* 1* 6.5* 1 6.5 3.7* 6.5* 1* 6.9* 1 6.9 3.7* 6.8* 1* 7.2* 1 7.2 4.1* 7.2* 1* 7.6* 1 7.6 CL = 15 pF 4.5* 7.6* 1* 8.2* 1 8.2 ns QH′ CL = 15 pF 4.1* 7.1* 1* 7.6* 1 7.6 ns 7.8 1 8.3 1 8.3 QH QA–Q CL = 50 pF 4.9 RCLK 5.8 8.9 1 9.7 1 9.7 8.6 1 9.1 1 9.1 QH′ CL = 50 pF 5.5 SRCLK 6 9.2 1 10.1 1 10.1 tPHL RCLR QA–QH CL = 50 pF 6.6 10 1 10.7 1 10.7 ns tPHL SRCLR QH′ CL = 50 pF 6 9.2 1 10.1 1 10.1 ns tPHL tPLH tPHL tPLH tPHL ns ns ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4) SN74AHCT594 PARAMETER MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 1 V Quiet output, minimum dynamic VOL –0.6 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 3.8 V High-level dynamic input voltage 2 VIL(D) Low-level dynamic input voltage NOTE 4: Characteristics are for surface-mount packages only. V 0.8 V TYP UNIT 112 pF operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz 7 SN54AHCT594, SN74AHCT594 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS417F – JUNE 1998 – REVISED NOVEMBER 2002 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw 3V 1.5 V Input 1.5 V th tsu 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL 1.5 V tPLZ ≈VCC 50% VCC Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V tPZL tPZH tPLH 50% VCC 3V Output Control VOL + 0.3 V VOL tPHZ 50% VCC VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002 N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 16 PINS SHOWN PINS ** 14 16 18 20 A MAX 0.775 (19,69) 0.775 (19,69) 0.920 (23,37) 1.060 (26,92) A MIN 0.745 (18,92) 0.745 (18,92) 0.850 (21,59) 0.940 (23,88) MS-100 VARIATION AA BB AC DIM A 16 9 0.260 (6,60) 0.240 (6,10) 1 C AD 8 0.070 (1,78) 0.045 (1,14) 0.045 (1,14) 0.030 (0,76) D D 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gauge Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.430 (10,92) MAX 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 14/18 PIN ONLY 20 pin vendor option D 4040049/E 12/2002 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001 D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 0.050 (1,27) 8 0.010 (0,25) 5 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 1 4 0.010 (0,25) 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.069 (1,75) MAX PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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