X RP 6 1 4 2 Synchronous Step-Down Controller with DDR Memory Termination March 2010 Rev. 1.0.0 GENERAL DESCRIPTION APPLICATIONS The XRP6142 is a synchronous step down switching controller for over 15 Amps point-ofloads converters and optimized to generate and support DDR I, II and III memory voltages requirements. • High-Power Point-of-Loads Converters • Audio-Video Equipments • FPGA and DSP Power Supplies • DDR Memory Based Embedded Systems Optimized to operate from standard 3.3V and 5V rails, the XRP6142 supports conversions down to 0.5V from an input voltage as low as 1V and can reach efficiencies of up to 96%. Based on a constant on-time control scheme and operating at a constant switching frequency over the whole input voltage range, it provides excellent load transient response while requiring no external compensation components. Three selectable on-time options allow for further switching frequency, solution footprint and efficiency optimization. FEATURES • Over 15A Point-of-Load Capable − Down to 0.5V Output Voltage Conversion − Up to 96% Efficiency • Wide 1.0V-5.5V Input Voltage Range Conversions − Single Input 3.3V and 5V rails Operations • Constant On-Time Operations − Constant Frequency Operations Dedicated support for DDR I, II and II memories is also provided. The XRP6142 easily generates VDDQ (VDD) or VTT voltages while an on board buffer provides the buffered VTT reference voltage. − No External Compensation • DDR I, II & III Termination Support − VDDQ/VDD or VTT Voltages Generation − Buffered VTT Ref. Voltage Generation Under-voltage Lock out, short-circuit and over-current and over-temperature protection insure safe operations under abnormal operating conditions. • Soft-Start and Enable Functions • UVLO, Short Circuit and Over Current Protection The XRP6142 is available in a compact RoHS compliant “green”/halogen free 16-pin QFN package. • RoHS Compliant “Green”/Halogen Free 3mm x 3mm 16-Pin QFN Package TYPICAL APPLICATION DIAGRAM Operation as DDR Supply VIN VDDQ CIN 3V-5.5V VIN VCC VOUT L1 BST EN VREF QT GH SW XRP6142 ILIM REFIN GL CSGND PGND AGND Thermal Pad VIN CFF RLIM R1 COUT R3 ACNTL VOUT VTT SP2996B REF EN QB R2 R4 GND FB VDDQ/2 VREF VTTREF Figure. 1: XRP6142 as a Step-Down Converter or a DDR Supply Exar Corporation 48720 Kato Road, Fremont CA 94538, USA www.exar.com Tel. +1 510 668-7000 – Fax. +1 510 668-7001 X RP 6 1 4 2 Synchronous Step-Down Controller with DDR Memory Termination ABSOLUTE MAXIMUM RATINGS OPERATING RATINGS These are stress ratings only, and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Input Voltage Range VCC .............................. 3.0V to 5.5V Input Voltage Range VIN ............................... 1.0V to 5.5V Junction Temperature Range ....................-40°C to 125°C Thermal Resistance θJA ................................... 33.3°C/W VCC ...................................................................... 7.0V VIN ....................................................................... 7.0V BST ....................................................................13.5V SW ............................................................. -1V to 7.0V BST-SW ...................................................... -0.3V to 6V All other pins ..................................... -0.3V to VCC+0.3V Storage Temperature .............................. -65°C to 150°C Power Dissipation ................................ Internally Limited Lead Temperature (Soldering, 10 sec) ................... 300°C ESD Rating (HBM - Human Body Model) .................... 2kV ESD Rating (MM - Machine Model) ...........................500V ELECTRICAL SPECIFICATIONS Specifications are for an Operating Junction Temperature of TJ = 25°C; limits applying over the full Operating Junction Temperature range are denoted by a “•”. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise indicated, VCC = VIN = 3.3V. Parameter VREF, Reference Voltage Min. Typ. Max. Units 0.495 0.5 0.505 V 0.492 0.5 0.508 V VFB offset VREFIN, Voltage Range 7 VDDQ/2, Input Impedance • VREFIN = VREF mV 1.3 VREF Conditions V 60 MΩ +1.25 % • VDDQ/2 = 0.75V, IVTTR=0mA ±40 ±65 mA • Sourcing: VTTREF=0, VDDQ/2=VREF Sinking: VTTREF=2V IQ, Operating Quiescent Current 400 600 IOFF, Shutdown current 0.1 VTTREF , Output Error -1.25 VTTREF Current Limit ±20 TON, Switch On-Time 1.15 All TON options ns 1.25 V 200 mV 50 VCCUVLO_HYS, Under-Voltage Lock out Hysteresis 500 V 75 % 42.5 50 57.5 µA 0.3 0 VFB=2.0V • VCC rising edge • % of VREFIN mV 65 -20 • nA 3.0 55 ILIM Current Temperature Coefficient (TON=500ns) ns 50 2.8 © 2010 Exar Corporation 400 µs 1.2 VCCUVLO, Under-Voltage Lockout Current Limit Blanking XR6142EL2-0-F (TON=2000ns) • 2.0 IFB, Feedback Pin Bias Current VILIM Current Limit Trip Level • 1.6 VEN_HYS, EN Pin Hysteresis ILIM Pin Source Current 2.4 0.8 50 VSC_TH, Feedback Pin Short Circuit Latch Threshold XR6142EL0-5-F XR6142EL1-0-F (TON=1000ns) 0.6 1.2 300 VIH_EN, EN Pin Rising Threshold • 0.5 1.0 TD, Gate Drive Dead-Time Not switching, VFB=VREFIN+0.1V EN=0V • 0.4 TOFF_MIN, Minimum Off-Time µA µA %/C +20 130 mV ns Page 2 of 17 • GL Rising > 1.0V Rev. 1.0.0 X RP 6 1 4 2 Synchronous Step-Down Controller with DDR Memory Termination Parameter Min. Hiccup Timeout Soft Start time RDS(ON)1, GH FET driver pull-up On resistance Typ. Max. Units 110 3 5 ms 10 Conditions 0.5μs, 1μs and 2μs option, VOUT=1V ms 2.5 Ω IGH=20 mA RDS(ON)2, GH FET driver pull-down On resistance 2 Ω IGH=20 mA RDS(ON)3, GL FET driver pull-up On resistance 2.5 Ω IGL=20 mA RDS(ON)4, GL FET driver pull-down On resistance 2 Ω IGL=20 mA BLOCK DIAGRAM Figure. 2: XRP6142 Block Diagram © 2010 Exar Corporation Page 3 of 17 Rev. 1.0.0 X RP 6 1 4 2 Synchronous Step-Down Controller with DDR Memory Termination PIN ASSIGNMENT Figure. 3: XRP6142 Pin Assignment PIN DESCRIPTION Name Pin Number AGND 1 Analog Ground Description VTTREF 2 Buffered output of VDDQ/2 VTT reference voltage for DDR applications. VDDQ/2 3 Buffer input voltage. Voltage used for the input to the VTTREF buffer VREF 4 Precision reference output REFIN 5 Reference input to the switching-regulator feedback comparator FB 6 Feedback input to feedback comparator CSGND 7 Current-sense ground ILIM 8 Connect a resistor between this pin and the low-side current-sense element in order to set the current-limit-trip threshold. See applications section for instructions on how to set this resistor PGND 9 Gate driver GND. GL 10 Low-side N-channel MOSFET driver SW 11 Switch node for floating-high-side gate drive GH 12 High-side N-channel MOSFET driver BST 13 Bootstrap capacitor to drive the high-side gate driver, GH VIN 14 Input voltage for the power train Vcc 15 Input voltage for the XRP6142 internal circuitry and gate drives. VIN and VCC can be tied together when VIN ≥ 3.0V EN 16 Thermal pad - © 2010 Exar Corporation Precision enable pin. Pulling this pin above 1.2V will turn the part on Internally connected to AGND Page 4 of 17 Rev. 1.0.0 X RP 6 1 4 2 Synchronous Step-Down Controller with DDR Memory Termination ORDERING INFORMATION Part Number Temperature Range XRP6142EL0-5-F -40°C≤TJ≤+125°C XRP6142ELTR0-5-F -40°C≤TJ≤+125°C XRP6142EL1-0-F -40°C≤TJ≤+125°C XRP6142ELTR1-0-F -40°C≤TJ≤+125°C XRP6142EL2-0-F -40°C≤TJ≤+125°C XRP6142ELTR2-0-F -40°C≤TJ≤+125°C XRP6142EVB XRP6142 Evaluation Marking Package Packing Quantity 6142E Bulk YYWW05 16-pin QFN X 6142E 3K/Tape & Reel YYWW05 16-pin QFN X 6142E Bulk YYWW10 16-pin QFN X 6142E 3K/Tape & Reel YYWW10 16-pin QFN X 6142E Bulk YYWW20 16-pin QFN X 6142E 3K/Tape & Reel YYWW20 16-pin QFN X Board – XRP6142EL2-0-F based Note 1 Note 2 RoHS Compliant Halogen Free 0.5µs on time RoHS Compliant Halogen Free 0.5µs on time RoHS Compliant Halogen Free 1.0µs on time RoHS Compliant Halogen Free 1.0µs on time RoHS Compliant Halogen Free 2.0µs on time RoHS Compliant Halogen Free 2.0µs on time “YY” = Year – “WW” = Work Week – “X” = Lot Number © 2010 Exar Corporation Page 5 of 17 Rev. 1.0.0 X RP 6 1 4 2 Synchronous Step-Down Controller with DDR Memory Termination TYPICAL PERFORMANCE CHARACTERISTICS All data taken at VIN = 3V to 5.5V, TJ = TA = 25°C, unless otherwise specified - Schematic and BOM from Application Information section of this datasheet. 1.2 4.0 XRP6142EL0.5-F XRP6142EL2.0-F 3.5 1.0 TON (μs) TON (μs) 3.0 2.5 VC C =5V IO=0A 2.0 0.8 VC C =5V IO=0A 0.6 1.5 0.4 1.0 XRP6142EL1.0-F 0.2 0.5 1 2 3 4 5 1 6 2 3 4 VIN (V) 2.520 100 XRP6142EL2.0-F XRP6142EL2.0-F 2.510 VOUT (V) 95 Efficiency (%) 6 Fig. 5: TON versus VIN Fig. 4: TON versus VIN 90 VIN=VC C =5V 2.500 VIN=VC C =5V VOUT=2.5V 2.490 85 2.480 80 0 5 10 15 0 20 5 10 15 20 IOUT (A) IOUT (A) Fig. 7: Load regulation Fig. 6: Efficiency versus IOUT 500 2.550 XRP6142EL2.0-F XRP6142EL2.0-F 450 2.525 Io=0A Io=10A f (kHz) VOUT (V) 5 VIN (V) 2.500 400 VIN=VC C =5V VC C =5V 350 2.475 2.450 3.5 300 4.0 4.5 5.0 0 5.5 10 15 20 Fig. 9: Frequency versus IOUT Fig. 8: Line regulation © 2010 Exar Corporation 5 IOUT (A) VIN (V) Page 6 of 17 Rev. 1.0.0 X RP 6 1 4 2 Synchronous Step-Down Controller with DDR Memory Termination 25 500 XRP6142EL2.0-F XRP6142EL2.0-F 20 IOCP (A) f (kHz) 450 400 VC C =5V IOUT=15A 350 300 3.5 15 10 tested Iocp 5 4.0 4.5 5.0 calculated Iocp 0 0.8 5.5 1.2 1.6 2.0 RLIM (kΩ) VIN (V) Fig. 11: IOCP versus RLIM Fig. 10: Frequency versus VIN 2ms/DIV 2ms/DIV VIN VIN 5V/DIV 5V/DIV XRP6142EL2.0-F VOUT VOUT 2V/DIV 2V/DIV VSW VSW 5V/DIV 5V/DIV IOUT IOUT XRP6142EL2.0-F 2V/DIV 2V/DIV Fig. 12: Power-up into a 15A load, VIN=5V, VOUT=2.5V Fig. 13: Power-down from a 15A load, VIN=5V, VOUT=2.5V 2μs/DIV 100μs/DIV XRP6142EL2.0-F VSW 5V/DIV VOUT VOUT 100mV/DIV 20mV/DIV AC coupled AC coupled IOUT IL 10A/DIV 10A/DIV XRP6142EL2.0-F Fig. 14: Steady state, output ripple is 30mV p-p, VOUT=2.5V © 2010 Exar Corporation Fig. 15: Transient response, 250mV p-p, 15A load step Page 7 of 17 Rev. 1.0.0 X RP 6 1 4 2 Synchronous Step-Down Controller with DDR Memory Termination THEORY OF OPERATION The XRP6142 synchronous buck controller utilizes the constant-on-time principle. The ontime is internally set and is available in three different set points to allow for different frequency options. The XRP6142 automatically adjusts the on-time during operation inversely with the input voltage VIN, to maintain a constant frequency. Therefore, the switching frequency is independent of the inductor and capacitor size, unlike hysteretic controllers. At the beginning of the cycle, the XRP6142 turns on the high-side FET for a fixed duration. The on time is internally set and adjusted by VIN. At the end of the on time, the high-side FET is turned off, for a predetermined minimum off time (nominally 300ns). After TOFF-MIN has expired, the high-side FET will stay off until the feedback comparator trip point of 0.5V has been reached. Then the high-side FET turns on again and the cycle repeats. The operation of the low-side FET is complementary to the high-side FET. A short dead-time prevents shoot-through from occurring. TIMING OPTIONS Three versions of XRP6142 (Timing Options) are identified by their on times at VIN=3.3V. For each version, TON is inversely proportional to VIN. The constant of proportionality K, is shown in the table below. Variation of TON versus VIN is shown graphically in figures 4 and 5. Part Number TON at VIN=3.3V K=TONxVIN (μs.V) 0.5μs 1.0μs 2.0μs XRP6142EL0.5-F XRP6142EL1.0-F XRP6142EL2.0-F VOUT 0.8 1.0 1.2 1.5 1.8 2.5 3.3 f(kHz) for each Timing Option 0.5μs 1.0μs 2.0μs 485 606 727 909 1091 ----- 242 303 364 455 545 758 --- 121 152 182 227 273 379 500 INTERNAL SOFT-START Soft-start time is internally set at 5ms (nominal). This removes the need for external components associated with soft-start function, and helps save cost and reduce PCB space. ENABLE A precision enable function is provided (1.20V ±0.05V). EN should be tied to VCC in applications that do not require this function. INTERNAL REFERENCE VOLTAGE A high-precision 0.5V internal reference is provided at the VREF pin. This is normally tied to the REFIN pin, thus setting the threshold of the voltage comparator. INTERNAL BOOTSTRAP DIODE XRP6142 includes an internal low-Vf bootstrap diode. Place a 0.1uF capacitor between BST and SW pins to provide drive voltage for the high-side FET. UNDER-VOLTAGE LOCKOUT 1.65 3.3 6.6 UVLO monitors VCC and ensures adequate voltage exists before starting to switch the FETs. Note that for a Buck converter the switching frequency is given by: VOUT f = VIN × TON Since for each XRP6142 Timing Option, the product of VIN and TON is a constant, then © 2010 Exar Corporation frequency is determined by VOUT as shown in the following table. SHORT CIRCUIT PROTECTION An internal short-circuit comparator monitors the feedback voltage. If feedback voltage falls below 65% of reference voltage (this is equivalent to output voltage falling below 65% of nominal value) the IC will latch off. VCC has Page 8 of 17 Rev. 1.0.0 X RP 6 1 4 2 Synchronous Step-Down Controller with DDR Memory Termination to be recycled in order for IC to resume operation. OVERCURRENT PROTECTION (OCP) OCP function is implemented by monitoring the voltage across the low-side FET when it is on. OCP is programmed via a resistor RLIM connected between ILIM and SW pins. An internal constant-current source ILIM (50uA nominal) establishes a voltage across RLIM. This voltage sets the trip point of the OCP comparator. If the OCP comparator is triggered for eight consecutive switching cycles, then a hiccup timeout, as described in the next section, is initiated. Calculate RLIM from: 110ms, following which, a soft-start is attempted. If the OCP condition is still present, then the timeout and soft-start cycle repeat. This is referred to as hiccup timeout. PROGRAMMING VOUT A pair of output resistors is used to set the output voltage VOUT. Calculate R1 from: ⎛V ⎞ R1 = R2⎜⎜ OUT − 1⎟⎟ ⎝ VREF ⎠ Where: R2 is nominally set at 10k (bottom resistor) VREF is reference voltage (0.5V) Note that VOUT must contain some voltage ripple in order for XRP6142 to regulate the output. Since XRP6142 regulates the bottom of the output ripple the average value will be higher (see figure 16). ⎡⎛ ⎤ ΔIL ⎞ ⎢⎜ IOCP + 2 ⎟ × RDS (ON ) ⎥ + 20mV ⎝ ⎠ ⎦ RLIM = ⎣ 42.5μA Where: IOCP is the output current at which overcurrent protection is activated (usually set 20% above maximum IOUT) ∆IL is inductor current ripple nominally set at 30% of IOUT RDS(ON) is the maximum rated on resistance of the FET 20mV is the OCP comparator offset spec Fig. 16: VOUT Voltage Ripple 42.5μA is the minimum spec of the ILIM source The actual IOCP is 50% to 100% higher than expected IOCP as seen in figure 11. This is because RLIM in the above equation is calculated based on worst case parameters. A temperature coefficient of 0.3%/°C has been designed into ILIM. This useful feature nulls out the positive temperature coefficient of the FET RDS(ON) to a first order. Thus IOCP should be largely independent of operating temperature. ⎛V − (0.5 × VOUT , ripple) ⎞ − 1⎟⎟ R1 = R 2⎜⎜ OUT VREF ⎝ ⎠ Where: VOUT , ripple = ΔIL × ESR ESR is the output capacitor’s Equivalent Series Resistance. OUTPUT CAPACITOR HICCUP TIMEOUT When an over current condition is detected, the internal FET drivers are turned off for © 2010 Exar Corporation VOUT can be programmed more precisely from: COUT is the most critical component for proper operation, since the XRP6142 relies on VOUT Page 9 of 17 Rev. 1.0.0 X RP 6 1 4 2 Synchronous Step-Down Controller with DDR Memory Termination voltage ripple for regulating the output. To ensure stable operation two constraints must be met: First the COUT must have sufficient ESR in order to get enough voltage ripple at feedback pin. It is recommended that XRP6142 be operated with at least 25mV ripple at feedback pin. Assuming majority of output voltage ripple is from ESR, we get: ESR ≥ 25mV ΔIL …………. (1) Where ∆IL is inductor current ripple nominally set at 30% of IOUT. Note that VOUT ripple, is attenuated by the resistor divider R1/R2, and a smaller ripple is seen at FB pin. For example if VOUT ripple is 25mV and R1=R2=10k, then the voltage ripple at FB is only 12.5mV. One solution to this problem is to increase the output ripple accordingly, such that ripple at FB is 25mV. A more desirable solution is to provide a highfrequency/low-impedance path for the output ripple to be transmitted to FB without attenuation. This can be done by placing a small feed-forward capacitor CFF in parallel with R1. As a starting point calculate CFF from: CFF = 2 Vos 2 − VOUT 2 Where: I2 is load step high-level current I1 is load step low-level current VOUT is output voltage including transient (nominally this is set 3% higher than VOUT) In general, the best capacitors are the ones with known and consistent ESR across operating temperature range. Examples include POSCAPs, Tantalums and certain Aluminum Electrolytics. OUTPUT INDUCTOR Select the output inductor for inductance and current rating. As a rule of thumb the DC current rating and saturation current should be at least 50% higher than maximum output current. Calculate the inductance from: L= (VIN − VOUT ) × D ΔIL × fs Where: D is duty cycle ∆IL is inductor current ripple nominally set at 30% of IOUT. In general, a CFF of 1nF should provide satisfactory feed-forward for most applications based on the XRP6142. The second constraint for stability establishes a relation between ESR and COUT. Ton COUT …………. (2) INPUT CAPACITOR Select the input capacitor for capacitance, voltage rating and RMS current rating. As a rule of thumb, the voltage rating should be twice the maximum input voltage of the converter. RMS current rating can be approximated from: I RMS = I OUT × D(1 − D ) Once ESR is calculated from equation (1), equation (2) can be used to calculate COUT. The aforementioned are in addition to the usual requirements for COUT for a buck converter. The usual constraint in order to meet load step transient requirement is given by: © 2010 Exar Corporation I 2 − I1 fs is switching frequency 10 2 × π × R1 × fs Where fs is the switching frequency ESR ≥ 2 C OUT ≥ Calculate CIN such that input voltage ripple does not exceed 2% of VIN. Ceramic input capacitors are recommended. This choice minimizes input voltage ripple due to ESL and ESR. Thus a simplified expression for CIN can be written: Page 10 of 17 Rev. 1.0.0 X RP 6 1 4 2 Synchronous Step-Down Controller with DDR Memory Termination C IN = I OUT , MAX × VOUT × (V IN − VOUT ) fs × 0.02V IN × V IN section the total target loss is 0.5W, and thus target conduction loss equals 0.25W. By using this value in the above equation RDS(ON) can be calculated. Rise and fall time can be approximated from: 2 SYNCHRONOUS FET (LOW-SIDE FET) Select the synchronous FET for voltage rating BVDSS, on resistance rating RDS(ON) and gate drive rating VGS. As a rule of thumb, voltage rating should be at least twice the converter input voltage. FETs with voltage rating of up to 30V should provide satisfactory performance. Drive voltage of 4.5V is sufficient for applications with minimum input voltage of 4.5V. For applications with a lower input voltage a FET with 2.5V gate drive should be selected. Switching losses of the Synchronous FET are negligible in comparison to its conduction losses. RDS(ON) is calculated based on conduction losses from: RDS ( ON ) ≤ PConduction (1 − D ) × I OUT 2 It is common practice to allocate 50% of the total FET losses to the synchronous FET. As an example, consider a 10W buck converter with a target efficiency of 90%. Therefore, the target total power loss is 1.1W. Assume that the only significant non-FET loss is the inductor loss estimated at 0.1W. Thus the maximum conduction loss of the synchronous FET should not exceed 0.5W. By using this value in the above equation RDS(ON) can be calculated and a suitable FET selected. tr + t f = PSwitching VIN × I out × f s Since the allotted switching loss budget is 0.25W, tr and tf can be calculated from the above equation. For a detailed explanation of FET losses and FET selection procedure refer to EXAR application note ANP-20. R-C SNUBBER (OPTIONAL) An R-C snubber placed across the synchronous FET eliminates the ringing and reduces the amplitude of overshoot at SW node. Use surface-mount components and place them close to the FET drain-source. Calculate the value of snubber capacitor Csnb from: Csnb = 3 × Coss Coss is the output capacitance of synchronous FET corresponding to VIN. the Calculate the value of the snubber resistor Rsnb from: Rsnb = 2 × VOUT I OUT SWITCHING FET (HIGH-SIDE FET) DDR MEMORY POWER APPLICATIONS Select the switching FET for voltage rating BVDSS, on-resistance rating RDS(ON), gate drive rating VGS, rise time tr and fall time tf. BVDSS and VGS selection guidelines are the same as Synchronous FET. The switching FET incurs switching (i.e., transitional) as well as conduction losses. RDS(ON) is calculated based on conduction losses from: XRP6142 can be used to generate the required VDDQ (VDD) or VTT Reference voltages for DDR I, II and III memories and provides a 40mA buffered VTT Reference voltage. When used in conjunction with Exar’s SP2996 DDR Memory Termination, the XRP6142 provides a complete DDR power management solution. A costeffective DDR2 solution is shown on page 15. XRP6142 provides the VDDQ and VTTREF voltages. SP2996 provides the VTT voltage. Please note that the current output of VDDQ can be increased up to 10A by using a larger QT/QB MOSFET and scaling the L1 and C3 accordingly. RDS (ON ) ≤ PConduction 2 D × I OUT It is common practice to allocate 50% of the total high-side FET losses to conduction. Proceeding with the example from previous © 2010 Exar Corporation Page 11 of 17 Rev. 1.0.0 X RP 6 1 4 2 Synchronous Step-Down Controller with DDR Memory Termination PCB LAYOUT GUIDELINES The following guidelines will help attain stable operation and reduce jitter: 1- Place all the power components; CIN, QT, QB, L1 and COUT on the same side of the board if possible. 2- Make the loop between CIN, QT and QB as small as possible and use lowimpedance traces. 3- Make the loop between QB, L1 and COUT as small as possible and use lowimpedance traces. 4- Place the source of QT, drain of QB and input connection of L1 as close as possible and use low-impedance traces. © 2010 Exar Corporation Page 12 of 17 5- Use a short trace and connect AGND to the thermal pad. This forms the signal ground. 6- Use a short trace and connect PGND to AGND. 7- Use a low-impedance trace and connect the PGND pin to the COUT. 8- Place CFF, R1 and R2 close to the IC, and connect R2 to signal ground. Use a short trace and connect R1 to COUT. 9- Bypass the VCC pin to signal ground with a ceramic capacitor(s) as close to the IC as possible. Connect the VCC pin to VIN or an independent VCC source through a 10Ω resistor. This will help filter out noise from VCC. Rev. 1.0.0 X RP 6 1 4 2 Synchronous Step-Down Controller with DDR Memory Termination DESIGN EXAMPLES 5V STEP-DOWN CONVERTER Note: The data shown in figures 6 trough 15 was collected using this circuit. RVCC 10 Ohm VIN=4.5V-5.5V CVCC 4.7uF CVCC1 0.1uF C4 0.1uF C1 47uF C2 47uF C3 47uF GL 9 RLIM 2.2k 4 3 2 1 CFF 1nF VOUT=2.5V, 0-15A C5 220uF C6 220uF Csnb 3.9nF Rsnb 0.2 Ohm GND C5-C6 SANY O POSCAP 6TPE220MI, 6.3V, 18mOhm R1 39.2k (1%) Snubber components are optional R2 10k (1%) © 2010 Exar Corporation C1-C3 ceramic, 10V L1, Wurth Elektronik 0.82uH, 27A, 0.9 mOhm 1 2 QB Vishay Si4164DY 10 5 6 7 8 FB 6 5 PGND 12 11 ILIM VREF CSGND VDDQ/2 3 2 1 14 13 BST VCC VIN SW U1 REFIN 4 GH VTTREF QT Vishay Si4164DY 4 XRP6142EL2.0-F 8 3 AGND 7 2 15 16 1 EN T. PAD 5 6 7 8 GND CBST 0.1uF Page 13 of 17 Rev. 1.0.0 X RP 6 1 4 2 Synchronous Step-Down Controller with DDR Memory Termination 3.3V STEP-DOWN CONVERTER RVCC 10 Ohm VIN=3V-3.6V CVCC 4.7uF CVCC1 0.1uF T POINT S C4 0.1uF C1 47uF C2 47uF C3 47uF 13 12 11 10 5 6 7 8 RLIM 3.65k 4 3 2 1 CFF 1nF T POINT S VOUT=1.2V, 0-10A T POINT S C5 220uF C6 220uF Csnb 3.9nF Rsnb 0.2 Ohm GND C5-C6 SANY O POSCAP 6TPE220MI, 6.3V, 18mOhm T POINT S R1 14k (1%) Snubber components are optional R2 10k (1%) © 2010 Exar Corporation C1-C3 ceramic, 10V L1, Wurth Elektronik1 0.72uH, 22A, 1.65 mOhm 1 2 QB Fairchild FDS6570 9 ILIM PGND 8 5 FB VREF CSGND GL 3 2 1 BST 14 VIN SW U1 VDDQ/2 REFIN 4 GH VTTREF QT Fairchild FDS6570 4 XRP6142EL1.0-F 7 3 AGND VCC 16 2 6 1 EN T. PAD 15 CBST 0.1uF 5 6 7 8 GND Page 14 of 17 Rev. 1.0.0 X RP 6 1 4 2 Synchronous Step-Down Controller with DDR Memory Termination DDR2 MEMORY SOLUTION RVCC 10 Ohm VIN=3.3V or 5V CVCC 1uF C1 C2 0.1uF 47uF, ceramic, 10V 12 11 L1, Vishay IHLP-2525CZ 1.5uH, 9A, 15 mOhm 1 2 10 3 CFF 1nF U2 SP2996B 1 2 QB Vishay , Si2312BDS 1 3 GND 4 C3 SANY O POSCAP 4TPE150MAZB, 4V, 35mOhm 2 RLIM 3.65k VDDQ=1.8V, 0-3A C3 150uF 9 ILIM FB PGND 8 5 CSGND GL 2 BST U1 VREF 3 13 14 VIN SW VDDQ/2 REFIN 4 GH VTTREF GND QT Vishay , Si2312BDS 1 XRP6142EL1.0-F 7 3 AGND VCC 16 2 6 1 EN T. PAD 15 CBST 0.1uF R1 25.5k (1%) VIN VCNTL GND VCNTL REFEN VCNTL VOUT VCNTL 8 7 6 5 VTT=0.9V, 1A peak, 0.5ADC R3 10k (1%) C4 R2 10k (1%) 47uF, ceramic, 6.3V VREF/VTT ENABLE Q1 CES7002A R4 10k (1%) VREF C5 1uF © 2010 Exar Corporation Page 15 of 17 Rev. 1.0.0 X RP 6 1 4 2 Synchronous Step-Down Controller with DDR Memory Termination PACKAGE SPECIFICATION 16-PIN QFN © 2010 Exar Corporation Page 16 of 17 Rev. 1.0.0 X RP 6 1 4 2 Synchronous Step-Down Controller with DDR Memory Termination REVISION HISTORY Revision Date 1.0.0 03/24/2010 Description Initial release of datasheet FOR FURTHER ASSISTANCE Email: [email protected] Exar Technical Documentation: http://www.exar.com/TechDoc/default.aspx? EXAR CORPORATION HEADQUARTERS AND SALES OFFICES 48720 Kato Road Fremont, CA 94538 – USA Tel.: +1 (510) 668-7000 Fax: +1 (510) 668-7030 www.exar.com NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. or its in all Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. © 2010 Exar Corporation Page 17 of 17 Rev. 1.0.0