FUJITSU SEMICONDUCTOR DATA SHEET DS501-00004-1v0-E Memory FRAM 1 M Bit (64 K × 16) MB85R1002A ■ DESCRIPTIONS The MB85R1002A is an FRAM (Ferroelectric Random Access Memory) chip consisting of 65,536 words × 16 bits of nonvolatile memory cells fabricated using ferroelectric process and silicon gate CMOS process technologies. The MB85R1002A is able to retain data without using a back-up battery, as is needed for SRAM. The memory cells used in the MB85R1002A can be used for 1010 read/write operations, which is a significant improvement over the number of read and write operations supported by Flash memory and E2PROM. The MB85R1002A uses a pseudo-SRAM interface that is compatible with conventional asynchronous SRAM. ■ FEATURES • • • • • • • Bit configuration Read/write endurance Operating power supply voltage Operating temperature range Data retention LB and UB data byte control Package : 65,536 words × 16 bits : 1010 times : 3.0 V to 3.6 V : − 40 °C to + 85 °C : 10 years ( + 55 °C) : 48-pin plastic TSOP (1) Copyright©2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2011.7 MB85R1002A ■ PIN ASSIGNMENTS (TOP VIEW) A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE CE2 VSS UB LB VDD NC A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC VSS I/O16 I/O8 I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 VDD I/O12 I/O4 I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 OE VSS CE1 A0 (FPT-48P-M48) ■ PIN DESCRIPTIONS Pin Number Pin Name 1 to 8, 18 to 25 A0 to A15 29 to 36, 38 to 45 I/O1 to I/O16 Data Input/Output pins 26 CE1 Chip Enable 1 Input pin 12 CE2 Chip Enable 2 Input pin 11 WE Write Enable Input pin 28 OE Output Enable Input pin 14, 15 LB, UB 16, 37 VDD Supply Voltage pins Connect all two pins to the power supply. 13, 27, 46 VSS Ground pins Connect all three pins to ground. 9, 10, 17, 47, 48 NC No Connect pins 2 Functional Description Address Input pins Data Byte Control Input pins DS501-00004-1v0-E MB85R1002A ■ BLOCK DIAGRAM Address Latch Row Decoder A0 A15 FRAM Array 65,536 × 16 Column Decoder S/A intWE intOE CE2 CE1 WE OE LB UB I/O1 to I/O8 I/O9 to I/O16 I/O16 I/O9 I/O8 I/O1 DS501-00004-1v0-E 3 MB85R1002A ■ FUNCTIONAL TRUTH TABLE Mode Standby Precharge Supply Current Hi-Z Hi-Z Standby (ISB) L Data Output Data Output L H Data Output Hi-Z H L Hi-Z Data Output L L Data Output Data Output L H Data Output Hi-Z H L Hi-Z Data Output L L Data Output Data Output L H Data Output Hi-Z H L Hi-Z Data Output L L Data Input Data Input L H Data Input Hi-Z H L Hi-Z Data Input L L Data Input Data Input L H Data Input Hi-Z H L Hi-Z Data Input L L Data Input Data Input L H Data Input Hi-Z H L Hi-Z Data Input WE OE LB UB H X X X X X X L X X X X X X H H X X X X X X H H L H L Read L L H H H L H L H Write L Write (Pseudo-SRAM, WE control*2) I/O9 to I/O16 CE2 H Read (Pseudo-SRAM, OE control*1) I/O1 to I/O8 CE1 L L H H H Operation (ICC) Note: L = VIL, H = VIH, X can be either VIL or VIH, Hi-Z = High Impedance : Latch address and latch data at falling edge, : Latch address and latch data at rising edge *1 : OE control of the Pseudo-SRAM means the valid address at the falling edge of OE to read. *2 : WE control of the Pseudo-SRAM means the valid address and data at the falling edge of WE to write. 4 DS501-00004-1v0-E MB85R1002A ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Min Max Unit Power Supply Voltage* VCC −0.5 +4.0 V Input Pin Voltage* VIN −0.5 VCC + 0.5 ( ≤ 4.0) V VOUT −0.5 VCC + 0.5 ( ≤ 4.0) V TA −40 +85 o TSTG −40 +125 o Output Pin Voltage* Operating Temperature Storage Temperature C C * : All voltages are referenced to VSS = 0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Min Typ Max Unit Power Supply Voltage* VCC 3.0 3.3 3.6 V High Level Input Voltage* VIH VCC × 0.8 ⎯ VCC + 0.5 ( ≤ 4.0) V Low Level Input Voltage* VIL −0.5 ⎯ +0.6 TA − 40 ⎯ +85 Operating Temperature V o C * : All voltages are referenced to VSS = 0 V. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. DS501-00004-1v0-E 5 MB85R1002A ■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics Parameter Symbol Condition (within recommended operating conditions) Value Unit Min Typ Max Input Leakage Current |ILI| VIN = 0 V to VCC ⎯ ⎯ 10 μA Output Leakage Current |ILO| VOUT = 0 V to VCC, CE1 = VIH or OE = VIH ⎯ ⎯ 10 μA Operating Power Supply Current ICC CE1 = 0.2 V, CE2 = VCC − 0.2 V, Iout = 0 mA*1 ⎯ 10 15 mA ⎯ 10 50 μA VCC × 0.8 ⎯ ⎯ V ⎯ ⎯ 0.4 V CE1 ≥ VCC − 0.2 V CE2 ≤ 0.2 V*2 Standby Current ISB OE ≥ VCC − 0.2 V, WE ≥ VCC − 0.2 V*2 LB ≥ VCC − 0.2 V, UB ≥ VCC − 0.2 V*2 High Level Output Voltage VOH IOH = − 1.0 mA Low Level Output Voltage VOL IOL = 2.0 mA *1 : During the measurement of ICC , the Address, Data In were taken to only change once per active cycle. Iout : output current *2 : All pins other than setting pins should be input at the CMOS level voltages such as H ≥ VCC − 0.2 V, L ≤ 0.2 V. 6 DS501-00004-1v0-E MB85R1002A 2. AC Characteristics • AC Test Conditions Supply Voltage Operating Temperature Input Voltage Amplitude Input Rising Time Input Falling Time Input Evaluation Level Output Evaluation Level Output Impedance : 3.0 V to 3.6 V : −40 oC to +85 oC : 0.3 V to 2.7 V : 5 ns : 5 ns : 2.0 V / 0.8 V : 2.0 V / 0.8 V : 50 pF (1) Read Cycle (within recommended operating conditions) Parameter Symbol Value Min Max Unit Read Cycle time tRC 150 ⎯ ns CE1 Active Time tCA1 120 ⎯ ns CE2 Active Time tCA2 120 ⎯ ns OE Active Time tRP 120 ⎯ ns LB, UB Active Time tBP 120 ⎯ ns Precharge Time tPC 20 ⎯ ns Address Setup Time tAS 0 ⎯ ns Address Hold Time tAH 50 ⎯ ns OE Setup Time tES 0 ⎯ ns LB, UB Setup Time tBS 5 ⎯ ns Output Data Hold time tOH 0 ⎯ ns Output Set Time tLZ 30 ⎯ ns CE1 Access Time tCE1 ⎯ 100 ns CE2 Access Time tCE2 ⎯ 100 ns OE Access Time tOE ⎯ 100 ns Output Floating Time tOHZ ⎯ 20 ns DS501-00004-1v0-E 7 MB85R1002A (2) Write Cycle (within recommended operating conditions) Parameter Symbol Value Min Max Unit Write Cycle Time tWC 150 ⎯ ns CE1 Active Time tCA1 120 ⎯ ns CE2 Active Time tCA2 120 ⎯ ns LB, UB Active Time tBP 120 ⎯ ns Precharge Time tPC 20 ⎯ ns Address Setup Time tAS 0 ⎯ ns Address Hold Time tAH 50 ⎯ ns LB, UB Setup Time tBS 5 ⎯ ns Write Pulse Width tWP 120 ⎯ ns Data Setup Time tDS 0 ⎯ ns Data Hold Time tDH 50 ⎯ ns Write Setup Time tWS 0 ⎯ ns 3. Pin Capacitance Parameter Input Capacitance Output Capacitance 8 Symbol CIN COUT Condition VIN = VOUT = 0 V, f = 1 MHz, TA = + 25 oC Value Unit Min Typ Max ⎯ ⎯ 10 pF ⎯ ⎯ 10 pF DS501-00004-1v0-E MB85R1002A ■ TIMING DIAGRAMS 1. Read Cycle Timing (CE1, CE2 Control) tRC tCA1 CE1 tPC CE2 tCA2 tBP tBS LB, UB tAS A0 to A15 tAH Valid H or L tES tRP OE tCE1, tCE2 tOHZ tOH Hi-Z tLZ I/O1 to I/O16 Valid Invalid Invalid 2. Read Cycle Timing (OE Control) tCA1 CE1 tCA2 CE2 tBP tBS LB, UB tAS A0 to A15 tAH Valid H or L tRC OE tPC tRP tOHZ tOE tOH tLZ I/O1 to I/O16 Invalid DS501-00004-1v0-E Hi-Z Valid Invalid 9 MB85R1002A 3. Write Cycle Timing (CE1, CE2 Control) tWC tCA1 CE1 CE2 tPC tCA2 tBP tBS LB, UB tAH tAS A0 to A15 Valid H or L tWS tWP WE tDS tDH Hi-Z Valid Data In H or L 4. Write Cycle Timing (WE Control) tCA1 CE1 tCA2 CE2 tBP tBS LB, UB tAS A0 to A15 tAH Valid H or L tWC tWP tPC WE tDS tDH Hi-Z Data In 10 Valid H or L DS501-00004-1v0-E MB85R1002A ■ POWER ON/OFF SEQUENCE tPD tR tPU VCC VCC CE2 CE2 3.0 V 3.0 V VIH (Min) VIH (Min) 1.0 V 1.0 V VIL (Max) VIL (Max) 0V 0V CE2 ≤ 0.2 V CE1 > VCC × 0.8* CE1 > VCC × 0.8* CE1 : Don't Care CE1 CE1 * : CE1 (Max) < VCC + 0.5 V Notes: • Use either of CE1 or CE2, or both for disable control of the device. • Because turning the power on from an intermediate level may cause malfunctions, when the power is turned on, VCC is required to be started from 0 V. • If the device does not operate within the specified conditions of read cycle, write cycle, power on/off sequence, memory data can not be guaranteed. • When turning the power on or off, it is recommended that CE2 is connected to ground to prevent unexpected writing. (within recommended operating conditions) Parameter Symbol CE1 LEVEL hold time for Power OFF Value Unit Min Typ Max tPD 85 ⎯ ⎯ ns CE1 LEVEL hold time for Power ON tPU 85 ⎯ ⎯ ns Power supply rising time tR 0.05 ⎯ 200 ms ■ NOTES ON USE After the IR reflow completed, it is not guaranteed to hold the data written prior to the IR reflow. DS501-00004-1v0-E 11 MB85R1002A ■ ORDERING INFOMATION Part number MB85R1002ANC-GE1 12 Package 48-pin plastic TSOP(1) (FPT-48P-M48) DS501-00004-1v0-E MB85R1002A ■ PACKAGE DIMENSIONS 48-pin plastic TSOP Lead pitch 0.50 mm Package width × package length 12.00 mm × 12.40 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.20 mm MAX Weight 0.36 g (FPT-48P-M48) Note 1) # : Resin protrusion. (Each side : +0.15 (.006) Max). Note 2) * : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. 48-pin plastic TSOP (FPT-48P-M48) 0.10±0.05 (.004±.002) (STAND OFF) 1 48 0.50(.020) INDEX #12.00±0.10 (.472±.004) +0.05 0.22 –0.04 (.009 +.002 –.002 ) 24 0.10(.004) M 25 1.13±0.07 (.044±.003) (MOUNTING HEIGHT) Details of A part 14.00±0.20(.551±.008) *12.40±0.10(.488±.004) 0.25(.010) +0.05 0.145 –0.03 (.006 +.002 –.001 ) C 0.08(.003) A 2010 FUJITSU SEMICONDUCTOR LIMITED F48048Sc-1-1 0.60±0.15 (.024±.006) 0~8 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ DS501-00004-1v0-E 13 MB85R1002A MEMO 14 DS501-00004-1v0-E MB85R1002A MEMO DS501-00004-1v0-E 15 MB85R1002A FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://sg.fujitsu.com/semiconductor/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fss/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 902 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fsk/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fsp/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department