633KB - Fujitsu

FUJITSU SEMICONDUCTOR
DATA SHEET
DS501-00024-3v1-E
Memory FRAM
4 M (256 K × 16) Bit
MB85R4M2T
 DESCRIPTIONS
The MB85R4M2T is an FRAM (Ferroelectric Random Access Memory) chip consisting of 262,144 words
× 16 bits of nonvolatile memory cells fabricated using ferroelectric process and silicon gate CMOS process
technologies.
The MB85R4M2T is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85R4M2T can be used for 1013 read/write operations, which is a
significant improvement over the number of read and write operations supported by Flash memory and
E2PROM. The MB85R4M2T uses a pseudo-SRAM interface.
 FEATURES
• Bit configuration
• LB and UB data byte control
• Read/write endurance
• Data retention
• Operating power supply voltage
• Low power operation
: 262,144 words × 16 bits
: Available Configuration of 524,288 words × 8 bits
: 1013 times / 16 bits
: 10 years ( + 85 °C)
: 1.8 V to 3.6 V
: Operating power supply current 20 mA (Max)
Standby current 150 μA (Max)
Sleep current 20 μA (Max)
• Operation ambient temperature range : − 40 °C to + 85 °C
• Package
: 44-pin plastic TSOP (FPT-44P-M34)
RoHS compliant
Copyright 2013-2015 FUJITSU SEMICONDUCTOR LIMITED
2015.5
MB85R4M2T
 PIN ASSIGNMENTS
(TOP VIEW)
A4
A3
A2
A1
A0
/ CE
I/ O0
I/ O1
I/ O2
I/ O3
VDD
VSS
I/ O4
I/ O5
I/ O6
I/ O7
/ WE
A17
A16
A15
A14
A13
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A5
A6
A7
/ OE
/ UB
/ LB
I/ O15
I/ O14
I/ O13
I/ O12
VSS
VDD
I/ O11
I/ O10
I/ O9
I/ O8
/ ZZ
A8
A9
A10
A11
A12
FPT- 44P- M34
2
DS501-00024-3v1-E
MB85R4M2T
 PIN DESCRIPTIONS
Pin Number
1 to 5, 18 to 22,
23 to 27, 42 to 44
Pin Name
A0 to A17
7 to 10, 13 to 16,
29 to 32, 35 to 38
6
I/O0 to I/O15
17
/WE
41
/OE
28
/ZZ
39, 40
/LB, /UB
11, 33
VDD
12, 34
VSS
/CE
Functional Description
Address Input pins
Select 262,144 words in FRAM memory array by 18 Address
Input pins. When these address inputs are changed during /CE
equals to “L” level, reading operation of data selected in the
address after transition will start.
Data Input/Output pins
These are 16 bits bidirectional pins for reading and writing.
Chip Enable Input pin
In case the /CE equals to “L” level and /ZZ equals to “H” level,
device is activated and enables to start memory access.
In writing operation, input data from I/O pins are latched at the
rising edge of /CE and written to FRAM memory array.
Write Enable Input pin
Writing operation starts at the falling edge of /WE.
Input data from I/O pins are latched at the rising edge of /WE
and written to FRAM memory array.
Output Enable Input pin
When the /OE is “L” level, valid data are output to data bus.
When the /OE is “H” level, all I/O pins become high impedance
(High-Z) state.
Sleep Mode Input pin
When the /ZZ becomes to “L” level, device transits to the Sleep
Mode.
During reading and writing operation, /ZZ pin shall be hold “H”
level.
Lower/Upper byte Control Input pins
In case /LB or /UB equals to “L” level, it enables
reading/writing operation of I/O0 to I/O7 or I/O8 to I/O15
respectively. In case /LB and /UB equal to “H” level, all I/O
pins become High-Z state.
Supply Voltage pins
Connect all two pins to the power supply.
Ground pins
Connect all two pins to ground.
Note: Please refer to the timing diagram for functional description of each pin.
DS501-00024-3v1-E
3
MB85R4M2T
 BLOCK DIAGRAM
A0 to A17
Row Decoder
Address
/ZZ
Control circuits
/CE
/WE
FRAM Array
262,144×16
Column Decoder / Sense Amp.
/ Write Amp.
/OE
I/O0 to I/O15
/UB
/LB
 FUNCTIONAL TRUTH TABLE
Operation Mode
Sleep
Standby
Read
Address Access Read
Write(/CE Control)*1
Write(/WE Control)*1*2
Address Access Write*1*3
Pre-charge
Note: H= “H” level,
L= “L” level,
/CE
×
H
↓
L
↓
L
L
↑
/WE
×
×
H
H
L
↓
↓
×
↑= Rising edge,
/OE
×
×
L
L
×
×
×
×
A0 to A17
×
×
H or L
↑ or ↓
H or L
H or L
↑ or ↓
×
↓= Falling edge,
/ZZ
L
H
H
H
H
H
H
H
×= H, L, ↓ or ↑
*1: In writing cycle, input data is latched at early rising edge of /CE or /WE.
*2: In writing sequence of /WE control, there exists time with data output of reading cycle at the falling
edge of /CE.
*3: In writing sequence of Address Access Write, there exists time with data output of reading cycle at the
address transition.
4
DS501-00024-3v1-E
MB85R4M2T
 State Transition Diagram
/CE=L, /ZZ=H
RD/WR
Operation
Standby
Power Up
/CE=H,/ZZ=H
/ZZ=H
/ZZ=L
Sleep
 FUNCTIONAL TRUTH TABLE OF BYTE CONTROL
Operation Mode
Read(Without Output)
Read(I/O8 to I/O15)
Read(I/O0 to I/O7)
Read(I/O0 to I/O15)
Write(I/O8 to I/O15)
Write(I/O0 to I/O7)
Write(I/O0 to I/O15)
/WE
H
H
/OE
H
×
H
L
↑
×
Note: H= “H” level,
L= “L” level,
Hi-Z= High Impedance
/LB
×
H
H
L
L
H
L
L
↑= Rising edge,
/UB
×
H
L
H
L
L
H
L
I/O0 to I/O7
Hi-Z
Hi-Z
Hi-Z
Output
Output
×
Input
Input
↓= Falling edge,
I/O8 to I/O15
Hi-Z
Hi-Z
Output
Hi-Z
Output
Input
×
Input
×= H, L, ↓ or ↑
In case the byte reading or writing are not selected, /LB and /UB pins shall be connected to GND pin.
DS501-00024-3v1-E
5
MB85R4M2T
 ABABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage*
Input Pin Voltage*
Output Pin Voltage*
Operation Ambient Temperature
Storage Temperature
Symbol
VDD
VIN
VOUT
TA
Tstg
Rating
Min
− 0.5
− 0.5
− 0.5
− 40
− 55
Max
+ 4.0
VDD + 0.5 ( ≤ 4.0)
VDD + 0.5 ( ≤ 4.0)
+ 85
+ 125
Unit
V
V
V
°C
°C
* : All voltages are referenced to VSS (ground 0 V).
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage,
current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these
ratings.
 RECOMMENDED OPERATING CONDITIONS
Parameter
*1
Power Supply Voltage
Operation Ambient Temperature*2
Symbol
VDD
TA
Min
1.8
− 40
Value
Typ
3.3
―
Max
3.6
+ 85
Unit
V
°C
*1: All voltages are referenced to VSS (ground 0 V).
*2: Ambient temperature when only this device is working. Please consider it to be the almost same as the
package surface temperature.
WARNING: The recommended operating conditions are required in order to ensure the normal
operation of the semiconductor device. All of the device's electrical characteristics are
warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition
ranges. Operation outside these ranges may adversely affect reliability and could result
in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not
represented on the data sheet. Users considering application outside the listed
conditions are advised to contact their representatives beforehand.
6
DS501-00024-3v1-E
MB85R4M2T
 ELECTRICAL CHARACTERISTICS
1.
DC Characteristics
Parameter
Symbol
Condition
(within recommended operating conditions)
Value
Unit
Min
Typ
Max
Input Leakage
Current
Output Leakage
Current
Operating Power
Supply Current*1
|ILI|
VIN = 0V to VDD
―
―
5
μA
|ILO|
VOUT = 0V to VDD
/CE = VIH or /OE = VIH
―
―
5
μA
IDD
/CE = 0.2 V, Iout = 0 mA
―
15
20
mA
Standby Current
ISB
―
30
150
μA
Sleep Current
IZZ
―
5
20
μA
High Level Input
Voltage
Low Level Input
Voltage
High Level
Output Voltage
Low Level Output
Voltage
/ZZ ≥ VDD − 0.2V
/CE, /WE, /OE ≥ VDD − 0.2V
/LB, /UB ≥ VDD − 0.2V
Others ≥ VDD − 0.2V or ≤ 0.2V
/ZZ = VSS
/CE, /WE, /OE ≥ VDD − 0.2V
/LB, /UB ≥ VDD − 0.2V
Others ≥ VDD − 0.2V or ≤ 0.2V
VIH
VDD = 1.8V to 3.6V
VDD × 0.8
―
VDD + 0.3
V
VIL
VDD = 1.8V to 3.6V
− 0.3
―
VDD × 0.17
V
VDD × 0.8
―
―
VDD − 0.2
―
―
―
―
0.4
―
―
0.2
VOH1
VOH2
VOL1
VOL2
VDD = 2.7V to 3.6V
IOH = − 1.0mA
VDD = 1.8V to 2.7V
IOH = − 100μA
VDD = 2.7V to 3.6V
IOL = 2.0mA
VDD = 1.8V to 2.7V
IOL = 150μA
V
V
*1: During the measurement of IDD, all Address and I/O were taken to only change once per active cycle.
Iout : output current
DS501-00024-3v1-E
7
MB85R4M2T
2. AC Characteristics
・AC Test Conditions
Power Supply Voltage
Operation Ambient Temperature
Input Voltage Amplitude
Input Rising Time
Input Falling Time
Input Evaluation Level
Output Evaluation Level
Output Load Capacitance
: 1.8 V to 3.6 V
: − 40 °C to + 85 °C
: 0 V / VDD
: 3 ns
: 3 ns
: VDD/2
: VDD/2
: 30 pF
(1) Read Cycle
Parameter
Read Cycle time
/CE Access Time
Address Access Time
/OE Output Data Hold time
Output Data Hold time
/CE Active Time
Pre-charge Time
/LB, /UB Access Time
Address Setup Time
Address Hold Time
/CE↑ to Address Transition time＊1
/OE Access Time
/CE Output Floating Time*1
/OE Output Floating Time
/LB, /UB Output Floating Time
Address Transition Time*1
Symbol
tRC
tCE
tAA
tOH
tOAH
tCA
tPC
tBA
tAS
tAH
tCAH
tOE
tHZ
tOHZ
tBHZ
tAX
Value
(VDD=1.8V to 2.7V)
Min
Max
185
―
―
95
―
185
0
―
20
―
95
―
90
―
―
35
0
―
95
―
0
―
―
―
―
―
―
35
10
10
10
15
Value
(VDD=2.7V to 3.6V)
Min
Max
150
―
―
75
―
150
0
―
20
―
75
―
75
―
―
20
0
―
75
―
0
―
―
―
―
―
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
―
ns
20
10
10
10
15
ns
ns
ns
ns
ns
*1: Same parameters with the Write cycle.
8
DS501-00024-3v1-E
MB85R4M2T
(2) Write Cycle
Parameter
Write Cycle Time
/CE Active Time
/CE↓ to /WE↑ Time
Pre-charge Time
Write Pulse Width
Address Setup Time
Address Hold Time
/WE↓ to /CE↑ Time
Address Transition to /WE↑ Time
/WE↑ to Address Transition Time
/LB, /UB Setup Time
/LB, /UB Hold Time
Data Setup Time
Data Hold Time
/WE Output Floating Time
/WE Output Access Time*1
Write Setup Time*1
Write Hold Time*1
Symbol
tWC
tCA
tCW
tPC
tWP
tAS
tAH
tWLC
tAWH
tWHA
tBS
tBH
tDS
tDH
tWZ
tWX
tWS
tWH
Value
(VDD=1.8V to 2.7V)
Min
Max
185
―
95
―
95
―
90
―
20
―
0
―
95
―
20
―
185
―
0
―
2
―
0
―
10
―
0
―
―
10
10
―
0
―
0
―
Value
(VDD=2.7V to 3.6V)
Min
Max
150
―
75
―
75
―
75
―
20
―
0
―
75
―
20
―
150
―
0
―
2
―
0
―
10
―
0
―
―
10
10
―
0
―
0
―
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*1: Writing operation applies “Write Cycle Timing 1” or “Write Cycle Timing 2” by the relation of /CE and
/WE timing. The values of tWX, tWS and tWH are defined by these operations. The conditions of tWS and
tWH are not checked at shipping test.
(3) Power ON/OFF Sequence and Sleep Mode Cycle
Parameter
/CE level hold time for Power ON
/CE level hold time for Power OFF
Power supply rising time
Power supply falling time
/ZZ active time
Sleep mode enable time
/CE level hold time for Sleep mode release
DS501-00024-3v1-E
Symbol
tPU
tPD
tVR
tVF
tZZL
tZZEN
tZZEX
Value
Min
450
85
50
100
1
―
450
Max
―
―
―
―
―
0
―
Unit
μs
ns
μs/V
μs/V
μs
μs
μs
9
MB85R4M2T
3.
Pin Capacitance
Parameter
Symbol
Input Capacitance
Input/Output Capacitance (I/O pin)
/ZZ Pin Input Capacitance
CIN
CI/O
CZZ
Condition
VDD = 3.3 V,
f = 1 MHz, TA = + 25 °C
Value
Min
―
―
―
Typ
―
―
―
Max
6
8
8
Unit
pF
pF
pF
 AC Test Load Circuit
VDD
1.2k
Output
30pF
10
0.95k
DS501-00024-3v1-E
MB85R4M2T
 TIMING DIAGRAMS
1.
Read Cycle Timing 1 (/CE Control)
tRC
t AH
tCAH
Val id Add ress
A0 to A17
tOH
tCA
t AS
/ CE
tPC
tHZ
tCE
tOE
/ OE
tOHZ
tBA
/ LB,/ UB
tBHZ
I/ O0 to I/ O15
Val id Out put Da ta
XXX : H or L
2.
Read Cycle Timing 2 (Address Access)
t PC
t AS
A0 to A17
t AX
t AH
t RC
Valid Address
t AX
tCAH
Valid Address
Valid Address
t AA
t AA
t CE
t RC
tOH
/ CE
t HZ
t OE
/ OE
tOH Z
t BA
/ LB,/ UB
t BHZ
t OAH
t OAH
I/ O0 to I/ O15
Valid Out put Data
Valid Out put Data
Valid Out put Data
XXX : H or L
DS501-00024-3v1-E
11
MB85R4M2T
3.
Write Cycle Timing 1 (/WE Control)
tWC
t AH
tCA
A0 to A17
Valid Address
tCAH
tCW
t AS
tWLC
t AS
tPC
/CE
tWHA
tWZ
/WE
tBS
tBH
tWX
tWP
/LB, /UB
tDH
tDS
tHZ
I/O0 to I/O15
Invalid Output Data
Valid Input Data
Invalid Output Data
XXX : H or L
* : In case the /OE is “L” level, invalid data are output to data bus.
* : In case the /OE is “L” level, any bus conflict of input and output data shall not occur.
4.
Write Cycle Timing 2 (/CE Control)
tWC
t AS
t AS
t AH
A0 to A17
Val id Address
tCAH
tCA
tPC
/ CE
tWS
tWH
/ WE
tBH
tBS
/ LB, / UB
tDS
tDH
I/ O0 to I/ O15
Valid Input Data
XXX : H or L
12
DS501-00024-3v1-E
MB85R4M2T
5.
Write Cycle Timing 3 (Address Access and /WE Control)
t PC
t AS
t AX
t AH
Valid Address
A0 to A17
t AX
t WC
Valid Address
t CAH
tWC
Valid Address
t HZ
/ CE
t WP
t WHA
t WHA
t AWH
tWHA
t AWH
/ WE
t BH
t BS
/ LB,/ UB
t WX
t DS t DH
t WZ
t WP
t WZ
t WX
tWP
t DS t DH
t WZ
t DS
t WX
t DH
I/ O0 to I/ O15
Valid Out put Data
Valid Input Data
Valid Input Data
Invalid Out put Data
Invalid Out put Data
Invalid Out put Data
Invalid Out put Data
XXX : H or L
* : In case t he / OE is ・L・level, invalid dat a are out put to data bus .
* : In case t he / OE is ・L・level, any bus c onf lict of inpu t and out put data shal l not occur.
6.
Sleep Mode Timing
tPC
t ZZEX
t ZZEN
/ CE
/ WE
t ZZL
/ ZZ
I/ O0 to I/ O15
DS501-00024-3v1-E
13
MB85R4M2T
 POWER ON/OFF SEQUENCE
tPD
tVF
tVR
tPU
VDD
VDD
VDD(Min)
VIH(Min)
VIH(Min)
1.0V
VIL(Max)
VIL(Max)
VSS
VSS
/CE
/CE >VDD×0.8*
/CE Don’t Care
/CE>VDD×0.8*
* : /CE (Max) < VDD+0.3V
 FRAM CHARACTERISTICS
Item
Read/Write Endurance*1
Data Retention*2
Min
1013
10
Max
―
―
Unit
Times/16 bits
Years
Parameter
Operation Ambient Temperature TA = + 85 °C
Operation Ambient Temperature TA = + 85 °C
*1: Total number of reading and writing defines the minimum value of endurance, as an FRAM memory
operates with destructive readout mechanism.
*2: Minimum values define retention time of the first reading/writing data right after shipment, and these
values are calculated by qualification results.
 NOTE ON USE
• We recommend programming of the device after reflow. Data written before reflow cannot be
guaranteed.
14
DS501-00024-3v1-E
MB85R4M2T
 ESD AND LATCH-UP
Test
ESD HBM (Human Body Model)
JESD22-A114 compliant
ESD MM (Machine Model)
JESD22-A115 compliant
ESD CDM (Charged Device Model)
JESD22-C101 compliant
Latch-Up (I-test)
JESD78 compliant
Latch-Up (Vsupply overvoltage test)
JESD78 compliant
Latch-Up (Current Method)
Proprietary method
Latch-Up (C-V Method)
Proprietary method
DUT
Value
≥ |2000 V|
≥ |200 V|
―
MB85R4M2TFN-G-ASE1
―
―
―
≥ |200 V|
・Current method of Latch-Up Resistance Test
Note: The voltage VIN is increased gradually and the current IIN of 300 mA at maximum shall flow.
Confirm the latch up does not occur under IIN =±300 mA.
In case the specific requirement is specified for I/O and IIN cannot be 300 mA, the voltage shall be
increased to the level that meets the specific requirement.
DS501-00024-3v1-E
15
MB85R4M2T
・C-V method of Latch-Up Resistance Test
Note: Charge voltage alternately switching 1 and 2 approximately 2 sec intervals. This switching process is
considered as one cycle.
Repeat this process 5 times. However, if the latch-up condition occurs before completing 5times, this
test must be stopped immediately.
 REFLOW CONDITIONS AND FLOOR LIFE
[ JEDEC MSL ] : Moisture Sensitivity Level 3 (ISP/JEDEC J-STD-020D)
 CURRENT STATUS ON CONTAINED RESTRICTED SUBSTANCES
This product complies with the regulations of REACH Regulations, EU RoHS Directive and China RoHS.
16
DS501-00024-3v1-E
MB85R4M2T
 ORDERING INFORMATION
Part Number
MB85R4M2TFN-G-ASE1
Package
Shipping form
Minimum shipping
quantity
44-pin plastic TSOP
(FPT-44P-M34)
Tray
―*
*: Please contact our sales office about minimum shipping quantity.
DS501-00024-3v1-E
17
MB85R4M2T
 PACKAGE DIMENSIONS
Lead pitch
0.8mm
Package width ×
package length
10.16 × 18.41mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.2mm
Weight
0.46 g
44-pin plastic TSOP
(FPT-44P-M34)
44-pin plastic TSOP
(FPT-44P-M34)
11.76±0.20
*
(10.76)
10.16±0.10
[23]
10.16±0.10
[44]
(0.50)
Note 1) # : Resin protrusion.(Each side:+0.15 Max).
Note 2) * : These dimensions do not include resin protrusion.
Note3)Pins width and pins thickness include plating thickness.
Note4)Pins width do not include tie bar cutting remainder.
LEAD No. [1]
(0.50)
INDEX
[22]
+0.075
(0.29)
1.20 MAX
18.41±0.10
0.45～0.75
0.125 –0.035
#
0.80TYP
0.30+0.10
–0.05
2013 FUJITSU SEMICONDUCTOR LIMITED F44025S-c-2-3
18
0.35+0.10
–0.05
0.05 MIN
0.10 MAX
(0.805)
0.25TYP
0～8°
Dimensions in mm.
Note : The values in parentheses are reference values.
DS501-00024-3v1-E
MB85R4M2T
 MARKING
[MB85R4M2TFN-G-ASE1]
[FPT-44P-M34]
DS501-00024-3v1-E
19
MB85R4M2T
 MAJOR CHANGES IN THIS EDITION
A change on a page is indicated by a vertical line drawn on the left side of that page.
Page
Section
16
 CURRENT STATUS ON CONTAINED
RESTRICTED SUBSTANCES
 PACKAGE DIMENSIONS
18
20
Change Results
Deleted the URL info.
Add Weight.
DS501-00024-3v1-E
MB85R4M2T
DS501-00024-3v1-E
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22
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MB85R4M2T
DS501-00024-3v1-E
23
MB85R4M2T
FUJITSU SEMICONDUCTOR LIMITED
Shin-Yokohama Chuo Building, 2-100-45 Shin-Yokohama,
Kohoku-ku, Yokohama, Kanagawa 222-0033, Japan
http://jp.fujitsu.com/fsl/en/
All Rights Reserved.
FUJITSU SEMICONDUCTOR LIMITED, its subsidiaries and affiliates (collectively, "FUJITSU SEMICONDUCTOR")
reserves the right to make changes to the information contained in this document without notice. Please contact your
FUJITSU SEMICONDUCTOR sales representatives before order of FUJITSU SEMICONDUCTOR device.
Information contained in this document, such as descriptions of function and application circuit examples is presented
solely for reference to examples of operations and uses of FUJITSU SEMICONDUCTOR device. FUJITSU
SEMICONDUCTOR disclaims any and all warranties of any kind, whether express or implied, related to such
information, including, without limitation, quality, accuracy, performance, proper operation of the device or
non-infringement. If you develop equipment or product incorporating the FUJITSU SEMICONDUCTOR device based on
such information, you must assume any responsibility or liability arising out of or in connection with such information or
any use thereof. FUJITSU SEMICONDUCTOR assumes no responsibility or liability for any damages whatsoever arising
out of or in connection with such information or any use thereof.
Nothing contained in this document shall be construed as granting or conferring any right under any patents, copyrights, or
any other intellectual property rights of FUJITSU SEMICONDUCTOR or any third party by license or otherwise, express
or implied. FUJITSU SEMICONDUCTOR assumes no responsibility or liability for any infringement of any intellectual
property rights or other rights of third parties resulting from or in connection with the information contained herein or use
thereof.
The products described in this document are designed, developed and manufactured as contemplated for general use
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless
extremely high levels of safety is secured, could lead directly to death, personal injury, severe physical damage or other
loss (including, without limitation, use in nuclear facility, aircraft flight control system, air traffic control system, mass
transport control system, medical life support system and military application), or (2) for use requiring extremely high
level of reliability (including, without limitation, submersible repeater and artificial satellite). FUJITSU
SEMICONDUCTOR shall not be liable for you and/or any third party for any claims or damages arising out of or in
connection with above-mentioned uses of the products.
Any semiconductor devices fail or malfunction with some probability. You are responsible for providing adequate designs
and safeguards against injury, damage or loss from such failures or malfunctions, by incorporating safety design measures
into your facility, equipments and products such as redundancy, fire protection, and prevention of overcurrent levels and
other abnormal operating conditions.
The products and technical information described in this document are subject to the Foreign Exchange and Foreign Trade
Control Law of Japan, and may be subject to export or import laws or regulations in U.S. or other countries. You are
responsible for ensuring compliance with such laws and regulations relating to export or re-export of the products and
technical information described herein.
All company names, brand names and trademarks herein are property of their respective owners.
Edited: System Memory Business Division