Brushless DC Motor Flash Type 8-Bit MCU HT45FM2C Revision: V1.10 Date: ������������ May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Table of Contents Features............................................................................................................. 7 CPU Features.......................................................................................................................... 7 Peripheral Features.................................................................................................................. 7 General Description.......................................................................................... 8 Block Diagram................................................................................................... 8 Pin Assignment................................................................................................. 9 Pin Description................................................................................................11 Absolute Maximum Ratings........................................................................... 14 D.C. Characteristics........................................................................................ 14 A.C. Characteristics ....................................................................................... 15 A/D Converter Characteristics....................................................................... 16 D/A Converter Characteristics....................................................................... 16 Operational Amplifier Characteristics.......................................................... 17 Comparator Electrical Characteristics......................................................... 17 Power on Reset Electrical Characteristics................................................... 17 System Architecture....................................................................................... 18 Clocking and Pipelining.......................................................................................................... 18 Program Counter.................................................................................................................... 19 Stack...................................................................................................................................... 20 Arithmetic and Logic Unit – ALU............................................................................................ 20 Flash Program Memory.................................................................................. 21 Structure................................................................................................................................. 21 Special Vectors...................................................................................................................... 21 Look-up Table......................................................................................................................... 21 Table Program Example......................................................................................................... 22 In Circuit Programming.......................................................................................................... 23 RAM Data Memory.......................................................................................... 24 Structure................................................................................................................................. 24 Special Function Register Description......................................................... 26 Indirect Addressing Registers – IAR0, IAR1.......................................................................... 26 Memory Pointers – MP0, MP1............................................................................................... 26 Bank Pointer – BP.................................................................................................................. 27 Accumulator – ACC................................................................................................................ 27 Program Counter Low Register – PCL................................................................................... 27 Look-up Table Registers – TBLP, TBHP, TBLH...................................................................... 28 Status Register – STATUS..................................................................................................... 28 Rev. 1.10 2 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU EEPROM Data Memory................................................................................... 31 EEPROM Data Memory Structure......................................................................................... 31 EEPROM Registers............................................................................................................... 31 Reading Data from the EEPROM.......................................................................................... 32 Writing Data to the EEPROM................................................................................................. 33 Write Protection...................................................................................................................... 33 EEPROM Interrupt................................................................................................................. 33 Programming Consideration.................................................................................................. 33 Programming Examples......................................................................................................... 34 Oscillator......................................................................................................... 35 Oscillator Overview................................................................................................................ 35 System Clock Configurations................................................................................................. 35 Internal 20MHz RC Oscillator – HIRC.................................................................................... 36 Internal 32kHz Oscillator – LIRC............................................................................................ 36 Supplementary Clocks........................................................................................................... 36 Operating Modes and System Clocks.......................................................... 37 System Clocks....................................................................................................................... 37 System Operation Modes....................................................................................................... 39 Control Register..................................................................................................................... 40 Fast Wake-up......................................................................................................................... 41 Operating Mode Switching and Wake-up............................................................................... 43 NORMAL Mode to SLOW Mode Switching............................................................................ 43 SLOW Mode to NORMAL Mode Switching............................................................................ 43 Entering the SLEEP Mode..................................................................................................... 45 Entering the IDLE0 Mode....................................................................................................... 45 Entering the IDLE1 Mode....................................................................................................... 45 Standby Current Considerations............................................................................................ 46 Wake-up................................................................................................................................. 46 Watchdog Timer.............................................................................................. 47 Watchdog Timer Clock Source............................................................................................... 47 Watchdog Timer Control Register.......................................................................................... 47 Watchdog Timer Operation.................................................................................................... 48 Reset and Initialisation................................................................................... 49 Reset Functions..................................................................................................................... 49 Reset Initial Conditions.......................................................................................................... 51 Input/Output Ports.......................................................................................... 55 Pull-high Resistors................................................................................................................. 55 Port A Wake-up...................................................................................................................... 56 I/O Port Control Registers...................................................................................................... 56 I/O Pin Structures................................................................................................................... 58 Programming Considerations................................................................................................. 59 Rev. 1.10 3 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Timer Modules – TM....................................................................................... 60 Introduction............................................................................................................................ 60 TM Operation......................................................................................................................... 60 TM Clock Source.................................................................................................................... 60 TM Interrupts.......................................................................................................................... 60 TM External Pins.................................................................................................................... 61 TM Input/Output Pin Control Registers.................................................................................. 61 Programming Considerations................................................................................................. 62 Compact Type TM – CTM............................................................................... 63 Compact TM Operation.......................................................................................................... 64 Compact Type TM Register Description................................................................................ 64 Compact Type TM Operating Modes..................................................................................... 71 Compare Match Output Mode................................................................................................ 71 Timer/Counter Mode.............................................................................................................. 74 PWM Output Mode................................................................................................................. 74 Buzzer control........................................................................................................................ 76 Capture Timer Module – CAPTM................................................................... 77 Capture Timer Overview........................................................................................................ 77 Capture Timer Register Description ...................................................................................... 77 Capture Timer Operation........................................................................................................ 81 Infrared Receiver............................................................................................ 82 Functional Description............................................................................................................ 82 RMT Timing............................................................................................................................ 83 Noise Filter Registers Description.......................................................................................... 83 Remote Control Timer – RMT................................................................................................ 84 RMT Register Description...................................................................................................... 85 Analog to Digital Converter........................................................................... 86 A/D Overview......................................................................................................................... 86 A/D Converter Register Description....................................................................................... 87 A/D Converter Data Registers – ADRL, ADRH...................................................................... 87 A/D Converter Control Registers – ADCR0, ADCR1, ANCSR0, ANCSR1, ADDL................. 88 A/D Converter Boundary Registers – ADLVDL, ADLVDH, ADHVDL, ADHVDH . .....................91 A/D Operation........................................................................................................................ 92 A/D Input Pins........................................................................................................................ 93 Summary of A/D Conversion Steps........................................................................................ 93 Programming Considerations................................................................................................. 94 A/D Transfer Function............................................................................................................ 94 A/D Programming Example.................................................................................................... 95 Over-current Detection................................................................................... 97 Over-current Functional Description...................................................................................... 97 Over-current Register Description.......................................................................................... 97 Rev. 1.10 4 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Linear Hall Sensor Detection......................................................................... 99 Hall Sensor Detection Function Description........................................................................... 99 Linear Hall Sensor Control Register Description.................................................................. 100 BLDC Motor Control Circuit......................................................................... 101 Functional Description.......................................................................................................... 101 PWM Counter Control Circuit .............................................................................................. 102 PWM Register Description................................................................................................... 103 Mask Function...................................................................................................................... 105 Register Description............................................................................................................. 108 Other Functions.................................................................................................................... 109 Hall Sensor Decoder.............................................................................................................111 Hall Sensor Decoder Register Description............................................................................116 Motor Protection Function.....................................................................................................118 Motor Protection Function Description..................................................................................119 Motor Position Detection Methods....................................................................................... 123 DC Motor Control.......................................................................................... 124 2-pin DC Motor Control........................................................................................................ 124 1-pin DC Motor Control........................................................................................................ 125 Register Description............................................................................................................. 126 Interrupts....................................................................................................... 127 Interrupt Registers................................................................................................................ 127 Interrupt Operation............................................................................................................... 138 External Interrupt 0............................................................................................................... 140 External Interrupt 1............................................................................................................... 140 Comparator Interrupt............................................................................................................ 140 Multi-function Interrupt......................................................................................................... 140 A/D Converter Interrupt........................................................................................................ 141 Fault Interrupt....................................................................................................................... 141 Pause Interrupt..................................................................................................................... 141 PWM Module Interrupts....................................................................................................... 141 Time Base Interrupt.............................................................................................................. 142 CAPTM Module Interrupt..................................................................................................... 143 TM Interrupt.......................................................................................................................... 143 RMT Module Interrupt.......................................................................................................... 143 EEPROM Interrupt............................................................................................................... 143 LVD Interrupt........................................................................................................................ 144 Interrupt Wake-up Function.................................................................................................. 144 Programming Considerations............................................................................................... 144 Low Voltage Detector – LVD........................................................................ 145 LVD Register........................................................................................................................ 145 LVD Operation...................................................................................................................... 146 Rev. 1.10 5 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Application Circuits...................................................................................... 147 Hall Sensor × 3.................................................................................................................... 147 Hall Sensor × 1.................................................................................................................... 148 Non-Hall Sensor................................................................................................................... 149 Instruction Set............................................................................................... 150 Introduction.......................................................................................................................... 150 Instruction Timing................................................................................................................. 150 Moving and Transferring Data.............................................................................................. 150 Arithmetic Operations........................................................................................................... 150 Logical and Rotate Operation.............................................................................................. 151 Branches and Control Transfer............................................................................................ 151 Bit Operations...................................................................................................................... 151 Table Read Operations........................................................................................................ 151 Other Operations.................................................................................................................. 151 Instruction Set Summary............................................................................. 152 Table Conventions................................................................................................................ 152 Instruction Definition.................................................................................... 154 Package Information.................................................................................... 163 16-pin NSOP (150mil) Outline Dimensions.......................................................................... 163 28-pin SKDIP (300mil) Outline Dimensions......................................................................... 164 28-pin SOP (300mil) Outline Dimensions............................................................................ 165 28-pin SSOP (150mil) Outline Dimensions.......................................................................... 166 44-pin QFP (10mm×10mm) Outline Dimensions................................................................. 167 Reel Dimensions.................................................................................................................. 168 Carrier Tape Dimensions...................................................................................................... 169 Rev. 1.10 6 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Features CPU Features • Operating Voltage: ♦♦ fSYS=32kHz ~ 20MHz: 4.5V~5.5V • Up to 0.2μs instruction cycle with 20MHz system clock at VDD=5V • Power down and wake-up functions to reduce power consumption • Two oscillators: ♦♦ Internal 20MHz RC - HIRC ♦♦ Internal 32kHz RC - LIRC • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • All instructions executed in one or two instruction cycles • Table read instructions • 63 powerful instructions • Up to 8-level subroutine nesting • Bit manipulation instruction Peripheral Features • Flash Program Memory: 4K×15 • RAM Data Memory: 256×8 • EEPROM Memory: 128×8 • Watchdog Timer function • Up to 28 bidirectional I/O lines • Six pin-shared external interrupts • Support IR cord Noise Filter function • Four 10-bit CTMs for Buzzer, RMT, up/down or left/right fan-head • Single 16-bit CTM for BLDC sensorless application • Single 16-bit CAPTM for motor protect • Two 8-bit RMTs for IR decode • A pair of 10-bit PWM with comlementary outputs for BLDC application • 9-channel 10-bit resolution A/D converter • Time-Base function for generation of fixed time interrupt signal • Single operational Amplifier for current detect • Two comparators with interrupt functions • Dual 8-bit D/A Converter • Low voltage reset function • Low voltage detect function • Package types: 16-pin NSOP, 28-pin SOP/SSOP/SKDIP,44-pin Rev. 1.10 7 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU General Description This device is Flash Memory with 8-bit high performance RISC architecture microcontroller device which includes a host of fully integrated special features specifically designed for the brushless DC motor applications. The advantages of low power consumption, I/O flexibility, Multiple and extremely flexible Timer Modules, oscillator options, multi-channel A/D and D/A Converter, Pulse Width Modulation function, 16-bit Capture Timer Module function, dual comparator functions, Motor Protect Module, Liner Hall Sensor detection, 8-bit RMT Module, Time Base function, LVD, EEPROM, powerdown and wake-up functions, although especially designed for brushless DC motor applications, the enhanced versatility of this device also makes it applicable for using in a wide range of A/D application possibilities such as sensor signal processing, motor driving, industrial control, consumer products, subsystem controllers, etc. Block Diagram 8-bit RISC MCU Core 256x8 RAM PB7/TCK0 10-bit CTM & 8-bit RMTx2 Interrupt 4kx15 Flash 16-bit CAPTMx1 128x8 EEPROM 9-ch 10-bit ADC x 1 PB6/TP0_0 PB5/TP1_0 PB4/TCK2 WDT 10-bit CTM DC MCTL0 LVR OPA LVD DAC x2 & CMP x2 IR Noise Filter PB2/RX_IN/INT1/TP2_0 PA0/AN0/INT0A PA1/AN1/INT0B PA2/AN2/INT0C PA3/AN3/TCK5 PA4/AN4/FH0_SAT/TCK3 PA5/AN5/FH0_SBT/TP3_1 PA6/AN6/FH0_LI/TP3_0 PA7/AN7/FH0_RI/TCK1 PB3/Is PB1/TP2_1 PB0 VDD PC7/Pause/TP5_1 PC6/Fault/TP5_0 VSS BLDC MCTL I/O Port 10-bit CTMx1 16-bit CTMx1 Rev. 1.10 DC MCTL1 10-bit CTM 8 PC0/GAT PC1/GAB PC2/GBT PC3/GBB PC4/GCT PC5/GCB PD1/FH1_SAT/TP1_1 PD0/FH1_SBT/TP0_1 PD2/FH1_LI PD3/FH1_RI May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Pin Assignment P A 4 /A N 4 /F H 0 _ S A T /T C K 3 P B 3 /Is 1 1 6 1 5 P A 2 /A N 2 /IN T 0 C V S S /A V S S 2 3 1 4 P A 1 /A N 1 /IN T 0 B V D D /A V D D P B 2 /R X _ IN /IN T 1 /T P 2 _ 0 4 1 3 P A 0 /A N 0 /IN T 0 A P B 0 5 1 2 P C 5 /G C B 6 1 1 7 1 0 P C 4 /G C T P C 3 /G B B 8 9 P C 2 /G B T P C 0 /G A T P C 1 /G A B P A 3 /A N 3 /T C K 5 16-pin NSOP PA3/AN3/TCK5 PA4/AN4/FH0_SAT/TCK3 PA5/AN5/FH0_SBT/TP3_1 PA6/AN6/FH0_LI/TP3_0 PA7/AN7/FH0_RI/TCK1 PB3/Is VSS/AVSS VDD/AVDD PB2/RX_IN/INT1/TP2_0 PB1/TP2_1 PB0 PC0/GAT PC1/GAB PC2/GBT 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 PA2/AN2/INT0C PA1/AN1/INT0B PA0/AN0/INT0A PC7/Pause/TP5_1 PC6/Fault/TP5_0 PB4/TCK2 PB5/TP1_0 PB6/TP0_0 PB7/TCK0 PD0/FH1_SAT/TP0_1 PD1/FH1_SBT/TP1_1 PC5/GCB PC4/GCT PC3/GBB 28-pin SOP-A/28-pin SKDIP-A PA4/AN4/FH0_SAT/TCK3 PA5/AN5/FH0_SBT/TP3_1 PA6/AN6/FH0_LI/TP3_0 PA7/AN7/FH0_RI/TCK1 PB3/Is VSS/AVSS VDD/AVDD PB2/RX_IN/INT1/TP2_0 PB1/TP2_1 PB0 PC0/GAT PC1/GAB PC2/GBT PC3/GBB 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 PA3/AN3/TCK5 PA2/AN2/INT0C PA1/AN1/INT0B PA0/AN0/INT0A PC7/Pause/TP5_1 PC6/Fault/TP5_0 PB4/TCK2 PB5/TP1_0 PB6/TP0_0 PB7/TCK0 PD0/FH1_SAT/TP0_1 PD1/FH1_SBT/TP1_1 PC5/GCB PC4/GCT 28-pin SSOP-A Rev. 1.10 9 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU NC NC PA0/AN0/INT0A PA1/AN1/INT0B PA2/AN2/INT0C PA3/AN3/TCK5 PA4/AN4/FH0_SAT/TCK3 PA5/AN5/FH0_SBT/TP3_1 PA6/AN6/FH0_LI/TP3_0 PA7/AN7/FH0_RI/TCK1 NC NC PB3/Is AVSS VSS AVDD VDD PB2/RX_IN/INT1/TP2_0 PB1/TP2_1 NC NC NC 44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 4 30 5 29 6 28 7 27 8 26 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 NC NC PC7/Pause/TP5_1 PC6/Fault/TP5_0 PB4/TCK2 PB5/TP1_0 PB6/TP0_0 PB7/TCK0 NC NC NC PD0/FH1_SAT/TP0_1 PD1/FH1_SBT/TP1_1 PD2/FH1_LI PD3/FH1_RI PC5/GCB PC4/GCT PC3/GBB PC2/GBT PC1/GAB PC0/GAT PB0 44-pin QFP-A Note: 1. If the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the “/” sign can be used for higher priority 2. VDD&AVDD means the VDD and AVDD are the double bonding. 3. VSS&AVSS means the VSS and AVSS are the double bonding. Rev. 1.10 10 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Pin Description Pin Name PA0/AN0/ INT0A PA1/AN1/ INT0B PA2/AN2/ INT0C PA3/AN3/ TCK5 PA4/AN4/ FH0_SAT /TCK3 PA5/AN5/ FH0_SBT/ TP3_1 PA6/AN6/ FH0_LI/ TP3_0 PA7/AN7/ FH0_RI /TCK1 PB0 PB1/TP2_1 Rev. 1.10 Function OP I/T O/T Description PA0 PAWU PAPU ST CMOS Bidirectional 8-bit I/O port. Register enabled pull-up and wake-up. AN0 ANCSR0 AN — A/D channel 0 INT0A INTC0 ST — External interrupt input PA1 PAPU PAWU ST CMOS AN1 ANCSR0 AN — A/D channel 1 INT0B INTC0 ST — External interrupt input PA2 PAPU PAWU ST CMOS AN2 ANCSR0 AN — A/D channel 2 INT0C INTC0 ST — External interrupt input PA3 PAPU PAWU ST CMOS AN3 ANCSR0 AN — A/D channel 3 TCK5 — ST — TM5 input PA4 PAPU PAWU ST CMOS AN4 ANCSR0 AN — A/D channel 4 FH0_SAT DCMCR1 — — DC FAN Head port output TCK3 — ST — TM3 input PA5 PAPU PAWU ST CMOS Bidirectional 8-bit I/O port. Register enabled pull-up and wake-up. Bidirectional 8-bit I/O port. Register enabled pull-up and wake-up. Bidirectional 8-bit I/O port. Register enabled pull-up and wake-up. Bidirectional 8-bit I/O port. Register enabled pull-up and wake-up. Bidirectional 8-bit I/O port. Register enabled pull-up and wake-up. AN5 ANCSR0 AN — A/D channel 5 FH0_SBT DCMCR1 — — DC FAN Head port output TP3_1 TMPC0 ST CMOS TM3 I/O PA6 PAPU PAWU ST CMOS Bidirectional 8-bit I/O port. Register enabled pull-up and wake-up. AN6 ANCSR0 AN — A/D channel 6 FH0_LI DCMCR1 — — DC FAN Head port output TP3_0 TMPC0 ST CMOS TM3 I/O PA7 PAPU PAWU ST CMOS Bidirectional 8-bit I/O port. Register enabled pull-up and wake-up. AN7 ANCSR0 AN — A/D channel 7 FH0_RI DCMCR1 — — DC FAN Head port output TCK1 — ST CMOS TM1 input PB0 PBPU ST CMOS Bidirectional 8-bit I/O port. Register enabled pull-up. PB1 PBPU ST CMOS Bidirectional 8-bit I/O port. Register enabled pull-up. TP2_1 TMPC0 — CMOS TM2 I/O 11 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Pin Name PB2/RX_IN/ INT1/TP2_0 PB3/Is PB4/TCK2 PB5/TP1_0 PB6/TP0_0 PB7/TCK0 Function OP I/T O/T PB2 PBPU ST RX_IN INTC0 ST — IR Receive input pin INT1 INTC0 ST — External interrupt input TP2_0 TMPC0 ST CMOS TM2 I/O PB3 PBPU ST CMOS Is OPOMS ST — PB4 PBPU ST CMOS TCK2 — ST — PB5 PBPU ST CMOS TP1_0 TMPC0 ST CMOS TM1 I/O PB6 PBPU ST CMOS TP0_0 TMPC0 ST CMOS TM0 I/O PB7 PBPU ST CMOS TCK0 — ST — PC0 PCPU ST CMOS Bidirectional 8-bit I/O port. Register enabled pull-up. GAT PWMC — CMOS Pulse Width Modulation complimentary output PC1 PCPU ST CMOS Bidirectional 8-bit I/O port. Register enabled pull-up. GAB PWMC — CMOS Pulse Width Modulation complimentary output PC2 PCPU ST CMOS Bidirectional 8-bit I/O port. Register enabled pull-up. GBT PWMC — CMOS Pulse Width Modulation complimentary output PC3 PCPU ST CMOS Bidirectional 8-bit I/O port. Register enabled pull-up. GBB PWMC — CMOS Pulse Width Modulation complimentary output PC4 PCPU ST CMOS Bidirectional 8-bit I/O port. Register enabled pull-up. GCT PWMC — CMOS Pulse Width Modulation complimentary output PC5 PCPU ST CMOS Bidirectional 8-bit I/O port. Register enabled pull-up. GCB PWMC — CMOS Pulse Width Modulation complimentary output PC6 PCPU ST CMOS Bidirectional 8-bit I/O port. Register enabled pull-up. Fault MPTC1 ST — TP5_0 TMPC1 ST PC0/GAT PC1/GAB PC2/GBT PC3/GBB PC4/GCT PC5/GCB PC6/Fault/ TP5_0 Rev. 1.10 Description Bidirectional 8-bit I/O port. Register enabled CMOS pull-up. 12 Bidirectional 8-bit I/O port. Register enabled pull-up. Operational amplifier input pin Bidirectional 8-bit I/O port. Register enabled pull-up. TM2 input Bidirectional 8-bit I/O port. Register enabled pull-up. Bidirectional 8-bit I/O port. Register enabled pull-up. Bidirectional 8-bit I/O port. Register enabled pull-up. TM0 input PWM Disable input pin. Active Low CMOS CAPTM I/O May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Pin Name PC7/Pause/ TP5_1 PD0/ FH1_SAT/ TP0_1 PD1/ FH1_SBT/ TP1_1 PD2/FH1_LI PD3/FH1_RI VSS Function OP I/T PC7 PCPU ST O/T Description Bidirectional 8-bit I/O port. Register enabled CMOS pull-up. Pause MPTC1 ST TP5_1 TMPC1 ST CMOS CAPTM I/O — PD0 PDPU ST CMOS FH1_SAT DCMCR1 — TP0_1 TMPC0 ST CMOS TM0 I/O PD1 PDPU ST CMOS FH1_SBT DCMCR1 — — TP1_1 TMPC0 ST CMOS TM1 I/O PD2 PDPU ST CMOS FH1_LI DCMCR1 — — PD3 PDPU ST CMOS FH1_RI DCMCR1 — — VSS — PWR — Negative power supply, ground — PWM Pause input pin Bidirectional 8-bit I/O port. Register enabled pull-up. DC FAN Head port output Bidirectional 8-bit I/O port. Register enabled pull-up. DC FAN Head port output Bidirectional 8-bit I/O port. Register enabled pull-up. DC FAN Head port output Bidirectional 8-bit I/O port. Register enabled pull-up. DC FAN Head port output AVSS AVSS — PWR — Ground connection for A/D converter. The VSS and AVSS are the same pin at 28 pin package VDD VDD — PWR — Positive power supply AVDD AVDD — PWR — Power supply connection for A/D converter. The VDD and AVDD are the same pin at 28 pin package Note: I/T: Input type; O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option; ST: Schmitt Trigger input CMOS: CMOS output; NMOS: NMOS output AN: Analog input pin VDD is the device power supply while AVDD is the ADC power supply. VSS is the device ground pin while AVSS is the ADC ground pin. As the Pin Description Summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. Rev. 1.10 13 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Absolute Maximum Ratings Supply Voltage.................................................................................................VSS−0.3V to VSS+6.0V Input Voltage...................................................................................................VSS−0.3V to VDD+0.3V Storage Temperature.....................................................................................................-50˚C to 125˚C Operating Temperature...................................................................................................-40˚C to 85˚C IOH Total.....................................................................................................................................-80mA IOL Total...................................................................................................................................... 80mA Total Power Dissipation ......................................................................................................... 500mW Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to this device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect devices reliability. D.C. Characteristics Ta=25˚C Symbol VDD Parameter Operating Voltage Test Conditions Min. Typ. Max. Unit fSYS=32 ~ 20000kHz 4.5 — 5.5 V — 8 10 mA — 60 100 μA VDD Conditions — IDD Operating Current (HIRC OSC) 5V No load, fH=20MHz, ADC off, WDT enable, Motor_CTL off, IR_RX off ISTB Standby Current — LIRC and LVR on, LVD off, WDT enable VIL Input Low Voltage for I/O Ports, TCKn, INT0A, INT0B, INT0C, INT1 — — 0 — 0.3VDD V VIH Input High Voltage for I/O Ports, TCKn, INT0A, INT0B, INT0C, INT1 — — 0.7VDD — VDD V VLVR LVR Voltage Level — LVR Enable, 3.15V option -5% 3.15 +5% V VLVD LVD Voltage Level — LVDEN=1, VLVD=3.6V -5% 3.6 +5% V VOL Output Low Voltage for I/O Ports 5V IOL=20mA — — 0.5 V VOH Output High Voltage for I/O Ports 5V IOH=-7.4mA RPH Pull-high Resistance for I/O Ports 5V Rev. 1.10 — 14 4.5 — — V 10 30 50 kΩ May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU A.C. Characteristics Ta=25˚C Symbol fSYS Parameter System Clock Test Conditions VDD — Conditions 4.5V~5.5V Min. Typ. Max. Unit 32 — Ta=-40˚C~85˚C -12% 20 20000 kHz +4% MHz 4.5V~5.5V Ta=-20˚C~85˚C -9% 20 +4% MHz MHz fHIRC System Clock (HIRC) -2% 20 +2% fTIMER Timer Input Pin Frequency — — — — 1 fSYS tINT Interrupt Pulse Width — — 1 — — tSYS Ta=25˚C tLVR Low Voltage Width to Reset — — 120 240 480 μs tLVD Low Voltage Width to Interrupt — — 20 45 90 μs tLVDS LVDO stable time — — 15 — — μs tEERD EEPROM Read Time — — — 45 90 μs tEEWR EEPROM Write Time — — — 2 4 ms tSST System Start-up Timer Period (Wake-up from HALT) — — 15~16 — tSYS System Reset Delay Time (Power On Reset) — — 25 50 100 ms System Reset Delay Time (Any Reset except Power On Reset) — — 8.3 16.7 33.3 ms tRSTD fSYS=HIRC Note: 1. tSYS=1/fSYS 2. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1μF decoupling capacitor should be connected between VDD and VSS and located as close to the device as possible. Rev. 1.10 15 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU A/D Converter Characteristics Ta=25˚C Symbol Test Conditions Parameter Min. Typ. Max. Unit — VLVR 5.0 5.5 V 3V — — 0.8 — mA 5V — — 1 — mA — — 1 μA VDD Condition — AVDD A/D Converter Operating Voltage IOP A/D Converter Operating Current ISTBY ADC Standby Current — VREF A/D Converter Reference Voltage — — Tconv A/D Conversion Time — — digital input no change 2 AVDD AVDD+0.1 14 V Tadck DNL A/D Differential non-linearity — — — — ±2 LSB INL A/D Integral non-linearity — — — ±2 — LSB Gerr Gain Error — — — — ±2 LSB Tadck ADCLK period — — — 0.166 — μs Tckh ADCLK high width — — — 83 — ns Tckl ADCLK low width — — — 83 — ns Tst1 Setup time for ADON — — 2 — — ns Tst2 Setup time for START latch — — 2 — — ns Tsth START high width — — 25 — — ns Tdeoc EOCB output delay — AVDD=5V — 3 — ns Tdout Output delay — AVDD=5V — 3 — ns Ton ADC wake up time — — 2 — — μs Toff ADC sleep time — — — — 5 ns D/A Converter Characteristics Ta=25˚C Symbol Test Conditions Parameter VDD Conditions — VDD D/A Operating Current — VDA D/A Output Voltage — 00h ~ FFh, no load tDAC D/A Conversion Time — VDD=5V, CL=10P RO D/A Output Resistance — — Min. Typ. Max. Unit VLVR — 5.5 V 0.01 — 0.99 VDD — — 2 μs — 10 — kΩ 8-bit R-2R D/A Converter(Analog Conditon VDD=5V, CL=10P) Model Corner TT SF FS SS FF 25 25 25 90 -40 Operating Average Current (VDD=5V, CL=10P) 352μA 330μA 374μA 297μA 413μA Analog Output 00000000 (B) ~11111111 (B) 0~4.98V 0~4.981V 0~4.98V 0~4.98V 0~4.981V ≤2μs ≤2μs ≤2μs ≤2μs ≤2μs Temperature Conversion Time Rev. 1.10 16 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Operational Amplifier Characteristics Symbol Ta=25˚C Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit IOPR1 Operating Current 5V — — 250 — μA IOFF1 Power Down Current 5V — — — 0.1 μA -15 — +15 mV mV VOPOS1 Input Offset Voltage 5V Without calibration, OPOF[3:0]=1000B VOPOS2 Input Offset Voltage 5V By calibration -4 — +4 VCM Common Mode Voltage Range — — VSS — VDD-1.4V V PSRR Power Supply Rejection Ratio 5V — 60 80 — dB CMRR Common Mode Rejuction Ratio 5V VCM=0 ~ VDD-1.4V 60 80 — dB SR Slew Rate+, Slew Rate- 5V No load 1.8 2.5 — V/μs GBW Gain Band Width 5V RL=1MΩ, CL=100pF — 2.5 — MHz Comparator Electrical Characteristics Ta=25˚C Symbol Test Conditions Parameter VDD Condition Min. Typ. Max. Unit IOPR0 Comparator operating voltage 5V — — 200 300 μA IOFF0 Comparator power down current 5V — — — 0.1 μA VOS Comparator input offset voltage — — -10 — +10 mV VCM Comparator common mode input voltage range — — VSS — VDD-1.4V V tPD Comparator response time (100mV overdrive) — — — 4 8 μs Power on Reset Electrical Characteristics Ta=25˚C Symbol Test Conditions Parameter VDD Condition Min. Typ. Max. Unit VPOR VDD Start Voltage to ensure Power-on Reset — — — — 100 mV RRVDD VDD Rise Rate to ensure Power-on Reset — — 0.035 — — V/ms tPOR Minimum Time for VDD to remain at VPOR to ensure Power-on Reset — — 1 — — ms Rev. 1.10 17 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. This makes this device suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a HIRC or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. System Clocking and Pipelining Rev. 1.10 18 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as “JMP” or “CALL” that demand a jump to a non-consecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Program Counter Program Counter High Byte PCL Register PC11~PC8 PCL7~PCL0 Program Counter The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly; however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Rev. 1.10 19 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has eight levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. P ro g ra m T o p o f S ta c k S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k P o in te r B o tto m C o u n te r S ta c k L e v e l 3 P ro g ra m M e m o ry o f S ta c k S ta c k L e v e l 8 Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly upgrated to reflect these changes. The ALU supports the following functions: • Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA • Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC • Increment and Decrement INCA, INC, DECA, DEC • Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI Rev. 1.10 20 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Flash Program Memory The Program Memory is the location where the user code or program is stored. For this device the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, this Flash device offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 4K×15 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 000H is reserved for use by this device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. Program Memory Structure Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the "TABRDC [m]" or "TABRDL [m]" instructions, respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as “0”. The accompanying diagram illustrates the addressing data flow of the look-up table. A d d re s s L a s t p a g e o r T B H P R e g is te r T B L P R e g is te r Rev. 1.10 D a ta 1 5 b its R e g is te r T B L H U s e r S e le c te d R e g is te r H ig h B y te L o w B y te 21 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is "F00H" which refers to the start address of the last page within the 4K Program Memory of the device. The table pointer is setup here to have an initial value of "06H". This will ensure that the first data read from the data table will be at the Program Memory address "F06H" or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the "TABRDC [m]" instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the "TABRDC [m]" instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Table Read Program Example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address ; is referenced mov tblp, a ; to the last page or present page mov a, 07h; initialise high table pointer mov tbhp, a : : tabrdl tempreg1 ; transfers value in table referenced by table pointer ; data at program memory address “F06H” transferred to ; tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address “F05H” transferred to ; tempreg2 and TBLH in this example the data “1AH” is ; transferred to tempreg1 and data “0FH” to register tempreg2 : : org F00h; sets initial address of program memory dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : Rev. 1.10 22 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU In Circuit Programming The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-circuit using a 5-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products sup plied with the latest program releases without removal and re-insertion of the device. MCU Programming Pins Function PA0 Serial Data Input/Output PA2 Serial Clock PB0 In Circuit Programming Mode Set VDD Power Supply VSS Ground The Program Memory and EEPROM data memory can both be programmed serially in-circuit using this 5-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply and in circuit programming Mode set. The technical details regarding the incircuit programming of the device is beyond the scope of this document and will be supplied in supple mentary literature. During the programming process the PB0 pin will be used to set the in circuit programing Mode and taking control of the PA0 and PA2 I/O pins for data and clock programming purposes. The user must there take care to ensure that no other outputs are connected to these two pins. Note: * may be resistor or capacitor. The resistance of * must be greater than 1kΩ or the capacitance of * must be less than 1nF. Programmer Pin MCU Pins ICPMS PB0 ICPDA PA0 ICPCK PA2 Programmer and MCU Pins Rev. 1.10 23 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU RAM Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. The capacity of this device is 256×8. Structure Divided into two sections, the first of these is an area of RAM, known as the Special Function Data Memory. Here are located registers which are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is known as the General Purpose Data Memory, which is reserved for general purpose use. All locations within this area are read and write accessible under program control. The Special Purpose Data Memory registers are accessible in all banks, with the exception of the EEC register at address 40H, which is only accessible in Bank 1. Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value. The start address of the Data Memory for all devices is the address 00H. 00H 7FH 80H FFH Data Memory Structure Rev. 1.10 24 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Special Purpose Data Memory Rev. 1.10 25 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section, however several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of “00H” and writing to the registers indirectly will result in no operation. Memory Pointers – MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to access data from all banks according to BP register. Direct Addressing can only be used with Bank 0, all other Banks must be addressed indirectly using MP1 and IAR1. The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4. Indirect Addressing Program Example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org00h start: mov a,04h; mov block,a mov a,offset adres1 ; mov mp0,a ; loop: clr IAR0 ; inc mp0; sdz block ; jmp loop continue: setup size of block Accumulator loaded with first RAM address setup memory pointer with first RAM address clear the data at address defined by MP0 increment memory pointer check if last memory location has been cleared The important point to note here is that in the example shown above, no reference is made to specific RAM addresses. Rev. 1.10 26 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Bank Pointer – BP The Data Memory is divided into two banks. Selecting the Data Memory area is achieved using the Bank Pointer. Bit 0 of the Bank Pointer is used to select Data Memory Banks 0 or 1. The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaffected. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing data from banks other than Bank 0 must be implemented using Indirect addressing. BP Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — — DMBP0 R/W — — — — — — — R/W POR — — — — — — — 0 Bit 7~1 Unimplemented, read as “0” Bit 0DMBP0: Select Data Memory Banks 0: Bank 0 1: Bank 1 Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Rev. 1.10 27 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointer and indicates the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the “INC” or “DEC” instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the "CLR WDT" or "HALT" instruction. The PDF flag is affected only by executing the "HALT" or "CLR WDT" instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the “CLR WDT” instruction. PDF is set by executing the “HALT” instruction. • TO is cleared by a system power-up or executing the “CLR WDT” or “HALT” instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Rev. 1.10 28 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU STATUS Register Bit 7 6 5 4 3 2 1 0 Name — — TO PDF OV Z AC C R/W — — R R R/W R/W R/W R/W POR — — 0 0 x x x x "x" unknown Bit 7, 6 Unimplemented, read as “0” Bit 5TO: Watchdog Time-Out flag 0: After power up or executing the “CLR WDT” or “HALT” instruction 1: A watchdog time-out occurred. Bit 4PDF: Power down flag 0: After power up or executing the “CLR WDT” instruction 1: By executing the “HALT” instruction Bit 3OV: Overflow flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Bit 2Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1AC: Auxiliary flag 0: No auxiliary carry 1: An operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction Bit 0C: Carry flag 0: No carry-out 1: An operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction. Rev. 1.10 29 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU System Control Register – CTRL Bit 7 6 5 4 3 2 Name FSYSON — — R/W R/W — — POR 0 — — — 1 0 — — — — LVRF LRF WRF R/W R/W — R/W × 0 0 " x" unknown Bit 7FSYSON: fSYS Control in IDLE Mode 0: Disable 1: Enable Bit 6~3 Unimplemented, read as "0" Bit 2LVRF: LVR function reset flag 0: Not occurred 1: Occurred This bit can be cleared to “0”, but can not be set to “1”. Bit 1LRF: LVR Control register software reset flag 0: Not occurred 1: Occurred This bit can be cleared to “0”, but can not be set to “1”. Bit 0WRF: WDT Control register software reset flag 0: Not occurred 1: Occurred This bit can be cleared to “0”, but can not be set to “1”. Rev. 1.10 30 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU EEPROM Data Memory The device contains an area of internal EEPROM Data Memory. EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form of re-programmable memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. The availability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. The process of reading and writing data to the EEPROM memory has been reduced to a very trivial affair. EEPROM Data Memory Structure The EEPROM Data Memory capacity is 128×8 bits. Unlike the Program Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. Read and Write operations to the EEPROM are carried out in single byte operations using an address and data register in Bank 0 and a single control register in Bank 1. EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory. These are the address register, EEA, the data register, EED and a single control register, EEC. As both the EEA and EED registers are located in Bank 0, they can be directly accessed in the same was as any other Special Function Register. The EEC register however, being located in Bank1, cannot be addressed directly and can only be read from or written to indirectly using the MP1 Memory Pointer and Indirect Addressing Register, IAR1. Because the EEC control register is located at address 40H in Bank 1, the MP1 Memory Pointer must first be set to the value 40H and the Bank Pointer register, BP, set to the value, 01H, before any operations on the EEC register are executed. EEPROM Register List Name Bit 7 6 5 4 3 2 1 0 EEA — D6 D5 D4 D3 D2 D1 D0 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC — — — — WREN WR RDEN RD EEA Register Bit 7 6 5 4 3 2 1 0 Name — D6 D5 D4 D3 D2 D1 D0 R/W — R/W R/W R/W R/W R/W R/W R/W POR — x x x x x x x “x” unknown Rev. 1.10 Bit 7 Unimplemented, read as “0” Bit 6~0 Data EEPROM address Data EEPROM address bit 6~bit 0 31 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU EEC Register Bit 7 6 5 4 3 Name — — — — R/W — — — — POR — — — — Bit 7~4 2 1 0 WREN WR RDEN RD R/W R/W R/W R/W 0 0 0 0 Undefined, read as “0” Bit 3WREN: Data EEPROM Write Enable 0: Disable 1: Enable This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations. Bit 2WR: EEPROM Write Control 0: Write cycle has finished 1: Activate a write cycle This is the Data EEPROM Write Control Bit and when set high by the application program will activate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Setting this bit high will have no effect if the WREN has not first been set high. Bit 1 RDEN: Data EEPROM Read Enable 0: Disable 1: Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data EEPROM read operations. Bit 0 RD : EEPROM Read Control 0: Read cycle has finished 1: Activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high. Note: The WREN, WR, RDEN and RD can not be set to “1” at the same time in one instruction. The WR and RD can not be set to “1” at the same time. Reading Data from the EEPROM To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register. The data will remain in the EED register until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading. Rev. 1.10 32 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Writing Data to the EEPROM To write data to the EEPROM, the write enable bit, WREN, in the EEC register must first be set high to enable the write function. The EEPROM address of the data to be written must then be placed in the EEA register and the data placed in the EED register. If the WR bit in the EEC register is now set high, an internal write cycle will then be initiated. Setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is powered-on the Write Enable bit in the control register will be cleared preventing any write operations. Also at power-on the Bank Pointer, BP, will be reset to zero, which means that Data Memory Bank 0 will be selected. As the EEPROM control register is located in Bank 1, this adds a further measure of protection against spurious write operations. During normal program operation, ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect write operations. EEPROM Interrupt The EEPROM write or read interrupt is generated when an EEPROM write or read cycle has ended. The EEPROM interrupt must first be enabled by setting the EPWE bit in the relevant interrupt register. However as the EEPROM is contained within a Multi-function Interrupt, the associated multi-function interrupt enable bit must also be set. When an EEPROM write cycle ends, the EPWF request flag and its associated multi-function interrupt request flag will both be set. If the global, EEPROM and Multi-function interrupts are enabled and the stack is not full, a jump to the associated Multi-function Interrupt vector will take place. When the interrupt is serviced only the Multi-function interrupt flag will be automatically reset, the EEPROM interrupt flag must be manually reset by the application program. More details can be obtained in the Interrupt section. Programming Consideration Care must be taken that data is not inadvertently written to the EEPROM. Protection can be enhanced by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Bank Pointer could be normally cleared to zero as this would inhibit access to Bank 1 where the EEPROM control register exist. Although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. Rev. 1.10 33 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Programming Examples Reading data from the EEPROM – polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, 040H MOV MP1, A MOV A, 01H MOV BP, A SET IAR1.1 SET IAR1.0 BACK: SZ IAR1.0 JMP BACK CLR IAR1 CLR BP MOV A, EEDATA MOV READ_DATA, A ; user defined address ; setup memory pointer MP1 ; MP1 points to EEC register ; setup Bank Pointer ; set RDEN bit, enable read operations ; start Read Cycle - set RD bit ; check for read cycle end ; disable EEPROM read/write ; move read data to register Writing data from the EEPROM – polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, EEPROM_DATA MOV EED, A MOV A, 040H MOV MP1, A MOV A, 01H MOV BP, A SET IAR1.3 SET IAR1.2 BACK: SZ IAR1.2 JMP BACK CLR IAR1 CLR BP Rev. 1.10 ; user defined address ; user defined data ; setup memory pointer MP1 ; MP1 points to EEC register ; setup Bank Pointer ; set WREN bit, enable write operations ; start Write Cycle - set WR bit ; check for write cycle end ; disable EEPROM read/write 34 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Oscillator Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of configuration options and registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupt. Fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. The higher frequency oscillator provides higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. With the capability of dynamically switching between fast and slow system clock, this device have the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. Name Freq. Internal High Speed RC Type HIRC 20MHz Internal Low Speed RC LIRC 32kHz Oscillator Types System Clock Configurations There are two methods of generating the system clock, a high speed oscillator and a low speed oscillator. The high speed oscillator is the internal 20MHz RC oscillator. The low speed oscillator is the internal 32kHz RC oscillator. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the HLCLK bit and CKS2~CKS0 bits in the SMOD register and as the system clock can be dynamically selected. High Speed Oscillation HIRC fH 6-stage Prescaler f H/2 fH/4 fH /8 fH/16 fH/32 Low Speed Oscillation fH/64 fSYS fL LIRC HLCLK, CKS2~CKS0 bits fSUB System Clock Configurations Rev. 1.10 35 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Internal 20MHz RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a fixed frequencies of 20MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of 25˚C degrees, the fixed oscillation frequency of 20MHz will have a tolerance within 2%. Internal 32kHz Oscillator – LIRC The Internal 32kHz System Oscillator is a low frequency oscillator choice. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of 25˚C degrees, the fixed oscillation frequency of 32kHz will have a tolerance within 10%. Supplementary Clocks The low speed oscillator, in addition to providing a system clock source are also used to provide a clock source to other device functions. These are the Watchdog Timer and the Time Base Interrupt. Rev. 1.10 36 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice versa, lower speed clocks reduce current consumption. As Holtek has provided this device with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks The device has many different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock options using configuration options and register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency, fH, or low frequency, fL, source, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system clock can be sourced from HIRC oscillator. The low speed system clock source can be sourced from internal clock fL. If f L is selected then it can be sourced by the LIRC oscillator. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. There are two additional internal clocks for the peripheral circuits, the substitute clock, fSUB, and the Time Base clock, fTBC. Each of these internal clocks is sourced by the LIRC oscillator. The fSUB clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times. Rev. 1.10 37 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU System Clock Configurations Note: When the system clock source fSYS is switched to fL from fH, the high speed oscillation will stop to conserve the power. Thus there is no fH~fH/64 for peripheral circuit to use. The fS is used as the clock source for the Watchdog timer. Together with fSYS/4, the fTBC clock is also used as a source for the Time Base interrupt function and for the TMs. Rev. 1.10 38 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU System Operation Modes There are five different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining three modes, the SLEEP, IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to conserve power. Description Operation Mode CPU fSYS fSUB fS NORMAL Mode On fH~fH/64 On On On SLOW Mode On fL On On On IDLE0 Mode Off Off On On On IDLE1 Mode Off On On On On SLEEP Mode Off Off On On On fTBC • NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator. This mode operates allowing the microcontroller to operate normally with a clock source will come from HIRC oscillator. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 and HLCLK bits in the SMOD register. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. • SLOW Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source used will be from the low speed oscillator, LIRC. Running the microcontroller in this mode allows it to run with much lower operating currents. In the SLOW Mode, the fH is off. • SLEEP Mode The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP Mode the CPU will be stopped. • IDLE0 Mode The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is low. In the IDLE0 Mode the system oscillator will be inhibited from driving the CPU but some peripheral functions will remain operational such as the Watchdog Timer and TMs. In the IDLE0 Mode, the system oscillator will be stopped. In the IDLE0 Mode the Watchdog Timer clock, fS, will be always on. • IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational such as the Watchdog Timer and TMs. In the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. In the IDLE1 Mode the Watchdog Timer clock, fS, will be on. Rev. 1.10 39 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Control Register A single register, SMOD, is used for overall control of the internal clocks within this device. SMOD Register Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 FSTEN LTO HTO IDLEN HLCLK R/W R/W R/W R/W R/W R R R/W R/W POR 0 0 0 0 0 0 1 1 Bit 7~5CKS2~CKS0: The system clock selection when HLCLK is “0” 000: fL (fLIRC) 001: fL (fLIRC) 010: fH/64 011: fH/32 100: fH/16 101: fH/8 110: fH/4 111: fH/2 These three bits are used to select which clock is used as the system clock source. In addition to the system clock source, which can be the LIRC, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4FSTEN: Fast Wake-up Control 0: Disable 1: Enable This is the Fast Wake-up Control bit which determines if the fSUB clock source is initially used after this device wake up. When the bit is high, the fSUB clock source can be used as a temporary system clock to provide a faster wake up time as the fSUB clock is available. Bit 3LTO: Low speed system oscillator ready flag 0: Not ready 1: Ready This is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. The flag will change to a high level after 1~2 clock cycles if the LIRC oscillator is used. Bit 2HTO: High speed system oscillator ready flag 0: Not ready 1: Ready This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. This flag is cleared to “0” by hardware when this device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as “1” by the application program after device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after a wake-up has occurred, the flag will change to a high level after 15~16 clock cycles if the HIRC oscillator is used. Bit 1IDLEN: IDLE Mode control 0: Disable 1: Enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed this device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 Mode. If the bit is low this device will enter the SLEEP Mode when a HALT instruction is executed. Rev. 1.10 40 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Bit 0HLCLK: System clock selection 0: fH/2~fH/64 or fL 1: fH This bit is used to select if the fH clock or the fH/2~fH/64 or fL clock is used as the system clock. When the bit is high the f H clock will be selected and if low the fH/2~fH/64 or fL clock will be selected. When system clock switches from the fH clock to the fL clock and the fH clock will be automatically switched off to conserve power. Fast Wake-up To minimise power consumption this device can enter the SLEEP or IDLE0 Mode, where the system clock source to this device will be stopped. However when this device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. To ensure the device is up and running as fast as possible a Fast Wake-up function is provided, which allows fSUB, namely the LIRC oscillator, to act as a temporary clock to first drive the system until the original system oscillator has stabilised. As the clock source for the Fast Wake-up function is fSUB, the Fast Wake-up function is only available in the SLEEP and IDLE0 modes. The Fast Wake-up enable/disable function is controlled using the FSTEN bit in the SMOD register. If the HIRC oscillator or LIRC oscillator is used as the system oscillator then it will take 15~16 clock cycles of the HIRC or 1~2 cycles of the LIRC to wake up the system from the SLEEP or IDLE0 Mode. The Fast Wake-up bit, FSTEN will have no effect in these cases. System FSTEN Oscillator Bit Wake-up Time (SLEEP Mode) Wake-up Time (IDLE0 Mode) Wake-up Time (IDLE1 Mode) HIRC x 15~16 HIRC cycles 1~2 HIRC cycles LIRC x 1~2 LIRC cycles 1~2 LIRC cycles Wake-Up Times Rev. 1.10 41 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Rev. 1.10 42 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Operating Mode Switching and Wake-up This device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether this device enter the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the CTRL register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, fH, to the clock source, fH/2~fH/64 or fL. If the clock is from the fL, the high speed clock source will stop running to conserve power. When this happens it must be noted that the fH/16 and fH/64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the TMs. The accompanying flowchart shows what happens when this device move between the various operating modes. NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the HLCLK bit to “0” and set the CKS2~CKS0 bits to “000” or “001” in the SMOD register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LIRC oscillator and therefore requires this oscillator to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register. SLOW Mode to NORMAL Mode Switching In SLOW Mode the system uses the LIRC low speed system oscillator. To switch back to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set to “1” or HLCLK bit is “0”, but CKS2~CKS0 is set to “010”, “011”, “100”, “101”, “110” or “111”. As a certain amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit is checked. The amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. Rev. 1.10 43 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Rev. 1.10 44 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Entering the SLEEP Mode There is only one way for this device to enter the SLEEP Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “0”. When this instruction is executed under the conditions described above, the following will occur: • The system clock and Time Base clock will be stopped and the application program will stop at the “HALT” instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE0 Mode There is only one way for this device to enter the IDLE0 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the FSYSON bit in CTRL register equal to “0”. When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the “HALT” instruction, but the Time Base clock and fSUB clock will be on. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE1 Mode There is only one way for this device to enter the IDLE1 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the FSYSON bit in CTRL register equal to “1”. When this instruction is executed under the conditions described above, the following will occur: • The system clock and Time Base clock and fSUB clock will be on and the application program will stop at the “HALT” instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Rev. 1.10 45 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of this device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on this device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonded pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the configuration options have enabled the LIRC oscillator. In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. Wake-up After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external reset • An external falling edge on Port A • A system interrupt • A WDT overflow If the system is woken up by an external reset, this device will experience a full system reset, however, if this device are woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the “HALT” instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the “HALT” instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the “HALT” instruction. In this situation, the interrupt which woke-up this device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Rev. 1.10 46 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal clock, fS, which can be sourced from the LIRC oscillator. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 2 18 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. The LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. Watchdog Timer Control Register A single register, WDTC, controls the overall operation of the Watchdog Timer. Any reset of this device, the initial value of the WDTC is always “01010011”, and it will not be changed in Power Down Mode. WDTC Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~3 WE4~WE0: WDT operation 10101 or 01010: Enable Other values: MCU reset (Reset will be active after 1~2 LIRC clock for debounce time.) If the MCU reset caused by the WE[4:0] in WDTC software reset, the WRF flag of CTRL register will be set) Bit 2~0 WS2~WS0: WDT time-out period selection 000: 28/fS 001: 210/fS 010: 212/fS 011: 214/fS 100: 215/fS 101: 216/fS 110: 217/fS 111: 218/fS These three bits determine the division ratio of the Watchdog Timer source clock, which in turn determines the timeout period. 47 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Watchdog Timer Operation Note that the Watchdog Timer function is always enabled. The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instruction. If the program malfunctions for whatever reason, jumps to an unkown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. There are five bits, WE4~WE0, in the WDTC register to offer a control of the Watchdog Timer. If WE4~WE0 bits are set to a specific value of "10101" or "01010", the WDT is alway enable. Any other values for these bits will keep the MCU reset. Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is an external hardware reset, the second is using the Watchdog Timer software clear instruction and the third is via a HALT instruction. To clear the Watchdog Timer is to use the single “CLR WDT” instruction. A simple execution of "CLR WDT" will clear the WDT. Watchdog Timer Rev. 1.10 48 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where the power supply voltage falls below a certain threshold. Reset Functions There are four ways in which a microcontroller reset can occur, through events occurring both internally and externally: • Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. VDD Power-on Reset tRSTD SST Time-out Note: tRSTD is power-on delay, typical time=50ms Power-on Reset Timing Chart • Low Voltage Reset – LVR This microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of this device, which is controlled by LVRC register. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally and set the LVRF in the CTRL register to high .The LVR includes the following specifications: For a valid LVR signal, a low voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for greater than the value tLVR specified in the A.C. characteristics. If the low voltage state does not exceed tLVR, the LVR will ignore it and will not perform a reset function. Note: tRSTD is power-on delay, typical time=16.7ms Low Voltage Reset Timing Chart Rev. 1.10 49 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU LVRC Register Bit 7 6 5 4 3 2 1 0 Name LVS7 LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7~3 LVS7~LVS0: LVR voltage select 01010101: 3.15V 00110011: 3.15V 10011001: 3.15V 10101010: 3.15V Other values: MCU reset (Reset will be active after 2~3 LIRC clock for debounce time.) If the MCU reset caused by the LVRC software reset, the LRF flag of CTRL register will be set. • Watchdog Time-out Reset during Normal Operation The Watchdog time-out flag TO will be set to “1”. Note: tRSTD is power-on delay, typical time=16.7ms WDT Time-out Reset during Normal Operation Timing Chart • Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to “0” and the TO flag will be set to “1”. Refer to the A.C. Characteristics for tSST details. Note: The tSST is 15~16 clock cycles if the system clock source is provided by HIRC. The tSST is 1~2 clock for LIRC. WDT Time-out Reset during SLEEP or IDLE Timing Chart Rev. 1.10 50 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: TO PDF RESET Conditions 0 0 Power-on reset u u LVR reset during NORMAL or SLOW Mode operation 1 u WDT time-out reset during NORMAL or SLOW Mode operation 1 1 WDT time-out reset during IDLE or SLEEP Mode operation “u” stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Condition After RESET Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Clear after reset, WDT begins counting Timer/Event Counter TM modules will be turned off Input/Output Ports I/O ports will be setup as inputs, and AN0~AN7 is as A/D input pin. Stack Pointer Stack Pointer will point to the top of the stack The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation for the larger package type. Reset (Power On) WDT Time-out (Normal Operation) LVR Reset WDT Time-out (IDLE) MP0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu MP1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ---- ---0 ---- ---0 ---- ---0 ---- ---u ACC xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 Register BP Rev. 1.10 TBLP xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TBLH -xxx xxxx -uuu uuuu -xxx xxxx -uuu uuuu TBHP ---- xxxx ---- uuuu ---- xxxx ---- uuuu STATUS --00 xxxx --1u uuuu --uu xxxx --11 uuuu SMOD 0000 0011 0000 0011 0000 0011 uuuu uuuu LVDC --00 -000 --00 -000 --00 -000 --uu –uuu LVRC 0101 0101 0101 0101 0101 0101 uuuu uuuu WDTC 0101 0011 0101 0011 0101 0011 uuuu uuuu TBC 0011 0111 0011 0111 0011 0111 uuuu uuuu INTC0 -000 0000 -000 0000 -000 0000 -uuu uuuu INTC1 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC2 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC3 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI0 -000 -000 -000 -000 -000 -000 -uuu -uuu 51 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Reset (Power On) WDT Time-out (Normal Operation) LVR Reset WDT Time-out (IDLE) MFI1 --00 --00 --00 --00 --00 --00 --uu –-uu MFI2 --00 --00 --00 --00 --00 --00 --uu --uu MFI3 --00 --00 --00 --00 --00 --00 --uu --uu MFI4 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI5 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI6 -000 -000 -000 -000 -000 -000 -uuu -uuu MFI7 --00 --00 --00 --00 --00 --00 --uu --uu Register Rev. 1.10 MFI8 --00 --00 --00 --00 --00 --00 --uu --uu PAWU 0000 0000 0000 0000 0000 0000 uuuu uuuu PAPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu PBPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PB 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCC 1111 1111 1111 1111 1111 1111 uuuu uuuu PDPU ---- 0000 ---- 0000 ---- 0000 ---- uuuu PD - - - - 1111 - - - - 1111 - - - - 1111 ---- uuuu PDC - - - - 1111 - - - - 1111 - - - - 1111 ---- uuuu NF_VIH 0 - - 11 0 0 1 0 - - 11 0 0 1 0 - - 11 0 0 1 u--u uuuu NF_VIL ---0 1010 ---0 1010 ---0 1010 ---u uuuu RMTC 0000 0000 0000 0000 0000 0000 uuuu uuuu RMT0 0000 0000 0000 0000 0000 0000 uuuu uuuu RMT1 0000 0000 0000 0000 0000 0000 uuuu uuuu HCHK_NUM ---0 0000 ---0 0000 ---0 0000 ---u uuuu HNF_MSEL ---- 0000 ---- 0000 ---- 0000 ---- uuuu CAPTC0 0000 0000 0000 0000 0000 0000 uuuu uuuu CAPTC1 0000 0000 0000 0000 0000 0000 uuuu uuuu CAPTMDL 0000 0000 0000 0000 0000 0000 uuuu uuuu CAPTMDH 0000 0000 0000 0000 0000 0000 uuuu uuuu CAPTMAL 0000 0000 0000 0000 0000 0000 uuuu uuuu CAPTMAH 0000 0000 0000 0000 0000 0000 uuuu uuuu CAPTMCL xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu CAPTMCH xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu OPOMS 00-- -010 00-- -010 00-- -010 uu-- -uuu OPCM 0000 0000 0000 0000 0000 0000 uuuu uuuu LHMC --00 --00 --00 --00 --00 --00 --uu --uu HACM 0000 0000 0000 0000 0000 0000 uuuu uuuu TMPC0 0000 0000 0000 0000 0000 0000 uuuu uuuu TMPC1 ---- --00 ---- --00 ---- --00 ---- --uu CTRL 0--- -x00 0--- -x00 0--- -x00 u--- -uuu EEC ---- 0000 ---- 0000 ---- 0000 ---- uuuu EEA -xxx xxxx -xxx xxxx -xxx xxxx -uuu uuuu EED xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADRL xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu 52 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Register ADRH Rev. 1.10 Reset (Power On) WDT Time-out (Normal Operation) LVR Reset WDT Time-out (IDLE) ---- --xx ---- --xx ---- --xx ---- --uu ADCR0 0 11 - 0 0 0 0 0 11 - 0 0 0 0 0 11 - 0 0 0 0 uuu- uuuu ADCR1 0000 0000 0000 0000 0000 0000 uuuu uuuu ANCSR0 1111 1111 1111 1111 1111 1111 uuuu uuuu ANCSR1 ---- ---1 ---- ---1 ---- ---1 ---- ---u ADDL 0000 0000 0000 0000 0000 0000 uuuu uuuu ADLVDL 0000 0000 0000 0000 0000 0000 uuuu uuuu ADLVDH xxxx xx00 xxxx xx00 xxxx xx00 uuuu uuuu ADHVDL 0000 0000 0000 0000 0000 0000 uuuu uuuu ADHVDH ---- --00 ---- --00 ---- --00 ---- --uu PWMC --00 0--0 --00 0--0 --00 0--0 --uu u--u DUTRL 0000 0000 0000 0000 0000 0000 uuuu uuuu DUTRH ---- --00 ---- --00 ---- --00 ---- --uu PRDRL 0000 0000 0000 0000 0000 0000 uuuu uuuu PRDRH 0000 0000 0000 0000 0000 0000 uuuu uuuu PWMRL 0000 0000 0000 0000 0000 0000 uuuu uuuu PWMRH ---- --00 ---- --00 ---- --00 ---- --uu MCF ---- 0100 ---- 0100 ---- 0100 ---- uuuu MCD --00 0000 --00 0000 --00 0000 --uu uuuu DTS 0000 0000 0000 0000 0000 0000 uuuu uuuu PLC --00 0000 --00 0000 --00 0000 --uu uuuu HDCR 0001 0000 0001 0000 0001 0000 uuuu uuuu HDCD ---- -000 ---- -000 ---- -000 ---- -uuu HDCT0 --00 0000 --00 0000 --00 0000 --uu uuuu HDCT1 --00 0000 --00 0000 --00 0000 --uu uuuu HDCT2 --00 0000 --00 0000 --00 0000 --uu uuuu HDCT3 --00 0000 --00 0000 --00 0000 --uu uuuu HDCT4 --00 0000 --00 0000 --00 0000 --uu uuuu HDCT5 --00 0000 --00 0000 --00 0000 --uu uuuu HDCT6 --00 0000 --00 0000 --00 0000 --uu uuuu HDCT7 --00 0000 --00 0000 --00 0000 --uu uuuu HDCT8 --00 0000 --00 0000 --00 0000 --uu uuuu HDCT9 --00 0000 --00 0000 --00 0000 --uu uuuu HDCT10 --00 0000 --00 0000 --00 0000 --uu uuuu HDCT11 --00 0000 --00 0000 --00 0000 --uu uuuu MPTC1 0000 0000 0000 0000 0000 0000 uuuu uuuu MPTC2 0000 0000 0000 0000 0000 0000 uuuu uuuu TM5C0 0000 0--- 0000 0--- 0000 0--- uuuu u--- TM5C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM5DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM5DH 0000 0000 0000 0000 0000 0000 uuuu uuuu TM5AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM5AH 0000 0000 0000 0000 0000 0000 uuuu uuuu TM5RP 0000 0000 0000 0000 0000 0000 uuuu uuuu OPACAL -001 0000 -001 0000 -001 0000 -uuu uuuu DCMCR0 0000 1010 0000 1010 0000 1010 uuuu uuuu DCMCR1 ---0 0000 ---0 0000 ---0 0000 ---u uuuu 53 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Reset (Power On) WDT Time-out (Normal Operation) LVR Reset WDT Time-out (IDLE) TM0C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0DH ---- --00 ---- --00 ---- --00 ---- --uu TM0AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM0AH ---- --00 ---- --00 ---- --00 ---- --uu TM1C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1DH ---- --00 ---- --00 ---- --00 ---- --uu TM1AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM1AH ---- --00 ---- --00 ---- --00 ---- --uu TM2C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2DH ---- --00 ---- --00 ---- --00 ---- --uu TM2AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM2AH ---- --00 ---- --00 ---- --00 ---- --uu TM3C0 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3C1 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3DL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3DH ---- --00 ---- --00 ---- --00 ---- --uu TM3AL 0000 0000 0000 0000 0000 0000 uuuu uuuu TM3AH 0000 0000 0000 0000 0000 0000 uuuu uuuu Register Note: “ - ” stands for not implement “ u ” stands for unchanged “ x ” stands for unknown Rev. 1.10 54 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. This device provide bidirectional input/output lines labeled with port names PA~PD These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction “MOV A, [m]”, where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. I/O Register List Bit Register Name 7 6 5 4 3 2 1 0 PAWU D7 D6 D5 D4 D3 D2 D1 D0 PAPU D7 D6 D5 D4 D3 D2 D1 D0 PA D7 D6 D5 D4 D3 D2 D1 D0 PAC D7 D6 D5 D4 D3 D2 D1 D0 PBPU D7 D6 D5 D4 D3 D2 D1 D0 PB D7 D6 D5 D4 D3 D2 D1 D0 PBC D7 D6 D5 D4 D3 D2 D1 D0 PCPU D7 D6 D5 D4 D3 D2 D1 D0 PC D7 D6 D5 D4 D3 D2 D1 D0 PCC D7 D6 D5 D4 D3 D2 D1 D0 PDPU — — — — D3 D2 D1 D0 PD — — — — D3 D2 D1 D0 PDC — — — — D3 D2 D1 D0 Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers, namely PAPU~PDPU, and are implemented using weak PMOS transistors. PAPU Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 PBPU Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 55 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU PCPU Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 I/O Port bit 7~bit 0 pull-high control PDPU Register Bit 7 6 5 4 3 2 1 0 Name — — — — D3 D2 D1 D0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as “0” Bit 3~0 Port D bit 3~bit 0 pull-high control Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. PAWU Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0PAWU: Port A bit 7~bit 0 Wake-up Control 0: Disable 1: Enable I/O Port Control Registers Each I/O port has its own control register known as PAC~PDC, to control the input/output configuration. With this control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a “1”. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a “0”, the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. Rev. 1.10 56 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU PAC Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 7 6 5 4 3 2 1 0 PBC Register Bit Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 PCC Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~0 I/O port bit 7~bit 0 Input/Output control PDC Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name — — — — D3 D2 D1 D0 R/W — — — — R/W R/W R/W R/W POR — — — — 1 1 1 1 Bit 7~4 Unimplemented, read as “0” Bit 3~0 I/O Port bit 3~bit 0 Input/Output Control 0: Output 1: Input 57 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. Generic Input/Output Structure A/D Input/Output Structure Rev. 1.10 58 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers, PAC~PDC, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA~PD, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the “SET [m].i” and “CLR [m].i” instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Rev. 1.10 59 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Timer Modules – TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions each device includes several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has either multiple interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Compact and Standard TM sections. Introduction The device contains five TMs having a reference name of TM0, TM1, TM2, TM3 and TM5. Each individual TM can be categorised as a certain type, namely Compact Type TM, four 10-bit CTM and one 16-bit CTM. The main features are summarised in the accompanying table. Function CTM Timer/Counter √ I/P Capture — Compare Match Output √ PWM Channels 1 Single Pulse Output — PWM Alignment Edge PWM Adjustment Period & Duty Duty or Period TM Function Summary TM Operation TM offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. When the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the TnCK2~TnCK0 bits in the TM control registers. The clock source can be a ratio of either the system clock fSYS or the internal high clock fH, the fTBC clock source or the external TCKn pin. Note that setting these bits to the value 101 will select an undefined clock input, in effect disconnecting the TM clock source. The TCKn pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting. TM Interrupts The Compact type TM has two internal interrupts, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. Rev. 1.10 60 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU TM External Pins Each of the TMs, irrespective of what type, has one TM input pin, with the label TCKn. The TM input pin, is essentially a clock source for the TM and is selected using the TnCK2~TnCK0 bits in the TMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. This external TM input pin is shared with other functions but will be connected to the internal TM if selected using the TnCK2~TnCK0 bits. The TM input pin can be chosen to have either a rising or falling active edge. The TMs each have two output pins with the label TPn. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external TPn output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other function, the TM output function must first be setup using registers. A single bit in one of the registers determines if its associated pin is to be used as an external TM output pin or if it is to have another function. All TM output pin names have a “_n” suffix. Pin names that include a “_0” or “_1” suffix indicate that they are from a TM with multiple output pins. This allows the TM to generate a complimentary output pair, selected using the I/O register data bits. CTM0 CTM1 CTM2 CTM3 CTM5 TP0_0,TP0_1 TP1_0,TP1_1 TP2_0,TP2_1 TP3_0,TP3_1 TP5_0,TP5_1 TM Output Pins TM Input/Output Pin Control Registers Selecting to have a TM input/output or whether to retain its other shared function, is implemented using one or two registers, with a single bit in each register corresponding to a TM input/output pin. Setting the bit high will setup the corresponding pin as a TM input/output, if reset to zero the pin will retain its original other function. Bit Registers 7 6 5 4 3 2 1 0 TMPC0 T3CP1 T3CP0 T2CP1 T2CP0 T1CP1 T1CP0 T0CP1 T0CP0 TMPC1 — — — — — — T5CP1 T5CP0 TM Input/Output Pin Control Registers List TMPC0 Register Bit 7 6 5 4 3 2 1 0 Name T3CP1 T3CP0 T2CP1 T2CP0 T1CP1 T1CP0 T0CP1 T0CP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7T3CP1: TP3_1 pin Control 0: Disable 1: Enable Bit 6T3CP0: TP3_0 pin Control 0: Disable 1: Enable Bit 5T2CP1: TP2_1 pin Control 0: Disable 1: Enable Rev. 1.10 61 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Bit 4T2CP0: TP2_0 pin Control 0: Disable 1: Enable Bit 3T1CP1: TP1_1 pin Control 0: Disable 1: Enable Bit 2T1CP0: TP1_0 pin Control 0: Disable 1: Enable Bit 1T0CP1: TP0_1 pin Control 0: Disable 1: Enable Bit 0T0CP0: TP0_0 pin Control 0: Disable 1: Enable TMPC1 Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — T5CP1 T5CP0 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1T5CP1: TP5_1 pin Control 0: Disable 1: Enable Bit 0T5CP0: TP5_0 pin Control 0: Disable 1: Enable Programming Considerations The TM Counter Registers and the Capture/Compare CCRA is 10-bit or 16-bit register, have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. T� Counter Register (Read onl�) T�xDL T�xDH 8-bit Buffer T�xAL T�xAH T� CCRA Register (Read/Write) Data Bus Rev. 1.10 62 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU The following steps show the read and write procedures: • Writing Data to CCRA ♦♦ Step 1. Write data to Low Byte TMxAL ––note that here data is only written to the 8-bit buffer. ♦♦ Step 2. Write data to High Byte TMxAH ––here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers. • Reading Data from the Counter Registers and CCRA ♦♦ Step 1. Read data from the High Byte TMxDH or TMxAH ––here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. ♦♦ Step 2. Read data from the Low Byte TMxDL or TMxAL ––this step reads data from the 8-bit buffer. Compact Type TM – CTM Although the simplest form of the TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive two external output pins. These two external output pins can be the same signal or the inverse signal. Compact Type TM Block Diagram (n=0, 1, 2, 3, 5) Rev. 1.10 63 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Compact TM Operation At its core is a 10-bit or 16-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is three bits wide whose value is compared with the highest three bits or eight bits in the counter while the CCRA is the ten bits or sixteen bits and therefore compares with all counter bits. The only way of changing the value of the 10-bit or 16-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Compact Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Compact Type TM Register Description Overall operation of the Compact TM is controlled using six registers. A read only register pair exists to store the internal counter 10-bit or 16-bit value, while a read/write register pair exists to store the internal 10-bit or 16-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three or eight CCRP bits. Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMnC0 TnPAU TnCK2 TnCK1 TnCK0 TnON TnRP2 TnRP1 TnRP0 TMnC1 TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR D0 TMnDL D7 D6 D5 D4 D3 D2 D1 TMnDH — — — — — — D9 D8 TMnAL D7 D6 D5 D4 D3 D2 D1 D0 TMnAH — — — — — — D9 D8 10-bit Compact TM Register List(n=0, 1, 2, 3) Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TM5C0 T5PAU T5CK2 T5CK1 T5CK0 T5ON T5RP2 T5RP1 T5RP0 TM5C1 T5M1 T5M0 T5IO1 T5IO0 T5OC T5POL T5DPX T5CCLR TM5DL D7 D6 D5 D4 D3 D2 D1 D0 TM5DH D15 D14 D13 D12 D11 D10 D9 D8 TM5AL D7 D6 D5 D4 D3 D2 D1 D0 TM5AH D15 D14 D13 D12 D11 D10 D9 D8 TM5RP D7 D6 D5 D4 D3 D2 D1 D0 16-bit Compact TM Register List TMnDL Register(n=0, 1, 2, 3) — 10-bit CTM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0TMnDL: TMn Counter Low Byte Register bit 7~bit 0 TMn 10-bit Counter bit 7~bit 0 Rev. 1.10 64 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU TMnDH Register(n=0, 1, 2, 3) — 10-bit CTM Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0TMnDH: TMn Counter High Byte Register bit 1~bit 0 TMn 10-bit Counter bit 9~bit 8 TMnAL Register(n=0, 1, 2, 3) — 10-bit CTM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0TMnAL: TMn CCRA Low Byte Register bit 7~bit 0 TMn 10-bit CCRA bit 7~bit 0 TMnAH Register(n=0, 1, 2, 3) — 10-bit CTM Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0TMnAH: TMn CCRA High Byte Register bit 1~bit 0 TMn 10-bit CCRA bit 9~bit 8 TM5DL Register — 16-bit CTM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0TM5DL: TM5 Counter Low Byte Register bit 7~bit 0 TM5 16-bit Counter bit 7~bit 0 TM5DH Register — 16-bit CTM Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0TM5DH: TM5 Counter High Byte Register bit 7~bit 0 TM5 16-bit Counter bit 15~bit 8 Rev. 1.10 65 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU TM5AL Register — 16-bit CTM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0TM5AL: TM5 CCRA Low Byte Register bit 7~bit 0 TM5 16-bit CCRA bit 7~bit 0 TM5AH Register — 16-bit CTM Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0TM5AH: TM5 CCRA High Byte Register bit 8~bit 0 TM5 16-bit CCRA bit 15~bit 8 TMnC0 Register(n=0, 1, 2, 3) — 10-bit CTM Bit 7 6 5 4 3 2 1 0 Name TnPAU TnCK2 TnCK1 TnCK0 TnON TnRP2 TnRP1 TnRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7TnPAU: TMn Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4TnCK2~TnCK0: Select TMn Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: Reserved 110: TCKn rising edge clock 111: TCKn falling edge clock These three bits are used to select the clock source for the TM0. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. Bit 3TnON: TMn Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TMn. Setting the bit high enables the counter to run, clearing the bit disables the TMn. Clearing this bit to zero will stop the counter from counting and turn off the TMn which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal Rev. 1.10 66 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU counter will retain its residual value. If the TMn is in the Compare Match Output Mode then the TMn output pin will be reset to its initial condition, as specified by the TnOC bit, when the TnON bit changes from low to high. Bit 2~0TnRP2~TnRP0: TMn CCRP 3-bit register, compared with the TMn Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TMn clocks 001: 128 TMn clocks 010: 256 TMn clocks 011: 384 TMn clocks 100: 512 TMn clocks 101: 640 TMn clocks 110: 768 TMn clocks 111: 896 TMn clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter’s highest three bits. The result of this comparison can be selected to clear the internal counter if the TnCCLR bit is set to zero. Setting the TnCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. TMnC1 Register(n=0, 1, 2, 3) — 10-bit CTM Bit 7 6 5 4 3 2 1 0 Name TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6TnM1~TnM0: Select TMn Operating Mode 00: Compare Match Output Mode 01: Undefined 10: PWM Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the TnM1 and TnM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4TnIO1~TnIO0: Select TPn_0, TPn_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Undefined Timer/counter Mode unused Rev. 1.10 67 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU These two bits are used to determine how the TMn output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TMn is running. In the Compare Match Output Mode, the TnIO1 and TnIO0 bits determine how the TMn output pin changes state when a compare match occurs from the Comparator A. The TMn output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TMn output pin should be setup using the TnOC bit in the TMnC1 register. Note that the output level requested by the TnIO1 and TnIO0 bits must be different from the initial value setup using the TnOC bit otherwise no change will occur on the TMn output pin when a compare match occurs. After the TMn output pin changes state it can be reset to its initial level by changing the level of the TnON bit from low to high. In the PWM Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the TnIO1 and TnIO0 bits only after the TMn has been switched off. Unpredictable PWM outputs will occur if the TnIO1 and TnIO0 bits are changed when the TM is running. Bit 3TnOC: TPn_0, TPn_1 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode 0: Active low 1: Active high This is the output control bit for the TMn output pin. Its operation depends upon whether TMn is being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the TMn is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of he TMn output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2TnPOL: TPn_0, TPn_1 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TPn_0 or TP0_1 output pin. When the bit is set high the TMn output pin will be inverted and not inverted when the bit is zero. It has no effect if the TMn is in the Timer/Counter Mode. Bit 1TnDPX: TMn PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0TnCCLR: Select TMn Counter clear condition 0: TMn Comparator P match 1: TMn Comparator A match This bit is used to select the method which clears the counter. Remember that the Compact TMn contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the TnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The TnCCLR bit is not used in the PWM Mode. Rev. 1.10 68 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU TM5C0 Register—16-bit CTM Bit 7 6 5 4 3 2 1 0 Name T5PAU T5CK2 T5CK1 T5CK0 T5ON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7T5PAU: TM5 Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4T5CK2~T5CK0: Select TM5 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: Reserved 110: TCK5 rising edge clock 111: TCK5 falling edge clock These three bits are used to select the clock source for the TM5. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. Bit 3T5ON: TM5 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM5. Setting the bit high enables the counter to run, clearing the bit disables the TM5. Clearing this bit to zero will stop the counter from counting and turn off the TM5 which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. If the TM5 is in the Compare Match Output Mode then the TM5 output pin will be reset to its initial condition, as specified by the T5OC bit, when the T5ON bit changes from low to high. Bit 2~0 Unimplemented, read as "0" TM5C1 Register — 16-bit CTM Bit 7 6 5 4 3 2 1 0 Name T5M1 T5M0 T5IO1 T5IO0 T5OC T5POL T5DPX T5CCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6T5M1~T5M0: Select TM5 Operating Mode 00: Compare Match Output Mode 01: Undefined 10: PWM Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T5M1 and T5M0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Rev. 1.10 69 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Bit 5~4T5IO1~T5IO0: Select TP5_0, TP5_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Undefined Timer/counter Mode unused These two bits are used to determine how the TM5 output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM5 is running. In the Compare Match Output Mode, the T5IO1 and T5IO0 bits determine how the TM5 output pin changes state when a compare match occurs from the Comparator A. The TM5 output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM5 output pin should be setup using the T5OC bit in the TM5C1 register. Note that the output level requested by the T5IO1 and T5IO0 bits must be different from the initial value setup using the T5OC bit otherwise no change will occur on the TM5 output pin when a compare match occurs. After the TM5 output pin changes state it can be reset to its initial level by changing the level of the T5ON bit from low to high. In the PWM Mode, the T5IO1 and T5IO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the T5IO1 and T5IO0 bits only after the TM5 has been switched off. Unpredictable PWM outputs will occur if the T5IO1 and T5IO0 bits are changed when the TM is running. Bit 3T5OC: TP5_0, TP5_1 Output control bit Compare Match output Mode 0: Initial low 1: Initial high PWM Mode 0: Active low 1: Active high This is the output control bit for the TM5 output pin. Its operation depends upon whether TM5 is being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the TM5 is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of he TM5 output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2T5POL: TP5_0, TP5_1 output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP5_0 or TP5_1 output pin. When the bit is set high the TM5 output pin will be inverted and not inverted when the bit is zero. It has no effect if the TMn is in the Timer/Counter Mode. Bit 1T5DPX: TM5 PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Rev. 1.10 70 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Bit 0T5CCLR: Select TM5 Counter clear condition 0: TM5 Comparator P match 1: TM5 Comparator A match This bit is used to select the method which clears the counter. Remember that the Compact TM5 contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the T5CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The T5CCLR bit is not used in the PWM Mode. TM5RP Register – 16-bit CTM Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 TM5 CCRP 8-bit register, compared with the TM5 Counter bit 15~bit 8 Comparator P Match Period 0: 1024 TMn clocks 1~255: 256×(1~255)TM5 clocks These three bits are used to setup the value on the internal CCRP 8-bit register, which are then compared with the internal counter’s highest eight bits. The result of this comparison can be selected to clear the internal counter if the T5CCLR bit is set to zero. Setting the T5CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. Compact Type TM Operating Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Match Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to “00” respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for the Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, or 16-bit, FFFF Hex ,value, however here the TnAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the TM output pin will change state. The TM output pin condition however only changes state when a TnAF interrupt request flag Rev. 1.10 71 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero then no pin change will take place. Counter Value Counter overflow CCRP=0 0x�FF or 0xFFFF TnCCLR = 0; Tn� [1:0] = 00 CCRP > 0 Counter cleared b� CCRP value CCRP > 0 Counter Restart Resume CCRP Pause Stop CCRA Time TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF T� O/P Pin Output pin set to initial Level Low if TnOC=0 Output not affected b� TnAF flag. Remains High until reset b� TnON bit Output Toggle with TnAF flag Here TnIO [1:0] = 11 Toggle Output select Note TnIO [1:0] = 10 Active High Output select Output Inverts when TnPOL is high Output Pin Reset to Initial value Output controlled b� other pin-shared function Compare Match Output Mode – TnCCLR=0 Note: 1. With TnCCLR=0, a Comparator P match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge 4. n=0, 1, 2, 3, 5 Rev. 1.10 72 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU TnCCLR = 1; TnM[1, 0] = 00 Counter Value CCRA = 0 Counter overflows CCRA > 0 Counter cleared by CCRA value 0x3FF or 0xFFFF CCRA = 0 CCRA Pause Resume Counter Reset Stop CCRP Time TnON bit TnPAU bit TnPOL bit No TnAF flag generated on CCRA overflow CCRA Int. Flag TnAF CCRP Int. Flag TnPF TM O/P Pin Output does not change TnPF not generated Output not affected by TnAF flag remains High until reset by TnON bit Output Pin set to Initial Level Low if TnOC = 0 Output Toggle with TnAF flag Now TnIO1, TnIO0 = 10 Active High Output Select Output controlled by other pin-shared function Output inverts when TnPOL is high Output Pin Reset to initial value Here TnIO1, TnIO0 = 11 Toggle Output Select Compare Match Output Mode – TnCCLR=1 Note: 1. With TnCCLR=1, a Comparator A match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge 4. The TnPF flag is not generated when TnCCLR=1 5. n=0, 1, 2, 3, 5 Rev. 1.10 73 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is used to reverse the polarity of the PWM output waveform. 10-bit CTM, PWM Mode, Edge-aligned Mode, TnDPX=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 Duty CCRA If fSYS=16MHz, TM clock source is fSYS/4, CCRP=100b and CCRA=128, The CTM PWM output frequency=(fSYS/4)/512=fSYS/2048=7.8125 kHz, duty=128/512=25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. 10-bit CTM, PWM Mode, Edge-aligned Mode, TnDPX=1 CCRP 001b 010b 011b 100b 128 256 384 512 Period Duty 101b 110b 111b 000b 768 896 1024 CCRA 640 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value. Rev. 1.10 74 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU 16-bit CTM, PWM Mode, Edge-aligned Mode, TnDPX=0 CCRP 1~255 Period CCRP×256 Duty 0 65536 CCRA If fSYS=16MHz, TM clock source is fSYS/4, CCRP=2 and CCRA=128, The CTM PWM output frequency=(f SYS /4)/(2×256)=f SYS /2048=7.8125 kHz, duty=128/ (2×256)=25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. 16-bit CTM, PWM Mode, Edge-aligned Mode, TnDPX=1 CCRP 1~255 Period 0 CCRA CCRP×256 Duty 65536 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the (CCRP×256) except when the CCRP value is equal to 0. Counter Value TnDPX = 0; TnM [1:0] = 10 Counter cleared by CCRP Counter Reset when TnON returns high CCRP Pause Resume Counter Stop if TnON bit low CCRA Time TnON TnPAU TnPOL CCRA Int. Flag TnAF CCRP Int. Flag TnPF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM Duty Cycle set by CCRA PWM Period set by CCRP PWM resumes operation Output controlled by Output Inverts other pin-shared function when TnPOL = 1 PWM Mode – TnDPX=0 Note: 1. Here TnDPX=0 – Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when TnIO [1:0]=00 or 01 4. The TnCCLR bit has no influence on PWM operation 5. n=0, 1, 2, 3, 5 Rev. 1.10 75 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Counter Value TnDPX = 1; TnM [1:0] = 10 Counter cleared by CCRA Counter Reset when TnON returns high CCRA Pause Resume Counter Stop if TnON bit low CCRP Time TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM Duty Cycle set by CCRP PWM Period set by CCRA PWM resumes operation Output controlled by Output Inverts other pin-shared function when TnPOL = 1 PWM Mode – TnDPX=1 Note: 1. Here TnDPX=1 – Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when TnIO [1:0]=00 or 01 4. The TnCCLR bit has no influence on PWM operation 5. n=0, 1, 2, 3, 5 Buzzer control 10-bit CTM TM2 Buzzer HT45FM2C The 10-bit CTM can drive an external buzzer using its PWM mode to provide volume control. Rev. 1.10 76 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Capture Timer Module – CAPTM The Capture Timer Module is a timing unit specifically used for Motor Control purposes. The CAPTM is controlled by a program selectable clock source and by three interrupt sources from the motor positioning hall sensors. Capture Timer Overview At the core of the Capture Timer is a 16-bit count-up counter which is driven by a user selectable internal clock source which is some multiple of the system clock or by the PWM. There is also an internal comparator which compares the value of this 16-bit counter with a pre-programmed 16bit value stored in two registers. There are two basic modes of operation, a Compare Mode and a Capture Mode, each of which can be used to reset the internal counter. When a compare match situation is reached a signal will be generated to reset the internal counter. The counter can also be cleared when a capture trigger is generated by the three external sources, INT0A, INT0B and INT0C. Ha_Int Hb_Int Hc_Int CAPTMCH /CAPTMCL Rising/Falling /Double edge Detector Ha Hb Hc CLR INT0A INT0B INT0C Noise Filter x3 Rising/Falling /Double edge Detector CapTM_Over 16-bit CAPTM CLK compare CapTM_Cmp Compare Register CAPTMAH /CAPTMAL CAPS1/CAPS CAPTCK[2:0 0 ] Clear capture counter PWMO fSYS/2 fSYS/64 fSYS/128 Capture Timer Block Diagram Capture Timer Register Description Overall operation of the Capture Timer is controlled using eight registers. A read only register pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store the internal 16-bit compare value. An additional read only register pair is used to store the capture value. The remaining two registers are control registers which setup the different operating and control modes. Rev. 1.10 77 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CAPTC0 CAPTPAU CAPTCK2 CAPTCK1 CAPTCK0 CAPTON — CAPS1 CAPS0 CAPTC1 CAPEG1 CAPEG0 CAPEN CAPNFT CAPNFS CAPFIL CAPCLR CAMCLR CAPTMDL D7 D6 D5 D4 D3 D2 D1 D0 CAPTMDH D15 D14 D13 D12 D11 D10 D9 D8 CAPTMAL D7 D6 D5 D4 D3 D2 D1 D0 CAPTMAH D15 D14 D13 D12 D11 D10 D9 D8 CAPTMCL D7 D6 D5 D4 D3 D2 D1 D0 CAPTMCH D15 D14 D13 D12 D11 D10 D9 D8 Capture Timer Register List CAPTC0 Register Bit Name 7 6 5 4 3 CAPTPAU CAPTCK2 CAPTCK1 CAPTCK0 CAPTON 2 1 0 — CAPS1 CAPS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7CAPTPAU: CAPTM Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the CAPTM will remain power up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again Bit 6~4CAPTCK2~CAPTCK0: Select CAPTM Counter clock 000: PWMO 001: fH/2 010: fH/4 011: fH/8 100: fH/16 101: fH/32 110: fH/64 111: fH/128 These three bits are used to select the clock source for the CAPTM. The clock source fH is the high speed system oscillator. Bit 3CAPTON: CAPTM Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the CAPTM. Setting the bit high enables the counter to run, clearing the bit disables the CAPTM. Clearing this bit to zero will stop the counter from counting and turn off the CAPTM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. Bit 2 Unimplemented, read as "0" Bit 1~0CAPS1~CAPS0: capture source select 00: INT0A 01: INT0B 10: INT0C 11: Unused Rev. 1.10 78 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU CAPTC1 Register Bit 7 6 5 4 3 Name CAPEG1 CAPEG0 CAPEN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 CAPNFT CAPNFS 2 CAPFIL 1 0 CAPCLR CAMCLR Bit 7~6CAPEG1~CAPEG0: Defines CAPTM capture active edge 00: Disabled CAPTM capture 01: Rising edge capture 10: Falling edge capture 11: Dual edge capture Bit 5CAPEN: CAPTM Capture input control 0: Disable 1: Enable This bit enables/disables the CAPTM capture input source. Bit 4CAPNFT: Defines CAPTM Noise Filter sample times 0: Twice 1: 4 times The CAPTM Noise Filter circuit requires sampling twice or 4 times continuously, when they are all the same, the signal will be acknowledged. The sample time is decided by CAPNFS. Bit 3CAPNFS: CAPTM Noise Filter clock source Select 0: tSYS 1: 4tSYS The clock source for Capture Timer Module Counter is provided by fSYS or fSYS /4. Bit 2CAPFIL: CAPTM capture input filter Control 0: Disable 1: Enable This bit enables/disables the CAPTM capture input filter. Bit 1CAPCLR: CAPTM Counter capture auto-reset Control 0: Disable 1: Enable This bit enables/disables the automatic reset of the counter when the value in CAPTMDL and CAPTMDH have been transferred into the capture registers CAPTMCL and CAPTMCH. Bit 0CAMCLR: CAPTM Counter compare match auto-reset Control 0: Disable 1: Enable This bit enables/disables the automatic reset of the counter when the a compare match has occurred. Rev. 1.10 79 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU CAPTMDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0CAPTMDL: CAPTM Counter Low Byte Register bit 7~bit 0 CAPTM 16-bit Counter bit 7 ~ bit 0 CAPTMDH Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0CAPTMDH: CAPTM Counter High Byte Register bit 7~bit 0 CAPTM 16-bit Counter bit 15 ~ bit 8. CAPTMAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0CAPTMAL: CAPTM Compare Low Byte Register bit 7~bit 0 CAPTM 16-bit Compare Register bit 7~bit 0. CAPTMAH Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0CAPTMAH: CAPTM Compare High Byte Register bit 7~bit 0 CAPTM 16-bit Compare Register bit 15~bit 8. CAPTMCL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR x x x x x x x x "x"unknown Bit 7~0CAPTMCL: CAPTM Capture Low Byte Register bit 7~bit 0 CAPTM 16-bit Capture Register bit 7~bit 0 Rev. 1.10 80 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU CAPTMCH Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R R R R R R R R POR x x x x x x x x "x"unknown Bit 7~0CAPTMCH: CAPTM Capture High Byte Register bit 7~bit 0 CAPTM 16-bit Capture Register bit 15~bit 8. Capture Timer Operation The Capture Timer is used to detect and measure input signal pulse widths and a periods. It can be used in both a Capture or Compare Mode. The timer inputs are the three capture inputs INT0A, INT0B and INT0C. Each of these capture inputs has its own edge detector selection, to choose between high, low or both edge trigger types. The CAPTON bit is used to control the overall Capture Timer enable/disable function. Disabling the Capture Module when not used will reduce the device power consumption. Additionally the capture input control is enabled/disabled using the CAPEN control bit. The trigger edge option are setup using the CAPEG1 and CAPEG0 bits, to select either positive edge, negative edge or both edges. Capture Mode Operation The capture timer module contains 2 capture registers, CAPTMCL and CAPTMCH, which are used to store the present value in the counter. When the Capture Module is enabled, then each time an external pin receives a valid trigger signal, the content of the free running 16-bit counter, which is contained in the CAPTMDL and CAPTMDH registers, will be captured into the capture registers, CAPTMCL and CAPTMCH. When this occurs, the CAPOF interrupt flag bit in the interrupt control register will be set. If this interrupt is enabled by setting the interrupt enable bit, CAPOE, high, an interrupt will be generated. If the CAPCLR bit is set high, then the 16-bit counter will be automatically reset after a capture event occurs. Compare Mode Operation When the timer is used in the compare mode, the CAPTMAL and CAPTMAH registers are used to store the 16-bit compare value. When the free running value of the count-up 16-bit counter reaches a value equal to the programmed values in these compare registers, the CAPCF interrupt flag will be set which will generate an interrupt if its related interrupt enable bit is set. If the CAMCLR bit is set high, then the counter will be reset to zero automatically when a compare match condition occurs. The rotor speed or a stalled motor condition can be detected by setting the compare registers to compare the captured signal edge transition time. If a rotor stall condition occurs, then a compare interrupt will be generated, after which the PWM motor drive circuit can be shut down to prevent a motor burn out situation. Noise Filter The timer also includes a noise Filter which is used to filter out unwanted glitches or pulses on the trigger input pins. This function is enabled using the CAPFIL bit. If the noise filter is enabled, the capture input signals must be sampled either 2 or 4 times, in order to recognize an edge as a valid capture event. The sampling 2 or 4 time units are based o either tSYS or 4 × tSYS determined using the CAPNFS bit. Rev. 1.10 81 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU I/P Noise Filter Sampling O/P Noise Filter with CAPNFT and CATNFS = 0 Infrared Receiver The device contains a function block to receive signals from infrared remote controls. These circuits assist with the implementation of integrated remote control functions for remote motor control. Functional Description The infrared receiver functional block contains a number of units to facilitate the implementation of infrared signal decoding such as IR code receiver circuit, noise filter, RMT capture circuit and RMTE control. RX_Int IR TX :SC5104 IR RX CKT RX_IN IO CKT Noise Filter 8-bitx� R�T R�T0F R�TVF R�T1F R�T0 R�T1 R�TE R�TE_CTL 10-bit CT� CT�_Int IR_RX Block Infrared Receiver Block Diagram The external RX_IN pin is connected to an internal filter to reduce the possibility of unwanted event counting events or inaccurate pulse width measurements due to adverse noise or spikes on the RX_ IN input signal. In order to ensure that the IR Code Rx circuit and the motor control circuit works normally. The RMT Capture circuit is implemented using two 8-bit RMT circuits, RMT0 and RMT1 registers to decode IR. As the IR code can be transmitted repeatedly, the RMTE control circuit can make the decoding time short and reduce the effects which generated by the remote controlling on the motor controlling. The noise filter circuit is a I/O filtering surge compare which can filter micro-second grade sharp-noise. Antinoise pulse width maximum: (NF_VIH[5:0]-NF_VIL[5:0])×5μs Rev. 1.10 82 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU RMT Timing Noise Filter A noise filter circuit is included to reduce the possibility of noise spikes or erroneous signal inputs being decoded as genuine inputs signals. Dat_In Dat_Out Noise Filter NF_VIH[4:0] NF_VIL[4:0] Dat_In Dat_Out Noise Filter Noise Filter Registers Description NF_VIH Register Bit 7 6 5 4 3 2 1 0 Name NF_BYPS — — D4 D3 D2 D1 D0 R/W R/W — — R/W R/W R/W R/W R/W POR 0 — — 1 1 0 0 1 3 2 1 0 Bit 7NF_BYPS: Bypass Noise Filter Enable 0: Disable 1: Enable, Dat_Out=Dat_In Bit 6~5 Unimplemented, read as "0" Bit 4~0 NF_VIH Bit 4~Bit 0 NF_VIL Register Rev. 1.10 Bit 7 6 5 Name — — — D4 D3 D2 D1 D0 R/W — — — R/W R/W R/W R/W R/W POR — — — 0 1 0 1 0 Bit 7~5 Unimplement, read as "0" Bit 4~0 NF_VIL Bit 4~Bit0 4 83 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Remote Control Timer – RMT The device contains two 8-bit RMT timer functions which are used for IR signal decoding. This function can be used to allow remote controllers to change the required motor operating mode. The Remote Control Timer can detect an edge transition on the RX_IN pin, after which three interrupt. signals can be generated. These are, rising edge interrupt signal, falling edge interrupt signal and a timer overflow interrupt signal. The control registers, RMT0 and RMT1, are used to store the captured data which measures the infrared input signal edge interval changes. The recorded data can then be used for IR decoding purposes. The application program can be used to decode the IR code frame data in the following ways: • Disabling the RMTE When an IR data frame has been decoded by the program, then the RMT can be disabled by the following: RME=0 → RMTE=0. • Enabling the RMTE Use the 10-bit CTM as the IR Decode scan restart mechanism to improve the motor control efficiency. ♦ S/W Mode: RME is set to high by the S/W. ♦ H/W Mode: when a CTM_Int is detected by the H/W (about 0.3s~1s) , then set RMTE. Note: fTBC is selected as the CTM clock source by S/W and adjusted using the TBC register. 0.3sec~1sec RMTE RME_Reg CTM_Int/RME_Reg Hardware Mode Rev. 1.10 84 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU RMT Register Description Three registers are used for overall control of the Remote Control Timer. A control register, RMTC, is used to setup the timer, while registers, RMT0 and RMT1, are used to store the decoded signal data. RMTC Register Bit 7 6 5 4 3 2 1 0 Name RMS1 RMS0 RMCS RME ERMTV ERMT1 ERMT0 RMEMS R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6RMS1, RMS0: Selects the Remote Control Timer clock 00: fX/25 01: fX/26 10: fX/27 11: fX/28 Bit 5RMCS: Selects the Remote Control Timer clock source fX 0: fsys/4 1: fsys Bit 4RME: Controls the remote control timer 0: Disable and clear counter to 0 1: Enable and start counting Bit 3ERMTV: Controls the Remote Control Timer overflow interrupt 0: Disable 1: Enable Bit 2ERMT1: Controls the Remote Control Timer falling edge interrupt 0: Disable 1: Enable Bit 1ERMT0: Controls the Remote Control Timer rising edge interrupt 0: Disable 1: Enable Bit 0RMEMS: RMTE Circuit Mode Select 0: S/W Mode, RMTE start circuit is defined by RME bit via S/W 1: H/W Mode, RMTE start circuit is defined by CTM interrupt via H/W RMT0 Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0RMT0: low level edge capture register Bit 7~Bit 0 RMT1 Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0RMT1: high level edge capture register Bit 7~Bit 0 Rev. 1.10 85 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Analog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. This device also includes some special A/D features for specific use in motor control applications. A/D Overview This device contains a 9-channel analog to digital converter, 8-channel can be directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 10-bit digital value. An additional channel is connected to the external current sense input pin, Is, via an internal operational amplifier for signal amplification, before being transferred to the A/D converter input. A set of what are known as high and low boundary registers, allow the A/D converter digital output value to be compared with upper and lower limit values and a corresponding interrupt to be generated. An additional delay function allows a delay to be inserted into the PWM triggered A/D conversion start process to reduce the possibility of erroneous analog value sampling when the output power transistors are switching large motor currents. Input Channels A/D Channel Select Bits Input Pins 9 ACS3~ACS0 AN0~AN7, Is The accompanying block diagram shows the overall internal structure of the A/D converter, together with its associated registers. Dela� Register ADDL PW� Period Interrupt signal PW� dut� Interrupt signal Start Convert Dela� Time �UX �UX DLSTR bit Dela� on/off control PWIS bit ADSTR bit ADSTS bit High Boundar� Value PA0/AN0 PA1/AN1 A/D Conversion Start Signal PA�/AN� Compare Converted Value with Upper and Lower Limits ADHVDH ADHVDL PA�/AN� PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 ADRH ADC ADRL Programmable Gain Amplifier Int_AD_EOC Current Sense Pin Input PB�/Is EOCB bit AD HL/LV Trigger Int_AHL_Lim Interrupt Signal ADLVDH ADLVDL Low Boundar� Value ACS�~ACS0 OPAVS0 ADCHVE OPAVS� ADCLVE Gain Control Bits Gain = X1/X5/X10/X�0 Comparison T�pe Control Bits A/D Converter Structure Rev. 1.10 86 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU A/D Converter Register Description Overall operation of the A/D converter is controlled using several registers. A read only register pair ADRL/ADRH exists to store the ADC data 10-bit value. The ADLVDL/ADLVDH and ADHVDL/ ADHVDH registers are used to store the boundary limit values of the ADC interrupt trigger while the ADDL register is used to setup the start conversion delay time. The remaining registers are control registers which setup the operating and control function of the A/D converter. Register Name ADRL Bit 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 ADRH — — — — — — D9 D8 ADCR0 ADSTR EOCB ADOFF — ACS3 ACS2 ACS1 ACS0 ADCR1 ADCHVE ADCLVE ADCK2 ADSTS DLSTR PWIS ADCK1 ADCK0 ANCSR0 PCR7 PCR6 PCR5 PCR4 PCR3 PCR2 PCR1 PCR0 ANCSR1 — — — — — — — PCR8 ADDL D7 D6 D5 D4 D3 D2 D1 D0 ADLVDL D7 D6 D5 D4 D3 D2 D1 D0 ADLVDH — — — — — — D9 D8 ADHVDL D7 D6 D5 D4 D3 D2 D1 D0 ADHVDH — — — — — — D9 D8 A/D Converter Register List A/D Converter Data Registers – ADRL, ADRH As this device contains an internal 10-bit A/D converter, it requires two data registers to store the converted value. These are a high byte register, known as ADRH, and a low byte register, known as ADRL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. ADRL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR x x x x x x x x "x"unknown Bit 7~0 A/D Low Byte Register Bit 7~Bit 0 ADRH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — x x "x"unknown Rev. 1.10 Bit 7~2 Unimplemented, read as "0" Bit 1~0 A/D High Byte Register Bit 1, Bit 0 87 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU A/D Converter Control Registers – ADCR0, ADCR1, ANCSR0, ANCSR1, ADDL To control the function and operation of the A/D converter, four control registers known as ADCR0, ADCR1, ANCSR0 and ANCSR1 are provided. These 8-bit registers define functions such as the selection of which analog channel is connected to the internal A/D converter, the digitised data format, the A/D clock source as well as controlling the start function and monitoring the A/D converter end of conversion status. The ACS3~ACS0 bits in the ADCR0 register define the ADC input channel number. As the device contains only one actual analog to digital converter hardware circuit, each of the individual 9 analog inputs must be routed to the converter. It is the function of the ACS3~ACS0 bits to determine which analog channel input pins or Is pin is actually connected to the internal A/D converter. The ANCSR0 and ANCSR1 control registers contain the PCR8~PCR0 bits which determine which pins on Port A or PB3 is used as analog inputs for the A/D converter input and which pins are not to be used as the A/D converter input. Setting the corresponding bit high will select the A/D input function, clearing the bit to zero will select either the I/O or other pin-shared function. When the pin is selected to be an A/D input, its original function whether it is an I/O or other pin-shared function will be removed. In addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an A/D input. The ADDL register exists to store the ADC delay start time. ADCR0 Register Bit 7 6 5 4 3 2 1 0 Name ADSTR EOCB ADOFF — ACS3 ACS2 ACS1 ACS0 R/W R/W R R/W — R/W R/W R/W R/W POR 0 1 1 — 0 0 0 0 Bit 7ADSTR: Start the A/D conversion 0→1→0: Start 0→1: Reset the A/D converter and set EOCB to “1” This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. When the bit is set high the A/D converter will be reset. Bit 6EOCB: End of A/D conversion flag 0: A/D conversion ended 1: A/D conversion in progress This read only flag is used to indicate when an A/D conversion process has completed. When the conversion process is running, the bit will be high. Bit 5ADOFF : ADC module power on/off control bit 0: ADC module power on 1: ADC module power off This bit controls the power to the A/D internal function. This bit should be cleared to zero to enable the A/D converter. If the bit is set high then the A/D converter will be switched off reducing the device power consumption. As the A/D converter will consume a limited amount of power, even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. Note: 1. it is recommended to set ADOFF=1 before entering IDLE/SLEEP Mode for saving power. 2. ADOFF=1 will power down the ADC module. Bit 4 Unimplemented, read as "0" Bit 3~0ACS3 ~ ACS0: Select A/D channel 0000: AN0 0001: AN1 Rev. 1.10 88 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU 0010: AN2 0011: AN3 0100: AN4 0101: AN5 0110: AN6 0111: AN7 1000: Is currrent sense input - via amplifier These are the A/D channel select control bits. As there is only one internal hardware A/D converter each of the eight A/D inputs must be routed to the internal converter using these bits. ADCR1 Register Bit 7 6 5 Name ADSTS DLSTR PWIS 4 R/W R/W R/W R/W R/W POR 0 0 0 0 3 2 1 0 ADCK2 ADCK1 ADCK0 R/W R/W R/W R/W 0 0 0 0 ADCHVE ADCLVE Bit 7ADSTS: Select ADC trigger circuit 0: Select ADSTR trigger circuit 1: Select DELAY trigger circuit Bit 6DLSTR: Delay start function control 0: Disable but need to set ADDL to "0" 1: Enable but need to set ADDL to non zero value Bit 5PWIS: Select PWM Module interrupt source 0: Select PWM period interrupt 1: Select PWM duty interrupt Bit 4~3ADCHVE~ADCLVE: Select ADC interrupt trigger source 00: ADLVD[9:0] < ADR[9:0] < ADHVD[9:0] 01: ADR[9:0] <= ADLVD[9:0] 10:ADR[9:0] >= ADHVD[9:0] 11: ADR[9:0] <= ADLVD[9:0] or ADR[9:0] >= ADHVD[9:0] Bit 2~0ADCK2~ADCK0: Select ADC clock source 000: fSYS 001: fSYS/2 010: fSYS/4 011: fSYS/8 100: fSYS/16 101: fSYS/32 110: fSYS/64 111: Undefined These three bits are used to select the clock source for the A/D converter. Rev. 1.10 89 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU ANCSR0 Register Bit 7 6 5 4 3 2 1 0 Name PCR7 PCR6 PCR5 PCR4 PCR3 PCR2 PCR1 PCR0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7PCR7: A/D input pin select 0: Not A/D input 1: A/D input, AN7 Bit 6PCR6: A/D input pin select 0: Not A/D input 1: A/D input, AN6 Bit 5PCR5: A/D input pin select 0: Not A/D input 1: A/D input, AN5 Bit 4PCR4: A/D input pin select 0: Not A/D input 1: A/D input, AN4 Bit 3PCR3: A/D input pin select 0: Not A/D input 1: A/D input, AN3 Bit 2PCR2: A/D input pin select 0: Not A/D input 1: A/D input, AN2 Bit 1PCR1: A/D input pin select 0: Not A/D input 1: A/D input, AN1 Bit 0PCR0: A/D input pin select 0: Not A/D input 1: A/D input, AN0 ANCSR1 Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — — PCR8 R/W — — — — — — — R/W POR — — — — — — — 1 Bit 7~1 Unimplemented, read as "0" Bit 0PCR8: A/D input pin select 0: Not A/D input 1: A/D input, Is input, AN8 ADDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.10 ADC Delay-Time register Bit 7~Bit 0 Delay-Time Value (count by system clock) 90 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU A/D Converter Boundary Registers – ADLVDL, ADLVDH, ADHVDL, ADHVDH The device contains what are known as boundary registers to store fixed values for comparison with the A/D converter converted value stored in ADRL and ADRH. There are two pairs of registers, a high boundary pair, known as ADHVDL and ADHVDH and a low boundary pair known as ADLVDL and ADLVDH. ADLVDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 ADC Low Boundary Low Byte Register Bit 7~Bit 0 ADLVDH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 2 1 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 ADC Low Boundary High Byte Register Bit 1, Bit 0 ADHVDL Register Bit 7 6 5 4 3 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 3 2 1 0 Bit 7~0 ADC High Boundary Low Byte Register Bit 7~Bit 0 ADHVDH Register Bit 7 6 5 4 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 "x"unknown Rev. 1.10 Bit 7~2 Unimplemented, read as "0" Bit 1~0 ADC High Boundary High Byte Register Bit 1~Bit 0 91 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU A/D Operation There are two ways to initiate an A/D Converter conversion cycle, selected using the ADSTS bit. The first of these is to use the ADSTR bit in the ADCR0 register used to start and reset the A/D converter. When the microcontroller program sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. When the ADSTR bit is brought from low to high but not low again, the EOCB bit in the ADCR0 register will be set high and the analog to digital converter will be reset. The second method of initiating a conversion is to uese the PWM interrupt signal. This can be sourced from either the PWM period or duty interrupt signal, selected using the PWIS bit. The DLSTR bit can activate a delay function which inserts a delay time between the incoming PWM interrupt signal and the actual start of the A/D conversion process, with the actual time being setup using the ADDL register. The actual delay time is calculated by the register content multiplied by the system clock period. The delay between the PWM interrupt and the start of the A/D conversion is to reduce the possibility of erroneous analog samples being taken during the time of large transient current switching by the motor drive transistors. Note that if the DLSTR bit selects no delay the ADDL register must be cleared to zero and vice-versa if the delay is selected, then a non-zero value must be programmed into the ADDL register. The EOCB bit in the ADCR0 register is used to indicate when the analog to digital conversion process is complete. This bit will be automatically set to zero by the microcontroller after a conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll the EOCB bit in the ADCR0 register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen to be either fSYS or a subdivided version of fSYS. The division ratio value is determined by the ADCK2~ADCK0 bits in the ADCR1 register. Although the A/D clock source is determined by the system clocky, fSYS, and by bits ADCK2~ADCK0, there are some limitations on the maximum A/D clock source speed that can be selected. As the minimum value of permissible A/D clock period, tADCK, is 0.5μs, care must be taken for system clock frequencies equal to or greater than 4MHz. For example, if the system clock operates at a frequency of 4MHz, the ADCK2~ADCK0 bits should not be set to “000”. Doing so will give A/D clock periods that are less than the minimum A/D clock period which may result in inaccurate A/D conversion values. Refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum A/D Clock Period. A/D Clock Period (tADCK) ADCK2, ADCK1, ADCK0 =000 (fSYS) ADCK2, ADCK1, ADCK0 =001 (fSYS/2) ADCK2, ADCK1, ADCK0 =010 (fSYS/4) ADCK2, ADCK1, ADCK0 =011 (fSYS/8) ADCK2, ADCK1, ADCK0 =100 (fSYS/16) ADCK2, ADCK1, ADCK0 =101 (fSYS/32) ADCK2, ADCK1, ADCK0 =110 (fSYS/64) ADCK2, ADCK1, ADCK0 =111 5MHz 200ns* 400ns* 800ns 1.6μs 3.2μs 6.4μs 12.8μs Undefined 10MHz 100ns* 200ns* 400ns* 800ns 1.6μs 3.2μs 6.4μs Undefined 20MHz 50ns* 100ns* 200ns* 400ns* 800ns 1.6μs 3.2μs Undefined fSYS A/D Clock Period Examples Controlling the power on/off function of the A/D converter circuitry is implemented using the ADOFF bit in the ADCR0 register. This bit must be zero to power on the A/D converter. Even if no pins are selected for use as A/D inputs by clearing the PCR7~PCR0 bits in the ANCSR0 register and PCR8 in the ANCSR1 register, if the ADOFF bit is zero then some power will still be consumed. In power conscious applications it is therefore recommended that the ADOFF is set high to reduce power consumption when the A/D converter function is not being used. Rev. 1.10 92 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU The boundary register pairs, ADHVDL/ADHVDH and ADLVDL/ADLVDH contain preset values which can be compared with the A/D converted values in the ADRL/ADRH registers. Various types of comparisons can be made as defined by the ADCLVE and ADCHVE bits and an interrupt generated to inform the system that either the lower or higher boundary has been exceeded. This function can be used to ensure that the motor current operates within safe working limits. A/D Input Pins All of the A/D analog input pins are pin-shared with the I/O pins on Port A as well as other functions. The PCR7~PCR0 bits in the ANCSR0 register and PCR8 bit in the ANCSR1 register, determine whether the input pins are setup as A/D converter analog inputs or whether they have other functions. If the PCR8~PCR0 bits for its corresponding pin is set high then the pin will be setup to be an A/D converter input and the original pin functions disabled. In this way, pins can be changed under program control to change their function between A/D inputs and other functions. All pullhigh resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as A/D inputs. Note that it is not necessary to first setup the A/D pin as an input in the PAC or PBC port control registers to enable the A/D input as when the PCR8~PCR0 bits enable an A/D input, the status of the port control register will be overridden. Summary of A/D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A/D conversion process. • Step 1 Select the required A/D conversion clock by correctly programming bits ADCK2~ADCK0 in the ADCR1 register. • Step 2 Enable the A/D by clearing the ADOFF bit in the ADCR0 register to zero. • Step 3 Select which channel is to be connected to the internal A/D converter by correctly programming the ACS3~ACS0 bits which are also contained in the ADCR0 register. • Step 4 Select which pins are to be used as A/D inputs and configure them by correctly programming the PCR7~PCR0 bits in the ANCSR0 register and PCR8 in the ANCSR1. • Step 5 Select which trigger circuit is to be used by correctly programming the ADSTS bits in the ADCR1. • Step 6 If the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the A/D converter interrupt function is active. The master interrupt control bit, EMI, and the A/D converter interrupt bit, AEOCE, must both be set high to do this. • Step 7 If the step 5 selects ADSTR trigger circuit, the analog to digital conversion process can be initialised by setting the ADSTR bit in the ADCR0 register from low to high and then low again. Note that this bit should have been originally cleared to zero. If the step 5 selects PWM interrupt trigger Delay circuit, the Delay start function can be enabled by setting the DLSTR bit in the ADCR1 register. • Step 8 To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR0 Rev. 1.10 93 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU register can be polled. The conversion process is complete when this bit goes low. When this occurs the A/D data register ADRL and ADRH can be read to obtain the conversion value. As an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an A/D interrupt to occur. Note: When checking for the end of the conversion process, if the method of polling the EOCB bit in the ADCR0 register is used, the interrupt enable step above can be omitted. The accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is 16tADCK where tADCK is equal to the A/D clock period. ADCLK 0 1 2 3 4 10 Tst START Tckl 11 12 Tadc k Tckh Tstart EOCB Tdeoc D[5:0] ADON 000H Ton Tdout Toff A/D Conversion Timing Programming Considerations During microcontroller operations where the A/D converter is not being used, the A/D internal circuitry can be switched off to reduce power consumption, by setting bit ADOFF high in the ADCR0 register. When this happens, the internal A/D converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. A/D Transfer Function As the device contains a 10-bit A/D converter, its full-scale converted digitised value is equal to 3FFH. Since the full-scale analog input value is equal to the VDD voltage, this gives a single bit analog input value of VDD divided by 4096. 1 LSB=VDD ÷ 4096 The A/D Converter input voltage value can be calculated using the following equation: A/D input voltage=A/D output digital value × VDD ÷ 4096 The diagram shows the ideal transfer function between the analog input value and the digitised output value for the A/D converter. Except for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 LSB below the VDD level. Rev. 1.10 94 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Ideal A/D Transfer Function A/D Programming Example The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR0 register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using an EOCB polling method to detect the end of conversion clr AEOCE mova,03H mov ADCR1,a clr ADOFF mov a,0Fh mov ANCSR0,a mova,00h mov ANCSR1,a mova,00h mov ADCR0 : start_conversion: clr ADSTR set ADSTR clr ADSTR polling_EOC: sz EOCB jmp polling_EOC mov a,ADRL mov ADRL_buffer,a mov a,ADRH mov ADRH_buffer,a : : jmp start_conversion ; disable ADC interrupt ; select fSYS/8 as A/D clock ; setup ANCSR0 and ANCSR1 to configure pins AN0~AN3 ; enable and connect AN0 channel to A/D converter ; high pulse on start bit to initiate conversion ; reset A/D ; start A/D ; ; ; ; ; ; ; ; start next a/d conversion poll the ADCR0 register EOCB bit to detect end of A/D conversion continue polling read low byte conversion result value save result to user defined register read high byte conversion result value save result to user defined register Example: using the interrupt method to detect the end of conversion clr MF1E CLR AEOCE mova,03H Rev. 1.10 ; disable ADC interrupt 95 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU mov ADCR1,a ; Clr ADOFF mov a,0Fh ; mov ANCSR0,a mova,00h mov ANCSR1,a mova,00h mov ADCR0,a ; Start_conversion: clr ADSTR ; set ADSTR ; clr ADSTR ; clr AEOCF ; set AEOCE ; set MF1E ; set EMI ; : : ; ADC_ISR: mov acc_stack,a ; mov a,STATUS mov status_stack,a ; : : mov a,ADRL ; mov adrl_buffer,a ; mov a,ADRH ; mov adrh_buffer,a ; : : EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; mov a,acc_stack ; reti Rev. 1.10 select fSYS/8 as A/D clock setup ANCSR0 and ANCSR1 to configure pins AN0~AN3 enable and connect AN0 channel to A/D converter high pulse on START bit to initiate conversion reset A/D start A/D clear ADC interrupt request flag enable ADC interrupt enable Multi_interrupt 1 enable global interrupt ADC interrupt service routine save ACC to user defined memory save STATUS to user defined memory read save read save low byte conversion result value result to user defined register high byte conversion result value result to user defined register restore STATUS from user defined memory restore ACC from user defined memory 96 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Over-current Detection The device contains an fully integrated over-current detect circuit which is used for motor protection. ADLVD/ADHVD ADR Int_AHL_ Lim AD HL/LV Trigger ADC Int_AD_EOC EOC OPA : Av=1/5/10/20 Is Comparator 0 + _ OPA Int Trigger Int_Is C0BPE DAC 8-bit OPCM Over-current Detector Block Diagram Over-current Functional Description The over-current functional block includes an amplifier, 10-bit A/D Converter, 8-bit D/A Converter and comparator. If an over-current situation is detected then the motor external drive circuit can be switched off immediately to prevent damage to the motor. Two kinds of interrupts are generated which can be used for over-current detection. 1. A/D Converter interrupt - Int_AHL_Lim 2. Comparator 0 interrupt - Int_Is Over-current Register Description There are three registers to control the function and operation of the over current detection circuits, known as OPOMS, OPCM and OPACAL. These 8-bit registers define functions such as the OPA operation mode selection, OPA calibration and comparison. OPCM is an 8-bit DAC register used for OPA comparison. Rev. 1.10 97 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU OPOMS Register Bit Name 7 6 CMP0_EG1 CMP0_EG0 5 4 3 2 1 0 — — — OPAVS2 OPAVS1 OPAVS0 R/W R/W R/W — — — R/W R/W R/W POR 0 0 — — — 0 1 0 Bit 7~6CMP0_EG1, CMP0_EG0: Defines Comparator active edge 00: Disable Comparator 0 and DAC0 01: Rising edge 10: Falling edge 11: Dual edge Bit 5~3 Unimplemented, read as "0" Bit 2~0OPAVS2~OPAVS0: OPA Av mode select 000: Disable OPA 001: Av=5 010: Av=10 011: Av=20 111: AV=1 OPCM Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 8-bit OPA comparison register bit 7 ~ bit 0 OPACAL Register Bit 7 6 5 4 3 2 1 0 Name — ARS AOFM AOF4 AOF3 AOF2 AOF1 AOF0 R/W R R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 1 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6ARS: Comparator input offset calibration reference select 0: Comparator negative input 1: Comparator positive input Bit 5AOFM: Normal or Calibration Mode select 0: Opamp or Comparator Mode 1: Offset Calibration Mode Bit 4~0AOF4~AOF0: Comparator input offset voltage calibration control 00000: Minimum 10000: Center 11111: Maximum Rev. 1.10 98 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Linear Hall Sensor Detection The motor position is detected using Hall Sensors for which the device includes circuitry to process signals from these sensors. ADLVD/ADHVD ADR Ha Hb Hc ADC Int_AD_EOC AD HL/LV Trigger Int_AHL_ Lim EOC ACS[3:0] + Int Trigger _ 8bit DAC C1BPE Comparator 1 HACM Int_HbDet Hall Sensor Detector Block Diagram Hall Sensor Detection Function Description The signals from the external linear Hall Sensors are monitored using the internal 8-bit DAC, the internal 10-bit ADC and internal comparator 1. The motor position is monitored by two interrupts Int_HbDet or Int_AHL_Lim which are enabled/disabled by the LHMC and HACM registers. The six step rotational change of state of the motor position can be tracked by setting the DAC data and the LHMC register, to control the motor direction and speed, as shown in the figure. 4V HL/Hb 2.5V 1V SHa SHb SHc S1 S2 S3 S4 S5 S6 S1 S2 S3 linear Hall Sensor Output Rev. 1.10 99 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Linear Hall Sensor Control Register Description The LHMC is the linear Hall sensor Mode control register and the HACM is the 8-bit DAC register for Linear Hall Sensor comparison. LHMC Register Bit 7 6 Name — — R/W — — R/W R/W POR — — 0 0 — Bit 7~6 5 4 CMP1_EG1 CMP1_EG0 3 2 1 0 — — C1BPE C0BPE — — R/W R/W — 0 0 1 0 Unimplemented, read as "0" Bit 5~4CMP1_EG1, CMP1_EG0: Defines Comparator active edge 00: Disable Comparator 1 and DAC1 01: Rising edge 10: Falling edge 11: Dual edge Bit 3~2 Unimplemented, read as "0" Bit 1C1BPE: Comparator 1 Interrupt Bypass(test option) 0: Disable Comparator 1 interrupt 1: Enable Comparator 1 interrupt Bit 0C0BPE: Comparator 0 Interrupt Bypass(test option) 0: Disable Comparator 0 interrupt 1: Enable Comparator 0 interrupt HACM Register Bit 6 5 4 3 2 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.10 7 8-bit Linear Hall Sensor comparison register bit 7 ~ bit 0 100 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU BLDC Motor Control Circuit This sections describes how the device can be used to control Brushless DC Motors, otherwise known as BLDC Motors. Its high level of functional integration and flexibility offer a full range of driving features for motor driving. Functional Description The PWM counter circuit output PWMO is has an adjustable PWM Duty to control the output motor power thus controlling the motor speed. Changing the PWM frequency can be used to enhance the motor drive efficiency or to reduce noise and resonance generated during physical motor operation. The internal Mask circuit is used to determine which PWM modulation signals are enabled or disabled for the motor speed control. The PWM modulation signal can be output both the upper arms, GAT/GBT/GCT and the lower arms, GAB/GBB/GCB, of the external Gate Driver Transistor Pairs under software control. The Dead-Time insertion circuit is used to ensure the upper and lower Gate Driver Transistor Pairs are not enabled simultaneously to prevent the occurrence of a virtual power short circuit. The dead time is selected under software control. The Staggered circuit can force all the outputs to an off status if the software detects an error condition which could be due to external factors such as ESD problems or both upper and lower external Gate Driver Transistor pairs being simultaneously on. The Polarity circuit can select the output polarity of the BLDC motor output control port to support many different types of external MOS gate drive device circuit combinations. The Motor Protect circuit includes many detection circuits for functions such as a motor stall condition, over current protection, external edge triggered Pause pin, external level trigger Fault pin etc. The Hall Sensor Decoder circuit is a six-step system which can be used control the motor direction. Twelve registers, each using 6 bits, are used to control the direction of the motor. The motor forward, backward, brake and free functions are controlled by the HDCD/HDCR registers. The Ha/Hb/Hc or SHA/SHB/SHC can be selected as the Hall Sensor Decoder circuit inputs. VCCM INT0A GAT MAT GBT MBT GCT MCT INT0B INT0C v v IR2101 x3 Gate Driver HT45FM2C Fault Pause GAB MAB GBB MBB GCB MCB PB3/Is Rev. 1.10 101 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU BLDC Application Circuit PWMR DUTR PRDR MCF PWMC MCD DTS PLC PWMD_Int PWMP_Int PWM Complement 10-bit PWM counter CKT Fpwm HCHK_NUM HDCD AT0 AB0 BT0 Dead BB0 Time CT0 Insert CB0 PWMB Mask AT1 AT2 AB1 AB2 BT1 BT2 Stall BB1 BB2 Polarity Circuit CT1 CT2 CB1 CB2 GAT GAB GBT GBB GCT GCB HNF_MSEL HAT HAB HBT HBB BRKE HTH HCB HDLY_MSEL CTM_SEL[1:0] HA HB HC PWMO Hall Noise Filter SHA SHB SHC 1 Hall Delay CKT SA SB SC 0 HDMS CTM16-Int HDCR PROTECT Hall Sensor Dcoder 12x6 Register BRKE FRS HD_EN MPTC1 Pause Fault Stall Protection S/W Over Current Protection MPTC2 Motor Protect CKT BLDC Motor Control Block Diagram PWM Counter Control Circuit The device includes a 10-bit PWM generator. The PWM signal has both adjustable duty cycle and frequency that can be setup by programming 10-bit values into the corresponding PWM registers. PWMR DUTR PRDR PWMC PWMO 10-bit PWM counter CKT fPWM PWMD_Int PWMP_Int PWM Block Diagram Rev. 1.10 102 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU PWM Register Description Overall PWM operation is controlled by a series of registers. The DUTRL/DUTRH register pair is used for PWM duty control for adjustment of the motor output power. The PRDRL/PRDRH register pair are used together to form a 10-bit value to setup the PWM period for PWM Frequency adjustment. Being able to change the PWM frequency is useful for motor characteristic matching for problems such as noise reduction and resonance. The PWMRL/PWMRH registers are used to monitor the PWM counter dynamically. The PWMON bit in the PWMC register is the 10-bit PWM counter on/off bit. The PWM clock source for the PWM counter can be selected by PCKS1~PCKS0 bits in the PWMC register. It should be noted that the order of writing data to PWM register is MSB. PWMC Register Bit 7 6 5 4 3 Name — — PCKS1 PCKS0 PWMON R/W — — R/W R/W R/W POR — — 0 0 0 — Bit 7~6 2 1 0 — — GATSEL — — R/W — 0 Unimplemented, read as "0" Bit 5~4PCKS1, PCKS0: Clock source of the PWM counter select 000: fPWM, PWM frequency Min.=20kHz, fPWM base on 20MHz 001: fPWM/2, PWM frequency Min.=10kHz 010: fPWM/4, PWM frequency Min.=5kHz 011: fPWM/8, PWM frequency Min.=2.5kHz Bit 3PWMON: PWM Circuit On/Off control 0: Off 1: On This bit controls the overall on/off function of the PWM. Setting the bit high enables the counter to run, clearing the bit disables the PWM. Clearing this bit to zero will stop the counter from counting and turn off the PWM which will reduce its power consumption. Bit 2~1 Unimplemented, read as "0" Bit 0GATSEL: GATE Driver output select 0: GAT/GAB/GBT/GBB/GCT/GCB are used for Gate driver output pins 1: GAT/GAB/GBT/GBB/GCT/GCB are used as PC[5:0] DUTRL Register Bit 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.10 7 10-bit PWM Duty register low byte register bit 7 ~ bit 0 10-bit DUTR register bit 7 ~ bit 0 103 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU DUTRH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 10-bit PWM Duty register high byte register bit 1 ~ bit 0 10-bit DUTR register bit 9 ~ bit 8 PRDRL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 2 1 0 Bit 7~0 10-bit PWM Period register low byte register bit 7~bit 0 10-bit PRDR register bit 7 ~ bit 0 PRDRH Register Bit 7 6 5 4 3 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 PWM Period high byte register Bit 1~Bit 0 10-bit DUTR register Bit 9 ~ Bit 8 PWMRL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 10-bit PWM Counter register low byte register Bit 7~Bit 0 10-bit PWM Counter Bit 7 ~ Bit 0 PWMRH Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 10-bit PWM Counter register high byte register Bit 1 ~ Bit 0 PWM 10-bit Counter Bit 9 ~ Bit 8 104 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Mask Function The device includes a Motor Control Mask Function for increased control flexibility. �CF DTS �CD PW�O PW�B �ask AT0 AT1 AT� GAT �AT AB0 AB1 AB� GAB �AB BT0 BT1 BT� BB0 CT0 Hall Sensor Decoder 1�x6 CB0 HAT/ HAB/ HBT/ HBB/ HCT/ HCB BRKE PLC Dead Time Insert BB1 Staggered circuit BB� CT1 CT� CB1 CB� �BT GBT Polarit� IR�101x� Gate Driver GBB �BB GCT �CT GCB �CB PROTECT Mask Function Block Diagram �oto HV �AT �BT �CT �otor U Power �OS V �AB �BB W �CB Mask Switching Functional Description The internal MASK circuit has three operation modes, which are known as the Normal Mode, Brake Mode and Motor Protect Mode. • Normal Mode In the Normal Mode, the motor speed control method is determined by the PWMS/MPWE bits in the MCF register. When PWMS =0, the bottom port PWM output selects transistor pair bottom arm GAB/ GBB/ GCB. When PWMS =1, the top port PWM output selects transistor pair top arm, GAB/ GBB/ GCB. When MPWE =0, the PWM output is disabled and AT0/BT0/CT0/AB0/BB0/CB0 are all on. When MPWE =1, the PWM output is enabled and AT0/BT0/CT0/AB0/BB0/CB0 can output a variable PWM signal for speed control. When MPWMS=0, the PWM has a Complementary output When MPWMS=1, the PWM has a Non-complementary output Rev. 1.10 105 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Complementary control, MPWMS=0 PWMS=0 PWMS=0 PWMS=0 HAT HAB AT0 AB0 HAT HAB AT0 AB0 0 0 0 0 0 1 PWMB PWMO 0 0 0 0 0 1 0 1 0 1 1 0 1 0 PWMO PWMB 1 1 0 0 1 1 0 0 HBT HBB BT0 BB0 HBT HBB BT0 BB0 0 0 0 0 0 1 PWMB PWMO 0 0 0 0 0 1 0 1 1 0 1 1 1 0 0 1 0 PWMO PWMB 0 1 1 0 0 HCT HCB 0 0 CT0 CB0 HCT HCB CT0 CB0 0 0 0 0 0 0 0 1 1 PWMB PWMO 0 1 0 1 0 1 0 1 0 PWMO PWMB 1 1 0 0 1 1 0 0 HAT HAB AT0 AB0 0 0 0 0 0 1 0 1 PWMS=1 PWMS=1 PWMS=1 Non-complementary control, MPWMS=1 PWMS=0 PWMS=0 PWMS=0 HAT HAB AT0 AB0 0 0 0 0 0 1 0 PWMO 1 0 1 0 1 0 PWMO 0 1 1 0 0 1 1 0 0 HBT HBB BT0 BB0 HBT HBB BT0 BB0 0 0 0 0 0 0 0 0 0 1 0 PWMO 0 1 0 1 1 0 1 0 1 0 PWMO 0 1 1 0 0 1 1 0 0 HCT HCB CT0 CB0 HCT HCB CT0 CB0 0 0 0 0 0 0 0 0 PWMS=1 PWMS=1 0 1 0 PWMO 0 1 0 1 1 0 1 0 1 0 PWMO 0 1 1 0 0 1 1 0 0 PWMS=1 • Brake Mode The Brake Mode has the highest priority. When activated, the external Gate Driver Transistor Pair Top arm will be off and the Bottom arm will be on. The Brake Truth decode table is shown below. BRKE=1 AT0 BT0 CT0 AB0 BB0 CB0 1 0 0 0 0 1 1 1 D9 D8 • Motor Protect Mode When the Motor Protect Mode is activated, the external Gate Driver Transistor Pair can select the brake, where the top arm is off and the bottom arm is on, or select free running where the top and Rev. 1.10 106 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU bottom arm are both off. The protection decode table is shown below. PROTECT =1 GAT GBT GCT GAB GBB GCB FMOS=0 0 0 0 0 0 0 FMOS=1 0 0 0 1 1 1 For 6-Step communication, if the U winding and W winding are on then turn off the V winding. If GAT =1 and GAB =0, turn on the U winding If GBT =0 and GBB =0, turn off the V Winding. If GCT=PWMD and GCB=PWM, turn on the W winding and adjust the output power of the motor using the DUTR register to control the speed. �AT �AB GAT GAB GBT GBB GCT GCB HT45F��C IR�10 1x� �BT �BB �CT �CB Drive Signal Block Diagram Moto HV 1 MAT Current direction 0 MAB U v Moto HV W V Moto HV 0 MBT MCT v PWMD 0 Motor MBB MCB PWM Motor Winding Connection Rev. 1.10 107 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Register Description The device has two registers connected with the Mask Function control. These are the MCF register which is used for control and the MCD register which is used to read the status of the gate driver outputs. MCF Register Bit 7 6 5 4 3 2 1 0 Name — — — — MPWMS MPWE FMOS PWMS R/W — — — — R/W R/W R/W R/W POR — — — — 0 1 0 0 Bit 7~4 Bit 3 Unimplemented, read as "0" MPWMS: Mask PWM Mode select 0: Complementary 1: Non-complementary Bit 2MPWE: PWM output control 0: PWM output disable (AT0/BT0/CT0/AB0/BB0/CB0 can not output PWM) 1: PWM output enable (AT0/BT0/CT0/AB0/BB0/CB0 can output PWM to control speed) Bit 1FMOS: Fault Mask output select 0: AT0/BT0/CT0=0, AB0/BB0/CB0=0 1: AT0/BT0/CT0=0, AB0/BB0/CB0=1 Bit 0PWMS: Top port/Bottom port PWM select 0: Select Bottom port PWM output 1: Select Top port PWM output Rev. 1.10 108 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU MCD Register Bit 7 6 5 4 3 2 1 0 Name — — GAT GAB GBT GBB GCT GCB R/W — — R R R R R R POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5~0 GAT/GAB/GBT/GBB/GCT/GCB: Gate diver output monitor Other Functions Several other functions exist for additional motor control drive signal flexibility. These are the Dead Time Function, Staggered Function and Polarity Function. MCF MCD PWMO PWMB Hall Sensor Decoder 12x6 HAT/ HAB/ HBT/ HBB/ HCT/ HCB Mask DTS AT0 AB0 BT0 Dead BB0 Time CT0 Insert CB0 PLC AT1 AT2 AB1 AB2 BT1 Stagger BT2 ed BB1 BB2 Polarity CT1 Circuit CT2 CB1 CB2 GAT GAB GBT GBB GCT GCB IR2101x3 Gate Driver MAT MAB MBT MBB MCT MCB BRKE PROTECT Dead Time, Staggered and Polarity Function Block Diagram Dead Time Function During transistor pair switching, the Dead Time function is used to prevent both upper and lower transistor pairs from conducting at the same time thus preventing a virtual short circuit condition from occurring. The actual dead time value can be setup to be within a value from 0.3μs to 5μs which is selected by the application program. The Dead Time Insertion circuit requires six independent output circuits: • When the AT0/AB0/BT0/BB0/CT0/CB0 outputs experience a rising edge, then a Dead Time is inserted. • When the AT0/AB0/BT0/BB0/CT0/CB0 outputs experience a falling edge, then the outputs remain unchanged. The Dead-Time Insertion Circuit is only during motor control. The Dead Time function is enabled/ disabled by the DTE bit in the DTS register. Rev. 1.10 109 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Dead-Time Insertion 1.Rising Add Dead-Time Insertion 2.Falling Unchange AT0,AB0,BT0,BB0,CT0,CB0 . AT1,AB1,BT1,BB1,CT1,CB1 Dead-Time Insertion Dead-Time Insertion Dead-Time Insertion Dead Time Insertion Timing A single register, DTS, is dedicated for use by the Dead Time function. DTS Register Bit 7 6 5 Name DTCKS1 DTCKS0 DTE D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 4 3 2 1 0 DTCKS1, DTCKS0: Dead-Time clock source selection 00: fDT is fSYS, fSYS based on 20MHz 01: fDT is fSYS/2 10: fDT is fSYS/4 11: fDT is fSYS/8 DTE: Dead-Time Enable 0: Dead-Time=0 1: Dead-Time = (DTS[4:0]+1)/fDT Bit 4~0D4~D0: Dead-Time Register bit 4 ~ bit 0 Dead-Time counter. 5-bit Dead-Time value bits for Dead-Time Unit. Dead-Time = (DTS[4:0]+1)/fDT Bit 5 Staggered Function The Staggered Function is used to force all output drive transistors to an off condition when a software error occurs or due to external factors such as ESD. AT1 AB1 AT2 AB2 0 0 0 0 0 1 0 1 1 0 1 0 1 1 0 0 The default condition for the BLDC motor control circuit is designed for default N-type transistor pairs. This means a “1” value will switch the transistor on and a “0”value will switch it off. Rev. 1.10 110 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Polarity Function This function allows setup of the external gate drive transistor On/Off polarity status. A single register, PLC, is used for overall control. PLC Register Bit 7 6 5 4 3 2 1 0 Name — — PCBC PCTC PBBC PBTC PABC PATC R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5PCBC: C pair Bottom port Gate output inverse control Bit 4PCTC: C pair Top port Gate output inverse control Bit 3PBBC: B pair Bottom port Gate output inverse control Bit 2PBTC: B pair Top port Gate output inverse control Bit 1PABC: A pair Bottom port Gate output inverse control Bit 0PATC: A pair Top port Gate output inverse control Bit Value Status 0 Output not inverted 1 Output inverted PLC Register Values Note that the default output pin GAT/GAB/GBT/GBB/GCT/GCB status is high impedance. Hall Sensor Decoder This device contains a fully integrated Hall Sensor decoder function which interfaces to the Hall Sensors in the BLDC motor for directional and speed control. HCHK_NUM HNF_MSEL HDLY_MSEL PWMO CTM_SEL[1:0] HA PWMB Hall Noise Filter HB 1 HC SA Hall Delay CKT AT0 HAT SB AB0 HAB SC HBT HBB SHA 0 SHB HDCD Hall Sensor Dcoder 12x6 Regsietr CTM-Int x3 SHC BT0 Mask BB0 HCT CT0 HCB CB0 FRS HDCR BRKE HDMS HDCEN BRKE PROTECT Hall Sensor Decoder Block Diagram The Hall Sensor input signals are selected by setting the HDMS bit high. If the HDMS bit is zero then SHA/SHB/SHC will be used instead of the actual Hall Sensor signals. Rev. 1.10 111 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Hall Sensor Noise Filter This device includes a Hall Noise Filter function to filter out the effects of noise generated by the large switching currents of the motor driver. This generated noise may affect the Hall Sensor inputs (HA/HB/HC), which in turn may result in incorrect Hall Sensor output decoding. Several registers are used to control the noise filter. The HNF_EN bit in the HNF_MSEL register is used as the overall enable/disable bit for the noise filter. HNF_EN bit Status 0 Noise Filter Off – HA/HB/HC not used 1 Noise Filter On Hall Sensor Noise Filter Enable The sampling frequency of the Hall noise filter is setup using the HFR_SEL [3:0] bits. The HCK_NUM [4:0] bits are used to setup the Hall Sensor input compare numbers. HCK_NUM [4:0] × Sampling space = Anti-noise ability = Hall Delay-Time. It should be noted that longer Hall delay times will result in higher rotor speed feedback signal distortion. Hall Sensor Delay Function The Hall sensor function in the device includes a Hall delay function which can implement a signal phase forward or phase backward operation. The following steps, which should be executed before the Hall Decoder is enabled, show how this function is activated. • Step 1 Set the Hall Decode table to select either the phase forward or phase backward function. • Step 2 Select which CTM is used to generate the Delay Time and set the selected CTM to run in the Compare Match Mode by programming the CTM_SEL1~CTM_SEL0 bits. • Step 3 Use the HDLY_MSEL bit to select the Hall Delay circuit operating mode. The default value of HDLY_MSEL is zero which will disable the Hall Delay circuit. If the HDLY_MSEL bit is set high, then the Hall Delay circuit will be enabled. • Step 4 Enable the Hall Decoder using the HDCEN bit. The following points should be noted regarding the HDLY_MSEL bit. ♦♦ When this bit is low, BUF1[2:0] and BUF2[2:0] will be cleared to zero. ♦♦ When this bit is low, TM0/TM1/TM5 retain their original TM functions. ♦♦ When the bit is high, the CTM which is selected by the Delay function will be dedicated for use by the Hall Delay circuit. The original TM functions will still remain active except for the TnON bit which will be controlled automatically by the hardware. Rev. 1.10 112 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU With regard to the TM functions the following steps should be taken before the Delay function is enabled. 1. Keep TnON and TnPAU = 0 2. The TM should be setup in the Compare Match Mode 3. TnCCLR=1, therefore the TM is cleared with a comparator A match condition. 4. Setup the Delay time using TMnA and TnCKx. After the Delay function is enabled, HDLY_MSEL will change from low to high. The Delay time must not be more than one step time of the Hall input, which has six steps, Otherwise the output can not be anticipated, will drop out of step. HA HB HC Hall Noise Filter Hall DELAY Circuit HA0 HB0 HC0 SA SB SC SHA HDCD SHB SHC HA1 D BUF1[2:0] HB1 HC1 HDMS D BUF2[2:0] Hall Sensor Decoder 12x6 Register HAT HAB HBT HBB HCT HCB HA2 HB2 HC2 D HDCEN CTM_SEL[1:0] CTM-16 (TM5) HDLY_MSEL CTM-10 (TM0) CTM-10 (TM1) Delay Function Block Diagram HA0 HB0 HC0 SA SB SC Delay time Delay Function Timing Rev. 1.10 113 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Motor Control Drive Signals The direction of the BLDC motor is controlled using the HDCR, HDCD registers and a set of six HDCT registers, HDCT0~HDCT11. When using the Hall Sensor Decoder function, the direction can be determined using the FRS bit and the brake can be controlled using the BRKE bit. Both bits are in the HDCR register. Six bits in the HDCT0~HDCT5 registers are used for the Motor Forward table, and six bits in the HDCT6~HDCT11 registers are used for the Motor Backward table. The accompanying tables show the truth tables for each of the registers. 60 degree SA Forward (HDCEN=1, FRS=0, BRKE=0) SB 120 degree SC SA SB SC Bit5 Bit4 HAT HAB HBT HBB HCT HCB Bit3 Bit2 1 0 0 1 0 0 HDCT0[5:0] 1 1 0 1 1 0 HDCT1[5:0] 1 1 1 0 1 0 HDCT2[5:0] 0 1 1 0 1 1 HDCT3[5:0] 0 0 1 0 0 1 HDCT4[5:0] 0 0 1 0 1 HDCT5[5:0] 0 Bit1 Bit0 Hall Sensor Decoder Forward Truth Table 60 degree SA Backward (HDCEN=1, FRS=1, BRKE=0) SB 120 degree SC SA SB SC Bit5 Bit4 HAT HAB HBT HBB HCT HCB Bit3 Bit2 1 0 0 1 0 0 HDCT6[5:0] 1 1 0 1 1 0 HDCT7[5:0] 1 1 1 0 1 0 HDCT8[5:0] 0 1 1 0 1 1 HDCT9[5:0] 0 0 1 0 0 1 HDCT10[5:0] 0 0 0 1 0 1 HDCT11[5:0] Bit1 Bit0 Hall Sensor Decoder Backward Truth Table The truth tables for the brake function, hall decoder disable function and hall decoder error function are also shown below. Brake (BRKE=1, HDCEN=X, FRS=X) 60 degree 120 degree Bit5 Bit4 HAB HBT HBB HCT HCB SA SB SC SA SB SC HAT V V V V V V 0 Bit3 Bit2 Bit1 Bit0 1 0 1 0 1 Bit3 Bit2 Bit1 Bit0 Brake Truth Table Hall Decoder disable (HDCEN=0) Bit5 Bit4 SA 60 degree SB SC SA 120 degree SB SC HAT HAB HBT HBB HCT HCB V V V V V V 0 0 0 0 0 0 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 HAB HBT HBB HCT HCB Hall Decoder Disable Truth Table 60 degree Hall Decoder error (HDCEN=X) 120 degree SA SB SC SA SB SC HAT 1 0 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Hall Decoder Error Truth Table Rev. 1.10 114 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU The relationship between the data in the truth tables and how they relate to actual motor drive signals is shown in the accompanying timing diagram. The full 6 step cycle for both forward and backward motor rotation is provided. Hall sensor :120 degree Motor Forward SA �AT �AB Ha SB �-pole �otor N S Sc Hb S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 �BT �BB Hc S6 �CT HAT �CB HAB HT45FM2C IR2101x3 HBT Moto HV HBB MAT MBT MCT MAB MBB MCB Motor U V W HCT HCB Motor Drive Signal Timing Diagram - Forward Direction Hall sensor :120 degree Motor Backward �AT �AB Ha SA N SB �-pole �otor S �BT �BB Hc Hb Sc �CT S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 �CB S6 HT45FM2C HAT HAB IR2101x3 Moto HV HBT MAT MBT MCT MAB MBB MCB HBB Motor U V W HCT HCB Motor Drive Signal Timing Diagram - Backward Direction Rev. 1.10 115 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Hall Sensor Decoder Register Description The HDCR register is the Hall Sensor Decoder control register, HDCD is the Hall Sensor Decoder input data register, and HDCT0~HDCT11 are the Hall Sensor Decoder tables. The HCHK_NUM register is the Hall Noise Filter check number register and HNF_MSEL is the Hall Noise Filter Mode select register HDCR Register Bit Name 7 6 5 CTM_SEL1 CTM_SEL0 HDLY_MSEL 4 3 2 1 0 HALS HDMS BRKE FRS HDCEN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 1 0 0 0 0 Bit 7~6CTM_SEL1~CTM_SEL0: CTM Timer select of the Hall Delay Circuit 00:TM5(16-bit CTM) 01:TM0(10-bit CTM) 10:TM1(10-bit CTM) 11:Unused HDLY_MSEL: Hall Delay Circuit select 0: Select original path 1: Select Hall Delay Circuit Bit 4HALS: Hall Sensor Decoder Mode select 0: Hall Sensor 60 degree 1: Hall Sensor 120 degree Bit 5 Bit 3 HDMS: Hall Sensor Decoder Mode select 0: S/W Mode 1: Hall Sensor Mode Bit 2BRKE: motor brake control 0: GAT/GBT/GCT/GAB/GBB/GCB=V 1: GAT/GBT/GCT=0, GAB/GBB/GCB=1 Bit 1FRS: Motor Forward/Backward select 0: Forward 1: Backward Bit 0HDCEN: Hall Sensor Decoder enable 0: Disable 1: Enable HDCD Register Bit 7 6 5 4 3 2 1 0 Name — — — — — SHC SHB SHA R/W — — — — — R/W R/W R/W POR — — — — — 0 0 0 Bit 7~3 Unimplemented, read as "0" Bit 2SHC: S/W Hall C Bit 1SHB: S/W Hall B Bit 0SHA: S/W Hall A Rev. 1.10 116 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU HDCT11~0 Register Bit 7 6 5 4 3 2 1 0 Name — — HATD HABD HBTD HBBD HCTD HCBD R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5HATD: GAT output state control Bit 4HABD: GAB output state control Bit 3HBTD: GBT output state control Bit 2HBBD: GBB output state control Bit 1HCTD: GCT output state control Bit 0HCBD: GCB output state control Bit Value Status 0 Output is low 1 Output is high Output Status HCHK_NUM Register Bit 7 6 5 4 3 2 1 0 Name — — — HCK_N4 HCK_N3 HCK_N2 HCK_N1 HCK_N0 R/W — — — R/W R/W R/W R/W R/W POR — — — 0 0 0 0 0 2 1 0 Bit 7~5 Unimplemented, read as "0" Bit 4~0HCK_N4~HCK_N0: Hall Noise Filter check number HNF_MSEL Register Bit 7 6 5 4 Name — — — — 3 HNF_EN HFR_SEL2 HFR_SEL1 HFR_SEL0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3HNF_EN: Hall noise filter enable 0: Disable(bypass) 1: Enable Bit 2~0HFR_SEL2~HFR_SEL0: Hall noise filter clock source select 000:fSYS/2 001:fSYS/4 010:fSYS/8 011:fSYS/16 100:fSYS/32 101:fSYS/64 110:fSYS/128 111:Unused Rev. 1.10 117 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Motor Protection Function Motors normally require large currents for their operation and as such need to be protected from the problems of excessive drive currents, motor stalling etc to reduce motor damage or for safety reasons. This device includes a range of protection and safety features. Int_Pau Pause Fault Int_FLT AT0 AB0 Int_AHL_Lim OPA & Compare CKT Is Motor Protect CKT Int_Is PROTECT Mask BT0 BB0 CT0 CB0 CapTM_Cmp INT0A INT0B INT0C CAPTM CapTM_Over MPTC2 MPTC1 Protection Function Block Diagram FLTHE Fault PSWPS=0 PSWE PSWD PSWPS=1 Int_Pause PROTECT PAUTS D PAUHE Pause Edge CKT Q reset AHLHE Int_AHL_Lim ISPS=0 Int_Is ISHE CapCHE CAPCPS=0 CAPOPS=1 CapTM_Cmp ISPS=1 CACPS=1 OPA & Compare CKT CAPTM CapTM_Over CAPOPS=0 CapOHE Protection Function Control Rev. 1.10 118 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Motor Protection Function Description This device provides five kinds of protection features, allowing action to be taken to protect the motor from damage or to provide additional safety. The protection features are: 1. An external edge trigger on the Pause pin - edge trigger 2. An external level trigger on Fault pin - level trigger 3. Stall detection function 4. Over current protection 5. Turn off the motor using software When the motor protection circuit is on, the external Gate Drive transistor pair can be put into two different protection modes. The first is the Brake Mode which is where the top arm is off and the bottom arm is on, and the second is the Free Running Mode where both top and bottom arms are off. The FMOS bit in the MCF register determines which type is used. The motor protection circuit operates in two modes, which is selected by the MPTC2 register. One mode is the Fault Mode and the other is Pause Mode. In the Fault Mode, activating the protect function is determined by the trigger source starting status. Ending the protect function is determined by the trigger source disarming status. In the Pause Mode, turning on the protect function is determined by the trigger source. Ending the protection function is determined by software. Fault Pin Function The Fault Pin is used to detect whether an external circuit has detected a motor stall or over current condition. The pin is a level trigger type and is active low and PROTECT is "1". The Fault pin and PROTECT are controlled by FLTHE bit in the MPTC1 register. Pause Pin Function The Pause pin is used to detect whether an external circuit has detected a motor stall or over current condition. The Pause pin is edge triggered and PROTECT is "1". It will cause the external Gate Driver to be shut down. The Pause pin Mode condition is determined by the PSWD/PSWE/PSWPS bits and PROTECT is "0", then the external Gate Driver circuit is controlled by the Hall Sensor Decoder circuit. The Pause pin function is controlled by the PAUHE and PAUTS bits in the MPTC1 and MPTC2 registers. Current Protection Function As the device contains a 10-bit A/D Converter, an 8-bit D/A Converter and an amplifier, they can be used together to measure the motor current and to detect for excessive current values. If an over current situation should occur, then the external drive circuit can be shut down immediately to prevent motor damage. The Int_AHL_Li MOS has a current limit protection mechanism. Disable the H/W Mode when AHLHE is "0" and enable the H/W Mode when AHLHE is "1". The limited current circuit is a hardware circuit, for which the A/D converter channel must select the operation amplifier to be active. If there is an over current during system startup, then this current limit circuit should be disabled. The Int_Is MOS has an over current protection mechanism. Disable the H/W Model when ISHE is "0" and enable the H/W Mode when ISHE is "1". Select the Fault Mode when ISPS is "0" and select the Pause Mode when ISPS is "1", . Rev. 1.10 119 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU HAT~HCB x6 S1 HAT~HCB x6 S2 S3 S4 S5 S6 S1 S2 15KHz ~64 us S3 S4 S5 15KHz ~64 us PWM counter PWM counter GAT~GCB (x6) (PWMO) GAT~GCB (x6) (PWMO) Time Int_ADC S6 Time Int_ADC Int_CMP MOS limited current protect：(AHLHE=1;AHLPS=1) Start the next cycle of the PWM output automaticly by hardware Int_CMP MOS over current protection：(ISHE=1;ISPS=0) Restar the PWM output must by software Over Current Motor Stall Detection Function For 3-phase BLDC applications with Hall Sensors, the 16-bit CAPTM can be used to monitor the INT0A, INT0B and INT0C inputs for rotor speed detection. The over current signal is selected by the CAPTMAH and CAPTMAL registers which can monitor the Hall sensor input pins INT0A, INT0B and INT0C to detect the rotor speed. When an over current condition occurs, a CapTM_ Cmp or CapTM_Over interrupt will be generated. Refer to the CAPTM chapter for details. In the CapTM_Cmp stall detect mechanism, disable the H/W Mode when CapCHE is "0", and enable the H/W Mode when CapCHE is "1". Select the Fault Mode when CAPCPS is "0" and select the Pause Mode when CAPCPS is "1". In the CapTM_Over stall detect mechanism, disable the H/W Mode when CapOHE is "0" and enable the H/W Mode when CapOHE is "1". Select the Fault Mode when CAPOPS is "0" and select the Pause Mode when CAPOPS is "1". Motor Protection Circuit Register Description There are two registers, MPTC1 and MPTC2, which are used for the motor protection control function. Rev. 1.10 120 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU MPTC1 Register Bit 7 6 5 4 3 2 1 0 Name PSWD PSWE CapOHE CapCHE ISHE AHLHE PAUHE FLTHE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7PSWD: Protect S/W Mode data 0: PSWD=0 1: PSWD=1 Bit 6PSWE: Protect S/W Mode enable 0: Disable 1: Enable Bit 5CapOHE: CapTM_Over H/W Mode enable 0: Disable 1: Enable Bit 4CapCHE: CapTM_Cmp H/W Mode enable 0: Disable 1: Enable Bit 3ISHE: Int_Is H/W Mode enable 0: Disable 1: Enable Bit 2AHLHE: Int_AHL_Lim H/W Mode enable 0: Disable 1: Enable Bit 1PAUHE: Pause Pin H/W Mode enable 0: Disable 1: Enable Bit 0FLTHE: Fault Pin H/W Mode enable 0: Disable 1: Enable Rev. 1.10 121 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU MPTC2 Register Bit 7 6 5 4 3 2 Name — PAUTS1 PAUTS0 PSWPS AHLPS ISPS R/W R R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 1 0 CAPCPS CAPOPS Unimplemented, read as "0" Bit 6~5PAUTS1~PAUTS0: Pause trigger select 00: Disable Pause Int. 01: Rising edge 10: Falling edge 11: Dual edge Bit 4PSWPS: Pause/Fault Mode select 0: Select Fault Mode 1: Select Pause Mode Bit 3AHLPS: Int_AHL_Lim Pause/Fault Mode select 0: Select Fault Mode 1: Select Pause Mode Bit 2ISPS: Int_Is Pause/Fault Mode select 0: Select Fault Mode 1: Select Pause Mode Bit 1CAPCPS: CapTM_Cmp Pause/Fault Mode select 0: Select Fault Mode 1: Select Pause Mode Bit 0CAPOPS: CapTM_Over Pause/Fault Mode select 0: Select Fault Mode 1: Select Pause Mode Rev. 1.10 122 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Motor Position Detection Methods There are three methods of BLDC motor positioning control available. These are Digital Hall Sensor Method, Linear Hall Sensor Method and Sensorless Method. Digital Hall Sensor Method In this method there are three external digital outputs from the hall sensors to detect the rotor position. INT0A, INT0B and INT0C can detect rising, falling and dual edge trigger interrupts. The numerical changes from the Hall sensors is detected is controlled by the application program and can be used to monitor the rotor position . Here HA/HB/HC and the 12 Hall decoder registers are used to control the direction of motor. The PWM functional block is used to control the motor speed. Ha Hb Hc Hall Detect INT0[A/B/C] Digital Hall Sensor Method Linear Hall Sensor Method: In this method a linear Hall sensor to detect the rotor position. The numerical changes of the external linear Hall sensor is monitored by the 8-bit DAC, 10-bit ADC and comparator 1. The LHMC register, HACM, and the Int_HbDet or Int_AHL_Lim, are used to monitor the motor position. Here SHA/SHB/SHC and the 12 Hall decoding registers are used to control the motor direction. The PWM functional block is used to control the motor speed. Int_HbDet Hb Linear Hall Detect Int_AHL_ Lim ADR Linear Hall Sensor Method Sensorless Method In this method the 3 channels, AN0/AN1/AN2, of the 10-bit A/D converter is used to detect the changes in the back EMF of the three-phase motor. The changes can be detected by the Int_AD_ EOC, Int_AHL_Lim and ADRL/ADRH registers. There is a set of 16-bit CTMs to monitor the position and speed of the motor. Use SHA/SHB/SHC and the 12 Hall decoder registers to control the motor direction. The PWM functional block is used to control the motor speed. U V W E�F Detect Int_AD_EOC Int_AHL_ Lim ADR Sensorless Method Rev. 1.10 123 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU DC Motor Control The device can control motors using 1 or 2 pins. Taking the example of DC Fan Head motor control. a 2-pin DC Motor Interface can control the fan head motor speed and direction, while the 1-pin DC Motor Interface can only control the motor speed. The FH_MS bit in the DCMCR1 register is used to select either a 1-pin or 2-pin DC Motor Interface. 2-pin DC Motor Control In this case the 2-pin DC Motor interface can control both the motor speed and direction. An external circuit using a limit switch or a VR circuit can be used to control the motor direction. The 10-bit CTM output PWMO is used to adjust the PWM duty cycle to control DC motor speed. The DC_MCTL circuit controls the DC motor direction. VDDM=5V VDDM=5V VDDM=5V 1 10-bit CTM TMR0 PWMO FH0_SAT 0 1 P P FH0_SBT 1 0 1 FH0_FR N FH0_LI N FH0_STOP FH_MS FH0_PB FH0_RI FH0_PA DC_MCTL L_LSW VDDM=5V VDDM=5V 10-bit CTM TMR1 PWMO R_LSW VDDM=5V FH1_SAT 0 1 P P FH1_SBT 1 0 FH1_FR FH1_LI N N FH1_STOP FH_MS FH1_RI FH1_PB FH1_PA DC_MCTL L_LSW R_LSW HT45FM2C 2-Pin DC Motor Interface Application Circuit The DC control order for the Motor direction is that the motor should be free (FH [0/1] _STOP) before forward (FH [0/1] _FR) and then change direction. It is used to adjust the output polarity according to the external gate drive configuration (P type or N type). The DC Fan Head interface reset default value is FH0_SAT = hi-z/FH0_SBT = hi-z and FH1_SAT = hi-z/FH1_SBT = hi-z. Rev. 1.10 FH[0/1]_STOP FH[0/1]_FR 0 1 Forward 0 0 Backward 1 V Free 124 DC_Motor May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU 1-pin DC Motor Control The 1-pin DC Motor interface is used only to control the motor speed. The 10-bit CTM output PWMO is used to adjust the PWM duty cycle to control the DC motor speed. It is used to adjust the output polarity according to the external gate drive configuration (P type or N type). The DC Fan Head interface reset default value is FH1_SAT= hi-z /FH1_SBT=hi-z. 1 10-bit CTM TMR0 VDDM=5V VDDM=5V PWMO FH0_SAT 0 1 P FH0_SBT 1 0 1 FH0_FR FH0_LI N FH0_STOP FH_MS FH0_PB FH0_PA FH0_RI DC_MCTL VDDM=5V 10-bit CTM TMR1 PWMO FH1_SAT 0 1 VDDM=5V P FH1_SBT 1 0 FH1_FR FH1_LI FH1_STOP FH_MS FH1_PB FH1_PA FH1_RI DC_MCTL HT45FM2C 1-Pin DC Motor Interface Application Circuit Rev. 1.10 125 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Register Description Two registers, DCMCR0 and DCMCR1 are used for overall control. DCMCR0 Register Bit 7 6 5 Name FH1_PB FH1_PA FH0_PB 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 1 0 1 0 FH0_PA FH1_STOP FH1_FR FH0_STOP FH0_FR Bit 7FH1_PB: polarity output control 0: Non-inverse 1: Inverse Bit 6FH1_PA: polarity output control 0: Non-inverse 1: Inverse Bit 5FH0_PB: polarity output control 0: Non-inverse 1: Inverse Bit 4FH0_PA: polarity output control 0: Non-inverse 1: Inverse Bit 3FH1_STOP: FAN Head 1 stop enable 0: Motor normal operation 1: Motor free run Bit 2FH1_FR: FAN Head 1 direction select 0: Backward 1: Forward Bit 1FH0_STOP: FAN Head 0 stop enable 0: Motor normal operation 1: Motor free run Bit 0FH0_FR: FAN Head 0 direction select 0: Backward 1: Forward DCMCR1 Register Bit 7 6 5 4 3 2 1 0 Name — — — FH1_BE FH1_AE FH0_BE FH0_AE FH_MS R/W — — — R/W R/W R/W R/W R/W POR — — — 0 0 0 0 0 Bit 7~5 Unimplemented, read as "0" Bit 4~1FH[1/0]_[A/B]E: Fan Head Interface output enable 0: Disable Fan Head Interface output 1: Enable Fan Head Interface output Bit 0FH_MS: FAN Head Mode select 0: 1-pin Mode for 1 FAN head 1: 2-pin Mode for 1 FAN head Rev. 1.10 126 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module or an A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. This device contains six external interrupt and 21 internal interrupt functions. The external interrupts are generated by the action of the external INT0A, INT0B, INT0C, INT1, Fault and Pause pins, while the internal interrupts are generated by various internal functions such as the 10-bit or 16-bit CTMs, Comparators, Motor Protect, Linear Hall Sensor detect, PWM Module, 16-bit CAPTM Module, 8-bit RMT Module, Time Base, LVD, EEPROM and the A/D converter. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the accompanying table. The number of registers fall into two categories. The first is the INTC0~INTC3 registers which setup the primary interrupts, the second is the MFI0~MFI8 registers which setup the Multi-function interrupts. Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an “E” for enable/disable bit or “F” for request flag. Function Global External interrupt 0 (Hall Sensor) External interrupt 1 Comparator Multifunction interrupt A/D Converter Enable Bit Request Flag Notes EMI — — HALLE HALLF — HALAE HALAF — HALBE HALBF — HALCE HALCF — INT1E INT1F — CnE CnF n=0,1 MFnE MFnF n=1~8 AEOCE AEOCF — ALIME ALIMF — External Fault interrupt FLTE FLTF — External Pause interrupt PAUE PAUF — PWMDE PWMDF — PWMPE PWMPF — TBE TBF — CAPOE CAPOF — CAPCE CAPCF — TMnAE TMnAF n=0,1,2,3,5 TMnPE TMnPF n=0,1,2,3,5 RMT0E RMT0F — RMT1E RMT1F — RMTVE RMTVF — LVD LVDE LVDF — EEPROM EPWE EPWF — PWM Time Base CAPTM TM RMT Interrupt Register Bit Naming Conventions Rev. 1.10 127 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Interrupt Register Contents Name INTC0 Bit 7 6 5 4 3 2 1 0 — C0F INT1F HALLF C0E INT1E HALLE EMI INTC1 PAUF FLTF MF1F C1F PAUE FLTE MF1E C1E INTC2 MF4F MF3F TBF MF2F MF4E MF3E TBE MF2E INTC3 MF8F MF7F MF6F MF5F MF8E MF7E MF6E MF5E MFI0 — HALCF HALBF HALAF — HALCE HALBE HALAE MFI1 — — ALIMF AEOCF — — ALIME AEOCE MFI2 — — PWMPF PWMDF — — PWMPE PWMDE MFI3 — — CAPCF CAPOF — — CAPCE CAPOE MFI4 TM1AF TM1PF TM0AF TM0PF TM1AE TM1PE TM0AE TM0PE MFI5 TM3AF TM3PF TM2AF TM2PF TM3AE TM3PE TM2AE TM2PE MFI6 — RMTVF RMT1F RMT0F — RMTVE RMT1E RMT0E MFI7 — — TM5AF TM5PF — — TM5AE TM5PE MFI8 — — EPWF LVDF — — EPWE LVDE INTC0 Register Bit 7 6 5 4 3 2 1 0 Name — C0F INT1F HALLF C0E INT1E HALLE EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6CP0F: Comparator 0 interrupt request flag 0: No request 1: Interrupt request Bit 5INT1F: External 1 interrupt request flag 0: No request 1: Interrupt request Bit 4HALLF: Hall sensor global interrupt request flag 0: No request 1: Interrupt request Bit 3C0E: Comparator 0 interrupt control 0: Disable 1: Enable Bit 2INT1E: External 1 interrupt control 0: Disable 1: Enable Bit 1HALLE: Hall sensor global interrupt control 0: Disable 1: Enable Bit 0EMI: Global interrupt control 0: Disable 1: Enable Rev. 1.10 128 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU INTC1 Register Bit 7 6 5 Name PAUF FLTF R/W R/W R/W POR 0 0 Bit 7 4 3 2 1 0 MF1F C1F PAUE FLTE MF1E C1E R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 PAUF: Pause Interrupt Request Flag 0: No request 1: Interrupt request Bit 6FLTF: Fault Interrupt Request Flag 0: No request 1: Interrupt request Bit 5MF1F: Multi-function Interrupt 1 Request Flag 0: No request 1: Interrupt request Bit 4C1F: Comparator 1 Interrupt Request Flag 0: No request 1: Interrupt request Bit 3PAUE: Pause Interrupt Interrupt Control 0: Disable 1: Enable Bit 2FLTE: Fault Interrupt Control 0: Disable 1: Enable Bit 1MF1E: Multi-function Interrupt 1 Control 0: Disable 1: Enable Bit 0C1E: Comparator 1 Interrupt Control 0: Disable 1: Enable Rev. 1.10 129 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Rev. 1.10 130 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU INTC2 Register Bit 7 6 5 4 3 2 Name MF4F R/W R/W POR 0 1 0 MF3F TBF MF2F MF4E R/W R/W R/W R/W MF3E TBE MF2E R/W R/W 0 0 0 0 R/W 0 0 0 Bit 7MF4F: Multi-function interrupt 4 request flag 0: No request 1: Interrupt request Bit 6MF3F: Multi-function interrupt 3 request flag 0: No request 1: Interrupt request Bit 5TBF: Time Base interrupt request flag 0: No request 1: Interrupt request Bit 4MF2F: Multi-function interrupt 2 Request flag 0: No request 1: Interrupt request Bit 3MF4E: Multi-function interrupt 4 control 0: Disable 1: Enable Bit 2MF3E: Multi-function interrupt 3 control 0: Disable 1: Enable Bit 1TBE: Time Base interrupt control 0: Disable 1: Enable Bit 0MF2E: Multi-function interrupt 2 control 0: Disable 1: Enable Rev. 1.10 131 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU INTC3 Register Bit 7 6 5 4 3 2 1 0 Name MF8F MF7F MF6F MF5F MF8E MF7E MF6E MF5E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7MF8F: Multi-function interrupt 8 request flag 0: No request 1: Interrupt request Bit 6MF7F: Multi-function interrupt 7 request flag 0: No request 1: Interrupt request Bit 5MF6F: Multi-function interrupt 6 request flag 0: No request 1: Interrupt request Bit 4MF5F: Multi-function interrupt 5 request flag 0: No request 1: Interrupt request Bit 3MF8E: Multi-function interrupt 8 control 0: Disable 1: Enable Bit 2MF7E: Multi-function interrupt 7 control 0: Disable 1: Enable Bit 1MF6E: Multi-function interrupt 6 control 0: Disable 1: Enable Bit 0MF5E: Multi-function interrupt 5 control 0: Disable 1: Enable Rev. 1.10 132 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU MFI0 Register Bit 7 6 5 4 3 2 1 0 Name — HALCF HALBF HALAF — HALCE HALBE HALAE R/W — R/W R/W R/W — R/W R/W R/W POR — 0 0 0 — 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6HALCF: Hall Sensor C interrupt request flag 0: No request 1: Interrupt request Bit 5HALBF: Hall Sensor B interrupt request flag 0: No request 1: Interrupt request Bit 4HALAF: Hall Sensor A interrupt request flag 0: No request 1: Interrupt request Bit 3 Unimplemented, read as "0" Bit 2HALCE: Hall Sensor C interrupt control 0: Disable 1: Enable Bit 1HALBE: Hall Sensor B interrupt control 0: Disable 1: Enable Bit 0HALAE: Hall Sensor A interrupt control 0: Disable 1: Enable MFI1 Register Bit 7 6 5 4 3 2 1 0 Name — — ALIMF AEOCF — — ALIME AEOCE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5ALIMF: A/D Converter EOC compare interrupt request flag 0: No request 1: Interrupt request Bit 4AEOCF: A/D Converter interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1ALIME: A/D Converter EOC compare interrupt control 0: Disable 1: Enable Bit 0AEOCE: A/D Converter interrupt control 0: Disable 1: Enable Rev. 1.10 133 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU MFI2 Register Bit 7 6 5 4 Name — — PWMPF PWMDF R/W — — R/W R/W POR — — 0 0 — Bit 7~6 3 2 1 0 — — PWMPE PWMDE — — R/W R/W — 0 0 2 1 0 Unimplemented, read as "0" Bit 5PWMPF: PWM Period match interrupt request flag 0: No request 1: Interrupt request Bit 4PWMDF: PWM Duty match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1PWMPE: PWM Period match interrupt control 0: Disable 1: Enable Bit 0PWMDE: PWM Duty match interrupt control 0: Disable 1: Enable MFI3 Register Bit 7 6 5 4 3 Name — — CAPCF CAPOF — — CAPCE CAPOE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5CAPCF: CAPTM compare match interrupt request flag 0: No request 1: Interrupt request Bit 4CAPOF: CAPTM capture overflow interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1CAPCE: CAPTM compare match interrupt control 0: Disable 1: Enable Bit 0CAPOE: CAPTM capture overflow interrupt control 0: Disable 1: Enable Rev. 1.10 134 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU MFI4 Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name TM1AF TM1PF TM0AF TM0PF TM1AE TM1PE TM0AE TM0PE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 TM1AF: TM1 Comparator A match interrupt request flag Bit 6 TM1PF: TM1 Comparator P match interrupt request flag Bit 5 TM0AF: TM0 Comparator A match interrupt request flag Bit 4 TM0PF: TM0 Comparator P match interrupt request flag Bit 3 TM1AE: TM1 Comparator A match interrupt control Bit 2 TM1PE: TM1 Comparator P match interrupt control Bit 1 TM0AE: TM0 Comparator A match interrupt control Bit 0 TM0PE: TM0 Comparator P match interrupt control 0: No request 1: Interrupt request 0: No request 1: Interrupt request 0: No request 1: Interrupt request 0: No request 1: Interrupt request 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable 135 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU MFI5 Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name TM3AF TM3PF TM2AF TM2PF TM3AE TM3PE TM2AE TM2PE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 TM3AF: TM3 Comparator A match interrupt request flag Bit 6 TM3PF: TM3 Comparator P match interrupt request flag Bit 5 TM2AF: TM2 Comparator A match interrupt request flag Bit 4 TM2PF: TM2 Comparator P match interrupt request flag Bit 3 TM3AE: TM3 Comparator A match interrupt control Bit 2 TM3PE: TM3 Comparator P match interrupt control Bit 1 TM2AE: TM2 Comparator A match interrupt control Bit 0 TM2PE: TM2 Comparator P match interrupt control 0: No request 1: Interrupt request 0: No request 1: Interrupt request 0: No request 1: Interrupt request 0: No request 1: Interrupt request 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable 136 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU MFI6 Register Bit 7 6 5 4 3 2 1 0 Name — RMTVF RMT1F R/W — R/W R/W RMT0F — RMTVE RMT1E RMT0E R/W — R/W R/W POR — 0 0 R/W 0 — 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6 RMTVF: RMT overflow interrupt request flag Bit 5 RMT1F: RMT falling edge interrupt request flag Bit 4 RMT0F: RMT rasing edge interrupt request flag Bit 3 Unimplemented, read as "0" Bit 2 RMTVE: RMT overflow interrupt control Bit 1 RMT1E: RMT falling edge interrupt control Bit 0 RMT0E: RMT rasing edge interrupt control 0: No request 1: Interrupt request 0: No request 1: Interrupt request 0: No request 1: Interrupt request 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable MFI7 Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name — — TM5AF TM5PF — — TM5AE TM5PE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 TM5AF: TM5 Comparator A match interrupt request flag Bit 4 TM5PF: TM5 Comparator P match interrupt request flag 0: No request 1: Interrupt request 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1 TM5AE: TM5 Comparator A match interrupt control Bit 0 TM5PE: TM5 Comparator P match interrupt control 0: Disable 1: Enable 0: Disable 1: Enable 137 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU MFI8 Register Bit 7 6 5 4 3 2 1 0 Name — — EPWF LVDF — — EPWE LVDE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5EPWF: Data EEPROM interrupt request flag 0: No request 1: Interrupt request Bit 4LVDF: LVD interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1EPWE: Data EEPROM interrupt control 0: Disable 1: Enable Bit 0LVDE: LVD interrupt control 0: Disable 1: Enable Interrupt Operation When the conditions for an interrupt event occur, such as a TM Compare P or Compare A match or A/D conversion completion etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a “JMP” which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a “RETI”, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from Rev. 1.10 138 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode. xxF Legend Request Flag, no auto reset in ISR xxF Request Flag, auto reset in ISR XXE Enable Bits Interrupt Name Multi-Function 0 INT0A HALAF HALAE INT0B HALBF HALBE INT0C HALCF HALCE ADC EOC AEOCF AHL_Lim ALIMF EMI auto disabled in ISR AEOCE INT1 Request Flags HALLF INT1F Enable Bits HALLE Master Enable EMI Vector 04H INT1E EMI 08H CMP0 C0F C0E EMI 0CH CMP1 C1F C1E EMI 10H MF1F MF1E EMI 14H FLTF FLTE EMI 18H PAUF PAUE EMI 1CH MF2F MF2E EMI 20H TBE EMI 24H Multi-Function 1 ALIME Fault Pause PWMD PWMDF PWMDE PWMP PWMPF PWMPE CAPOF CAPOE CapTM_Cmp CAPCF CAPCE Multi-Function 3 MF3F MF3E EMI 28H TM0 P TM0PF TM0PE Multi-Function 4 MF4F MF4E EMI 2CH TM0 A TM0AF TM0AE TM1 P TM1PF TM1PE TM1 A TM1AF TM1AE TM2 P TM2PF TM2PE Multi-Function 5 MF5F MF5E EMI 30H TM2 A TM2AF TM2AE TM3 P TM3PF TM3PE TM3 A TM3AF TM3AE RMT 0 Multi-Function 6 MF6F MF6E EMI 34H Multi-Function 7 MF7F MF7E EMI 38H Multi-Function 8 MF8F MF8E EMI 3CH CapTM_Over Priority High RMT0F RMT0E RMT 1 RMT1F RMT1E RMT V RMTVF RMTVE TM5 P TM5PF TM5PE TM5 A TM5AF TM5AE LVD LVDF LVDE EEPROM EPWF EPWE Multi-Function 2 Time Base TBF Low Interrupts contained within Multi- Function Interrupts Interrupt Structure Rev. 1.10 139 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU External Interrupt 0 The external interrupt 0, also known as the Hall Sensor interrupt, is contained within the Multifunction Interrupt. It is controlled by signal transitions on the pins, Hall Sensor input pins, INT0A, INT0B and INT0C. An external interrupt request will take place when the external interrupt request flag, HALAF HALBF and HALCF is set, which will occur when a transition, appears on the external interrupt pins. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the Multi-function interrupt controlled bit, HALLE must first be set. When the Multi-function interrupt controlled bit HALLE is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts and the related Multi-Function request flag HALLF, will be automatically reset, but the Multi-function interrupt request flags, HALAF,HALBF,HALCF, must be manually cleared by the application program.. External Interrupt 1 The external interrupt 1 is controlled by signal transitions on the pin INT1. An external interrupt request will take place when the external interrupt request flag, INT1F, is set, which will occurs when a transition appears on the external interrupt pin. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INT1E, must first be set. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flag, INT1F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. Comparator Interrupt The comparator interrupts are controlled by the two internal comparators. A comparator interrupt request will take place when the comparator interrupt request flag, C0F or C1F, is set, a situation that will occur when the comparator output changes state. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and comparator interrupt enable bit, C0E or C1E, must first be set. When the interrupt is enabled, the stack is not full and the comparator inputs generate a comparator output transition, a subroutine call to the comparator interrupt vector, will take place. When the interrupt is serviced, the comparator interrupt request flags, C0F or C1F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Multi-function Interrupt Within this device are nine Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the Hall Sensor interrupts, A/D interrupts, PWM Module interrupts, CAPTM Interrupts, TM Interrupts, RMT Interrupts, EEPROM and LVD Interrupt. A Multi-function interrupt request will take place when any of the Multi-function interrupt request flags, HALLF and MF1F~MF8F are set. The Multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a Rev. 1.10 140 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU subroutine call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related Multi-Function request flag, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the Multi-function Interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts, namely the Hall Sensor interrupts, A/D interrupts, PWM Module interrupts, CAPTM Interrupts, TM Interrupts, RMT Interrupts, EEPROM and LVD Interrupt will not be automatically reset and must be manually reset by the application program. A/D Converter Interrupt The A/D Converter has two interrupts. All of them are contained in Multi-function interrupt. The one is controlled by the termination of an A/D conversion process. An A/D Converter interrupt request will take place when the A/D Converter Interrupt request flag, ALIMF, is set, which occurs when the A/D conversion process finishes. The other is controlled by the ADCHVE/ADCLVE bit in the ADCR1 register and the value in the ADLVDH/ADLVDL and ADHVDH/ADHVDL boundary control registers. An A/D Converter Interrupt request will take place after EOC comparing. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit, AEOCE or ALIME, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended or after EOC comparing a subroutine call to the A/D Converter Interrupt vector, will take place. When the interrupt is serviced, the A/D Converter Interrupt flag, AEOCF or ALIMF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Fault Interrupt Fault pin is Motor Control disable pin, it supports low active level trigger interrupt. When this happens, its interrupt request flag, FLTF will be set. To allow the program to branch to its interrupt vector address, the global interrupt enable bit, EMI and enable bit, FLTE, must first be set. When the interrupt is enabled, the stack is not full and a low active level appears on the pin, a subroutine call to this vector location will take place. When the interrupt is serviced, the interrupt request flag, FLTF, will be automatically reset and the EMI bit will be cleared to disable other interrupts. Pause Interrupt Pause pin is Motor Control enable pin, it support rising/falling/both trigger interrupt. When this happens, its interrupt request flag, PAUF will be set. To allow the program to branch to its interrupt vector address, the global interrupt enable bit, EMI and the corresponding enable bit, PAUE, must first be set. When the interrupt is enabled, the stack is not full and a rising/falling/both edge trigger appears on the pin, a subroutine call to this vector location will take place. When the interrupt is serviced, the interrupt request flag, PAUF, will be automatically reset and the EMI bit will be cleared to disable other interrupts. PWM Module Interrupts The PWM Module has two interrups. The two of them are contained in Multi-function interrupt, which is known as PWMD and PWMP. They are the Duty or the Period maching of the PWM Module. An PWM interrupt request will take place when the PWM interrupt request flag, PWMDF or PWMPF, is set, which occurs when the PWM Duty or PWM Period matches. When the interrupt is enabled, the stack is not full and PWM Duty or PWM Period maches, a subroutine call to this vector location will take place. When the interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts and the related Multi-Function request flag will be automatically Rev. 1.10 141 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU reset, but the interrupt request flag, PWMDF or PWMPF, must be manually cleared by the application program. Time Base Interrupt The function of the Time Base Interrupt is to provide regular time signal in the form of an internal interrupt. They are controlled by the overflow signals from its timer function. When this happens its interrupt request flag, TBF will be set. To allow the program to branch to its interrupt vector address, the global interrupt enable bit, EMI and Time Base enable bit, TBE, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflow, a subroutine call to its vector location will take place. When the interrupt is serviced, the interrupt request flag, TBF, will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Its clock source originates from the internal clock source fTB. This fTB input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges. The clock source that generates fTB, which in turn controls the Time Base interrupt period, can originate from several different sources, as shown in the System Operating Mode section. TBC Register Bit 7 6 5 4 3 2 1 0 Name TBON TBCK R/W R/W R/W TB1 TB0 — — — — R/W R/W — — — POR 0 0 1 — 1 — — — — Bit 7TBON: TB Control 0: Disable 1: Enable Bit 6TBCK: Select fTB Clock 0: fTBC 1: fSYS/4 Bit 5~4TB1~TB0: Select Time Base Time-out Period 00: 4096/fTB 01: 8192/fTB 10: 16384/fTB 11: 32768/fTB Bit 3~0 Unimplemented, read as "0" fS L IR C Y S fT T B 1 ~ T B 0 /4 M B C fT U X B 2 1 2 ~ 2 1 5 T im e B a s e In te r r u p t T B C K B it Time Base Interrupt Rev. 1.10 142 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU CAPTM Module Interrupt The CAPTM Module has two interrupts. All of them are contained within the Multi-function Interrupt, which are known as CapTM_Over and CapTM_Cmp. A CAPTM Interrupt request will take place when the CAPTM Interrupts request flag, CAPOF or CAPCF, is set, which occurs when CAPTM capture overflows or compare maches. To allow the program to branch to their respective interrupt vector address, the global interrupt enable bit, EMI, and the CAPTM Interrupt enable bit, and Muti-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and CAPTM capture overflows or compare maches, a subroutine call to the respective Multi-function Interrupt vector, will take place. When the CAPTM Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the CAPOF and CAPCF flag will not be automatically cleared, it has to be cleared by the application program. TM Interrupt The Compact TM has two interrupts. All of the TM interrupts are contained within the Multifunction Interrupts. For the Compact Type TM, there are two interrupt request flags TnPF and TnAF and two enable bits TnPE and TnAE. A TM interrupt request will take place when any of the TM request flags is set, a situation which occurs when a TM comparator P or A match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. RMT Module Interrupt The RMT Module has three interrupts. All of them are contained within the Multi-function Interrupt, which are known as RMT0, RMT1 and RMTV. The RMT Interrupts request will take place when the RMT Interrupts request flag, RMT0F, RMT1F or RMTVF, is set, which will occurs when raising edge transition or falling edge transition appears on the Rx_IN pin or Timer overflows. To allow the program to branch to their respective interrupt vector address, the global interrupt enable bit, EMI, RMT interrupt enable bit, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and raising edge transition or falling edge transition appears on the Rx_IN pin or Timer overflow, a subroutine call to the respective Multi-function Interrupt, will take place. When the RMT Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the RMT0, RMT1 and RMTV flags will not be automatically cleared, thy have to be cleared by the application program. EEPROM Interrupt The EEPROM Interrupt, is contained within the Multi-function Interrupt. An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, EPWF, is set, which occurs when an EEPROM Write or Read cycle ends. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, EEPROM Interrupt enable bit, EPWE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective Multi-function Interrupt vector, will take place. When the EEPROM Interrupt is serviced, the EMI bit will be Rev. 1.10 143 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the EPWF flag will not be automatically cleared, it has to be cleared by the application program. LVD Interrupt The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. An LVD Interrupt request will take place when the LVD Interrupt request flag, LVDF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low Voltage Interrupt enable bit, LVDE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the Multi-function Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the LVDF flag will not be automatically cleared, it has to be cleared by the application program. Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though this device are in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, HALLF and MF1F~MF8F, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the “CALL” instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in the SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service Rev. 1.10 144 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Low Voltage Detector – LVD Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be determined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Bit 7 6 5 4 3 2 1 0 Name — — LVDO LVDEN — VLVD2 VLVD1 VLVD0 R/W — — R R/W — R/W R/W R/W POR — — 0 0 — 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5LVDO: LVD Output Flag 0: No Low Voltage Detect 1: Low Voltage Detect Bit 4LVDEN: Low Voltage Detector Control 0: Disable 1: Enable Bit 3 Unimplemented, read as "0" Bit 2~0VLVD2~VLVD0: Select LVD Voltage 000: 3.6V 001: 3.6V 010: 3.6V 011: 3.6V 100: 3.0V 101: 3.6V 110: 3.6V 111: 3.6V Rev. 1.10 145 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a pre-specified voltage level stored in the LVDC register. This has a specified voltage 3.6V. When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is powered down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that of VLVD, there may be multiple bit LVDO transitions. LVD Operation The Low Voltage Detector also has its own interrupt which is contained within one of the Multifunction interrupts, providing an alternative means of low voltage detection, in addition to polling the LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been set high by a low voltage condition. When the device is powered down the Low Voltage Detector will remain active if the LVDEN bit is high. In this case, the LVDF interrupt request flag will be set, causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the device to wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake up function is not required then the LVDF flag should be first set high before the device enters the SLEEP or IDLE Mode. Rev. 1.10 146 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Application Circuits Hall Sensor × 3 Key Matix 3x2 AC220V DC+370V DC +15V DC+370V IP-N PC0/GAT PB7/TCK0 PC1/GAB PB6/TP0_0 IP-L PB5/TP1_0 VDD VB HIN HO LIN VS COM LO IR2101 PB4/TCK2 +15V DC+370V PA3/AN3/TCK5 PC2/GBT PC3/GBB VDD VB HIN HO LIN VS COM LO v 1 H H 3 v IR2101 H2 DC+370V IR RX CKT VIPER12 Drain VDD Drain FB VDD VB PC4/GCT HIN HO PC5/GCB LIN VS COM LO PB2/RxIN/INT1/TP2_0 IR2101 PB3/Is +5V Drain Source PC6/Fault/TP5_0 PC7/Pause/TP5_1 Drain Source VDD PA0/AN0/INT0A PA1/AN1/INT0B VSS HT7150 VIN VOUT GND PA2/AN2/INT0C v Gate Driver CKT PA4/AN4/FH0_SAT/TCK3 DC +5V PB0 PA5/AN5/FH0_SBT/TP3_1 PA6/AN6/FH0_LI/TP3_0 PA7/AN7/FH0_RI/TCK1 v Gate Driver CKT PD0/FH1_SAT/TP0_1 PD1/FH1_SBT/TP1_1 PD2/FH1_LI PD3/FH1_RI PB1/TP2_1 Buzzer Pull-low Or Pull-high HT45FM2C Rev. 1.10 147 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Hall Sensor × 1 DC+370V DC +15V DC+370V IP-N +5V Key Matix 3x2 AC220V PC0/GAT PC1/GAB PB7/TCK0 PB6/TP0_0 IP-L VDD VB HIN HO LIN VS COM LO IR2101 PB5/TP1_0 DC+370V PB4/TCK2 +15V PA3/AN3/TCK5 PC2/GBT PC3/GBB VDD VB HIN HO LIN VS COM LO v v IR2101 H2 DC+370V IR RX CKT VIPER12 Drain VDD Drain FB VDD VB PC4/GCT HIN HO PC5/GCB LIN VS COM LO PB2/RxIN/INT1/TP2_0 IR2101 PB3/Is +5V Drain Source PC6/Fault/TP5_0 PC7/Pause/TP5_1 Drain Source VDD PA0/AN0/INT0A PA1/AN1/INT0B VSS HT7150 VIN VOUT GND PA2/AN2/INT0C v Gate Driver CKT PA4/AN4/FH0_SAT/TCK3 DC +5V PB0 PA5/AN5/FH0_SBT/TP3_1 PA6/AN6/FH0_LI/TP3_0 PA7/AN7/FH0_RI/TCK1 v Gate Driver CKT PD0/FH1_SAT/TP0_1 PD1/FH1_SBT/TP1_1 PD2/FH1_LI PD3/FH1_RI PB1/TP2_1 Buzzer Pull-low Or Pull-high HT45FM2C Rev. 1.10 148 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Non-Hall Sensor DC +15V DC+370V IP-N Key Matix 3x2 AC220V PC0/GAT PC1/GAB PB7/TCK0 PB6/TP0_0 IP-L VDD VB HIN HO LIN VS COM LO IR2101 PB5/TP1_0 DC+370V PB4/TCK2 +15V DC+370V VDD VB PC2/GBT HIN HO PC3/GBB LIN VS COM LO PA3/AN3/TCK5 v v IR2101 DC+370V IR RX CKT VIPER12 Drain VDD Drain FB PB2/RxIN/INT1/TP2_0 VDD VB PC4/GCT HIN HO PC5/GCB LIN VS COM LO IR2101 PB3/Is Drain Source PC6/Fault/TP5_0 +5V Drain Source PC7/Pause/TP5_1 PA0/AN0/INT0A VDD PA1/AN1/INT0B VSS PA2/AN2/INT0C Back EMF & Filter CKT v HT7150 VI N VOU GN T D DC +5V Gate Driver CKT PA4/AN4/FH0_SAT/TCK3 PB0 PA5/AN5/FH0_SBT/TP3_1 PA6/AN6/FH0_LI/TP3_0 PA7/AN7/FH0_RI/TCK1 v Gate Driver CKT PD0/FH1_SAT/TP0_1 PD1/FH1_SBT/TP1_1 PD2/FH1_LI PD3/FH1_RI PB1/TP2_1 Buzzer Pull-low pull-high HT45FM2C Rev. 1.10 149 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be “CLR PCL” or “MOV PCL, A”. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Rev. 1.10 150 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application which rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction “RET” in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the “SET [m].i” or “CLR [m].i” instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the “HALT” instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 1.10 151 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rev. 1.10 152 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Mnemonic Description Cycles Flag Affected Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Read table to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the “CLR WDT1” and “CLR WDT2” instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both “CLR WDT1” and “CLR WDT2” instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.10 153 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Instruction Definition ADC A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C ADCM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC ADD A,[m] Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C ADD A,x Description Operation Affected flag(s) Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ← ACC + x OV, Z, AC, C ADDM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C AND A,[m] Description Operation Affected flag(s) Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z AND A,x Description Operation Affected flag(s) Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ x Z ANDM A,[m] Description Operation Affected flag(s) Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z Rev. 1.10 154 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU CALL addr Description Operation Affected flag(s) Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack ← Program Counter + 1 Program Counter ← addr None CLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None CLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None CLR WDT Description Operation Affected flag(s) Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO ← 0 PDF ← 0 TO, PDF CLR WDT1 Description Operation Affected flag(s) Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF CLR WDT2 Description Operation Affected flag(s) Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF CPL [m] Description Operation Affected flag(s) Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z Rev. 1.10 155 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU CPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z DAA [m] Description Operation Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C DEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z DECA [m] Description Operation Affected flag(s) Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z HALT Description Operation Affected flag(s) Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ← 0 PDF ← 1 TO, PDF INC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z INCA [m] Description Operation Affected flag(s) Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z Rev. 1.10 156 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU JMP addr Description Operation Affected flag(s) Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter ← addr None MOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None MOV A,x Description Operation Affected flag(s) Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC ← x None MOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None NOP Description Operation Affected flag(s) No operation No operation is performed. Execution continues with the next instruction. No operation None OR A,[m] Description Operation Affected flag(s) Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z OR A,x Description Operation Affected flag(s) Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ x Z ORM A,[m] Description Operation Affected flag(s) Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z RET Description Operation Affected flag(s) Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter ← Stack None Rev. 1.10 157 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU RET A,x Description Operation Affected flag(s) Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter ← Stack ACC ← x None RETI Description Operation Affected flag(s) Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter ← Stack EMI ← 1 None RL [m] Description Operation Affected flag(s) Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None RLA [m] Description Operation Affected flag(s) Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None RLC [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C RLCA [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C RR [m] Description Operation Affected flag(s) Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None Rev. 1.10 158 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU RRA [m] Description Operation Affected flag(s) Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None RRC [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C RRCA [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C SBC A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C SBCM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C SDZ [m] Description Operation Affected flag(s) Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None Rev. 1.10 159 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU SDZA [m] Description Operation Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None SET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None SET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None SIZ [m] Description Operation Affected flag(s) Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None SIZA [m] Description Operation Affected flag(s) Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None SNZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None SUB A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C Rev. 1.10 160 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU SUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C SUB A,x Description Operation Affected flag(s) Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − x OV, Z, AC, C SWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None SWAPA [m] Description Operation Affected flag(s) Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None SZ [m] Description Operation Affected flag(s) Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None SZA [m] Description Operation Affected flag(s) Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None SZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None Rev. 1.10 161 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU TABRDC [m] Description Operation Affected flag(s) Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDL [m] Description Operation Affected flag(s) Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None XOR A,[m] Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z XORM A,[m] Description Operation Affected flag(s) Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z XOR A,x Description Operation Affected flag(s) Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ x Z Rev. 1.10 162 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website (http://www.holtek.com.tw/english/literature/package.pdf) for the latest version of the package information. 16-pin NSOP (150mil) Outline Dimensions MS-012 Symbol Min. Nom. Max. A 0.228 ― 0.244 B 0.150 ― 0.157 C C׳ 0.012 ― 0.020 0.386 ― 0.402 D ― ― 0.069 E ― 0.050 ― F 0.004 ― 0.010 G 0.016 ― 0.050 H 0.007 ― 0.010 α 0˚ ― 8˚ Symbol Rev. 1.10 Dimensions in inch Dimensions in mm Min. Nom. Max. A 5.79 ― 6.20 B 3.81 ― 3.99 C C׳ 0.30 ― 0.51 9.80 ― 10.21 D ― ― 1.75 E ― 1.27 ― F 0.10 ― 0.25 G 0.41 ― 1.27 H 0.18 ― 0.25 α 0˚ ― 8˚ 163 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU 28-pin SKDIP (300mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A 1.375 — 1.395 B 0.278 — 0.298 C 0.125 — 0.135 D 0.125 — 0.145 E 0.016 — 0.020 0.070 F 0.050 — G — 100 — H 0.295 — 0.315 I — 375 — Symbol Rev. 1.10 Dimensions in mm Min. Nom. Max. A 34.93 — 35.43 B 7.06 — 7.57 C 3.18 — 3.43 D 3.18 — 3.68 E 0.41 — 0.51 F 1.27 — 1.78 G — 2.54 — H 7.49 — 8.00 I — 9.53 — 164 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU 28-pin SOP (300mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A 0.393 — 0.419 B 0.256 — 0.300 C C׳ 0.012 — 0.020 0.697 — 0.713 D — — 0.104 E — 0.050 — F 4 — 0.012 G 16 — 0.050 H 8 — 0.013 α 0° — 8° Symbol Rev. 1.10 Dimensions in mm Min. Nom. Max. A 9.98 — 10.64 B 6.50 — 7.62 C C׳ 0.30 — 0.51 17.70 — 18.11 D — — 2.64 E — 1.27 — F 0.10 — 0.30 G 0.41 — 1.27 H 0.20 — 0.33 α 0° — 8° 165 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU 28-pin SSOP (150mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A 0.228 — 0.244 B 0.150 — 0.157 C 0.008 — 0.012 C׳ 0.386 — 0.394 D 0.054 — 0.060 E — 0.025 — F 0.004 — 0.010 G 0.022 — 0.028 H 0.007 — 0.010 α 0° — 8° Symbol Rev. 1.10 Dimensions in mm Min. Nom. Max. A 5.79 — 6.20 B 3.81 — 3.99 C C׳ 0.20 — 10.01 D 1.37 — 1.52 E — 0.64 — F 0.10 — 0.25 G 0.56 — 0.71 H 0.18 — 0.25 α 0° — 8° 0.30 9.80 166 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU 44-pin QFP (10mm×10mm) Outline Dimensions Symbol Dimensions in mm Min. Nom. Max. A 0.512 — 0.528 B 0.390 — 0.398 C 0.512 — 0.528 D 0.390 — 0.398 E — 0.031 — F — 0.012 — G 0.075 — 0.087 H — — 0.106 I 0.010 — 0.020 J 0.029 — 0.037 K 0.004 — 0.008 L — 0.004 — α 0° — 7° Symbol A Rev. 1.10 Dimensions in mm Min. Nom. Max. 13.00 — 13.40 B 9.90 — 10.10 C 13.00 — 13.40 D 9.90 — 10.10 E — 0.8 — F — 0.3 — G 1.90 — 2.20 H — — 2.70 I 0.25 — 0.50 J 0.73 — 0.93 K 0.10 — 0.20 L — 0.10 — α 0° — 7° 167 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Reel Dimensions 16-pin NSOP(150mil) Symbol A Description Dimensions in mm Reel Outer Diameter 330.0±1.0 B Reel Inner Diameter 100.0±1.5 C Spindle Hole Diameter 13.0+0.5/-0.2 D Key Slit Width T1 Space Between Flang 16.8+0.3/-0.2 2.0±0.5 T2 Reel Thickness 22.2±0.2 SOP 28W(300mil) Symbol Description Dimensions in mm A Reel Outer Diameter 330.0±1.0 B Reel Inner Diameter 100.0±1.5 C Spindle Hole Diameter 13.0+0.5/-0.2 D Key Slit Width T1 Space Between Flang 24.8+0.3/-0.2 2.0±0.5 T2 Reel Thickness 30.2±0.2 SSOP 28S (150mil) Symbol Rev. 1.10 Description Dimensions in mm A Reel Outer Diameter 330.0±1.0 B Reel Inner Diameter 100.0±1.5 C Spindle Hole Diameter 13.0+0.5/-0.2 D Key Slit Width T1 Space Between Flang 16.8+0.3/-0.2 T2 Reel Thickness 22.2±0.2 2.0±0.5 168 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Carrier Tape Dimensions 16-pin NSOP (150mil) Symbol W Rev. 1.10 Description Carrier Tape Width Dimensions in mm 16.0±0.3 P Cavity Pitch 8.0±0.1 E Perforation Position 1.75±0.1 F Cavity to Perforation(Width Direction) D Perforation Diameter 1.55+0.10/-0.00 7.5±0.1 D1 Cavity Hole Diameter 1.50+0.25/-0.00 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation(Length Direction) 2.0±0.1 A0 Cavity Length 6.5±0.1 B0 Cavity Width 10.3±0.1 K0 Cavity Depth 2.1±0.1 t Carrier Tape Thickness 0.30±0.05 C Cover Tape Width 13.3±0.1 169 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU SOP 28W (300mil) Symbol Description Dimensions in mm W Carrier Tape Width P Cavity Pitch 12.0±0.1 E Perforation Position 1.75±0.10 24.0+0.3 F Cavity to Perforation(Width Direction) 11.5±0.1 D Perforation Diameter 1.5+0.10/-0.0 D1 Cavity Hole Diameter 1.50+0.25/-0.00 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation(Length Direction) 2.0±0.1 A0 Cavity Length B0 Cavity Width 10.85±0.1 2.97±0.1 K0 Cavity Depth 2.97±0.10 t Carrier Tape Thickness 0.35±0.01 C Cover Tape Width 21.3±0.1 SSOP 28S (150mil) Symbol Rev. 1.10 Description Dimensions in mm W Carrier Tape Width P Cavity Pitch 8.0±0.1 E Perforation Position 1.75±0.1 F Cavity to Perforation(Width Direction) 7.5±0.1 D Perforation Diameter 1.55+0.1/-0.0 D1 Cavity Hole Diameter 1.50+0.25/-0.00 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation(Length Direction) 2.0±0.1 16.0±0.3 A0 Cavity Length 6.5±0.1 B0 Cavity Width 10.3±0.1 K0 Cavity Depth 2.1±0.1 t Carrier Tape Thickness 0.30±0.05 C Cover Tape Width 13.3±0.1 170 May 30, 2012 Preliminary HT45FM2C Brushless DC Motor Flash Type 8-Bit MCU Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com Copyright© 2012 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.10 171 May 30, 2012