iC-JJ POWER MANAGEMENT iC Rev A1, Page 1/17 FEATURES APPLICATIONS ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° ° Supply voltage range of VBAT= 6 to 16.5V Autarky function to maintain temporarily output voltages with breakdown of supply voltage Adjustable 200mA boost converter (VA1= VBAT+2V to 48V) 6V step-down regulator with integrated 125kHz oscillator Two downstream 5V linear regulators with 200mA/60mA output current 12V/30mA tri-state output Low standby current of typ. 30µA Integrated high/low-side drivers e.g. to attach indicator lamps Overtemperature shutdown of high- and low-side drivers Undervoltage detection Serial single-wire communication interface Watchdog for monitoring of the external µ-controller CMOS-compatible inputs TTL-/CMOS-compatible outputs ESD protection Universal voltage supply iC with monitoring and autarky function for the voltage supply of automotive and industrial applications PACKAGE MFQ44 BLOCK DIAGRAM VBAT+2V...48V +VBAT CKL 33nF D2 D1 +5V/200mA +5V/60mA D3 LA1 270µH LVB 150µH VBL CVA1 100µF CVA 2200µF CVB 100µF VA1 VVA VA VB CVH 33µF LVH VHL CVCC 4.7µF VCC VH CVREF 1µF NFL VREF NAKS R1 VA1x R2 VH-SWITCHING PGND AUTARKY GND BOOST CONVERTER REGULATOR REG VCC 200mA REG VREF AUTARKY CONTROL DRIVER ESD NCRD VB COS COS HD NRHD 50mA DRIVER + + OSCILLATOR TWD WATCHDOG TEMPERATUR TFL LOGIC VCC iC-JJ RSET RSET 10k: RKLR 511: CRA TAKS + BIAS CVBG 100nF 511: 30mA DRIVER REFERENCE VBG RKL 30mA DRIVER + IN-/OUTPUT STAGES VM TCRD STANDBY TEST AID & VCC VMR TCRA PCRD VCC PAKS & PFL K-INTERFACE AGND REG VFP AUTARKY DETECTION NVTA RESET VTU RXD TXD K CVFP 10nF © 2000 iC-Haus GmbH Integrated Circuits Am Kuemmerling 18, D-55294 Bodenheim PCRA VFP TFP ENA +12V/30mA NRES ENABLE Tel. +49-6135-9292-0 Fax +49-6135-9292-192 http://www.ichaus.com iC-JJ POWER MANAGEMENT IC Rev A1, Page 2/17 GENERAL DESCRIPTION Monolithic device iC-JJ supplies electronic systems from a single input voltage VBAT (6V to 16.5V) with voltages which range from 5V to 48V. The autarky function guarantees that the output voltages are maintained for up to several hundred milliseconds, even after the input voltage has been aborted. A step-up converter produces a voltage of VBAT+2V to 48V, whose setpoint is adjusted via two external resistors at VA1x. Two 5V linear regulators provide 200mA (VCC) and 60mA (VREF). Alternatively, 260mA are available from the 6V step-down converter (VH) whose switching frequency is generated by an integrated 120kHz oscillator. An additional tristate-competent output provides 12V to 30mA and can be activated via a control input for writing data to EEPROMs, for example. The integrated low voltage and autarky detection function indicates at the error message outputs VTU and NVTA when the relevant low voltage thresholds are reached; there are two different error message outputs for this purpose. The error message is deleted by an external low signal and not when the supply voltage rises again. Information on temporary voltage drops is retained. If the autarky voltage threshold is undershot, the iC automatically switches into autarky mode. This mode can also be simulated in order to test the autarky capacitor CVA. Integrated high- and low-side drivers permit various loads to be connected, such as panel indicators (visual monitors), for example. The drivers are switched via control inputs and status outputs are signaling the current switching state back to the controller. iC-JJ monitors the chip temperature; with excessive temperature the high- and low-side drivers are switched off to reduce the power dissipation. The integrated watchdog can monitor the correct operation of an external processor. If used, the bi-directional serial communication interface connects the chip with external diagnosis components. The iC can be switched to standby via the input ENA and then draws a low standby current of typically 30 µA. The device is protected against destruction due to ESD. iC-JJ POWER MANAGEMENT IC Rev A1, Page 3/17 PACKAGE MQFP44 according to the JEDEC standard PIN CONFIGURATION MQFP44 (top view) PCRD 1 33 VA1 TAKSE 2 32 VHL TCRD 3 31 VFP TCRA 4 30 VA NRES 5 29 n.c. VVA 6 28 n.c. GND 7 27 VB VBG 8 26 VA1x RSET 9 25 VMR AGND 10 24 VM ENA 11 23 K JJ Code... yyww ... PIN FUNCTIONS No. Name Function No. Name Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PCRD TAKS TCRD TCRA NRES VVA GND VBG RSET AGND ENA COS TFP TWD NRHD TXD RXD VTU NVTA VREF VH VCC K VM Message Output for Pin NCRD Trigger Input for Output NAKS Trigger Input for Output NCRD Trigger Input for Output CRA Reset, low active Capacitor Test Output Ground Bandgap Reference Voltage Attachment RSET Analog Ground Enable Capacitor for Oscillator Adjustment Trigger Input for Output VFP Trigger Input for Watchdog Trigger Input for Pin HD Trigger Input K-Interface Digital Output K-Interface Message Output Undervoltage Detection Message Output Autarky Detection +5V Output (60mA) +6V Output +5V Output (200mA) Bidirectional K-Interface Measurement Input Undervoltage- and Autarky Detection 25 VMR 26 27 28 29 30 31 32 VA1x VB n.c. n.c. VA VFP VHL Measurement Input Undervoltage- and Autarky Detection Setpoint Assignment VA1 Supply during autarky mode 33 34 VA1 VBL 35 36 37 38 39 40 41 42 43 44 PGND NFL NAKS NCRD CRA HD TFL PFL PAKS PCRA Voltage VA +12V Tri-state Output (30mA) Attachment Inductance for Step-down Regulator VBAT+2V...+48V Output Attachment Inductance for Boost Converter Ground 200mA Low-side Driver Output 30mA Low-side Driver Output 30mA Low-side Driver Output 50mA High-side Driver Output Tri-state Output, Low-side Driver Trigger Input for Output NFL Message Output for Pin NFL Message Output for Pin NAKS Message Output for Pin CRA iC-JJ POWER MANAGEMENT IC Rev A1, Page 4/17 ABSOLUTE MAXIMUM RATINGS Values beyond which damage may occur; device operation is not guaranteed. Item Symbol Parameter Conditions Fig. Unit Min. Max. G001 V() Voltage at COS, TWD, VBG, RSET, V() # VCC+ 0.3V RXD, TXD, TFP, TAKS, TFL, TCRD, TCRA, PFL, PAKS, PCRD, PCRA, NRES, NVTA, VTU, NRHD, VVA -0.3 5.5 V G002 I() Current in Pins COS, TWD, VBG, RSET, RXD, TXD, TFP, TAKS, TFL, TCRD, TCRA, PFL, PAKS, PCRD, PCRA, NRES, NVTA, VTU, NRHD, VVA -10 10 mA G003 ESD ESD Susceptibility at VM, VMR, VHL MIL-STD-883, Method 3015.7 HBM 100pF discharged through 1.5kS 0.8 kV G004 ESD ESD Susceptibility at all other Pins 1.4 kV G201 V(NAKS) Voltage at NAKS -1.2 48 V G202 I(AKS) Current in NAKS -30 30 mA G401 V(ENA) Voltage at ENA -0.3 48 V G402 I(ENA) Current in ENA -4 4 mA G501 V(VHL) Voltage at VHL G502 I(VHL) Current in VHL G503 V(VH) Voltage at VH G504 I(VH) Current in VH G505 V(VH) MIL-STD-883, Method 3015.7 HBM 100pF discharged through 1.5kS V(VHL) # V(VA1) -1.4 48 V -600 10 mA V(VH) $ V(VCC) V(VH) $ V(VREF) -0.3 7 V -6 600 mA Voltage at VH V(VH) $ V(VCC) V(VH) $ V(VREF), I < 50mA -0.3 10 V G601 V(VCC) Voltage at VCC V(VCC) # V(VH) G602 I(VCC) Current in VCC G701 V(VREF) Voltage at VREF G702 I(VREF) Current in VREF G901 V(VFP) Voltage at VFP -0.3 12.5 V G902 I(VFP) Current in VFP -40 6 mA GA01 V(VA1) Voltage at VA1 -0.3 48 V GA02 I(VA1) Current in VA1 -1600 10 mA GA03 V(VA1x) Voltage at VA1x -0.3 7 V GA04 I(VA1x) Current in VA1x -4 4 mA GA05 V(VBL) Voltage at VBL -0.3 48 V GA06 I(VBL) Current in VBL -10 1600 mA GB01 V(K) Voltage at K -8.8 48 V GB02 I(K) Current in K -6 200 mA GC01 V(HD) Voltage at HD -0.3 48 V GC02 I(HD) Current in HD -4 4 mA GD01 V(NFL) Voltage at NFL -1.2 48 V GD02 I(NFL) Current in NFL -200 200 mA GG01 V(VA) Voltage at VA -0.3 48 V GG02 I(VA) Current in VA -20 500 mA V(VREF) # V(VH) applied via lamp of 2W V(VA, VB)< 3V, t< 2s All voltages are referenced to ground unless otherwise noted. All currents into the device pins are positive; all currents out of the device pins are negative. -0.3 5.5 V -300 10 mA -0.3 5.5 V -100 10 mA iC-JJ POWER MANAGEMENT IC Rev A1, Page 5/17 ABSOLUTE MAXIMUM RATINGS Values beyond which damage may occur; device operation is not guaranteed. Item Symbol Parameter Conditions Fig. Unit Min. Max. -0.3 48 V GG03 V(VB) Voltage at VB GG04 I(VB) Current in VB V(VA, VB)< 3V, t< 2s -500 50 mA GG05 Imax(VB) Max. Current Load at VB during Autarky Case VA1< 30.6V, CVB< 120µF, RVB> 9.5S -200 0 mA GH01 V(NCRD) Voltage at NCRD -1.2 48 V GH02 I(NCRD) Current in NCRD -30 30 mA GI01 V(CRA) Voltage at CRA -8.8 48 V GI02 I(CRA) Current in CRA GP01 V(VM) Voltage at VM -50 50 mA via 511S -1.5 48 V GP02 I(VM) Current in VM GP03 V(VMR) Voltage at VMR -55 20 mA via 511S -1.5 48 V GP04 I(VMR) Current in VMR GP05 I(VM) -55 20 mA Current in VM t < 100ms -160 20 mA GP06 I(VMR) Current in VMR t < 100ms -160 20 mA TG1 Tj Junction Temperature -40 125 TG2 Ts Storage Temperature Range -40 125 EC EC TG3 Tl Lead Temperature 260 EC soldering, 10sec THERMAL DATA Operating conditions: +VBAT= 6..16.5V, PGND= GND, COS= 680pF, RSET= 10kS, RKL= 511S, RKLR= 511S, Tj= -40..125EC, unless otherwise noted Item Symbol Parameter Conditions Fig. Unit Min. T001 Ta Operating Ambient Temperature Range T002 Rthja Thermal Resistance Chip / Ambient Typ. -40 Max. 95 40 EC K/W iC-JJ POWER MANAGEMENT IC Rev A1, Page 6/17 ELECTRICAL CHARACTERISTICS Operating conditions: +VBAT= 6..16.5V, PGND= GND, COS= 680pF, RSET= 10kS, RKL= 511S, RKLR= 511S, Tj= -40..125EC, unless otherwise noted Item Symbol Parameter Conditions Tj EC Fig. Unit Min. Typ. Max. Total Device 1 Supply Current in VA1 outputs passive, VA1= 30V, VH= 6V 8 3 52 mA 002 I(VH) Supply Current in VH in-/outputs passive, VA1= 30V, VH= 6V 25 5 75 mA 003 I(KL, KLR) Supply Current in KL, KLR in-/outputs passive, switching regulator active, V(KL, KLR)= 12V 8 12 16 mA 004 I(KL, KLR) Supply Current in KL, KLR in-/outputs passive, switching regulator active, V(KL, KLR)= 6.5V 20 25 32 mA Supply Current in KL, KLR no external capacitance at VA1, VA, VB; ENA= lo, V(KL, KLR) < 18V 100 µA 15.4 kS kS 24.6 kS kS 5 I(VA1) I(KL, KLR) 006 Rpu() 7 Rpd() Pull-up Resistor to VCC at Inputs TWD, TXD, NRHD, NRES, NVTA, VTU Pull-down Resistor to GND at Inputs TFP, TAKS, TFL, TCRD, TCRA 5.4 27 for TFP test mode= lo Vpu() Pull-up Voltage to VCC at Inputs Vpu()= V()- VCC; TWD, TXD, NRHD, NRES, NVTA, I()= -10..10µA VTU 9 Vpd() Pull-down Voltage to GND at Inputs TFP, TAKS, TFL, TCRD, TCRA 10 Vt()hi Threshold Voltage hi at Inputs TWD, TXD, TFP, TAKS, TFL, TCRD, TCRA, NRHD, NRES, NVTA, VTU 11 Vt()lo Threshold Voltage lo at Inputs TWD, TXD, TFP, TAKS, TFL, TCRD, TCRA, NRHD, NRES, NVTA, VTU 12 Vt()hys Hysteresis at Inputs TWD, TXD, TFP, TAKS, TFL, TCRD, TCRA, NRHD, NRES, NVTA, VTU Vt()hys= Vt()hi- Vt()lo 13 Vs()lo Saturation Voltage lo at Outputs NRES, NVTA, VTU, RXD, PFL, PAKS, PCRD, PCRA I()= 1.6mA, outputs lo 14 Vs()hi Saturation Voltage hi vs. VCC at Outputs RXD, PFL, PAKS, PCRD, PCRA Vs()= V()- VCC; I()= -1mA, outputs hi 15 Isc() Short-circuit Current in Outputs NRES, NVTA, VTU, HD V()= VCC, pins= lo, V(HD)= VA1 tsup() 8.8 27 8 16 9.1 14.7 -0.3 V I()= -10..10µA, for TFP test mode= lo Permissible Spurious Pulse Width no switching triggered at Inputs TWD, TXD, TFP, TAKS, TFL, TCRD, TCRA, NRHD, NRES, NVTA, VTU 0.3 V 67 %VCC 33 %VCC 500 mV 0.4 -0.8 27 V V 30 mA mA 40 ns 10 iC-JJ POWER MANAGEMENT IC Rev A1, Page 7/17 ELECTRICAL CHARACTERISTICS Operating conditions: +VBAT= 6..16.5V, PGND= GND, COS= 680pF, RSET= 10kS, RKL= 511S, RKLR= 511S, Tj= -40..125EC, unless otherwise noted Item Symbol Parameter Conditions Tj EC Fig. Unit Min. Typ. Max. Total Device (continued) 17 Vc()lo against GND, I()= -10mA ESD Clamp Voltage lo at COS, TWD, VBG, RSET, AGND, RXD, TXD, NRES, NVTA, VTU, VM, VMR, TFP, TFL, PFL, VH, VREF, VCC, ENA, TAKS, PAKS, TCRD, TCRA, PCRD, PCRA, NRHD, VVA, HD, VA1x, VA, VB -1.4 -0.3 V 18 Vc()lo ESD Clamp Voltage lo at NFL, VHL, VFP, VA1, VBL, NCRD, NAKS against PGND, I()= -10mA -1.4 -0.3 V 19 Vc()lo ESD Clamp Voltage lo at K against GND, I()= -10mA -15 -5.5 V 20 Vc()lo ESD Clamp Voltage lo against PGND at CRA against PGND, I()= -10mA -15 -5.5 V 21 Vc()hi against GND, I()= 10mA ESD Clamp Voltage hi at COS, TWD, VBG, RSET, AGND, RXD, TXD, NRES, NVTA, VTU, VREF, VCC, VH, VA1x, VVA, TAKS, PAKS, TFL, PFL, TCRD, TCRA, PCRD, PCRA, NRHD 5.5 14 V 22 Vc()hi ESD Clamp Voltage hi at TFP against GND, I()= 10mA 5.5 16 V 023 Vc()hi ESD Clamp Voltage hi at VFP against PGND, I()= 10mA 12.5 28 V 24 against PGND, I()= 10mA ESD Clamp Voltage hi at CRA, NCRD, K, VM, VMR, NFL, NAKS, VHL, VA1, VBL, VA, VB, ENA, HD 60 V Vc()hi 48 27 52 Fall Time at RXD, PFL, PAKS, PCRD, PCRA, NRES, NVTA, VTU CL= 75pF V(): hi= 80% 6 lo= 20% VCC 60 ns 026 tTHL Rise Time at RXD, PFL, PAKS, PCRD, PCRA CL= 75pF V(): lo= 20% 6 hi= 80% VCC 80 ns 27 Permissible Voltage at VA1, VA, VB, VBL 48 V 2.52 V V 2.52 V V 1 V 200 mA mA 25 100 µA 2.25 2.75 V 25 tTHL V() Reference and Bias 101 V(VBG) Voltage at VBG CVBG= 10..200nF 2.36 27 102 V(RSET) Voltage at RSET R(RSET/AGND)= 10kS ±1% 2.44 2.36 27 2.44 30mA Low-side Driver 201 VsNAKS Saturation Voltage at NAKS I(NAKS)= 30mA, T < Tab, TAKS= hi, NAKS= lo 202 IscNAKS Short-circuit Current in NAKS V(NAKS) < 18V, T < Tab, TAKS= hi, NAKS= lo 203 IpdNAKS Pull-down Current in NAKS 204 VtNAKS Switching Threshold at NAKS for PAKS 205 VfNAKS Free-wheeling Voltage at NAKS V(NAKS)= 2..16.5V, TAKS= lo I(NAKS)= 10mA, TAKS= lo, NAKS= hi 27 65 48 V iC-JJ POWER MANAGEMENT IC Rev A1, Page 8/17 ELECTRICAL CHARACTERISTICS Operating conditions: +VBAT= 6..16.5V, PGND= GND, COS= 680pF, RSET= 10kS, RKL= 511S, RKLR= 511S, Tj= -40..125EC, unless otherwise noted Item Symbol Parameter Conditions Tj EC Fig. Unit Min. Typ. Max. Thermal Shutdown 301 Toff Thermal Shutdown Threshold for NFL, NAKS, CRA, NCRD, K 135 160 EC 302 Ton Thermal Lock-on Threshold for NFL, NAKS, CRA, NCRD, K 110 145 EC 303 Thys Temperature Hysteresis Thys= Toff- Ton EC 12 Standby 401 V(ENA)lo Lower Enable Threshold 2 V 402 V(ENA)hi Upper Enable Threshold 403 VENAhys Hysteresis Enable Input 404 V(ENA) 80 Permissible Voltage at ENA 405 Ipd(ENA) Pull-down Current in ENA V(ENA)= 2..48V 5 4 V 800 mV 48 V 50 µA 6.3 V V VH-Switching Regulator 501 VHn 502 Ia(VHL) Voltage at VH Max. DC cutoff Current in VHL LVH= 150µH±20%..470µH±20%, CVH= 33µF ±20%, Ri(LVH) < 1.1S, I(VH)= -200..0mA VH < VHn 5.6 27 6 -800 -500 mA 503 Vs(VHL) Saturation Voltage at VHL Vs()= V(VA1)- V(VHL); I(VHL)= -300mA 1.3 V 504 Vf(VHL) Free-wheeling Diode Forward Voltage Vf()= V(GND)- V(VHL); I(VHL)= -300mA 1.4 V 505 Ilk(VHL) Leakage Current in VHL VHL= lo, V(VHL)= 0V..VA1 100 µA 506 0VH VH-Switching Regulator Efficiency I(VH)= -200..-20mA 601 VCCn Voltage at VCC I(VCC)= -200..0mA, VH= 5.6..6.3V, CVCC $ 4.7FF ±30% 4.85 602 CVCC Permissible Capacitance at VCC to AGND Tolerance ±30% 3.3 -100 70 % Regulator VCC 5.15 V µF 603 RiCVCC Permissible Internal Resistance of Capacitor at VCC 10 S 604 dVCCoff Turn-off Threshold Over- and Undervoltage |VCCoff - VCCn| for NRES= lo 200 mV 605 dVCCon Turn-on Threshold Over- and Undervoltage dVCCon= |VCCon - VCCn|, NRES= hi 40 mV 606 dVCCres Hysteresis of Turn-un and Turnoff Threshold at VCC dVCCres= |VCCon - VCCoff| 40 mV 607 tl(NRES) Reset Pulse Width lo at NRES Triggered by VCC 6.8 608 Vr(VCC) Voltage Ratio VCC / VREF I(VCC)= 0..200mA 0.99 µs 101 iC-JJ POWER MANAGEMENT IC Rev A1, Page 9/17 ELECTRICAL CHARACTERISTICS Operating conditions: +VBAT= 6..16.5V, PGND= GND, COS= 680pF, RSET= 10kS, RKL= 511S, RKLR= 511S, Tj= -40..125EC, unless otherwise noted Item Symbol Parameter Conditions Tj EC Fig. Unit Min. Typ. Max. Regulator VREF 701 VREFn Voltage at VREF I(VREF)= -60..0mA, VH= 5.6..6.3V, CVREF $ 1FF ±30% 702 CVREF Permissible Capacitor at VREF to AGND tolerance ±30% 4.9 5.1 1 V µF 703 RiCVREF Permissible Internal Resistance of Capacitor at VREF 10 S 200 mV 704 dVREFoff Turn-off Threshold Over- and Undervoltage dVREFoff= |VREFoff - VREFn|, NRES= lo 705 dVREFon Turn-on Threshold Over- and Undervoltage dVREFon= |VREFon - VREFn|, NRES= hi 40 mV 706 dVREFres Hysteresis of Turn-on and Turnoff Threshold at VREF dVREFres= |VREFon-VREFoff| 20 mV 707 tl(NRES) Reset Pulse Width lo at NRES Triggered by VREF 6.8 708 Vf Forward Voltage Discharging Diode between VREF and VCC I()= 20mA Voltage at VFP I(VFP) # -30mA, VA1 > 15V, TFP= hi µs 1.2 V 12.5 12 V V -90 mA mA VFP-Regulator 901 V(VFP) 902 Isc(VFP) Short-circuit Current in VFP 11.5 27 V(VFP) < 11.5V, TFP= hi -200 27 903 Ilk(VFP) Leakage Current in VFP V(VFP)= 0..10V, TFP= lo -10 10 µA 904 Ilk(VFP) Leakage Current in VFP V(VFP)= 10..12.5V, TFP= lo -10 250 µA 10 µs 905 tsu(VFP) Settle Time at VFP V(VFP)= 12V ±0.5V Boost Converter A01 VA1n Voltage at VA1 VB= 14V, LVB= 150µH ±20%, Ri(LVB) < 1S, I(VA1)= -200..0mA 28.4 30.6 V A02 VA1n Voltage at VA1 VB= 5V, I(VA1)= -25..0mA 28.4 30.6 V A03 VA1n Voltage at VA1 VB= 6.5V, I(VA1)= -60mA 284 306 V A04 VA1 Voltage at VA1 VB= 6.5V, I(VA1)= -120mA 190 306 V A05 VA1 Voltage at VA1 VB= 6.5V, I(VA1)= -200mA 14.0 30.6 V A06 Ico(VBL) DC Cutoff Current in VBL V(VA1) < 28.5V 1 A07 Vs(VBL) Saturation Voltage at VBL VBL= lo, I(VBL)= 600mA 1 V A08 Vf(VBL) Forward Voltage Free-wheeling Diode Vf()= V(VBL) - V(VA1); VBL= hi, I(VBL)= 20mA 1.1 V A09 Vf(VBL) Forward Voltage Free-wheeling Diode Vf()= V(VBL) - V(VA1); VBL= hi, I(VBL)= 600mA 1.4 V A10 0VA1 Efficiency of VA1-Regulator VB= 5V, V(VA1) > 28.5V 50 % A11 0VA1 Efficiency of VA1-Regulator VB= 6.5V, V(VA1) > 28.5V 65 % A12 0VA1 Efficiency of VA1-Regulator VB= 18V, V(VA1) > 28.5V 80 % A13 Ilk(VBL) Leakage Current in VBL V(VBL)= 0V..VA1, VBL= hi -100 100 A14 Vr(VA1) Voltage Ratio V(VA1) / V(VREF) internal VA1-voltage divider 5.7 6.1 27 5.9 A µA iC-JJ POWER MANAGEMENT IC Rev A1, Page 10/17 ELECTRICAL CHARACTERISTICS Operating conditions: +VBAT= 6..16.5V, PGND= GND, COS= 680pF, RSET= 10kS, RKL= 511S, RKLR= 511S, Tj= -40..125EC, unless otherwise noted Item Symbol Parameter Conditions Tj EC Fig. Unit Min. Typ. Max. Boost Converter (continued) A15 Ipu(VA1x) Pull-Up Current in VA1x V(VA1x) < 1V -25 27 A16 Vr(VA1x) Transformation Ratio with external Voltage Divider R(VA1/VA1x) / R(VA1x/AGND) -1 -5 2 V(VA1)= (1+R(VA1/VA1x) / R(VA1x/AGND)) × V(VBG), R(VA1x/AGND)= 1..5k, V(VA1)= V(VB)..48V µA µA 18 K-Interface B01 Vs(K) Saturation Voltage at K I(K)= 15.7mA, TXD= lo, T < Tab 1.4 V B02 Vs(K) Saturation Voltage at K I(K)= 32.4mA, TXD= lo, T < Tab 1.7 V B03 Isc(K) Short-circuit Current in K V(K)= 2..27V, TXD= lo, t < 100ms 150 mA mA 27 60 B04 C(K) Permissible Input Capacitance K 25 pF B05 Ipu(K) Pull-Up Current in K V(KL, KLR)= 8..16.5V, V(K)= 0.2V..V(KL, KLR)-1V V(VA1) > V(VM) + 2V, TXD= hi -80 -20 µA B06 Vt(K) Switching Threshold at K related to Maximum V(KL, KLR) V(KL, KLR)= 6..16.5V, TXD= hi 45 55 % B07 Vt(K) Switching Threshold at K during Autarky V(KL, KLR) < 5.5V 66 %VCC %VCC B08 Vhys(K) Hysteresis at K V(KL, KLR)= 6..16.5V or Autarky 300 mV B09 tf(K) Fall Time at K R(KLR/K)= 511S, CK < 5nF, V(K) from hi= 80% 6 lo= 20% V(KLR), TXD from hi to lo 2 µs B10 In(K) Current in K V(K)= -3V, TXD= hi -8 B11 Ilk(K) Leakage Current in K V(K) > KL, KLR, TXD = hi, V(K) < 27V, VM, VMR > 0V -20 B12 Vf(K) Free-wheeling Voltage at K I(K)= 10mA, TXD= hi 48 B13 Vpu(K) Pull-up Current at K against V(VM, VMR) I(K)= -20µA, TXD= hi, V(VM), V(VMR)= 8..16.5V V(VA1) > V(VM) + 2V -0.3 B14 tp(K) Transmission Delay K 6 RXD f # 200kHz, V(K) from 25% 6 75% V(VM, VMR) B15 tp(K) Transmission Delay TXD6K f # 200kHz, V(K) from 75% 6 25% V(VM, VMR) B16 dtp(K) Transmission Delay Difference K 6 RXD, K lo 6 hi to K hi 6 lo B17 tf(K) Fall Time at K 54 27 60 50 mA 20 µA V 0.3 V 6 2 µs 4 2 µs f # 200kHz, V(K) from 25% 6 75% V(VM, VMR) 1 µs R(KLR/K)= 511S,, CK< 10nF, V(K) from hi= 80% 6 lo= 20% V(KLR), TXD from hi to lo 1 µs 6.5 8.9 µs 404 558 µs µs 885 ms ms 649.9 ms Watchdog C01 tl(NRES) Reset Pulse Width lo at NRES triggered by watchdog C02 Tu(TWD) Lower TWD Period for Reset 27 C03 To(TWD) Upper TWD Period for Reset 480 652 27 C04 tp(TWD) Permissible Pulse Width at TWD TWD detection at lo pulse 770 18 iC-JJ POWER MANAGEMENT IC Rev A1, Page 11/17 ELECTRICAL CHARACTERISTICS Operating conditions: +VBAT= 6..16.5V, PGND= GND, COS= 680pF, RSET= 10kS, RKL= 511S, RKLR= 511S, Tj= -40..125EC, unless otherwise noted Item Symbol Parameter Conditions Tj EC Fig. Unit Min. Typ. Max. Watchdog (continued) C05 tt(TWD) Permissible Spurious Pulse Width no TWD detection at lo pulse at TWD C06 Ilk(HD) Leakage Current in HD C07 Vs(HD)lo Saturation Voltage lo at Output HD V(HD)= 0V..VA1, NRHD= lo -10 I()= 1.6mA, output lo 6.5 µs 10 µA 0.5 V 200mA Low-side Driver D01 Vs(NFL) Saturation Voltage at NFL I(NFL)= 100mA, TFL= hi, NFL= lo, T < Tab 1 V D02 Vs(NFL) Saturation Voltage at NFL I(NFL)= 200mA, TFL= hi, NFL= lo, T < Tab 2 V 500 mA mA 500 mA mA 2.25 2.75 V 0.25 1 mA D03 Isc(NFL) Short-circuit Current in NFL D04 Isc(NFL) Short-circuit Current in NFL D05 Vt(NFL) V(NFL) < 18V, TFL= hi, NFL= lo, T < Tab 27 300 V(NFL) < 18V, T < Tab, no supply voltage 27 300 Threshold Voltage at NFL D06 Ipd(NFL) Pull-down Current in NFL V(NFL)= 2..16.5V,TFL= lo, NFL= hi D07 Vs(NFL) Saturation Voltage at NFL I(NFL)= 100mA, T < Tab, without supply voltage 3.5 V D08 Vs(NFL) Saturation Voltage at NFL I(NFL)= 200mA, T < Tab, without supply voltage 4 V D09 Vf(NFL) Free-wheeling Voltage at NFL I(NFL)= 10mA, TFL= lo, NFL= hi 48 V D10 Vf(NFL) Free-wheeling Voltage at NFL I(NFL)= 200mA, TFL= lo, NFL= hi 48 V Autarky G01 Il(VA) Charging Current from VA1 to VA V(VA)= 0..V(VA1)- 2V -33 27 G02 Vs(VA) Saturation Voltage at VA I(VA)= -2mA, V(VA1) - V(VA) G03 Vs(VB) Saturation Voltage VB referred to VA Vs()= V(VA)- V(VB); I(VB)= -500..0mA, LSA= on G04 Ilk(VB) Leakage Current in VB V(VA) > V(VB), LSA= off G05 Iilk(VB) Inverse Leakage Current in VB V(VB)- V(VA)= 0..5V, LSA= off G06 V(VVA) Output Voltage at VVA related to V(VA) I(VVA)= -10..10µA, V(VVA)= 0.6V..VREF- 0.1V G07 Isc(VVA) Short-circuit Current in VVA G08 VAmini G09 Vvalo Lower Turn-off Threshold of Converter G10 Vvahi Upper Turn-off Threshold of Converter G11 Vhys Hysteresis Turn-off Threshold G12 VAminx Minimal Discharge Voltage at VA external VA1-voltage divider at Test-Discharging by NVTA G13 Imax (VA,VB) Maximal Current Load at VA during Autarky mA mA 0.2 V 3 V -100 µA 12 27 V(VVA)= 0V..VREF Minimal Discharge Voltage at internal VA1-voltage divider, VA1x VA at Test-Discharging by NVTA against GND -27 -30 40 mA 13 % % 10 mA 22 V 12.5 -1 20 27 21 5.5 Vhys= Vvahi- Vvalo VA1 < 30.6V, CVB < 120µF, RVB > 9.5 V 0.2 66 27 7 V 1 V 76 %VA1 %VA1 200 mA 71 iC-JJ POWER MANAGEMENT IC Rev A1, Page 12/17 ELECTRICAL CHARACTERISTICS Operating conditions: +VBAT= 6..16.5V, PGND= GND, COS= 680pF, RSET= 10kS, RKL= 511S, RKLR= 511S, Tj= -40..125EC, unless otherwise noted Item Symbol Parameter Conditions Tj EC Fig. Unit Min. Typ. Max. 30mA Low-side Driver H01 Vs(NCRD) Saturation Voltage at NCRD I(NCRD)= 10mA, TCRD= hi, T < Tab 0.5 V H02 Vs(NCRD) Saturation Voltage at NCRD I(NCRD)= 30mA, TCRD= hi, T < Tab 1.5 V H03 IscNCRD Short-circuit Current in NCRD V(NCRD) < 18V, TCRD= hi, T < Tab 200 mA mA 25 100 µA 2.25 2.75 V H04 IpdNCRD Pull-down Current in NCRD 27 V(NCRD)= 2..16.5V, TCRD= lo H05 Vt(NCRD) Switching Threshold at NCRD 65 H06 Vf(NCRD) Free-wheeling Voltage at NCRD I(NCRD)= 10mA, TCRD= lo, NCRD= hi H07 tlh(NCRD) Rise Time at NCRD R(KLR/NCRD)= 1k, V(NCRD) from lo= 10% 6 hi= 90% V(KL, KLR) 10 µs H08 thl(NCRD) Fall Time at NCRD R(KLR/NCRD)= 1k, CNCRD < 50nF, V(NCRD) from lo= 90% 6 hi= 10%, V(KL, KLR) 20 µs H09 tf(NCRD) Requested Turn-on Duration at NCRD TCRD= hi, T > Tab, Vs(NCRD) > 2.75V 31.2 µs 2 V 55 % 66 %VCC %VCC 300 mV 48 V 16.2 50mA High-side Driver I01 Vs(CRA) Saturation Voltage hi at CRA against VB Vs()= V(VB)- V(CRA), I(CRA)= -50mA, V(KL, KLR)= 6..16.5V, TCRA= hi, T < Tab I02 Vt(CRA) Switching Threshold at CRA related to Maximum V(KL, KLR) V(KL, KLR)= 6..16.5V, TCRA= lo I03 Vt(CRA) Switching Threshold at CRA during Autarky V(KL, KLR) < 5.5V 45 54 27 60 I04 VhysCRA Hysteresis at CRA V(KL, KLR)= 6..16.5V or autarky 50 I05 Vf(CRA) I(CRA)= 10mA, TCRA= lo, VB open 48 I06 Ipu(CRA) Pull-up Current in CRA V(CRA) < VB- 2V, TCRA= lo I07 Isc(CRA) Short-circuit Current in CRA V(CRA) < 18V, TCRA= hi, T < Tab Free-wheeling Voltage at CRA I08 Ir(CRA) Inverse Current in CRA V(CRA) > V(B), TCRA= lo I09 tf(CRA) Requested Turn-on Duration at CRA TCRA= hi, Vs(CRA) > 2V, T > Tab Oscillator Frequency COS= 680pF ±5%, VA1 > 4.2V V -100 -25 -200 27 mA mA -100 16.2 µA 50 mA 31.2 µs 149.5 kHz kHz Oscillator J01 fos 110.5 27 130 iC-JJ POWER MANAGEMENT IC Rev A1, Page 13/17 ELECTRICAL CHARACTERISTICS Operating conditions: +VBAT= 6..16.5V, PGND= GND, COS= 680pF, RSET= 10kS, RKL= 511S, RKLR= 511S, Tj= -40..125EC, unless otherwise noted Item Symbol Parameter Conditions Tj EC Fig. Unit Min. Typ. Max. Autarky Detection P01 Ri() Input Resistance at VM, VMR 100 kS kS V V 50 27 220 Lower Undervoltage Threshold at RKL= RKLR= 511S ±1% KL, KLR 27 9 Upper Undervoltage Threshold at RKL= RKLR= 511S ±1% KL, KLR 27 10 Hysteresis Undervoltage Detection Vhys= Vvtuhi- Vvtulo 27 P05 Vautlo Lower Autarky Threshold at KL, KLR RKL= RKLR= 511S ±1% P06 Vauthi Upper Autarky Threshold at KL, KLR RKL= RKLR= 511S ±1% P07 Vhys Hysteresis Autarky Detection Vhys= Vauthi- Vautlo P08 V(VM, VMR) P09 tt(VM, VMR) P02 Vvtulo P03 Vvtuhi P04 Vhys 8.75 0.8 10.3 V V 1.2 V V 1 5.5 V 6 V 300 mV Permissible Voltage at KL, KLR 48 V Permissible Spurious Pulse Width no undervoltage detection, at VM, VMR no autarky detection 6.5 µs 80 iC-JJ POWER MANAGEMENT IC Rev A1, Page 14/17 DESCRIPTION OF FUNCTIONS BOOST CONVERTER If VA1x is connected to ground, a voltage of 30V becomes available at VA1. An external voltage divider can be used to adjust voltages at VA1 from VBAT+2V to +48V. In this case the band gap voltage of 2.44V is present VA1 R1 VA1x R2 Figure 1: Adjustment V(VA1) at VA1x. The voltage at VA1 can be calculated via VA1= 2.44V ( (R1+R2)/R2). AUTARKY / LOW VOLTAGE DETECTION To create a system with a redundant voltage supply, measurement inputs VM and VMR are connected to KL15 and KL15R respectively via a 511S resistor. If both supply inputs are used they need to be connected with 511S to VBAT. If only one of the two inputs (VM or VMR) is used the unused inputs must be connected to GND. The system is checked for low voltage and autarky via the internal voltage dividers (at 100kS each). The voltage dividers are shut off in standby mode. The outputs of the two comparators for low voltage and autarky are ANDgated, meaning that a message at VTU or NVTA delayed by one clock pulse (8us) is only generated when the relevant voltage thresholds are undershot at both measurement inputs. A reset of the outputs VTU and/or NVTA via the microcontroller with a rising edge at VTU is only possible if low voltage or autarky is no longer detected. AUTARKY CIRCUIT / MEASUREMENT OF AUTARKY CAPACITANCE The switch between VA and VB is closed for at least 5 clock cycles after autarky has been detected. With this, the voltage of the autarky capacitor is connected to the input of the VA1 up converter; a stable VA1 voltage can thus be maintained during autarky. At the same time the 30mA current source, which supplies current for charging the autarky capacitor, is switched off. The voltage of the autarky capacitor can be measured at output VVA (V(VVA)= 1/8 V(VA). This serves to check whether the capacitor is charged to a suitably high voltage to sustain the system during autarky. The capacitance of the capacitor can be determined while the capacitor is being charged. The system’s energy consumption can be determined during autarky. Autarky can be simulated using NVTA as an input. If V(VA) > 21V, then the switch between VA and VB can be closed via a rising edge at NVTA. The 30mA current source is then shut down and the autarky capacitor is discharged to the level of the threshold voltage (V(VA)= 21V). This is automatically followed by the switch being opened and the current source switched on again. A second falling edge at NVTA will stop discharging the capacitor if V (VA) >21V. iC-JJ POWER MANAGEMENT IC Rev A1, Page 15/17 WATCHDOG If the watchdog is not activated within the stipulated period (500µs..800ms), a reset is triggered via NRES. The watchdog counter restarts with each falling edge at TWD. Reset pulses from the microcontroller or V(VCC) or V(VREF) not included in the specifications also reset the watchdog counter. NRHD and HD activate external hardware in conjunction with the watchdog. NRDH: CMOS input with a pull-up resistor to activate output HD. HD: after 128 correct watchdog cycles and when pin NRHD = high, the open-drain transistor is activated (HD = low). Via NRHD = low, a reset (NRES) or false operation of the watchdog, the output is switched to tristate and can only become low again when 128 correct watchdog cycles have again occurred. RESET If V(VCC) or V(VREF) are not within specifications range or if the watchdog is operated incorrectly a reset is triggered via the open-drain output NRES. The microcontroller can also trigger a reset externally, thus resetting the watchdog and switching the indicator lamp on via NFL. VFP REGULATOR The VFP regulator provides the microcontroller with 12V programming supply voltage. When TFP= high, output VFP is activated; otherwise this output is switched to tristate. STANDBY Via input ENA a sleep mode can be set; current consumption is reduced to a minimum of 30µA approximately. K-Interface The K-Interface uses two pins that can be connected with the serial interface of the microcontroller. TXD is used to send data via the interface. If TXD is switched from high to low then K switches from V (VM) to low. RXD switches to low if V(RXD) < V (VM)/2 (in Autarky mode RXD < 3V). If TXD is open then RXD will reflect the external voltage at K. TEMPERATURE MONITORING The K interface, indicator lamp output and NAKS output are shut off in the event of excessive temperature. The two driver outputs can be forcibly switched on with excessive temperature for a short period if they are the cause of this excessive temperature. If the level falls below that of the shutdown temperature (hysteresis) the drivers can be switched on again. OSCILLATOR The oscillator provides an internal frequency of ca. 125kHz for the switching converters, watchdog counter and autarky control. iC-JJ POWER MANAGEMENT IC Rev A1, Page 16/17 30mA LOW-SIDE DRIVER (NCRD) The low-side driver is switched on by the microcontroller via TCRD = high. A comparator at output PCRD signals the state of the digital crash output to the microcontroller. TCRD PCRD State of the Driver Output NCRD low low Output off low high Short circuit to ground or broken wire high low Short circuit to KL15, KL15R high high Output on 50mA HIGH-SIDE DRIVER (CRA) The high-side driver is switched on by the microcontroller via TCRA = high. A comparator at output PCRA signals the state of the analog crash output to the microcontroller. TCRA PCRA State of the Driver Output CRA low low Output off low high Short circuit vs. VBAT or broken wire high low Short circuit to ground high high Output on 200mA LOW-SIDE DRIVER (NFL) The low-side driver which is switched on by the microcontroller via TFL = high. It is also switched on by a flip-flop which mirrors the reset state. This flip-flop can be reset via a falling edge at TFL after the reset has ended. A comparator at output PFL signals the state of the indicator lamp output to the microcontroller. The driver is normally on when no supply voltage is available at the iC. TFL PFL State of the Driver Output low low Output off, lamp off low high Short circuit to ground or broken wire high low Short circuit to KL15, KL15R high high Output on, lamp on iC-JJ POWER MANAGEMENT IC Rev A1, Page 17/17 30mA LOW-SIDE DRIVER (NAKS) The NAKS output is a low-side driver which is switched on by the microcontroller via TAKS= high. A comparator at output PAKS signals the state of the NAKS output to the microcontroller. TAKS PAKS State of NAKS Output low low Output off, lamp off low high Short circuit to ground or broken wire high low Short circuit vs. VBAT high high Output on ORDERING INFORMATION Type Package Order designation iC-JJ MQFP44 iC-JJ MQFP44 For information about prices, terms of delivery, options for other case types ec., please contact: iC-Haus GmbH Am Kuemmerling 18 D-55294 Bodenheim Germany Tel. +49-6135-9292-0 Fax +49-6135-9292-192 http://www.ichaus.com This specification is for a newly developed product. iC-Haus therefore reserves the right to modify data without further notice. Please contact us to ascertain the current data. The data specified is intended solely for the purpose of product description and is not to be deemed guaranteed in a legal sense. Any claims for damage against us - regardless of the legal basis - are excluded unless we are guilty of premeditation or gross negligence. We do not assume any guarantee that the specified circuits or procedures are free of copyrights of third parties. Copying - even as an excerpt - is only permitted with the approval of the publisher and precise reference to source.