ICS84325 Integrated Circuit Systems, Inc. CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS84325 is a Crystal-to-3.3V LVPECL Frequency Synthesizer with Fanout Buffer and a HiPerClockS™ member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The output frequency can be programmed using frequency select pins. The low phase noise characteristics of the ICS84325 make it an ideal clock source for Fibre Channel 1, Fibre Channel 2, Infiniband and Gigabit Ethernet applications. • 6 differential 3.3V LVPECL outputs ICS • Crystal oscillator interface • Output frequency range: 106.25MHz to 250MHz • Crystal input frequency: 25MHz and 25.5MHz • Output skew: 60ps (maximum) • RMS phase jitter at 212.5MHz, using a 25.5MHz crystal (637KHz to 10MHz): 2.76ps • Phase noise: Typical at 212.5MHz Offset Noise Power 100Hz ................. -92 dBc/Hz 1KHz ................. -112 dBc/Hz 10KHz ................. -120 dBc/Hz 100KHz ................. -122 dBc/Hz • 3.3V supply voltage • 0°C to 70°C ambient operating temperature • Lead-Free package available. FUNCTION TABLE Inputs XTAL • Industrial temperature information available upon request Output Frequency MR F_SEL1 F_SEL0 F_OUT 1 X X LOW 0 0 0 25.5MHz 106.25MHz 0 0 1 25.5MHz 212.5MHz 0 1 0 25MHz 125MHz 0 1 1 25MHz 250MHz BLOCK DIAGRAM PIN ASSIGNMENT XTAL1 0 OSC Output Divider XTAL2 1 PLL 6 Q0:Q5 6 nQ0:nQ5 / / Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Feedback Divider 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCCO F_SEL0 F_SEL1 MR XTAL1 XTAL2 VEE VCCA VCC PLL_SEL VEE VCCO ICS84325 24-Lead, 300-MIL SOIC 7.5mm x 15.33mm x 2.3mm body package M Package Top View F_SEL1 84325EM MR PLL_SEL F_SEL0 www.icst.com/products/hiperclocks.html 1 REV. B OCTOBER 11, 2004 ICS84325 Integrated Circuit Systems, Inc. CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 Q0, nQ0 Type Description Output Differential output pair. LVPECL interface levels. 3, 4 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 5, 6 Q2, nQ2 Output Differential output pair. LVPECL interface levels. 7, 8 Q3, nQ3 Output Differential output pair. LVPECL interface levels. 9, 10 Q4, nQ4 Output Differential output pair. LVPECL interface levels. 11, 12 Q5, nQ5 Output Differential output pair. LVPECL interface levels. 13, 24 VCCO Power Output supply pins. 16 VCC Power Core supply pin. 14, 18 VEE 15 PLL_SEL Input 17 VCCA Power Analog supply pin. 19, 20 XTAL2, XTAL1 Input Cr ystal oscillator interface. XTAL1 is the input. XTAL2 is the output. Negative supply pins. Pullup Selects between the PLL and cr ystal inputs as the input to the dividers. When HIGH, selects PLL. When LOW, selects XTAL1, XTAL2. LVCMOS / LVTTL interface levels. 21 MR Input Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs Pulldown nQx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. 22 F_SEL1 Input Pulldown Feedback frequency select pin. LVCMOS / LVTTL interface levels. 23 F_SEL0 Input Pullup Output select pin. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ 84325EM Test Conditions www.icst.com/products/hiperclocks.html 2 Minimum Typical Maximum Units REV. B OCTOBER 11, 2004 ICS84325 Integrated Circuit Systems, Inc. CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 50°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V I EE Power Supply Current 210 mA ICCA Analog Supply Current 27 mA Maximum Units 2 VCC + 0.3 V -0.3 0.8 V TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical PLL_SEL, MR, F_SEL0, F_SEL1 PLL_SEL, MR, F_SEL0, F_SEL1 MR, F_SEL1 VCC = VIN = 3.465V 150 µA PLL_SEL, F_SEL0 VCC = VIN = 3.465V 5 µA MR, F_SEL1 VCC = 3.465V, VIN = 0V -5 µA PLL_SEL, F_SEL0 VCC = 3.465V, VIN = 0V -150 µA TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCCO - 1.4 Typical VCCO - 0.8 V VOL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.2 V NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. 84325EM www.icst.com/products/hiperclocks.html 3 REV. B OCTOBER 11, 2004 Integrated Circuit Systems, Inc. ICS84325 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental 25.5 MHz Equivalent Series Resistance (ESR) Frequency 25 50 Ω Shunt Capacitance 7 pF TABLE 5. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter FOUT Output Frequency tsk(o) Output Skew; NOTE 1, 2 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical 106.25 20% to 80% 300 Units 250 MHz 60 ps 800 ps fOUT = 106.25MHz 48 52 % fOUT = 125MHz 46 54 % fOUT = 212.5MHz 43 57 % fOUT = 250MHz 40 60 % 1 ms tLOCK PLL Lock Time See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VCCO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. 84325EM Maximum www.icst.com/products/hiperclocks.html 4 REV. B OCTOBER 11, 2004 ICS84325 Integrated Circuit Systems, Inc. CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER TYPICAL PHASE NOISE ➚ Fibre Channel 1 0 -10 -20 Bandpass Filter Z (dBc H ) PHASE NOISE -30 -40 -50 Jitter BW -60 Source -70 -80 Mode Jitter Filter Process Result Noise only Freq. carrier 106.250M Hz Start Freq. -90 -100 -110 -120 -130 10.000 Raw phase noise data -140 -150 Diff. Jitter Stop Freq. Jitter 40.000M Hz 2.62 ps ➚ ➚ Phase noise result by adding Bandpass Filter to raw data -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) ➚ Fibre Channel 2 0 -10 Bandpass Filter -20 -30 ( ) dBc HZ PHASE NOISE -40 -50 Jitter BW -60 Source -70 Mode -80 -90 -100 Jitter Filter Process Result Noise only Freq. carrier 212.500M Hz Start Freq. Stop Freq. 10.000 Raw phase noise data -110 -120 -130 -140 -150 -160 -170 -180 -190 Diff. Jitter 40.000M Hz Jitter 2.76 ps ➚ ➚ Phase noise result by adding Bandpass Filter to raw data 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 84325EM www.icst.com/products/hiperclocks.html 5 REV. B OCTOBER 11, 2004 ICS84325 Integrated Circuit Systems, Inc. CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 2V VCC, VCCA Qx SCOPE nQx Qx LVPECL nQy nQx VEE Qy t sk(o) -1.3V ± 0.165V OUTPUT SKEW 3.3V OUTPUT LOAD AC TEST CIRCUIT nQ0:nQ5 80% Q0:Q5 80% Pulse Width t odc = Clock Outputs PERIOD 20% 20% tR tF t PW t PERIOD OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 84325EM www.icst.com/products/hiperclocks.html 6 REV. B OCTOBER 11, 2004 ICS84325 Integrated Circuit Systems, Inc. CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS84325 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 24Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01µF 24Ω V CCA .01µF 10 µF FIGURE 2. POWER SUPPLY FILTERING TERMINATION FOR LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 3A. LVPECL OUTPUT TERMINATION 84325EM 125Ω 84Ω FIGURE 3B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 7 REV. B OCTOBER 11, 2004 ICS84325 Integrated Circuit Systems, Inc. CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER CRYSTAL INPUT INTERFACE were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. The ICS84325 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 3 below were determined using a 25MHz, 18pF parallel resonant crystal and XTAL2 C1 22p X1 18pF Parallel Cry stal XTAL1 C2 22p Figure 4. CRYSTAL INPUt INTERFACE SCHEMATIC EXAMPLE Figure 5A shows a schematic example of using an ICS84325. In this example, the input is a 25MHz parallel resonant crystal with load capacitor CL=18pF. The frequency fine tuning capacitors C1 and C2 are 22pF respectively. This example also shows logic control input handling. The configuration is set at F_SEL[1:0]=11 therefore the output frequency is 250MHz. It is recommended to have one decouple capacitor per power pin. Each decoupling capacitor should be located as close as possible to the power pin. The low pass filter R7, C11 and C16 for clean analog supply should also be located as close to the VCCA pin as possible. VCC R4 1K VCC R7 24 VCCA 22p C11 0.1u C1 C16 10u X1 25MHz,18pF F_SEL1 R5 F_SEL0 1K C2 VCC U7 VCC Zo = 50 13 14 15 16 17 18 19 20 21 22 23 24 VCC VEE PLL_SEL VCC VCCA VEE XTAL2 XTAL1 MR F_SEL1 F_SEL0 VCC nQ5 Q5 nQ4 Q4 nQ3 Q3 nQ2 Q2 nQ1 Q1 nQ0 Q0 12 11 10 9 8 7 6 5 4 3 2 1 - Zo = 50 + R1 50 R2 50 R3 50 22p ICS84325 RU2 1K RU3 1K VCC=3.3V F_SEL1 F_SEL0 RD2 SP RD3 SP (U1,13) VCC (U1,16) C6 0.1u e.g. F_SEL[1:0]=11 (U1,24) C5 0.1u C3 0.1u SP = Spare, Not Installed FIGURE 5A. ICS84325 SCHEMATIC EXAMPLE 84325EM www.icst.com/products/hiperclocks.html 8 REV. B OCTOBER 11, 2004 ICS84325 Integrated Circuit Systems, Inc. CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER The following component footprints are used in this layout example: • The differential 100Ω output traces should have the same length. All the resistors and capacitors are size 0603. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. POWER AND GROUNDING Place the decoupling capacitors C3, C5 and C6, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. • Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible. • Make sure no other signal traces are routed between the clock trace pair. CLOCK TRACES • The matching termination resistors should be located as close to the receiver input pins as possible. AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. CRYSTAL The crystal X1 should be located as close as possible to the pins 20 (XTAL1) and 19 (XTAL2). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. C6 GND VCC C1 C5 Signals R7 VCCA C16 VIA C11 X1 C2 C3 U1 ICS84325 FIGURE 5B. PCB BOARD LAYOUT 84325EM Pin1 FOR ICS84325 www.icst.com/products/hiperclocks.html 9 50 Ohm Traces REV. B OCTOBER 11, 2004 ICS84325 Integrated Circuit Systems, Inc. CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS84325. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS84325 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 210mA = 727.7mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 6 * 30.2mW = 181mW Total Power_MAX (3.465V, with all outputs switching) = 727.7mW + 181mW = 908.7mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.909W * 43°C/W = 113.9°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 24-PIN SOIC, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 50°C/W 43°C/W 38°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 84325EM www.icst.com/products/hiperclocks.html 10 REV. B OCTOBER 11, 2004 ICS84325 Integrated Circuit Systems, Inc. CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 6. LVPECL DRIVER CIRCUIT TERMINATION AND To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, VOUT = V OH_MAX (V CCO_MAX • -V OH_MAX OL_MAX CCO_MAX -V CCO_MAX – 1.0V ) = 1.0V For logic low, VOUT = V (V =V =V CCO_MAX – 1.7V ) = 1.7V OL_MAX Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CCO_MAX - 2V))/R ] * (V CCO_MAX L -V OH_MAX ) = [(2V - (V CCO_MAX -V OH_MAX ))/R ] * (V CCO_MAX L -V )= OH_MAX [(2V - 1V)/50Ω) * 1V = 20.0mW Pd_L = [(V OL_MAX – (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX ))/R ] * (V L CCO_MAX -V )= OL_MAX [(2V - 1.7V)/50Ω) * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW 84325EM www.icst.com/products/hiperclocks.html 11 REV. B OCTOBER 11, 2004 ICS84325 Integrated Circuit Systems, Inc. CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD SOIC θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 50°C/W 43°C/W 500 38°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS84325 is: 3500 84325EM www.icst.com/products/hiperclocks.html 12 REV. B OCTOBER 11, 2004 ICS84325 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - M SUFFIX CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER FOR 24 LEAD SOIC TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum Maximum N A 24 -- 2.65 A1 0.10 -- A2 2.05 2.55 B 0.33 0.51 C 0.18 0.32 D 15.20 15.85 E 7.40 e H 7.60 1.27 BASIC 10.00 10.65 h 0.25 0.75 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-013, MO-119 84325EM www.icst.com/products/hiperclocks.html 13 REV. B OCTOBER 11, 2004 ICS84325 Integrated Circuit Systems, Inc. CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS84325EM ICS84325EM 24 Lead SOIC 30 per tube 0°C to 70°C ICS84325EMT ICS84325EM 24 Lead SOIC on Tape and Reel 1000 0°C to 70°C ICS84325EMLN ICS84325EMLN 30 per tube 0°C to 70°C ICS84325EMLNT ICS84325EMLN 24 Lead "Lead-Free" SOIC 24 Lead "Lead-Free" SOIC on Tape and Reel 1000 0°C to 70°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 84325EM www.icst.com/products/hiperclocks.html 14 REV. B OCTOBER 11, 2004 Integrated Circuit Systems, Inc. ICS84325 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER REVISION HISTORY SHEET Rev Table T3 Page 3 B T9 84325EM 14 Description of Change LVPECL DC Characteristics Table Changed VOH max. from VCCO - 1.0V to VCCO - 0.8V. Changed VSWING max. from 1.0V to 1.2V. Corrected Units. Ordering Information Table - added Lead-Free par t number. www.icst.com/products/hiperclocks.html 15 Date 10/1/03 10/11/04 REV. B OCTOBER 11, 2004