ICS8531-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8531-01 is a low skew, high performance 1-to-9 Differential-to-3.3V LVPECL Fanout Buffer HiPerClockS™ and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8531-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. • 9 differential 3.3V LVPECL outputs Guaranteed output skew and part-to-part skew characteristics make the ICS8531-01 ideal for high performance workstation and server applications. • Output skew: 50ps (maximum) ,&6 • Selectable CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL • Maximum output frequency up to 500MHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to 3.3V LVPECL levels with resistor bias on nCLK input • Part-to-part skew: 250ps (maximum) • Propagation delay: 2ns (maximum) • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT VCCO nQ2 Q2 1 nQ1 CLK_SEL 0 Q1 CLK nCLK PCLK nPCLK nQ0 Q LE Q0 VCCO D CLK_EN 32 31 30 29 28 27 26 25 Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 VCC 1 24 VCCO CLK 2 23 Q3 nCLK 3 22 nQ3 CLK_SEL 4 21 Q4 PCLK 5 20 nQ4 nPCLK 6 19 Q5 VEE 7 18 nQ5 CLK_EN 8 17 VCCO ICS8531-01 9 10 11 12 13 14 15 16 Vcco Q6 nQ6 Q7 nQ7 Q8 Q5 nQ5 nQ8 Vcco Q4 nQ4 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View Q6 nQ6 Q7 nQ7 Q8 nQ8 8531AY-01 www.icst.com/products/hiperclocks.html 1 REV. B AUGUST 9, 2001 ICS8531-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 VCC Power Type Description 2 CLK Input Pulldown 3 nCLK Input Pullup 4 CLK_SEL Input Pulldown 5 PCLK Input Pulldown 6 nPCLK Input Pullup 7 VEE Power 8 CLK_EN Input Positive supply pin. Connect to 3.3V. Pullup Non-inver ting differential clock input. Inver ting differential clock input. Clock Select input. When HIGH, selects PCLK, nPCLK inputs. When LOW, selects CLK, nCLK. LVTTL / LVCMOS interface levels. Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. Negative supply pin. Connect to ground. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVTTL / LVCMOS interface levels. 9, 16, 17, 24, 25, 32 10, 11 VCCO Power Output supply pins. Connect to 3.3V. nQ8, Q8 Output Differential output pair. LVPECL interface level. 12, 13 nQ7, Q7 Output Differential output pair. LVPECL interface level. 14, 15 nQ6, Q6 Output Differential output pair. LVPECL interface level. 18, 19 nQ5, Q5 Output Differential output pair. LVPECL interface level. 20, 21 nQ4, Q4 Output Differential output pair. LVPECL interface level. 22, 23 nQ3 Q3 Output Differential output pair. LVPECL interface level. 26, 27 nQ2, Q2 Output Differential output pair. LVPECL interface level. 28, 29 nQ1, Q1 Output Differential output pair. LVPECL interface level. 30, 31 nQ0, Q0 Output Differential output pair. LVPECL interface level. NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical CLK, nCLK, PCLK, nPLCK CLK_EN, CLK_SEL Maximum Units 4 pF CIN Input Capacitance RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ 8531AY-01 4 www.icst.com/products/hiperclocks.html 2 pF REV. B AUGUST 9, 2001 ICS8531-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs Outputs CLK_EN CLK_SEL Selected Sourced Q0 thru Q8 nQ0 thru nQ8 0 0 CLK, nCLK Disabled; LOW Disabled; HIGH 0 1 PCLK, nPCLK Disabled; LOW Disabled; HIGH 1 0 CLK, nCLK Enabled Enabled 1 1 PCLK, nPCLK Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described in Table 3B. Enabled Disabled nCLK, nPCLK CLK, PCLK CLK_EN nQ0 - nQ8 Q0 - Q8 FIGURE 1: CLK_EN TIMING DIAGRAM TABLE 3B. CLOCK INPUTS FUNCTION TABLE Inputs CLK or PCLK Outputs nCLK or nPCLK Q0 thru Q8 nQ0 thru nQ8 Input to Output Mode Polarity 0 1 LOW HIGH Differential to Differential Non Inver ting 1 0 HIGH LOW Differential to Differential Non Inver ting 0 Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inver ting 1 Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inver ting Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inver ting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information section on page 8, Figure 9, which discusses wiring the differential input to accept single ended levels. 8531AY-01 www.icst.com/products/hiperclocks.html 3 REV. B AUGUST 9, 2001 ICS8531-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCCx 4.6V Inputs, VI Outputs, VO Package Thermal Impedance, θ JA Storage Temperature, TSTG -0.5V to VCC + 0.5V -0.5V to VCCO + 0.5V 47.9°C/W -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC VCCO Positive Supply Voltage 3.135 3.3 3.465 V Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 50 70 mA Typical TABLE 4B. LVCMOS DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH CLK_EN, CLK_SEL VIL CLK_EN, CLK_SEL IIH Input High Current IIL Input Low Current Test Conditions Minimum Maximum Units 2 3.765 V -0.3 0.8 V CLK_EN VCC = VIN = 3.465V 5 µA CLK_SEL VCC = VIN = 3.465V 150 µA CLK_EN VIN = 0V, VCC = 3.465V -150 µA CLK_SEL VIN = 0V, VCC = 3.465V -5 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current IIL Input Low Current Test Conditions CLK Minimum Typical VCC = VIN = 3.465V Units 150 µA nCLK VCC = VIN = 3.465V CLK VIN = 0V, VCC = 3.465V -5 5 µA nCLK VIN = 0V, VCC = 3.465V -150 µA VPP Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR VEE + 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK and nCLK is VCC + 0.3V. NOTE 2: Common mode input voltage is defined as VIH. 8531AY-01 Maximum www.icst.com/products/hiperclocks.html 4 µA 1.3 V VCC - 0.85 V REV. B AUGUST 9, 2001 ICS8531-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current Test Conditions PCLK Typical VCC = VIN = 3.465V Maximum Units 150 µA nPCLK VCC = VIN = 3.465V PCLK VIN = 0V, VCC = 3.465V -5 µA nPCLK VIN = 0V, VCC = 3.465V -150 µA IIL Input Low Current V PP VOH Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 Output High Voltage; NOTE 3 VOL Output Low Voltage; NOTE 3 VCMR Minimum 5 µA 0.3 1 V VEE + 1.5 VCC V VCCO - 1.4 VCCO - 1.0 V VCCO - 2.0 VCCO - 1.7 V 0.85 V Maximum Units 500 MHz 2 ns 50 ps VSWING Peak-to-Peak Output Voltage Swing 0.6 NOTE 1: Common mode input voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VCC + 0.3V. NOTE 3: Outputs terminated with 50Ω to VCCO - 2V. TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum ƒ≤ 250MHz 1 Typical fMAX Maximum Output Frequency tPD Propagation Delay; NOTE 1 t sk(o) Output Skew; NOTE 2, 4 t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 250 ps tR Output Rise Time 20% to 80% @ 50MHz 300 700 ps tF Output Fall Time 20% to 80% @ 50MHz 300 700 ps 52 % odc Output Duty Cycle 48 50 All parameters measured at 250MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 8531AY-01 www.icst.com/products/hiperclocks.html 5 REV. B AUGUST 9, 2001 ICS8531-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION VCCO V CC SCOPE Qx LVPECL VCC = 2.0V VCCO = 2.0V nQx VEE = -1.3V ± 0.135V FIGURE 2 - OUTPUT LOAD TEST CIRCUIT VCC CLK, PCLK V PP Cross Points V CMR nCLK, nPCLK VEE FIGURE 3 - DIFFERENTIAL INPUT LEVEL Qx nQx Qy nQy tsk(o) FIGURE 4 - OUTPUT SKEW 8531AY-01 www.icst.com/products/hiperclocks.html 6 REV. B AUGUST 9, 2001 ICS8531-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Qx PART 1 nQx Qy PART 2 nQy tsk(pp) FIGURE 5 - PART-TO-PART SKEW 80% 80% V 20% SWING 20% Clock Inputs and Outputs t t R FIGURE 6 - INPUT AND OUTPUT RISE AND F FALL TIME CLK, PCLK nCLK, nPCLK Q0 - Q8 nQ0 - nQ8 t PD FIGURE 7 - PROPAGATION DELAY CLK, PCLK, Qx nCLK, nPCLK, nQx Pulse Width t t odc = t PERIOD PW PERIOD FIGURE 8 - odc & tPERIOD 8531AY-01 www.icst.com/products/hiperclocks.html 7 REV. B AUGUST 9, 2001 ICS8531-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 9 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC VCC CLK_IN R1 1K R1 1K + CLK_IN V_REF + - V_REF C1 0.1uF C1 0.1uF R2 1K R2 1K FIGURE 9: SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 8531AY-01 www.icst.com/products/hiperclocks.html 8 REV. B AUGUST 9, 2001 ICS8531-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8531-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8531-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 70mA = 242.6mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 9 * 30.2mW = 271.8mW Total Power_MAX (3.465V, with all outputs switching) = 242.6mW + 271.8mW = 514.4mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.514W * 42.1°C/W = 91.6°C. This is well below the limit of 125°C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). Table 6. Thermal Resistance qJA for 32-pin LQFP Forced Convection qJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W 200 500 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8531AY-01 www.icst.com/products/hiperclocks.html 9 REV. B AUGUST 9, 2001 ICS8531-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 10. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 10 - LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX - 2V))/R ] * (VCC_MAX - VOH_MAX) L Pd_L = [(V OL_MAX • – (V CC_MAX - 2V))/R ] * (V CC_MAX L For logic high, VOUT = V OH_MAX -V OL_MAX =V ) – 1.0V CC_MAX Using VCC_MAX = 3.465, this results in VOH_MAX = 2.465V • For logic low, VOUT = V OL_MAX Using V CC_MAX =V CC_MAX – 1.7V = 3.465, this results in V OL_MAX = 1.765V Pd_H = [(2.465V - (3.465V - 2V))/50Ω] * (3.465V - 2.465V) = 20mW Pd_L = [(1.765V - (3.465V - 2V))/50Ω] * (3.465V - 1.765V) = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW 8531AY-01 www.icst.com/products/hiperclocks.html 10 REV. B AUGUST 9, 2001 ICS8531-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE q by Velocity (Linear Feet per Minute) JA 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W 200 55.9°C/W 42.1°C/W 500 50.1°C/W 39.4°C/W NOTE: Most all modern PCB designs use multi-layered boards, so the data in the second row will pertain to most designs. TRANSISTOR COUNT The transistor count for ICS8531-01 is: 632 8531AY-01 www.icst.com/products/hiperclocks.html 11 REV. B AUGUST 9, 2001 ICS8531-01 Integrated Circuit Systems, Inc. PACKAGE OUTLINE AND LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER DIMENSIONS - Y SUFFIX TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. 0.80 BASIC e L 0.45 0.60 0.75 q 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 8531AY-01 www.icst.com/products/hiperclocks.html 12 REV. B AUGUST 9, 2001 ICS8531-01 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Count ICS8531AY-01 ICS8531AY-01 32 Lead LQFP 250 per tray Temperature 0°C to 70°C ICS8531AY-01T ICS8531AY-01 32 Lead LQFP on Tape and Reel 1000 0°C to 70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8531AY-01 www.icst.com/products/hiperclocks.html 13 REV. B AUGUST 9, 2001