NEC UPD178P018AGC-3B9

PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD178P018A
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µ PD178P018ANote is a device in which the internal mask ROM of the µ PD178018A is replaced with a onetime PROM or EPROM.
Because this device can be programmed by users, it is ideally suited for system evaluation, small-lot and multipledevice production, and early development and time-to-market.
The µ PD178P018A is a PROM version corresponding to the µPD178004A, 178006A, and 178016A.
Note
Caution
Under development
The µ PD178P018AKK-T does not maintain planned reliability when used in your system’s massproduced products. Please use only experimentally or for evaluation purposes during trial manufacture.
For more information on functions, refer to the following User’s Manuals. Be sure to read them when
designing.
µ PD178018A Subseries User’s Manual: To be prepared
78K/0 Series User’s Manual Instruction: U12326E
FEATURES
• Pin-compatible with mask ROM version (except for VPP pin)
• Internal PROM: 60 Kbytes
• µPD178P018AGC : One-time programmable (ideally suited for small-lot production)
• µPD178P018AKK-T : Reprogrammable (ideally suited for system evaluation)
• Internal high-speed RAM: 1 024 bytes
• Internal expansion RAM: 2 048 bytes
• Buffer RAM: 32 bytes
• Can be operated in the same power supply voltage as the mask ROM version
(During PLL operation: VDD = 4.5 to 5.5 V)
The electrical specifications (power supply current, etc.) and PLL analog specifications of the µPD178P018A differ
from that of mask ROM versions. So, these differences should be considered and verified before application sets
are mass-produced.
In this document, the term PROM is used in parts common to one-time PROM versions and EPROM versions.
The information in this document is subject to change without notice.
Document No. U12642EJ1V0DS00 (1st Edition)
Date Published July 1997 N
Printed in Japan
©
1997
µ PD178P018A
APPLICATIONS
Car stereo, home stereo systems
ORDERING INFORMATION
Part Number
µPD178P018AGC-3B9 Note
µPD178P018AKK-T Note
Note
Package
Internal ROM
80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch)
80-pin ceramic WQFN (14 × 14 mm, 0.65-mm pitch)
One-Time PROM
EPROM
Quality Grade
Standard
Not applicable
Under planning
Please refer to the Quality grade on NEC Semiconductor Devices (Document number C11531E) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
µ PD178018A SUBSERIES AND µPD178003 SUBSERIES EXPANSION
µ PD178018A Subseries
80 pins
µ PD178P018A Note
80 pins
PROM : 60 KB
RAM : 3 KB
µ PD178018A
ROM : 60 KB
RAM : 3 KB
80 pins
µPD178016A
ROM : 48 KB
RAM : 3 KB
80 pins
µ PD178006A
ROM : 48 KB
RAM : 1 KB
80 pins
µ PD178004A
ROM : 32 KB
RAM : 1 KB
80 pins
µ PD178003 Note
ROM : 24 KB
RAM : 0.5 KB
80 pins
µPD178002 Note
ROM : 16 KB
RAM : 0.5 KB
µ PD178003 Subseries
Note
2
Under development
µ PD178P018A
FUNCTION DESCRIPTION
(1/2)
Item
Internal memory
Function
• PROM
: 60 Kbytes
• RAM
High-speed RAM
: 1 024 bytes
Expansion RAM
: 2 048 bytes
Buffer RAM
: 32 bytes
General register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Instruction cycle
With variable instruction execution time function
0.44 µ s/0.88 µs/1.78 µs/3.56 µ s/7.11 µs/14.22 µs (with 4.5-MHz crystal resonator)
Instruction set
•
•
•
•
I/O port
Total
:
• CMOS input
:
• CMOS I/O
:
• N-ch open-drain I/O
:
• N-ch open-drain output :
A/D converter
8-bit resolution × 6 channels
Serial interface
• 3-wire/SBI/2-wire/I2 C bus Note mode selectable
: 1 channel
• 3-wire serial I/O mode
(with automatic transmit/receive function of up to 32 bytes) : 1 channel
Timer
•
•
•
•
Buzzer (BEEP) output
1.5 kHz, 3 kHz, 6 kHz
Vectored
interrupt
source
Maskable
Internal: 8, external: 7
Non-maskable
Internal: 1
Software
Internal: 1
Test input
Note
16-bit operation
Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
Bit manipulate (set, reset, test, Boolean operation)
BCD Adjust, etc.
62
1
54
4
3
pins
pin
pins
pins
pins
Basic timer (timer carry FF (10 Hz))
:
8-bit timer/event counter
:
8-bit timer (D/A converter: PWM output) :
Watchdog timer
:
1
2
1
1
channel
channels
channel
channel
Internal: 1
When using the I2 C bus mode (including when this mode is implemented by program without using the
peripheral hardware), consult your local NEC sales representative when you place an order for mask.
3
µ PD178P018A
(2/2)
Item
PLL frequency
synthesizer
Function
Division mode
Two types
• Direct division mode (VCOL pin)
• Pulse swallow mode (VCOH and VCOL pins)
Reference frequency
7 types selectable by program (1, 3, 5, 9, 10, 25, 50 kHz)
Charge pump
Error out output: 2 (EO0 and EO1 pins Note 1)
Phase comparator
Unlock detectable by program
Frequency counter
• Frequency measurement
• AMIFC pin: for 450-kHz count
• FMIFC pin: for 450-kHz/10.7-MHz count
D/A converter (PWM output)
8-/9-bit resolution × 3 channels (shared by 8-bit timer)
Standby function
• HALT mode
• STOP mode
Reset
• Reset via the RESET pin
• Internal reset by watchdog timer
• Reset by power-ON clear circuit (3-value detection)
• Detection of less than 4.5 V Note 2 (CPU clock: fX)
• Detection of less than 3.5 V Note 2 (CPU clock: fX/2 or less and on power application)
• Detection of less than 2.5 V Note 2 (in STOP mode)
Power supply voltage
• VDD = 4.5 to 5.5 V (with PLL operating)
• VDD = 3.5 to 5.5 V (with CPU operating, CPU clock: fX/2 or less)
• VDD = 4.5 to 5.5 V (with CPU operating, CPU clock: fX)
Package
• 80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch)
• 80-pin ceramic WQFN (14 × 14 mm, 0.65-mm pitch)
Notes 1. The EO1 pin can be set to high impedance for the µ PD178P018A.
The following figure shows an application example.
µ PD178P018A
EO0
LPF
VCO
To Mixer
EO1
VCOH
VCOL
LPF : Low path filter
VCO : Voltage controlled oscillator
• To lock to a target frequency at high speed
Setting the EO0 and EO1 pins to error out output improves the output current potential and LPF
voltage control potential.
• Normal state
Setting only the EO0 pin to error out output maintains the LPF stable.
2. These voltage values are maximum values. Reset is actually executed at a voltage lower than these
values.
4
µ PD178P018A
PIN CONFIGURATIONS (TOP VIEW)
(1) Normal operating mode
• 80-PIN PLASTIC QFP (14 × 14 mm, 0.65-mm pitch)
µPD178P018AGC-3B9 Note
• 80-PIN CERAMIC WQFN (14 × 14 mm, 0.65-mm pitch)
P120
P121
P122
P123
P124
P125
P00/INTP0
P01/INTP1
P02/INTP2
P03/INTP3
P04/INTP4
P05/INTP5
P06/INTP6
REGCPU
GND
X2
X1
REGOSC
VDD
RESET
µPD178P018AKK-T Note
8
53
P30
P22/SCK1
9
52
P67
P23/STB
10
51
P66
P24/BUSY
11
50
P65
P25/SI0/SB0/SDA0
12
49
P64
P26/SO0/SB1/SDA1
13
48
P63
P27/SCK0/SCL
14
47
P62
P132/PWM0
15
46
P61
P133/PWM1
16
45
P60
P134/PWM2
17
44
P57
P40
18
43
P56
P41
19
42
P55
P42
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P54
Note
P53
P31
P21/SO1
P52
54
P51
7
P50
P32
P20/SI1
VPP
55
EO1
6
EO0
P33/TI1
P15/ANI5
GNDPLL
56
VCOL
5
VCOH
P34/TI2
P14/ANI4
VDDPLL
P13/ANI3
57
FMIFC
P35
4
AMIFC
58
P47
3
P46
P36/BEEP
P12/ANI2
P45
59
P44
2
P43
P37
P11/ANI1
VDDPORT
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
GNDPORT
P10/ANI0
Under development
Cautions 1.
2.
3.
4.
Connect
Connect
Connect
Connect
the V PP pin to GND directly.
the V DD PORT and VDD PLL pins to VDD.
the GNDPORT and GNDPLL pins to GND.
each of the REGOSC and REGCPU pins to GND via a 0.1- µ F capacitor.
5
µ PD178P018A
AMIFC
ANI0 to ANI5
BEEP
BUSY
EO0, EO1
FMIFC
GND
GNDPLL
GNDPORT
INTP0 to INTP6
P00 to P06
P10 to P15
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P120 to P125
P132 to P134
6
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
AM Intermediate Frequency Counter Input
A/D Converter Input
Buzzer Output
Busy Output
Error Out Output
FM Intermediate Frequency Counter Input
Ground
PLL Ground
Port Ground
Interrupt Inputs
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 12
Port 13
PWM0 to PWM2
REGCPU
REGOSC
RESET
SB0, SB1
SCK0, SCK1
SCL
SDA0, SDA1
SI0, SI1
SO0, SO1
STB
TI1, TI2
VCOL, VCOH
VDD
VDDPLL
VDDPORT
VPP
X1, X2
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
PWM Output
Regulator for CPU Power Supply
Regulator for Oscillator
Reset Input
Serial Data Bus Input/Output
Serial Clock Input/Output
Serial Clock Input/Output
Serial Data Input/Output
Serial Data Input
Serial Data Output
Strobe Output
Timer Clock Input
Local Oscillation Input
Power Supply
PLL Power Supply
Port Power Supply
Programming Power Supply
Crystal Resonator Connection
µ PD178P018A
(2) PROM programming mode
• 80-PIN PLASTIC QFP (14 × 14 mm)
µPD178P018AGC-3B9 Note
• 80-PIN CERAMIC WQFN
(L)
PGM
(L)
A9
(L)
RESET
VDD
VDD
(L)
Open
GND
VDD
µPD178P018AKK-T Note
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
(L)
Open
A0
A1
A2
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
D7
D6
D5
D4
D3
D2
D1
D0
(L)
CE
OE
(L)
A15
A14
A13
A12
Note
VPP
A8
A16
A10
A11
Open
GND
(L)
VDD
(L)
GND
VDD
A3
A4
A5
A6
A7
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Under planning
Cautions 1.
2.
3.
4.
A0 to A16
CE
D0 to D7
(L)
:
GND :
RESET :
Open :
Individually connect to GND via a pull-down resistor.
Connect to GND.
Set to the low level.
Leave open.
: Address Bus
: Chip Enable
: Data Bus
GND
OE
PGM
: Ground
: Output Enable
: Program
RESET : Reset
VDD
: Power Supply
VPP
: Programming Power Supply
7
µ PD178P018A
BLOCK DIAGRAM
TI1/P33
8-bit TIMER/
EVENT COUNTER 1
PORT 0
TI2/P34
8-bit TIMER/
EVENT COUNTER 2
8-bit TIMER3
WATCHDOG TIMER
BASIC TIMER
SI0/SB0/SDA0/P25
SO0/SB1/SDA1/P26
SCK0/SCL/P27
SERIAL
INTERFACE 0
SI1/P20
SO1/P21
SCK1/P22
STB/P23
BUSY/P24
ANI0/P10 to
ANI5/P15
INTP0/P00 to
INTP6/P06
BEEP/P36
RESET
X1
X2
VDDPORT
GNDPORT
VDD
REGOSC
REGCPU
GND
8
78K/0
CPU
CORE
SERIAL
INTERFACE 1
RAM
(3 072 bytes)
6
7
P00
6
P01 to P06
PORT 1
6
P10 to P15
PORT 2
8
P20 to P27
PORT 3
8
P30 to P37
PORT 4
8
P40 to P47
PORT 5
8
P50 to P57
PORT 6
8
P60 to P67
PORT 12
6
P120 to P125
PORT 13
3
P132 to P134
D/A CONVERTER
(PWM)
3
PWM0/P132 to
PWM2/P134
PROM
(60 Kbytes)
A/D CONVERTER
INTERRUPT
CONTROL
BUZZER OUTPUT
FREQUENCY
COUNTER
AMIFC
FMIFC
PLL
EO0
EO1
VCOL
VCOH
RESET
SYSTEM
CONTROL
CPU
PERIPHERAL
PLL
VOLTAGE
REGULATOR
VOLTAGE
REGULATOR
VOSC
VCPU
VDDPLL
GNDPLL
VPP
µ PD178P018A
CONTENTS
1. PIN FUNCTION LIST ..........................................................................................................................
1.1 Pins in Normal Operating Mode ...............................................................................................
1.2 Pins in PROM Programming Mode ...........................................................................................
1.3 Pins Input/Output Circuits and Recommended Connection of Unused Pins ......................
10
10
12
13
2. PROM PROGRAMMING ....................................................................................................................
2.1 Operating Modes ........................................................................................................................
2.2 PROM Write Procedure .............................................................................................................
2.3 PROM Read Procedure ..............................................................................................................
16
16
18
22
3. PROGRAM ERASURE (µPD178P018AKK-T ONLY) ..................................................................... 23
4. OPAQUE FILM ON ERASURE WINDOW (µPD178P018AKK-T ONLY) ..................................... 23
5. ONE-TIME PROM VERSION SCREENING .................................................................................... 23
6. ELECTRICAL SPECIFICATIONS (PRELIMINARY) .......................................................................... 24
7. PACKAGE DRAWINGS ..................................................................................................................... 46
APPENDIX A. DIFFERENCES BETWEEN µPD178018A AND µPD178018 SUBSERIES ................... 48
APPENDIX B. DEVELOPMENT TOOLS ................................................................................................ 49
APPENDIX C. RELATED DOCUMENTS ................................................................................................ 53
9
µ PD178P018A
1. PIN FUNCTION LIST
1.1 Pins in Normal Operating Mode
(1) Port pins
Pin Name
P00
I/O
Input
P01 to P06 I/O
P10 to P15 I/O
P20
I/O
Function
Port 0.
7-bit input/output port.
Input only
After Reset Alternate Function
Input
Input/output mode can be specified bit-wise. Input
INTP1 to INTP6
Port 1.
6-bit input/output port.
Input/output mode can be specified bit-wise.
Input
ANI0 to ANI5
Port 2.
Input
SI1
8-bit input/output port.
Input/output mode can be specified bit-wise.
P21
INTP0
SO1
P22
SCK1
P23
STB
P24
BUSY
P25
SI0/SB0/SDA0
P26
SO0/SB1/SDA1
P27
SCK0/SCL
P30 to P32 I/O
Port 3.
P33
8-bit input/output port.
Input/output mode can be specified bit-wise.
Input
—
TI1
P34
TI2
P35
—
P36
BEEP
P37
—
P40 to P47 I/O
Port 4.
8-bit input/output port.
Input/output mode can be specified in 8-bit units.
Test input flag (KRIF) is set to 1 by falling edge detection.
Input
—
P50 to P57 I/O
Port 5.
8-bit input/output port.
Input/output mode can be specified bit-wise.
Input
—
P60 to P63 I/O
Port 6.
8-bit input/output port.
Input/output mode can be
specified bit-wise.
Input
—
Input
—
P64 to P67
Middle voltage N-ch open-drain
input/output port.
LEDs can be driven directly.
P120 to
P125
I/O
Port 12.
6-bit input/output port.
Input/output mode can be specified bit-wise.
P132 to
P134
Output
Port 13.
3-bit output port.
N-ch open-drain output port.
10
—
PWM0 to
PWM2
µ PD178P018A
(2) Non-port pins (1 of 2)
Pin Name
I/O
Function
After Reset Alternate Function
INTP0 to
INTP6
Input
External maskable interrupt inputs with specifiable valid edges (rising
edge, falling edge, both rising and falling edges).
Input
P00 to P06
SI0
Input
Serial interface serial data input
Input
P25/SB0/SDA0
SI1
P20
SO0
Output
Serial interface serial data output
Input
SO1
P26/SB1/SDA1
P21
SB0
I/O
Serial interface serial data input/output
Input
P25/SI0/SDA0
SB1
P26/SO0/SDA1
SDA0
P25/SI0/SB0
SDA1
P26/SO0/SB1
SCK0
I/O
Serial interface serial clock input/output
Input
P27/SCL
SCK1
P22
SCL
P27/SCK0
STB
Output
Serial interface automatic transmit/receive strobe output
Input
P23
BUSY
Input
Serial interface automatic transmit busy input
Input
P24
TI1
Input
External count clock input to 8-bit timer (TM1)
Input
P33
TI2
External count clock input to 8-bit timer (TM2)
BEEP
Buzzer output
Input
P36
ANI0 to ANI5 Input
A/D converter analog input
Input
P10 to P15
PWM0 to
PWM2
Output
PWM output
—
P132 to P134
EO0, EO1
Output
Error out output from charge pump of the PLL frequency synthesizer
—
—
VCOL
Input
Inputs PLL local band oscillation frequency (In HF, MF mode).
—
—
VCOH
Input
Inputs PLL local band oscillation frequency (In VHF mode).
—
—
AMIFC
Input
Inputs AM intermediate frequency counter.
—
—
FMIFC
Input
Inputs FM intermediate frequency counter.
—
—
RESET
Input
System reset input
—
—
X1
Input
Crystal resonator connection for system clock oscillation
—
—
X2
—
—
—
REGOSC
—
Regulator for oscillator. Connected to GND via a 0.1-µF capacitor.
—
—
REGCPU
—
Regulator for CPU power supply. Connected to GND via a 0.1-µF capacitor.
—
—
VDD
—
Positive power supply
—
—
GND
—
Ground
—
—
VDDPORT
—
Positive power supply for port block
—
—
GNDPORT
—
Ground for port block
—
—
V DDPLL Note
—
Positive power supply for PLL
—
—
GNDPLL Note
—
Ground for PLL
—
—
Note
Output
P34
Connect a capacitor of approximately 1 000 pF between VDDPLL pin and GNDPLL pin.
11
µ PD178P018A
(2) Non-port pins (2/2)
Pin Name
I/O
VPP
—
Function
After Reset Alternate Function
High-voltage applied during program write/verification.
—
—
Connected directly to GND in normal operating mode.
1.2 Pins in PROM Programming Mode
Pin Name
I/O
Function
RESET
Input
PROM programming mode setting
When +5 V or +12.5 V is applied to VPP pin and a low-level signal is applied to the RESET pin, this
chip is set in the PROM programming mode.
VPP
Input
PROM programming mode setting and high-voltage applied during program write/verification.
A0 to A16
Input
Address bus
D0 to D7
I/O
Data bus
CE
Input
PROM enable input/program pulse input
OE
Input
Read strobe input to PROM
PGM
Input
Program/program inhibit input in PROM programming mode.
VDD
—
Positive power supply
GND
—
Ground potential
12
µ PD178P018A
1.3 Pins Input/Output Circuits and Recommended Connection of Unused Pins
Table 1-1 shows the input/output circuit types of pins and the recommended conditions for unused pins.
Refer to Figure 1-1 for the configuration of the input/output circuit of each type.
Table 1-1. Type of I/O Circuit of Each Pin
Pin Name
I/O Circuit Type
I/O
Recommended Connections of Unused Pins
P00/INTP0
2
Input
Connected to GND or GNDPORT
P01/INTP1 to P06/INTP6
8
I/O
P10/ANI0 to P15/ANI5
11-A
Set in general-purpose input port mode by software and
individually connected to VDD, VDDPORT, GND, or GNDPORT
via a resistor.
P20/SI1
8
P21/SO1
5
P22/SCK1
8
P23/STB
5
P24/BUSY
8
P25/SI0/SB0/SDA0
P26/SO0/SB1/SDA1
P27/SCK0/SCL
10
P30 to P32
5
P33/TI1, P34/TI2
8
P35
P36/BEEP
P37
5
P40 to P47
5-G
P50 to P57
5
P60 to P63
13-D
P64 to P67
5
Output
Set to the low-level output by software and open
P120 to P125
P132/PWM0 to P134/PWM2
19
EO0
DTS-EO1
EO1
DTS-EO3
VCOL, VCOH
DTS-AMP
Input
—
—
Open
Set to disabled status by software and open
AMIFC, FMIFC
VPP
Connected to GND or GNDPORT directly
13
µ PD178P018A
Figure 1-1. Types of Pin Input/Output Circuits (1/2)
Type 2
Type 8
VDD
data
P-ch
IN/OUT
IN
output
disable
N-ch
Schmitt-Triggered Input with Hysteresis Characteristics
Type 5
Type 10
VDD
VDD
data
data
P-ch
P-ch
IN/OUT
output
disable
IN/OUT
open-drain
output disable
N-ch
N-ch
input
enable
Type 5-G
Type 11-A
VDD
VDD
data
data
P-ch
IN/OUT
IN/OUT
output
disable
P-ch
N-ch
output
disable
comparator
N-ch
P-ch
+
–
N-ch
VREF (Threshold voltage)
input
enable
Remark All VDD and GND in the above figures are the positive power supply and ground potential of the ports,
and should be read as V DDPORT and GNDPORT, respectively.
14
µ PD178P018A
Figure 1-1. Types of Pin Input/Output Circuits (2/2)
Type 13-D
Type DTS-EO3
IN/OUT
VDDPLL
data
output disable
N-ch
DW
P-ch
VDD
OUT
RD
UP
P-ch
N-ch
GNDPLL
Middle-Voltage Input Buffer
Type 19
Type DTS-AMP
VDDPLL
OUT
N-ch
IN
Type DTS-EO1
VDDPLL
DW
P-ch
OUT
UP
N-ch
GNDPLL
Remark All VDD and GND in the above figures are the positive power supply and ground potential of the ports,
and should be read as VDD PORT and GNDPORT, respectively.
15
µ PD178P018A
2. PROM PROGRAMMING
The µ PD178P018A has an internal 60-Kbyte PROM as a program memory. For programming, set the PROM
programming mode with the V PP and RESET pins. For the connection of unused pins, refer to “PIN CONFIGURATIONS (TOP VIEW) (2) PROM programming mode.”
Caution Programs must be written in addresses 0000H to EFFFH (the last address EFFFH must be
specified). They cannot be written by a PROM writer which cannot specify the write address.
2.1 Operating Modes
When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, the PROM
programming mode is set. This mode will become the operating mode as shown in Table 2-1 when the CE, OE, and
PGM pins are set as shown.
Further, when the read mode is set, it is possible to read the contents of the PROM.
Table 2-1. Operating Modes of PROM Programming
Pin
RESET
VPP
VDD
CE
OE
PGM
+12.5 V
+6.5 V
H
L
H
D0 to D7
Operating Mode
Page data latch
L
Data input
Page write
H
H
L
High-impedance
Byte write
L
H
L
Data input
Program verify
L
L
H
Data output
Program inhibit
×
H
H
High-impedance
×
L
L
L
L
H
Data output
Output disable
L
H
×
High-impedance
Standby
H
×
×
High-impedance
Read
Remark × : L or H
16
+5 V
+5 V
µ PD178P018A
(1) Read mode
Read mode is set if CE = L and OE = L are set.
(2) Output disable mode
Data output becomes high-impedance, and is in the output disable mode, if OE = H is set.
Therefore, it allows data to be read from any device by controlling the OE pin, if multiple µ PD178P018As are
connected to the data bus.
(3) Standby mode
Standby mode is set if CE = H is set.
In this mode, data outputs become high-impedance irrespective of the OE status.
(4) Page data latch mode
Page data latch mode is set if CE = H, PGM = H, and OE = L are set at the beginning of page write mode.
In this mode, 1 page 4-byte data is latched in an internal address/data latch circuit.
(5) Page write mode
After 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed
by applying a 0.1-ms program pulse (active low) to the PGM pin with CE = H and OE = H. Then, program
verification can be performed, if CE = L and OE = L are set.
If programming is not performed by a one-time program pulse, X times (X ≤ 10) write and verification operations
should be executed repeatedly.
(6) Byte write mode
Byte write is executed when a 0.1-ms program pulse (active low) is applied to the PGM pin with CE = L and OE
= H. Then, program verification can be performed if OE = L is set.
If programming is not performed by a one-time program pulse, X times (X ≤ 10) write and verification operations
should be executed repeatedly.
(7) Program verify mode
Program verify mode is set if CE = L, PGM = H, and OE = L are set.
In this mode, check if a write operation is performed correctly after the write.
(8) Program inhibit mode
Program inhibit mode is used when the OE pin, VPP pin, and D0 to D7 pins of multiple µ PD178P018As are
connected in parallel and a write is performed to one of those devices.
When a write operation is performed, the page write mode or byte write mode described above is used. At this
time, a write is not performed to a device which has the PGM pin driven high.
17
µ PD178P018A
2.2 PROM Write Procedure
Figure 2-1. Page Program Mode Flow Chart
Start
Address = G
VDD = 6.5 V, VPP = 12.5 V
X=0
Latch
Address = Address + 1
Latch
Address = Address + 1
Latch
Address = Address + 1
Address = Address + 1
Latch
X=X+1
No
X = 10?
0.1-ms Program Pulse
Verify
4 bytes
Yes
Fail
Pass
No
Address = N?
Yes
VDD = 4.5 to 5.5 V, VPP = VDD
Pass
Verify
All Bytes
Fail
All Pass
Write End
Remark G = Start address
N = Program last address
18
Defective Product
µ PD178P018A
Figure 2-2. Page Program Mode Timing
Page Data Latch
Page Program
Program Verify
A2 to A16
A0, A1
D0 to D7
Data Input
Data Output
VPP
VPP
VDD
VDD + 1.5
VDD
VDD
VIH
CE
VIL
VIH
PGM
VIL
VIH
OE
VIL
19
µ PD178P018A
Figure 2-3. Byte Program Mode Flow Chart
Start
Address = G
VDD = 6.5 V, VPP = 12.5 V
X=0
X=X+1
No
X = 10?
0.1-ms Program Pulse
Address = Address + 1
Vefity
Yes
Fail
Pass
No
Address = N?
Yes
VDD = 4.5 to 5.5 V, VPP = VDD
Pass
Verify
All Bytes
Fail
All Pass
Write End
Remark G = Start address
N = Program last address
20
Defective Product
µ PD178P018A
Figure 2-4. Byte Program Mode Timing
Program
Program Verify
A0 to A16
D0 to D7
Data Input
Data Output
VPP
VPP
VDD
VDD + 1.5
VDD
VDD
VIH
CE
VIL
VIH
PGM
VIL
VIH
OE
VIL
Cautions 1.
2.
3.
VDD should be applied before VPP , and removed after VPP.
VPP must not exceed +13.5 V including overshoot.
Reliability may be adversely affected if removal/reinsertion is performed while +12.5 V is being
applied to VPP.
21
µ PD178P018A
2.3 PROM Read Procedure
The contents of PROM are readable to the external data bus (D0 to D7) according to the read procedure shown
below.
(1) Fix the RESET pin at low level, supply +5 V to the VPP pin, and connect all other unused pins as shown in
“PIN CONFIGURATIONS (TOP VIEW) (2) PROM programming mode”.
(2) Supply +5 V to the VDD and V PP pins.
(3) Input address of read data into the A0 to A16 pins.
(4) Read mode
(5) Output data to D0 to D7 pins.
The timings of the above steps (2) to (5) are shown in Figure 2-5.
Figure 2-5. PROM Read Timings
A0 to A16
Address Input
CE (Input)
OE (Input)
D0 to D7
22
Hi-Z
Data Output
Hi-Z
µ PD178P018A
3. PROGRAM ERASURE (µPD178P018AKK-T ONLY)
The µPD178P018AKK-T is capable of erasing (FFH) the data written in a program memory and rewriting.
To erase the programmed data, expose the erasure window to light having a wavelength shorter than about 400
nm. Normally, irradiate ultraviolet rays of 254-nm wavelength. The amount of exposure required to completely erase
the programmed data is as follows:
• UV intensity x erasure time: 30 W•s/cm2 or more
• Erasure time: 40 min. or more (When a UV lamp of 12 000 µ W/cm 2 is used. However, a longer time may be
needed because of deterioration in performance of the UV lamp, soiled erasure window, etc.)
When erasing the contents of the data, set up the UV lamp within 2.5 cm from the erasure window. Further, if a
filter is provided for a UV lamp, irradiate the ultraviolet rays after removing the filter.
4. OPAQUE FILM ON ERASURE WINDOW (µPD178P018AKK-T ONLY)
To protect from an intentional erasure by rays other than that of the lamp for erasing EPROM contents, or to protect
internal circuit other than EPROM from misoperating by rays, cover the erasure window with an opaque film when
EPROM contents erasure is not performed.
5. ONE-TIME PROM VERSION SCREENING
The one-time PROM version (µPD178P018AGC-3B9) cannot be tested completely by NEC before it is shipped,
because of its structure. It is recommended to perform screening to verify PROM after writing necessary data and
performing high-temperature storage under the condition below.
Storage Temperature
Storage Time
125 °C
24 hours
23
µ PD178P018A
6. ELECTRICAL SPECIFICATIONS (PRELIMINARY)
Caution The following electrical specifications are preliminary values for this product. When designing,
be sure to refer to the data sheet describing the official electrical specifications.
µ PD178P018A Data Sheet: to be prepared
ABSOLUTE MAXIMUM RATINGS (T A = 25 °C)
Parameter
Symbol
Power supply voltage
Input voltage
Output voltage
Test Conditions
Ratings
Unit
VDD
–0.3 to +7.0
V
VPP
–0.3 to +13.5
V
–0.3 to VDD + 0.3
V
–0.3 to +16
V
–0.3 to +13.5
V
–0.3 to VDD + 0.3
V
VI1
Excluding P60 to P63
VI2
P60 to P63
N-ch open-drain
VI3
A9
PROM programming mode
VO
Output withstand
voltage
VBDS
P132 to P134
N-ch open-drain
16
V
Analog input voltage
VAN
P10 to P15
Analog input pin
–0.3 to VDD + 0.3
V
Output current high
I OH
1 pin
–10
mA
P01 to P06, P30 to P37, P56, P57, P60 to P67,
–15
mA
–15
mA
Peak value
15
mA
r.m.s. value
7.5
mA
TA
–40 to +85
°C
Tstg
–65 to +150
°C
P120 to P125 total
P10 to P15, P20 to P27, P40 to P47, P50 to P55,
P132 to P134 total
Output current low
Operating ambient
I OL Note
1 pin
temperature
Storage temperature
Note
r.m.s. (root mean square) value should be calculated as follows: [r.m.s value] = [Peak value] × √duty
Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single
parameter even momentarily. That is, the absolute maximum ratings are rated values at which
the product is on the verge of suffering physical damage, and therefore the product must be
used under conditions which ensure that the absolute maximum ratings are not exceeded.
Remark The characteristics of an alternate-function pin and a port pin are the same unless specified otherwise.
RECOMMENDED SUPPLY VOLTAGE RANGES (T A = –40 to +85 °C)
Parameter
Power supply voltage
Symbol
Test Conditions
TYP.
MAX.
Unit
VDD1
During CPU operation and PLL operation.
4.5
5.5
V
VDD2
While the CPU is operating and the PLL is stopped.
Cycle Time: TCY ≥ 0.89 µ s
3.5
5.5
V
VDD3
While the CPU is operating and the PLL is stopped.
Cycle Time: TCY = 0.44 µs
4.5
5.5
V
Remark T CY: Cycle Time (Minimum instruction execution time)
24
MIN.
µ PD178P018A
DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 3.5 to 5.5 V)
(1/3)
Parameter
Symbol
Input voltage high
VIH1
P10
P30
P40
P64
VIH2
P00 to P06, P20, P22,
P24 to P27, P33, P34,
RESET
VIH3
P60 to P63
(N-ch open-drain)
VIL1
P10
P30
P40
P64
VIL2
P00 to P06, P20, P22,
P24 to P27, P33, P34,
RESET
VIL3
P60 to P63
(N-ch open-drain)
Input voltage low
Output voltage high
Output voltage low
Test Conditions
to
to
to
to
to
to
to
to
P15,
P32,
P47,
P67,
P15,
P32,
P47,
P67,
P21, P23,
P35 to P37,
P50 to P57,
P120 to P125
VOL1
VOL2
TYP.
MAX.
Unit
0.7 VDD
VDD
V
0.85 VDD
VDD
V
0.7 VDD
15
V
0
0.3 VDD
V
0
0.15 VDD
V
4.5 V ≤ VDD ≤ 5.5 V
0
0.3 VDD
V
3.5 V ≤ VDD < 4.5 V
0
0.2 VDD
V
4.5 V ≤ VDD ≤ 5.5 V,
IOH = –1 mA
VDD – 1.0
V
3.5 V ≤ VDD < 4.5 V,
IOH = –100 µA
VDD – 0.5
V
P21, P23,
P35 to P37,
P50 to P57,
P120 to P125
VOH1
MIN.
P50 to P57, P60 to P63
VDD = 4.5 to 5.5 V,
IOH = 15 mA
P01 to P06, P10 to P15,
P20 to P27, P30 to P37,
P40 to P47, P64 to P67,
P120 to P125,
P132 to P134
VDD = 4.5 to 5.5 V,
IOL = 1.6 mA
SB0, SB1, SCK0
VDD = 4.5 to 5.5 V,
N-ch open-drain pulled-up
(R = 1 KΩ)
0.4
2.0
V
0.4
V
0.2 VDD
V
Remark The characteristics of an alternate-function pin and a port pin are the same unless specified otherwise.
25
µ PD178P018A
DC CHARACTERISTICS (TA = –40 to +85 °C, V DD = 3.5 to 5.5 V)
Parameter
Input leakage
current high
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
VIN = VDD
3
µA
VIN = 15 V
80
µA
VIN = 0 V
–3
µA
–3 Note
µA
I LIH1
P00 to P06,
P20 to P27,
P40 to P47,
P64 to P67,
RESET
I LIH2
P60 to P63
I LIL1
P00 to P06,
P20 to P27,
P40 to P47,
P64 to P67,
RESET
I LIL2
P60 to P63
Output leakage
current high
ILOH
P132 to P134
VOUT = 15 V
3
µA
Output leakage
current low
ILOL
P132 to P134
VOUT = 0 V
–3
µA
Output off leak
current
I LOF
EO0, EO1
VOUT = VDD,
VOUT = 0 V
±1
µA
Input leakage
current low
Note
P10 to P15,
P30 to P37,
P50 to P57,
P120 to P125,
(2/3)
P10 to P15,
P30 to P37,
P50 to P57,
P120 to P125,
When an input instruction is executed, the low-level input leakage current for P60 to P63 becomes –200
µ A (MAX.) only in one clock cycle (at no wait). It remains at –3 µ A (MAX.) for other than an input instruction.
Remark The characteristics of an alternate-function pin and a port pin are the same unless specified otherwise.
REFERENCE CHARACTERISTICS (TA = 25 °C, VDD = 5 V)
Parameter
Symbol
Output current high
IOH1
Test Conditions
EO0
IOL1
EO0
EO1 (EOCON0 = 0)
26
MIN.
VOUT = VDD – 1 V
EO1 (EOCON0 = 0)
Output current low
(1/2)
TYP.
–4
–1.8
VOUT = 1 V
Unit
mA
mA
6
3.5
MAX.
mA
mA
µ PD178P018A
DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 3.5 to 5.5 V)
Parameter
Power supply
Symbol
MAX.
Unit
2.5
15
mA
TCY = 0.89 µs
IDD2
fX = 4.5-MHz operation
TCY = 0.44 µs Note 3
VDD = 4.5 to 5.5 V
4.0
27
mA
IDD3
While the CPU is operating
and the PLL is stopped
HALT Mode.
TCY = 0.89 µs Note 2
1
4
mA
IDD4
Pin X1 sine wave
input VIN = VDD
fX = 4.5-MHz operation
TCY = 0.44 µs Note 3
VDD = 4.5 to 5.5 V
1.6
6
mA
When the crystal is oscillating
TCY = 0.44 µs
4.5
5.5
V
TCY = 0.89 µs
3.5
5.5
V
2.7
5.5
V
2
4
µA
2
30
µA
VDDR1
power supply
VDDR2
power supply current
TYP.
While the CPU is operating
and the PLL is stopped
Data hold
Data hold
MIN.
IDD1
current Note 1
voltage
Test Conditions
(3/3)
Note 2
VDDR3
When the crystal oscillation is stopped
When power off by Power On Clear is detected
I DDR1
While the crystal oscillation
I DDR2
is stopped
TA = 25 °C, V DD = 5 V
Notes 1. The port current is not included.
2. When the Processor Clock Control register (PCC) is set at 00H, and the Oscillation Mode Select
register (OSMS) is set to 00H.
3. When PCC is set to 00H and OSMS is set to 01H.
Remarks 1. TCY: Cycle Time (Minimum instruction execution time)
2. fX: System clock oscillation frequency.
REFERENCE CHARACTERISTICS (TA = 25 °C, VDD = 5 V)
Parameter
Power supply
current
Symbol
IDD5
(2/2)
Test Conditions
During CPU operation
and PLL operation.
TCY = 0.44 µs
MIN.
Note
TYP.
7
MAX.
Unit
mA
VCOH pin sine wave
input
fIN = 130 MHz,
VIN = 0.15 Vp-p
Note
When the Processor Clock Control register (PCC) is set to 00H, and the Oscillation Mode Select register
(OSMS) is set to 01H.
Remark TCY: Cycle Time (Minimum instruction execution time)
27
µ PD178P018A
AC CHARACTERISTICS
(1) BASIC OPERATION (TA = –40 to +85 °C, V DD = 3.5 to 5.5 V)
Parameter
Symbol
Cycle time
TCY
Test Conditions
f XX = fX/2
Note 1
MIN.
, f X = 4.5-MHz operation
TYP.
MAX.
Unit
0.89
14.22
µs
(Minimum instruction
f XX = f
,
4.5 ≤ V DD ≤ 5.5 V
0.44
7.11
µs
execution time)
f X = 4.5-MHz operation
3.5 ≤ V DD < 4.5 V
0.89
7.11
µs
4.5 ≤ VDD ≤ 5.5 V
0
4.5
MHz
3.5 V ≤ V DD < 4.5 V
0
275
kHz
TI1, TI2 input
fTI
frequency
X Note 2
TI1, TI2 input high/
tTIH ,
4.5 ≤ VDD ≤ 5.5 V
111
ns
low-level width
tTIL
3.5 V ≤ V DD < 4.5 V
1.8
µs
µs
sam Note 3
Interrupt input high/
TINTH,
INTP0
low-level width
TINTL
8/f
INTP1 to INTP6
RESET low-level
width
t RSL
10
µs
10
µs
Notes 1. When the Oscillation Mode Selection register (OSMS) is set to 00H.
2. When OSMS is set to 01H.
3. In combination with bits 0 (SCS0) and 1 (SCS1) of the Sampling Clock Select register (SCS),
selection of f sam is possible among fXX/2 N, f XX/32, fXX /64, and fXX/128 (when N = 0 to 4).
TCY vs V DD
T CY vs V DD
(when system clock fXX is operating at fX /2)
(when system clock fXX is operating at f X)
60
60
10
10
Cycle Time T CY [µ s]
Cycle Time T CY [µ s]
Remarks 1. f XX: System clock frequency (f X or fX/2)
2. f X: System clock oscillation frequency
Operation
Guaranteed
Range
2.0
1.0
0.5
0.4
0
2.0
1.0
0.5
0.4
1
2
3
4
5
Power Supply Voltage VDD [V]
28
Operation
Guaranteed
Range
6
0
1
2
3
4
5
Power Supply Voltage VDD [V]
6
µ PD178P018A
(2) SERIAL INTERFACE (T A = –40 to +85 °C, VDD = 3.5 to 5.5 V)
(a) Serial interface channel 0
(i) 3-wire serial I/O mode (SCK0 ... internal clock output)
Parameter
SCK0 cycle time
SCK0 high-/low-level width
SI0 setup time (to SCK0↑)
Symbol
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
3.5 V ≤ VDD < 4.5 V
1 600
ns
tKH1,
4.5 V ≤ VDD ≤ 5.5 V
tKCY1/2 – 50
ns
t KL1
3.5 V ≤ VDD < 4.5 V
tKCY1/2 – 100
ns
tSIK1
4.5 V ≤ VDD ≤ 5.5 V
100
ns
3.5 V ≤ VDD < 4.5 V
150
ns
400
ns
tKCY1
SI0 hold time (from SCK0↑)
tKSI1
SO0 output delay time from SCK0↓
t KSO1
Note
Test Conditions
C = 100 pF Note
300
ns
MAX.
Unit
C is the load capacitance of the SO0 output line.
(ii) 3-wire serial I/O mode (SCK0 ... external clock input)
Parameter
SCK0 cycle time
SCK0 high-/low-level width
Symbol
Test Conditions
MIN.
TYP.
4.5 V ≤ VDD ≤ 5.5 V
800
ns
3.5 V ≤ VDD < 4.5 V
1 600
ns
tKH2,
4.5 V ≤ VDD ≤ 5.5 V
400
ns
t KL2
3.5 V ≤ VDD < 4.5 V
800
ns
tKCY2
SI0 setup time (to SCK0↑)
tSIK2
100
ns
SI0 hold time (from SCK0↑)
tKSI2
400
ns
SO0 output delay time from SCK0↓
t KSO2
SCK0 rising or falling edge time
Note
C = 100 pF Note
t R2, tF2
300
ns
1 000
ns
C is the load capacitance of the SO0 output line.
29
µ PD178P018A
(iii) SBI mode (SCK0 ... internal clock output)
Parameter
SCK0 cycle time
SCK0 high-/low-level width
SB0, SB1 setup time (to SCK0↑)
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
3.5 V ≤ VDD < 4.5 V
3 200
ns
t KH3,
4.5 V ≤ VDD ≤ 5.5 V
tKCY3/2 – 50
ns
t KL3
3.5 V ≤ VDD < 4.5 V
tKCY3/2 – 150
ns
t SIK3
4.5 V ≤ VDD ≤ 5.5 V
100
ns
3.5 V ≤ VDD < 4.5 V
300
ns
t KCY3/2
ns
t KCY3
SB0, SB1 hold time (from SCK0↑)
t KSI3
SB0, SB1 output delay time from
tKSO3
SCK0↓
4.5 V ≤ VDD ≤ 5.5 V
0
250
ns
C = 100 pF Note 3.5 V ≤ VDD < 4.5 V
0
1 000
ns
R = 1 kΩ
SB0, SB1↓ from SCK0↑
t KSB
tKCY3
ns
SCK0↓ from SB0, SB1↓
t SBK
tKCY3
ns
SB0, SB1 high-level width
t SBH
tKCY3
ns
SB0, SB1 low-level width
tSBL
tKCY3
ns
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
(iv) SBI mode (SCK0 ... external clock input)
Parameter
SCK0 cycle time
SCK0 high-/low-level width
SB0, SB1 setup time (to SCK0↑)
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
3.5 V ≤ VDD < 4.5 V
3 200
ns
t KH4,
4.5 V ≤ VDD ≤ 5.5 V
400
ns
t KL4
3.5 V ≤ VDD < 4.5 V
1 600
ns
t SIK4
4.5 V ≤ VDD ≤ 5.5 V
100
ns
3.5 V ≤ VDD < 4.5 V
300
ns
tKCY4/2
ns
t KCY4
SB0, SB1 hold time (from SCK0↑)
t KSI4
SB0, SB1 output delay time from
tKSO4
SCK0↓
4.5 V ≤ VDD ≤ 5.5 V
0
300
ns
C = 100 pF Note 3.5 V ≤ VDD < 4.5 V
0
1 000
ns
R = 1 kΩ
SB0, SB1↓ from SCK0↑
t KSB
tKCY4
ns
SCK0↓ from SB0, SB1↓
t SBK
tKCY4
ns
SB0, SB1 high-level width
t SBH
tKCY4
ns
SB0, SB1 low-level width
tSBL
tKCY4
ns
SCK0 rising or falling edge time
Note
30
tR4, t F4
1 000
R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
ns
µ PD178P018A
(v) 2-wire serial I/O mode (SCK0 ... internal clock output)
Parameter
SCK0 cycle time
Symbol
tKCY5
SCK0 high-level width
t KH5
SCK0 low-level width
t KL5
SB0, SB1 setup time (to SCK0↑)
Test Conditions
R = 1 kΩ
C = 100 pF
Note
tSIK5
MIN.
MAX.
Unit
1 600
ns
tKCY5/2 – 160
ns
4.5 V ≤ VDD ≤ 5.5 V tKCY5/2 – 50
ns
3.5 V ≤ VDD < 4.5 V tKCY5/2 – 100
ns
4.5 V ≤ VDD ≤ 5.5 V
300
ns
3.5 V ≤ VDD < 4.5 V
350
ns
400
ns
ns
SB0, SB1 hold time (from SCK0↑)
tKSI5
600
SB0, SB1 output delay time from
SCK0↓
tKSO5
0
Note
TYP.
300
ns
R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines.
(vi) 2-wire serial I/O mode (SCK0 ... external clock input)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK0 cycle time
tKCY6
1 600
ns
SCK0 high-level width
t KH6
650
ns
SCK0 low-level width
t KL6
800
ns
SB0, SB1 setup time (to SCK0↑)
tSIK6
100
ns
SB0, SB1 hold time (from SCK0↑)
tKSI6
t KCY6/2
ns
SB0, SB1 output delay time from
tKSO6
SCK0↓
C = 100 pF
SCK0 at rising or falling edge time
Note
R = 1 kΩ
tR6, tF6
Note
4.5 V ≤ VDD ≤ 5.5 V
0
300
ns
3.5 V ≤ VDD < 4.5 V
0
500
ns
1 000
ns
R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
31
µ PD178P018A
(vii) I2C bus mode (SCL ... internal clock output)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
10
µs
tKCY7 – 160
ns
t KL7
t KCY7 – 50
ns
SDA0, SDA1 setup time (to SCL↑)
t SIK7
200
ns
SDA0, SDA1 hold time
(from SCL↓)
t KSI7
0
ns
SDA0, SDA1 output delay time
(from SCL↓)
tKSO7
SDA0, SDA1↓ from SCL↑ or
SDA0, SDA1↑ from SCL↑
t KSB
200
ns
SCL↓ from SDA0, SDA1↓
t SBK
400
ns
SDA0, SDA1 high-level width
t SBH
500
ns
SCL cycle time
t KCY7
R = 1 kΩ
SCL high-level width
t KH7
C = 100 pF Note
SCL low-level width
Note
4.5 V ≤ VDD ≤ 5.5 V
0
300
ns
3.5 V ≤ VDD < 4.5 V
0
500
ns
R and C are the load resistance and load capacitance of the SCL, SDA0, and SDA1 output lines.
(viii) I 2C bus mode (SCL ... external clock input)
Parameter
SCL cycle time
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
t KCY8
1 000
ns
t KH8, tKL8
400
ns
SDA0, SDA1 setup time (to SCL↑)
t SIK8
200
ns
SDA0, SDA1 hold time
(from SCL↓)
t KSI8
0
ns
SDA0, SDA1 output delay time
tKSO8
SCL high-/low-level width
from SCL↓
4.5 V ≤ VDD ≤ 5.5 V
0
300
ns
C = 100 pF Note 3.5 V ≤ VDD < 4.5 V
0
500
ns
R = 1 kΩ
SDA0, SDA1↓ from SCL↑ or
SDA0, SDA1↑ from SCL↑
t KSB
200
ns
SCL↓ from SDA0, SDA1↓
t SBK
400
ns
SDA0, SDA1 high-level width
t SBH
500
ns
SCL rising or falling edge time
tR8, t F8
Note
32
1 000
R and C are the load resistance and load capacitance of the SDA0 and SDA1 output lines.
ns
µ PD178P018A
(b) Serial interface channel 1
(i) 3-wire serial I/O mode (SCK1 ... internal clock output)
Parameter
SCK1 cycle time
SCK1 high-/low-level width
SI1 setup time (to SCK1↑)
SI1 hold time (from SCK1↑)
SO1 output delay time (from SCK1↓)
Note
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
3.5 V ≤ VDD < 4.5 V
1 600
ns
tKH9,
4.5 V ≤ VDD ≤ 5.5 V
tKCY9/2 – 50
ns
t KL9
3.5 V ≤ VDD < 4.5 V
tKCY9/2 – 100
ns
tSIK9
4.5 V ≤ VDD ≤ 5.5 V
100
ns
3.5 V ≤ VDD < 4.5 V
150
ns
400
ns
tKCY9
tKSI9
t KSO9
C = 100 pF
Note
300
ns
MAX.
Unit
C is the load capacitance of the SO1 output line.
(ii) 3-wire serial I/O mode (SCK1 ... external clock input)
Parameter
SCK1 cycle time
SCK1 high-/low-level width
Symbol
Test Conditions
MIN.
TYP.
4.5 V ≤ VDD ≤ 5.5 V
800
ns
3.5 V ≤ VDD < 4.5 V
1 600
ns
t KH10,
4.5 V ≤ VDD ≤ 5.5 V
400
ns
t KL10
3.5 V ≤ VDD < 4.5 V
800
ns
tKCY10
SI1 setup time (to SCK1↑)
t SIK10
100
ns
SI1 hold time (from SCK1↑)
t KSI10
400
ns
SO1 output delay time (from SCK1↓)
tKSO10
SCK1 rising or falling edge time
Note
C = 100 pF Note
tR10, tF10
300
ns
1 000
ns
C is the load capacitance of the SO1 output line.
33
µ PD178P018A
(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... internal clock
output)
Parameter
SCK1 cycle time
SCK1 high-/low-level width
SI1 setup time (to SCK1↑)
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
3.5 V ≤ VDD < 4.5 V
1 600
ns
t KH11 ,
4.5 V ≤ VDD ≤ 5.5 V
tKCY11/2 – 50
ns
t KL11
3.5 V ≤ VDD < 4.5 V
tKCY11/2 – 100
ns
t SIK11
4.5 V ≤ VDD ≤ 5.5 V
100
ns
3.5 V ≤ VDD < 4.5 V
150
ns
400
ns
t KCY11
SI1 hold time (from SCK1↑)
t KSI11
SO1 output delay time (from SCK1↓)
t KSO11
C = 100 pF Note
300
ns
STB↑ from SCK1↑
t SBD
tKCY11/2 – 100
tKCY11/2 + 100
ns
Strobe signal high-level width
tSBW
tKCY11 – 30
tKCY11 + 30
ns
Busy signal setup time
(to busy signal detection timing)
t BYS
100
ns
Busy signal hold time
t BYH
4.5 V ≤ VDD ≤ 5.5 V
100
ns
3.5 V ≤ VDD < 4.5 V
150
ns
(from busy signal detection timing)
SCK1↓ from busy inactive
Note
t SPS
2t KCY11
ns
C is the load capacitance of the SO1 output line.
(iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... external clock
input)
Parameter
SCK1 cycle time
SCK1 high-/low-level width
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
3.5 V ≤ VDD < 4.5 V
1 600
ns
t KH12 ,
4.5 V ≤ VDD ≤ 5.5 V
400
ns
t KL12
3.5 V ≤ VDD < 4.5 V
800
ns
t KCY12
SI1 setup time (to SCK1↑)
t SIK12
100
ns
SI1 hold time (from SCK1↑)
t KSI12
400
ns
SO1 output delay time (from SCK1↓)
t KSO12
SCK1 rising or falling edge time
Note
34
C = 100 pF Note
t R12, t F12
C is the load capacitance of the SO1 output line.
300
ns
1 000
ns
µ PD178P018A
AC Timing Test Point (Excluding X1 Input)
0.8 VDD
0.2 VDD
0.8 VDD
Test Points
0.2 VDD
TI Timing
1/fTI
tTIL
tTIH
tINTL
tINTH
TI1, TI2
Interrupt Input Timing
INTP0 to INTP6
RESET Input Timing
tRSL
RESET
35
µ PD178P018A
Serial Transfer Timing
3-Wire Serial I/O Mode:
tKCYm
tKLm
tKHm
tRn
tFn
SCK0, SCK1
tSIKm
tKSIm
Input Data
SI0, SI1
tKSOm
Output Data
SO0, SO1
Remark m = 1, 2, 9, 10
n = 2, 10
SBI Mode (Bus Release Signal Transfer):
tKL3, 4
tKCY3, 4
tKH3, 4
tR4
tF4
SCK0
tKSB
tSBL
tSBH
tSIK3, 4
tSBK
SB0, SB1
tKSO3, 4
36
tKSI3, 4
µ PD178P018A
SBI Mode (Command Signal Transfer):
tKCY3, 4
tKL3, 4
tR4
tKH3, 4
tF4
SCK0
tKSB
tSIK3, 4
tSBK
tKSI3, 4
SB0, SB1
tKSO3, 4
2-Wire Serial I/O Mode:
tKCY5, 6
tKL5, 6
tR6
tKH5, 6
tF6
SCK0
tSIK5, 6
tKSO5, 6
tKSI5, 6
SB0, SB1
I 2C Bus Mode:
tR8
tF8
tKCY7, 8
SCL
tKL7, 8
tKSI7, 8
tKH7, 8
tSIK7, 8
tKSO7, 8
tKSB
tKSB
tSBK
SDA0, SDA1
tSBH
tSBK
37
µ PD178P018A
3-Wire Serial I/O Mode with Automatic Transmit/Receive Function:
SO1
D2
SI1
D2
D1
D0
D1
D7
D0
D7
tKSI11, 12
tSIK11, 12
tKH11, 12
tKSO11, 12
tF12
SCK1
tR12
tKL11, 12
tKCY11, 12
tSBD
tSBW
STB
3-Wire Serial I/O Mode with Automatic Transmit/Receive Function (Busy Processing):
SCK1
7
8
9 Note
10 Note
tBYS
10 + n Note
tBYH
1
tSPS
BUSY
(Active high)
Note
38
The signal is not actually driven low here; it is shown as such to indicate the timing.
µ PD178P018A
A/D CONVERTER CHARACTERISTICS (TA = –40 to +85 °C, VDD = 4.5 to 5.5 V)
Parameter
Symbol
Test Conditions
Resolution
MIN.
TYP.
MAX.
Unit
8
8
8
bit
±3.0
LSB
44.4
µs
Conversion total
error
Conversion time
t CONV
22.2
Sampling time
t SAMP
15/fXX
Analog input
voltage
VIAN
0
µs
VDD
V
MAX.
Unit
Remarks 1. fXX: System clock frequency (f X/2)
2. fX: System clock oscillation frequency
PLL CHARACTERISTICS (T A = –40 to +85 °C, VDD = 4.5 to 5.5 V)
Parameter
Operating
frequency
Symbol
Test Conditions
MIN.
TYP.
f IN1
VCOL Pin MF Mode Sine wave input VIN = 0.1 V p-p
0.5
3
MHz
f IN2
VCOL Pin HF Mode Sine wave input VIN = 0.2 Vp-p
9
55
MHz
f IN3
VCOH Pin VHF Mode Sine wave input VIN = 0.15 Vp-p
60
160
MHz
IFC CHARACTERISTICS (T A = –40 to +85 °C, VDD = 4.5 to 5.5 V)
Parameter
Operating
frequency
Note
Symbol
MAX.
Unit
f IN4
AMIFC Pin AMIF Count Mode
Sine wave input VIN = 0.1 Vp-p Note
Test Conditions
MIN.
0.4
TYP.
0.5
MHz
f IN5
FMIFC Pin FMIF Count Mode
Sine wave input VIN = 0.1 Vp-p Note
10
11
MHz
f IN6
FMIFC Pin AMIF Count Mode
Sine wave input VIN = 0.1 Vp-p Note
0.4
0.5
MHz
The condition of a sine wave input of VIN = 0.1 Vp-p is the standard value for operation of this device during
stand-alone operation, so in consideration of the effect of noise, it is recommended that operation be at
an input amplitude condition of V IN = 0.15 V p-p.
39
µ PD178P018A
PROM PROGRAMMING CHARACTERISTICS
DC CHARACTERISTICS
(1) PROM Write Mode (TA = 25 ± 5 °C, VDD = 6.5 ± 0.25 V, VPP = 12.5 ± 0.3 V)
Parameter
Symbol Symbol Note
Test Conditions
MIN.
TYP.
MAX.
Unit
Input voltage, high
VIH
VIH
0.7 VDD
VDD
V
Input voltage, low
VIL
VIL
0
0.3 VDD
V
Output voltage, high
VOH
V OH
I OH = –1 mA
Output voltage, low
VOL
VOL
I OL = 1.6 mA
I LI
I LI
0 ≤ VIN ≤ V DD
VPP supply voltage
VPP
VPP
VDD supply voltage
VDD
VCC
VPP supply current
I PP
I PP
VDD supply current
I DD
I CC
Input leakage current
VDD – 1.0
V
–10
0.4
V
+10
µA
V
12.2
12.5
12.8
6.25
6.5
6.75
V
50
mA
50
mA
PGM = V IL
(2) PROM Read Mode (TA = 25 ± 5 °C, V DD = 5.0 ± 0.5 V, VPP = VDD ± 0.6 V)
Parameter
Input voltage, high
Input voltage, low
Output voltage, high
Output voltage, low
Input leakage current
Symbol Symbol Note
VIH
Test Conditions
VIH
MAX.
Unit
0.7 V DD
MIN.
TYP.
VDD
V
0
0.3 VDD
V
VIL
VIL
VOH1
VOH1
I OH = –1 mA
VDD – 1.0
V
VOH2
VOH2
I OH = –100 µA
VDD – 0.5
V
VOL
VOL
I OL = 1.6 mA
I LI
I LI
0 ≤ VIN ≤ V DD
0 ≤ VOUT ≤ VDD, OE = VIH
–10
V
µA
+10
µA
Output leakage current
I LO
I LO
VPP supply voltage
VPP
VPP
VDD – 0.6
VDD
VDD + 0.6
V
VDD supply voltage
VDD
VCC
4.5
5.0
5.5
V
VPP supply current
I PP
I PP
VDD supply current
I DD
I CCA1
Note Corresponding µ PD27C1001A symbol.
40
VPP = VDD
CE = VIL, V IN = V IH
–10
0.4
+10
100
µA
50
mA
µ PD178P018A
AC CHARACTERISTICS
(1) PROM Write Mode
(a) Page program mode (T A = 25 ± 5 °C, V DD = 6.5 ± 0.25 V, VPP = 12.5 ± 0.3 V)
Parameter
Symbol Symbol Note
Test Conditions
MIN.
TYP.
MAX.
Unit
Address setup time (to OE ↓)
t AS
t AS
2
µs
OE setup time
t OES
t OES
2
µs
CE setup time (to OE ↓)
tCES
tCES
2
µs
Input data setup time (to OE ↓)
t DS
t DS
2
µs
Address hold time (from OE ↑)
t AH
t AH
2
µs
t AHL
t AHL
2
µs
µs
tAHV
tAHV
0
Input data hold time (from OE ↑)
t DH
t DH
2
Data output float delay time
t DF
t DF
0
VPP setup time (to OE ↓)
t VPS
t VPS
1.0
ms
VDD setup time (to OE ↓)
tVDS
tVCS
1.0
ms
Program pulse width
t PW
t PW
0.095
Valid data delay time from OE ↓
t OE
t OE
OE pulse width during data
t LW
t LW
1
µs
t PGMS
t PGMS
2
µs
CE hold time
t CEH
t CEH
2
µs
OE hold time
t OEH
t OEH
2
µs
µs
250
ns
from OE ↑
0.1
0.105
ms
1
µs
latching
PGM setup time
(b) Byte program mode (T A = 25 ± 5 °C, V DD = 6.5 ± 0.25 V, VPP = 12.5 ± 0.3 V)
Parameter
Symbol Symbol Note
Test Conditions
MIN.
TYP.
MAX.
Unit
Address setup time (to PGM ↓)
t AS
t AS
2
µs
OE set time
t OES
t OES
2
µs
CE setup time (to PGM ↓)
tCES
tCES
2
µs
Input data setup time (to PGM ↓)
t DS
t DS
2
µs
Address hold time (from OE ↑)
t AH
t AH
2
µs
Input data hold time
t DH
t DH
2
µs
t DF
t DF
0
VPP setup time (to PGM ↓)
t VPS
t VPS
1.0
VDD setup time (to PGM ↓)
tVDS
tVCS
1.0
Program pulse width
t PW
t PW
0.095
Valid data delay time from OE ↓
t OE
t OE
OE hold time
t OEH
—
(from PGM ↑)
Data output float delay time
250
ns
from OE ↑
Note
2
ms
ms
0.1
0.105
ms
1
µs
µs
Corresponding µ PD27C1001A symbol.
41
µ PD178P018A
(2) PROM Read Mode (TA = 25 ± 5 °C, V DD = 5.0 ± 0.5 V, VPP = V DD ± 0.6 V)
Parameter
Symbol Symbol Note
MAX.
Unit
tACC
tACC
CE = OE = V IL
800
ns
Data output delay time CE ↓
t CE
t CE
OE = VIL
800
ns
Data output delay time OE ↓
t OE
t OE
CE = VIL
200
ns
Data output float delay time
t DF
t DF
CE = VIL
0
60
ns
t OH
t OH
CE = OE = V IL
0
Data output delay time from
Test Conditions
MIN.
TYP.
address
from OE ↑
Data hold time to address
ns
Note Corresponding µ PD27C1001A symbol.
(3) PROM Programming Mode Setting (TA = 25 °C, V SS = 0 V)
Parameter
PROM programming mode
setup time
42
Symbol
t SMA
Test Conditions
MIN.
10
TYP.
MAX.
Unit
µs
µ PD178P018A
PROM Write Mode Timing (page program mode)
Page Data Latch
Page Program
Program Verify
A2 to A16
tAS
tAHL
tAHV
tDS
tDH
tDF
A0, A1
D0 to D7
Hi-Z
Hi-Z
tVPS
Data Input
Hi-Z
tPGMS
tOE
VPP
Data
Output
tAH
VPP
VDD
tVDS
VDD + 1.5
VDD
VDD
tCES
tOEH
VIH
CE
VIL
tCEH
tPW
VIH
PGM
VIL
tLW
tOES
VIH
OE
VIL
43
µ PD178P018A
PROM Write Mode Timing (byte program mode)
Program
Program Verify
A0 to A16
tDF
tAS
D0 to D7
Hi-Z
Hi-Z
Data Input
tDS
Hi-Z
Data Output
tDH
tAH
VPP
VPP
VDD
tVPS
VDD + 1.5
VDD
VDD
tVDS
tOEH
VIH
CE
VIL
tCES
tPW
VIH
PGM
VIL
tOES
tOE
VIH
OE
VIL
Cautions 1.
2.
3.
VDD should be applied before V PP, and removed after VPP .
VPP must not exceed +13.5 V including overshoot.
Reliability may be adversely affected if removal/reinsertion is performed while +12.5 V is being
applied to VPP .
PROM Read Mode Timing
A0 to A16
Effective Address
VIH
CE
VIL
tCE
VIH
OE
VIL
tACC Note1
D0 to D7
Hi-Z
tOE Note 1
tDF Note 2
tOH
Data Output
Hi-Z
Notes 1. If you want to read within the range of tACC , make the OE input delay time from the fall of CE a maximum
of tACC – tOE .
2. tDF is the time from when either OE or CE first reaches VIH .
44
µ PD178P018A
PROM Programming Mode Setting Timing
VDD
VDD
0
RESET
VDD
VPP
0
tSMA
A0 to A16
Effective Address
45
µ PD178P018A
7. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14×14)
A
B
41
40
60
61
detail of lead end
C D
S
R
Q
21
20
80
1
F
J
G
I
H
M
K
P
M
N
L
NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
INCHES
A
17.2±0.4
0.677±0.016
B
14.0±0.2
0.551 +0.009
–0.008
C
14.0±0.2
0.551 +0.009
–0.008
D
17.2±0.4
0.677±0.016
F
0.825
0.032
G
0.825
0.032
H
0.30±0.10
0.012 +0.004
–0.005
I
0.13
0.005
J
0.65 (T.P.)
0.026 (T.P.)
K
1.6±0.2
L
0.8±0.2
0.063±0.008
0.031 +0.009
–0.008
M
0.15 +0.10
–0.05
0.006 +0.004
–0.003
N
0.10
0.004
P
2.7
0.106
Q
0.1±0.1
0.004±0.004
R
5°±5°
5°±5°
S
3.0 MAX.
0.119 MAX.
S80GC-65-3B9-4
46
µ PD178P018A
80 PIN CERAMIC WQFN
A
Q
K
B
D
80
S
W
C
U1
T
H
U
1
I M
R
G
F
J
Z
X80KW-65A-1
NOTE
Each lead centerline is located within 0.06
mm (0.003 inch) of its true position (T.P.) at
maximum material condition.
ITEM
MILLIMETERS
INCHES
A
14.0 ± 0.2
0.551 ± 0.008
B
13.6
0.535
C
13.6
0.535
D
14.0 ± 0.2
0.551 ± 0.008
F
1.84
0.072
G
3.6 MAX.
0.142 MAX.
H
0.45 ± 0.10
0.018+0.004
–0.005
I
0.06
0.003
J
0.65 (T.P.)
0.024 (T.P.)
K
1.0 ± 0.15
0.039+0.007
–0.006
Q
C 0.3
C 0.012
R
0.825
0.032
S
0.825
0.032
T
R 2.0
R 0.079
U
9.0
0.354
U1
2.1
0.083
W
0.75 ± 0.15
0.030+0.006
–0.007
Z
0.10
0.004
47
µ PD178P018A
APPENDIX A. DIFFERENCES BETWEEN µPD178018A AND µPD178018 SUBSERIES
Product Name
µ PD178004
Reference
frequency
7 types selectable by program
(1, 3, 5, 9, 10, 25, 50 kHz)
11 types selectable by program
(1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 25, 50 kHz)
EO0 pin output
format
Buffer type
EO1 pin output
format
Buffer type
EO1 pin highNot supported
impedance function
Note
µPD178018 Subseries
µPD178004A µPD178006A µ PD178016A µ PD178018A
µPD178P018A Note
Item
PLL
frequency
synthesizer
µ PD178018A Subseries
µ PD178006
µ PD178016
µ PD178018
µ PD178P018
Constant-current power supply type
Supported
Not supported
Under development
Remark The mask ROM of mask versions ( µ PD178018A and µ PD178018) is replaced with one-time PROM
or EPROM in the one-time PROM versions ( µPD178P018A and µ PD178P018).
48
µ PD178P018A
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD178P018A Subseries.
Language Processing Software
RA78K/0 Notes 1, 2, 3, 4
CC78K/0
Notes 1, 2, 3, 4
DF178018
Notes 1, 2, 3, 4, 8
CC78K/0-L
Notes 1, 2, 3, 4
78K/0 Series common assembler package
78K/0 Series common C compiler package
µPD178018A Subseries common device file
78K/0 Series common C compiler library source file
PROM Writing Tools
PG-1500
PROM writer
PG-178P018GC
Program writer adapters connected to a PG-1500
PA-178P018KK-T
PG-1500 controller Notes 1, 2
PG-1500 control program
Debugging Tools
IE-78000-R
In-circuit emulator common to 78K/0 Series
IE-78000-R-A
In-circuit emulator common to 78K/0 Series (for the integrated debugger)
IE-78000-R-BK
Break board common to 78K/0 Series
IE-178018-R-EM
Emulation board common to µPD178018A Subseries
IE-78000-R-SV3
Interface adapter and cable when using EWS as a host machine (for IE-78000-R-A)
IE-70000-98-IF-B
Interface adapter when using the PC-9800 Series (except notebooks) as a host machine
(for IE-78000-R-A)
IE-70000-98N-IF
Interface adapter and cable when using the PC-9800 Series notebook as a host machine
(for IE-78000-R-A)
IE-70000-PC-IF-B
Interface adapter when using IBM PC/ATTM as a host machine (for IE-78000-R-A)
EP-78230GC-R
Emulation probe common to µPD78234 Subseries
EV-9200GC-80
Socket for mounting on target system board created for 80-pin plastic QFP (GC-3B9 type)
EV-9900
Jig used when removing the µPD178P018AKK-T from the EV-9200GC-80.
SM78K0
ID78K0
Notes 5, 6, 7
Notes 4, 5, 6, 7
SD78K/0
Notes 1, 2
DF178018
Notes 1, 2, 4, 5, 6, 7, 8
78K/0 series common system simulator
Integrated debugger for IE-78000-R-A
IE-78000-R screen debugger
µPD178018A Subseries device file
49
µ PD178P018A
Real-Time OS
RX78K/0 Notes 1, 2, 3, 4
MX78K0
78K/0 Series real-time OS
Notes 1, 2, 3, 4
Notes 1.
2.
3.
4.
5.
6.
7.
8.
78K/0 Series OS
PC-9800 Series (MS-DOS TM) based
IBM PC/AT and compatibles (PC DOS TM/IBM DOSTM/MS-DOS) based
HP9000 Series 300 TM (HP-UX™) based
HP9000 Series 700 TM (HP-UXTM ) based, SPARCstationTM (SunOS TM) based, EWS4800 Series
(EWS-UX/V) based
PC-9800 Series (MS-DOS + WindowsTM ) based
IBM PC/AT and compatibles (PC DOS/IBM DOS/MS-DOS + Windows) based
NEWS TM (NEWS-OSTM ) based
Under development
Fuzzy Inference Development Support System
FE9000 Note 1/FE9200 Note 2
FT9080
FI78K0
Note 1
/FT9085
Notes 1, 3
FD78K0
Notes 1, 3
Note 3
Fuzzy knowledge data creation tool
Translator
Fuzzy inference module
Fuzzy inference debugger
Notes 1. PC-9800 Series (MS-DOS) based
2. IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS + Windows) based
3. IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS) based
Remarks 1. Please refer to the 78K/0 Series Selection Guide (U11126E) for information on third party
development tools.
2. The RA78K/0, CC78K/0, SD78K/0, ID78K/0, SM78K/0, and RX78K/0 are used in combination with
the DF178018.
50
µ PD178P018A
CONVERSION SOCKET DRAWING AND RECOMMENDED FOOTPRINT
Figure B-1. Drawing of EV-9200GC-80 (for Reference only)
Based on EV-9200GC-80
(1) Package drawing (in mm)
A
E
M
B
N
O
L
K
S
J
C
D
R
F
EV-9200GC-80
Q
1
No.1 pin index
P
G
H
I
EV-9200GC-80-G1E
ITEM
MILLIMETERS
INCHES
A
18.0
0.709
B
14.4
0.567
C
14.4
0.567
D
18.0
0.709
E
4-C 2.0
4-C 0.079
F
0.8
0.031
G
6.0
0.236
H
16.0
0.63
I
18.7
0.736
J
6.0
0.236
K
16.0
0.63
L
18.7
0.736
M
8.2
0.323
N
8.0
0.315
O
2.5
0.098
P
2.0
0.079
Q
0.35
0.014
R
φ 2.3
φ 0.091
S
φ 1.5
φ 0.059
51
µ PD178P018A
Figure B-2. Recommended Footprint of EV-9200GC-80 (for Reference only)
Based on EV-9200GC-80
(2) Pad drawing (in mm)
G
J
H
D
E
F
K
I
L
C
B
A
EV-9200GC-80-P1E
ITEM
MILLIMETERS
A
19.7
0.776
B
15.0
0.591
C
+0.003
0.65±0.02 × 19=12.35±0.05 0.026+0.001
–0.002 × 0.748=0.486 –0.002
D
+0.003
0.65±0.02 × 19=12.35±0.05 0.026+0.001
–0.002 × 0.748=0.486 –0.002
E
15.0
0.591
F
19.7
0.776
G
6.0 ± 0.05
0.236+0.003
–0.002
H
6.0 ± 0.05
0.236+0.003
–0.002
I
0.35 ± 0.02
0.014+0.001
–0.001
J
φ 2.36 ± 0.03
φ 0.093+0.001
–0.002
K
φ 2.3
φ 0.091
L
φ 1.57 ± 0.03
φ 0.062+0.001
–0.002
Caution
52
INCHES
Dimensions of mount pad for EV-9200 and that for target
device (QFP) may be different in some parts. For the
recommended mount pad dimensions for QFP, refer to
"SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY
MANUAL" (C10535E).
µ PD178P018A
APPENDIX C. RELATED DOCUMENTS
Device Documents
Document No.
(Japanese)
Document No.
(English)
µ PD178018A Subseries User’s Manual
To be prepared
To be prepared
78K/0 Series User’s Manual—Instruction
U12326J
U12326E
78K/0 Series Instruction Set
U10904J
—
78K/0 Series Instruction Table
U10903J
—
µ PD178018A Subseries Special Function Register Table
To be prepared
—
Title
78K/0 Series Application Note
Basics (II)
U10121J
U10121E
Development Tool Documents (User’s Manual)
Document No.
(Japanese)
Title
RA78K Series Assembler Package
Operation
EEU-809
EEU-1399
Language
EEU-815
EEU-1404
EEU-817
EEU-1402
Operation
U11802J
U11802E
Assembly Language
U11801J
U11801E
Structured Assembly
Language
U11789J
U11789E
Operation
EEU-656
EEU-1280
Language
EEU-655
EEU-1284
Operation
U11517J
U11517E
Language
U11518J
U11518E
Programming Know-how
EEA-618
EEA-1208
RA78K Series Structured Assembler Preprocessor
RA78K0 Assembler Package
CC78K Series C Compiler
CC78K/0 C Compiler
CC78K/0 C Compiler Application Notes
Document No.
(English)
CC78K Series Library Source File
U12322J
PG-1500 PROM Programmer
U11940J
EEU-1335
—
PG-1500 Controller PC-9800 Series (MS-DOS) Based
EEU-704
EEU-1291
PG-1500 Controller IBM PC Series (PC DOS) Based
EEU-5008
U10540E
IE-78000-R
U11376J
U11376E
IE-78000-R-A
U10057J
U10057E
IE-78000-R-BK
EEU-867
EEU-1427
IE-178018-R-EM
U10668J
U10668E
EP-78230
EEU-985
EEU-1515
SM78K0 System Simulator Windows Based
Reference
U10181J
U10181E
SM78K Series System Simulator
External Parts User
open Interface
Specifications
U10092J
U10092E
ID78K0 Integrated Debugger EWS Based
Reference
U11151J
U11151E
ID78K0 Integrated Debugger PC Based
Reference
U11539J
U11539E
ID78K0 Integrated Debugger Windows Based
Guide
U11649J
U11649E
SD78K/0 Screen Debugger PC-9800 Series (MS-DOS) Based
Introduction
EEU-852
U10539E
Reference
U10952J
—
SD78K/0 Screen Debugger IBM PC/AT (PC DOS) Based
Introduction
EEU-5024
EEU-1414
Reference
U11279J
U11279E
Caution The contents of the above documents are subject to change without notice. Please ensure that
the latest versions are used in design work, etc.
53
µ PD178P018A
Related Documents for Embedded Software (User’s Manual)
Title
78K/0 Series Realtime OS
78K/0 Series OS MX78K0
Document No.
Document No.
(Japanese)
(English)
Basics
U11537J
—
Installation
U11536J
—
Basics
U12257J
—
Fuzzy Knowledge Data Creation Tool
EEU-829
EEU-1438
78K/0, 78K/II, 87AD Series
EEU-862
EEU-1444
78K/0 Series Fuzzy Inference Development Support System—Fuzzy Inference Module
EEU-858
EEU-1441
78K/0 Series Fuzzy Inference Development Support System
EEU-921
EEU-1458
Fuzzy Inference Development Support System—Translator
—Fuzzy Inference Debugger
Other Documents
Title
Document No.
Document No.
(Japanese)
(English)
IC Package Manual
C10943X
Semiconductor Device Mounting Technology Manual
C10535J
C10535E
Quality Guides on NEC Semiconductor Devices
C11531J
C11531E
NEC Semiconductor Device Reliability and Quality Control System
C10983J
C10983E
Electrostatic Discharge (ESD) Test
MEM-539
Semiconductor Device Quality Assurance Guide
C11893J
MEI-1202
Microcomputer-related Product Guide (Products by other Manufacturers)
U11416J
—
—
Caution The contents of the above documents are subject to change without notice. Ensure that the
latest versions are used in design work, etc.
54
µ PD178P018A
[MEMO]
55
µ PD178P018A
[MEMO]
56
µ PD178P018A
[MEMO]
57
µ PD178P018A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it once, when it has occurred.
Environmental control must be
adequate. When it is dry, humidifier should be used. It is recommended to avoid
using insulators that easily build static electricity. Semiconductor devices
must be stored and transported in an anti-static container, static shielding bag
or conductive material. All test and measurement tools including work bench
and floor should be grounded. The operator should be grounded using wrist
strap. Semiconductor devices must not be touched with bare hands. Similar
precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level
may be generated due to noise, etc., hence causing malfunction. CMOS device
behave differently than Bipolar or NMOS devices. Input levels of CMOS devices
must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have
a possibility of being an output pin. All handling related to the unused pins must
be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset function
have not yet been initialized. Hence, power-on does not guarantee out-pin
levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after
power-on for devices having reset function.
58
µ PD178P018A
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583
NEC Electronics (France) S.A.
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd.
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
J96. 8
59
µ PD178P018A
Purchase of NEC I2 C components conveys a license under the Philips I 2C Patent Rights to use these components in an I2 C
system, provided that the system conforms to the I2 C Standard Specification as defined by Philips.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United
States and/or other countries.
IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
HP9000 Series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
The export of these products from Japan is regulated by the Japanese government. The export of some or all of
these products may be prohibited without governmental license. To export or re-export some or all of these
products from a country other than Japan may also be prohibited without a license from that country. Please call
an NEC sales representative.
License not needed
: µPD178P018AKK-T
The customer must judge the need for license : µPD178P018AGC-3B9
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
60