TPS54620 www.ti.com SLVS949A – MAY 2009 – REVISED JANUARY 2010 4.5V to 17V Input, 6A Synchronous Step Down SWIFT™ Converter Check for Samples: TPS54620 FEATURES • 1 • • • • • • • • • Integrated 26mΩ / 19mΩ MOSFETs Split Power Rail: 1.6V to 17V on PVIN 200kHz to 1.6MHz Switching Frequency Synchronizes to External Clock 0.8V ±1% Voltage Reference Over Temperature Low 2uA Shutdown Quiescent Current Monotonic Start-Up into Pre-biased Outputs –40°C to 150°C Operating Junction Temperature Range Adjustable Slow Start/Power Sequencing • • • Power Good Output Monitor for Undervoltage & Overvoltage Adjustable Input Undervoltage Lockout Supported by SwitcherPro™ Software Tool For SWIFT™ Documentation and SwitcherPro™, visit http://www.ti.com/swift APPLICATIONS • • • High Density Distributed Power Systems High Performance Point of Load Regulation Broadband, Networking and Optical Communications Infrastructure DESCRIPTION The TPS54620 in thermally enhanced 3.5mm x 3.5mm QFN package is a full featured 17V, 6A synchronous step down converter which is optimized for small designs through high efficiency and integrating the high-side and low-side MOSFETs. Further space savings are achieved through current mode control, which reduces component count, and by selecting a high switching frequency, reducing the inductor's footprint. The output voltage startup ramp is controlled by the SS/TR pin which allows operation as either a stand alone power supply or in tracking situations. Power sequencing is also possible by correctly configuring the enable and the open drain power good pins. Cycle by cycle current limiting on the high-side FET protects the device in overload situations and is enhanced by a low-side sourcing current limit which prevents current runaway. There is also a low-side sinking current limit which turns off the low-side MOSFET to prevent excessive reverse current. Thermal shutdown disables the part when die temperature exceeds thermal shutdown temperature. WHITE SPACE SIMPLIFIED SCHEMATIC 100 PVIN VIN TPS54620 BOOT VIN Cin 8V 95 Cboot 90 85 PH Co PWRGD R1 17 V 12 V Efficiency - % VOUT Lo EN 80 75 70 VSENSE SS/TR RT/CLK COMP Css Rrt C2 R3 C1 65 R2 GND 60 Exposed Thermal Pad 55 VOUT = 3.3 V Fsw = 480 kHz 50 0 1 2 3 Load Current - A 4 5 6 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2010, Texas Instruments Incorporated TPS54620 SLVS949A – MAY 2009 – REVISED JANUARY 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) (1) (2) TJ PACKAGE PART NUMBER (2) –40°C to 150°C 14 Pin QFN TPS54620RGY For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. The RGY package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54620RGYR). See applications section of data sheet for layout information ABSOLUTE MAXIMUM RATINGS (1) over operating temperature range (unless otherwise noted) Input Voltage VALUE UNIT VIN –0.3 to 20 V PVIN –0.3 to 20 V EN –0.3 to 6 V BOOT –0.3 to 27 V VSENSE –0.3 to 3 V COMP –0.3 to 3 V PWRGD –0.3 to 6 V SS/TR –0.3 to 3 V RT/CLK –0.3 to 6 V BOOT-PH Output Voltage 0 to 7 V PH –1 to 20 V PH 10ns Transient –3 to 20 V –0.2 to 0.2 V Vdiff(GND to exposed thermal pad) ±100 µA PH Current Limit A PH Current Limit A PVIN Current Limit A ±200 µA –0.1 to 5 mA 2 kV 500 V Operating Junction Temperature –40 to 150 °C Storage Temperature –65 to 150 °C Source Current Sink Current RT/CLK COMP PWRGD Electrostatic Discharge (HBM) QSS 009-105 (JESD22-A114A) Electrostatic Discharge (CDM) QSS 009-147 (JESD22-C101B.01) (1) 2 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 TPS54620 www.ti.com SLVS949A – MAY 2009 – REVISED JANUARY 2010 PACKAGE DISSIPATION RATINGS (1) (1) (2) (3) (4) (2) (3) (4) PACKAGE THERMAL IMPEDANCE JUNCTION TO AMBIENT qJP THERMAL IMPEDANCE JUNCTION TO EXPOSED THERMAL PAD yJT THERMAL CHARACTERISTIC JUNCTION TO TOP RGY 32°C/W 5.2°C/W 5°C/W Maximum power dissipation may be limited by overcurrent protection Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below 150°C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more information. Test board conditions: (a) 2.5 inches × 2.5 inches, 4 layers, thickness: 0.062 inch (b) 2 oz. copper traces located on the top of the PCB (c) 2 oz. copper ground planes on the 2 internal layers and bottom layer (d) 4 0.010 inch thermal vias located under the device package For information on thermal characteristics see SPRA953A ELECTRICAL CHARACTERISTICS TJ = –40°C to 150°C, VIN = 4.5V to 17V, PVIN = 1.6V to 17V (unless otherwise noted) DESCRIPTION CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE (VIN AND PVIN PINS) PVIN operating input voltage 1.6 17 V VIN operating input voltage 4.5 17 V 4.5 V VIN internal UVLO threshold VIN rising 4.0 VIN internal UVLO hysteresis 150 VIN shutdown supply Current EN = 0 V VIN operating – non switching supply current VSENSE = 810 mV mV 2 5 mA 600 800 mA 1.21 1.26 V ENABLE AND UVLO (EN PIN) Enable threshold Rising Enable threshold Falling Input current EN = 1.1 V 1.15 mA Hysteresis current EN = 1.3 V 3.4 mA 1.10 1.17 VOLTAGE REFERENCE Voltage reference 0 A ≤ Iout ≤ 6 A 0.792 0.800 0.808 V MOSFET High-side switch resistance BOOT-PH = 3 V 32 60 mΩ High-side switch resistance (1) BOOT-PH = 6 V 26 40 mΩ Low-side Switch Resistance (1) VIN = 12 V 19 30 mΩ ERROR AMPLIFIER Error amplifier Transconductance (gm) –2 mA < ICOMP < 2 mA, V(COMP) = 1 V Error amplifier dc gain VSENSE = 0.8 V Error amplifier source/sink V(COMP) = 1 V, 100 mV input overdrive 1000 Start switching threshold 1300 mMhos 3100 V/V ±110 mA 0.25 COMP to Iswitch gm V 16 A/V CURRENT LIMIT High-side switch current limit threshold 8 11 A Low-side switch sourcing current limit 7 10 A 2.3 A Low-side switch sinking current limit (1) Measured at pins Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 3 TPS54620 SLVS949A – MAY 2009 – REVISED JANUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 150°C, VIN = 4.5V to 17V, PVIN = 1.6V to 17V (unless otherwise noted) DESCRIPTION CONDITIONS MIN TYP MAX UNIT 160 175 °C 10 °C THERMAL SHUTDOWN Thermal shutdown Thermal shutdown hysteresis TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) Minimum switching frequency Rrt = 240 kΩ (1%) 160 200 240 kHz Switching frequency Rrt = 100 kΩ (1%) 400 480 560 kHz Maximum switching frequency Rrt = 29 kΩ (1%) 1440 1600 1760 kHz Minimum pulse width 20 RT/CLK high threshold RT/CLK low threshold RT/CLK falling edge to PH rising edge delay ns 2 0.8 Measure at 500 kHz with RT resistor in series Switching frequency range (RT mode set point and PLL mode) V V 66 200 ns 1600 kHz 135 ns PH (PH PIN) Minimum on time Measured at 90% to 90% of VIN, 25°C, IPH = 2A Minimum off time BOOT-PH ≥ 3 V 94 0 ns BOOT (BOOT PIN) BOOT-PH UVLO 2.1 3 V 60 mV SLOW START AND TRACKING (SS/TR PIN) SS charge current SS/TR to VSENSE matching 2.3 mA V(SS/TR) = 0.4 V 29 VSENSE falling (Fault) 91 % Vref VSENSE rising (Good) 94 % Vref VSENSE rising (Fault) 109 % Vref VSENSE falling (Good) 106 POWER GOOD (PWRGD PIN) VSENSE threshold Output high leakage VSENSE = Vref, V(PWRGD) = 5.5 V Output low I(PWRGD) = 2 mA Minimum VIN for valid output V(PWRGD) < 0.5V at 100 mA Minimum SS/TR voltage for PWRGD 4 Submit Documentation Feedback 30 0.6 % Vref 100 nA 0.3 V 1 V 1.4 V Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 TPS54620 www.ti.com SLVS949A – MAY 2009 – REVISED JANUARY 2010 DEVICE INFORMATION PIN ASSIGNMENTS RGY (Top View) RT/CLK 1 PWRGD 14 GND 2 13 BOOT GND 3 PVIN 4 12 PH Exposed Thermal Pad (15) PVIN 5 11 PH 10 EN VIN 6 9 SS/TR 7 VSENSE 8 COMP PIN FUNCTIONS PIN NAME RT/CLK DESCRIPTION No. 1 Automatically selects between RT mode and CLK mode. An external timing resistor adjusts the switching frequency of the device; In CLK mode, the device synchronizes to an external clock. GND 2, 3 Return for control circuitry and low-side power MOSFET. PVIN 4, 5 Power input. Supplies the power switches of the power converter. VIN 6 Supplies the control circuitry of the power converter. VSENSE 7 Inverting input of the gm error amplifier. COMP 8 Error amplifier output, and input to the output switch current comparator. Connect frequency compensation to this pin. SS/TR 9 Slow-start and tracking. An external capacitor connected to this pin sets the internal voltage reference rise time. The voltage on this pin overrides the internal reference. It can be used for tracking and sequencing. EN 10 Enable pin. Float to enable. Adjust the input undervoltage lockout with two resistors. PH 11, 12 The switch node. BOOT 13 A bootstrap cap is required between BOOT and PH. The voltage on this cap carries the gate drive voltage for the high-side MOSFET. PWRGD 14 Power Good fault pin. Asserts low if output voltage is low due to thermal shutdown, dropout, over-voltage, EN shutdown or during slow start. Exposed Thermal PAD 15 Thermal pad of the package and signal ground and it must be soldered down for proper operation. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 5 TPS54620 SLVS949A – MAY 2009 – REVISED JANUARY 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM PWRGD VIN EN Thermal Shutdown Shutdown Ip Ih PVIN PVIN UVLO Enable Comparator Shutdown UV Shutdown Logic Logic Enable Threshold OV Boot Charge Current Sense Minimum Clamp Pulse Skip ERROR AMPLIFIER VSENSE BOOT Boot UVLO SS/TR HS MOSFET Current Comparator Voltage Reference Power Stage & Deadtime Control Logic PH PH Slope Compensation VIN Overload Recovery and Clamp Oscillator with PLL Regulator LS MOSFET Current Limit Current Sense GND GND COMP 6 RT/CLK Submit Documentation Feedback Exposed Thermal Pad Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 TPS54620 www.ti.com SLVS949A – MAY 2009 – REVISED JANUARY 2010 TYPICAL CHARACTERISTICS CHARACTERISTIC CURVES HIGH-SIDE Rdson vs TEMPERATURE LOW-SIDE Rdson vs TEMPERATURE 30 40 VIN = 12 V RDS(on) − On Resistance − mΩ RDS(on) − On Resistance − mΩ VIN = 12 V 35 30 25 20 −50 −25 0 25 50 75 100 125 27 24 21 18 15 −50 150 −25 TJ − Junction Temperature − °C 0 50 75 100 125 150 TJ − Junction Temperature − °C Figure 1. Figure 2. VOLTAGE REFERENCE vs TEMPERATURE OSCILLATOR FREQUENCY vs TEMPERATURE 0.805 490 fO − Oscillator Frequency − kHz Vref − Voltage Resistance − V 25 0.803 0.801 0.799 0.797 0.795 −50 −25 0 25 50 75 100 125 RT = 100 kΩ 485 480 475 470 −50 150 TJ − Junction Temperature − °C −25 0 25 50 75 100 125 Figure 3. Figure 4. SHUTDOWN QUIESCENT CURRENT vs INPUT VOLTAGE EN PIN HYSTERISIS CURRENT vs TEMPERATURE N μ Isd – Shutdown Quiescent Current – mA 150 TJ − Junction Temperature − °C Figure 5. Figure 6. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 7 TPS54620 SLVS949A – MAY 2009 – REVISED JANUARY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) PIN PULL-UP CURRENT vs TEMPERATURE PIN UVLO THRESHOLD vs TEMPERATURE 1.220 μ En Pin UVLO Threshold − V VIN = 12 V 1.215 1.210 1.205 1.200 −50 −25 0 25 50 75 100 Figure 7. Figure 8. NON-SWITCHING OPERATING QUIESCENT CURRENT (VIN) vs INPUT VOLTAGE SLOW START CHARGE CURRENT vs TEMPERATURE 150 125 150 2.5 ISS − Slow Start Charge Current − µA Non-Switching Operating Quiescent Current − µA 125 TJ − Junction Temperature − °C °C 800 TJ = −40°C 700 TJ = −25°C TJ = 150°C 600 500 2.4 2.3 2.2 2.1 −50 400 3 6 9 12 −25 15 0 25 50 75 100 TJ − Junction Temperature − °C VI − Input Voltage − V Figure 9. Figure 10. (SS/TR - VSENSE) OFFSET vs TEMPERATURE PWRGD THRESHOLD vs TEMPERATURE 120 PWRGD Threshold Current − µA (SS/TR - Vsense) Offset − V 0.05 0.04 0.03 0.02 0.01 −50 −25 0 25 50 75 100 125 150 VIN = 12 V VSENSE Falling 100 VSENSE Rising 90 80 −50 TJ − Junction Temperature − °C VSENSE Falling −25 0 25 50 75 100 125 150 TJ − Junction Temperature − °C Figure 11. 8 VSENSE Rising 110 Figure 12. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 TPS54620 www.ti.com SLVS949A – MAY 2009 – REVISED JANUARY 2010 TYPICAL CHARACTERISTICS (continued) HIGH-SIDE CURRENT LIMIT THRESHOLD vs INPUT VOLTAGE MINIMUM CONTROLLABLE ON TIME vs TEMPERATURE 120 Minimum Controllable On Time − ns IcI − Current Limit Threshold − A 13 12 11 10 TJ = −40°C 9 TJ = 25°C TJ = 150°C 8 7 6 5 9 13 110 100 90 80 70 −50 5 1 VIN = 12 V IOUT = 2A 17 −25 0 25 50 75 100 125 150 TJ − Junction Temperature − °C VI − Input Voltage − V Figure 14. MINIMUM CONTROLLABLE DUTY RATIO vs JUNCTION TEMPERATURE BOOT-PH UVLO THRESHOLD vs TEMPERATURE Ω BOOT-PH UVLO Threshold – V Figure 13. °C Figure 15. Figure 16. OVERVIEW The device is a 17-V, 6-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs. To improve performance during line and load transients the device implements a constant frequency, peak current mode control which also simplifies external frequency compensation. The wide switching frequency of 200 kHz to 1600 kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The device also has an internal phase lock loop (PLL) controlled by the RT/CLK pin that can be used to synchronize the switching cycle to the falling edge of an external system clock. The device has been designed for safe monotonic startup into pre-biased loads. The default start up is when VIN is typically 4.0V. The EN pin has an internal pull-up current source that can be used to adjust the input voltage under voltage lockout (UVLO) with two external resistors. In addition, the EN pin can be floating for the device to operate with the internal pull-up current. The total operating current for the device is approximately 600mA when not switching and under no load. When the device is disabled, the supply current is typically less than 2mA. The integrated MOSFETs allow for high efficiency power supply designs with continuous output currents up to 6 amperes. The MOSFETs have been sized to optimize efficiency for lower duty cycle applications. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 9 TPS54620 SLVS949A – MAY 2009 – REVISED JANUARY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) The device reduces the external component count by integrating the boot recharge circuit. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor between the BOOT and PH pins. The boot capacitor voltage is monitored by a BOOT to PH UVLO (BOOT-PH UVLO) circuit allowing PH pin to be pulled low to recharge the boot capacitor. The device can operate at 100% duty cycle as long as the boot capacitor voltage is higher than the preset BOOT-PH UVLO threshold which is typically 2.1V. The output voltage can be stepped down to as low as the 0.8V voltage reference (Vref). The device has a power good comparator (PWRGD) with hysteresis which monitors the output voltage through the VSENSE pin. The PWRGD pin is an open drain MOSFET which is pulled low when the VSENSE pin voltage is less than 91% or greater than 109% of the reference voltage Vref and asserts high when the VSENSE pin voltage is 94% to 106% of the Vref. The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing during power up. A small value capacitor or resistor divider should be coupled to the pin for slow start or critical power supply sequencing requirements. The device is protected from output overvoltage, overload and thermal fault conditions. The device minimizes excessive output overvoltage transients by taking advantage of the overvoltage circuit power good comparator. When the overvoltage comparator is activated, the high-side MOSFET is turned off and prevented from turning on until the VSENSE pin voltage is lower than 106% of the Vref. The device implements both high-side MOSFET overload protection and bidirectional low-side MOSFET overload protections which help control the inductor current and avoid current runaway. The device also shuts down if the junction temperature is higher than thermal shutdown trip point. The device is restarted under control of the slow start circuit automatically when the junction temperature drops 10°C typically below the thermal shutdown trip point. DETAILED DESCRIPTION Fixed Frequency PWM Control The device uses a adjustable fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output is converted into a current reference which compares to the high-side power switch current. When the power switch current reaches current reference generated by the COMP voltage level the high-side power switch is turned off and the low-side power switch is turned on. Continuous Current Mode Operation (CCM) As a synchronous buck converter, the device normally works in CCM (Continuous Conduction Mode) under all load conditions. VIN and Power VIN Pins (VIN and PVIN) The device allows for a variety of applications by using the VIN and PVIN pins together or separately. The VIN pin voltage supplies the internal control circuits of the device. The PVIN pin voltage provides the input voltage to the power converter system. If tied together, the input voltage for VIN and PVIN can range from 4.5V to 17V. If using the VIN separately from PVIN, the VIN pin must be between 4.5V and 17V, and the PVIN pin can range from as low as 1.6V to 17V. A voltage divider connected to the EN pin can adjust the either input voltage UVLO appropriately. Adjusting the input voltage UVLO on the PVIN pin helps to provide consistent power up behavior. Voltage Reference The voltage reference system produces a precise ±1% voltage reference over temperature by scaling the output of a temperature stable bandgap circuit. 10 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 TPS54620 www.ti.com SLVS949A – MAY 2009 – REVISED JANUARY 2010 Adjusting the Output Voltage The output voltage is set with a resistor divider from the output (VOUT) to the VSENSE pin. It is recommended to use 1% tolerance or better divider resistors. Referring to the application schematic of Figure 34, start with a 10 kΩ for R6 and use Equation 1 to calculate R5. To improve efficiency at light loads consider using larger value resistors. If the values are too high the regulator is more susceptible to noise and voltage errors from the VSENSE input current are noticeable. Vo - Vref R5 = R6 Vref (1) Where Vref = 0.8V The minimum output voltage and maximum output voltage can be limited by the minimum on time of the high-side MOSFET and bootstrap voltage (BOOT-PH voltage) respectively. More discussions are located in Minimum Output Voltage and Bootstrap Voltage (BOOT) and Low Dropout Operation. Safe Start-up into Pre-Biased Outputs The device has been designed to prevent the low-side MOSFET from discharging a pre-biased output. During monotonic pre-biased startup, the low-side MOSFET is not allowed to sink current until the SS/TR pin voltage is higher than 1.4V. Error Amplifier The device uses a transconductance error amplifier. The error amplifier compares the VSENSE pin voltage to the lower of the SS/TR pin voltage or the internal 0.8V voltage reference. The transconductance of the error amplifier is 1300 mA/V during normal operation. The frequency compensation network is connected between the COMP pin and ground. Slope Compensation The device adds a compensating ramp to the switch current signal. This slope compensation prevents sub-harmonic oscillations. The available peak inductor current remains constant over the full duty cycle range. Enable and Adjusting Under-Voltage Lockout The EN pin provides electrical on/off control of the device. Once the EN pin voltage exceeds the threshold voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching and enters low Iq state. The EN pin has an internal pull-up current source, allowing the user to float the EN pin for enabling the device. If an application requires controlling the EN pin, use open drain or open collector output logic to interface with the pin. The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 150mV. If an application requires either a higher UVLO threshold on the VIN pin or a secondary UVLO on the PVIN, in split rail applications, then the EN pin can be configured as shown in Figure 17, Figure 18 and Figure 19. When using the external UVLO function it is recommended to set the hysteresis to be greater than 500mV. The EN pin has a small pull-up current Ip which sets the default state of the pin to enable when no external components are connected. The pull-up current is also used to control the voltage hysteresis for the UVLO function since it increases by Ih once the EN pin crosses the enable threshold. The UVLO thresholds can be calculated using Equation 2 and Equation 3. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 11 TPS54620 SLVS949A – MAY 2009 – REVISED JANUARY 2010 www.ti.com TPS54620 VIN ip ih R1 R2 EN Figure 17. Adjustable VIN Under Voltage Lock Out TPS54620 PVIN ip ih R1 R2 EN Figure 18. Adjustable PVIN Under Voltage Lock Out, VIN ≥ 4.5V TPS54620 PVIN VIN ip ih R1 R2 EN Figure 19. Adjustable VIN and PVIN Under Voltage Lock Out æV ö VSTART ç ENFALLING ÷ - VSTOP V è ENRISING ø R1 = æ VENFALLING ö Ip ç1 ÷ + Ih VENRISING ø è R2 = VSTOP (2) R1´ VENFALLING - VENFALLING + R1(Ip + Ih ) (3) Where Ih = 3.4 mA, Ip = 1.15 mA, VENRISING = 1.21 V, VENFALLING = 1.17 V Adjustable Switching Frequency and Synchronization (RT/CLK) The RT/CLK pin can be used to set the switching frequency of the device in two modes. 12 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 TPS54620 www.ti.com SLVS949A – MAY 2009 – REVISED JANUARY 2010 In RT mode, a resistor (RT resistor) is connected between the RT/CLK pin and GND. The switching frequency of the device is adjustable from 200 kHz to 1600 kHz by placing a maximum of 240 kΩ and minimum of 29 kΩ respectively. In CLK mode, an external clock is connected directly to the RT/CLK pin. The device is synchronized to the external clock frequency with PLL. The CLK mode overrides the RT mode. The device is able to detect the proper mode automatically and switch from the RT mode to CLK mode. Adjustable Switching Frequency (RT Mode) To determine the RT resistance for a given switching frequency, use Equation 4 or the curve in Figure 20. To reduce the solution size one would set the switching frequency as high as possible, but tradeoffs of the supply efficiency and minimum controllable on time should be considered. - 0.997 Rrt(k W ) = 48000 × Fsw (kHz ) -2 (4) RT − Resistance − kΩ 250 200 150 100 50 0 200 400 600 800 1000 1200 1400 1600 Fsw − Oscillator Frequency − kHz Figure 20. RT Set Resistor vs Switching Frequency Synchronization (CLK mode) An internal Phase Locked Loop (PLL) has been implemented to allow synchronization between 200kHz and 1600kHz, and to easily switch from RT mode to CLK mode. To implement the synchronization feature, connect a square wave clock signal to the RT/CLK pin with a duty cycle between 20% to 80%. The clock signal amplitude must transition lower than 0.8V and higher than 2.0V. The start of the switching cycle is synchronized to the falling edge of RT/CLK pin. In applications where both RT mode and CLK mode are needed, the device can be configured as shown in Figure 21. Before the external clock is present, the device works in RT mode and the switching frequency is set by RT resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the SYNC pin is pulled above the RT/CLK high threshold (2.0V), the device switches from the RT mode to the CLK mode and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. It is not recommended to switch from the CLK mode back to the RT mode because the internal switching frequency drops to 100kHz first before returning to the switching frequency set by RT resistor. RT/CLK mode select TPS54620 RT/CLK Rrt Figure 21. Works with Both RT mode and CLK mode Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 13 TPS54620 SLVS949A – MAY 2009 – REVISED JANUARY 2010 www.ti.com Slow Start (SS/TR) The device uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow start time. The device has an internal pull-up current source of 2.3mA that charges the external slow start capacitor. The calculations for the slow start time (Tss, 10% to 90%) and slow start capacitor (Css) are shown in Equation 5. The voltage reference (Vref) is 0.8 V and the slow start charge current (Iss) is 2.3mA. Tss(ms) = Css(nF) ´ Vref(V) Iss(m A) (5) When the input UVLO is triggered, the EN pin is pulled below 1.21V, or a thermal shutdown event occurs the device stops switching and enters low current operation. At the subsequent power up, when the shutdown condition is removed, the device does not start switching until it has discharged its SS/TR pin to ground ensuring proper soft start behavior. Power Good (PWRGD) The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 106% of the internal voltage reference the PWRGD pin pull-down is de-asserted and the pin floats. It is recommended to use a pull-up resistor between the values of 10kΩ and 100kΩ to a voltage source that is 5.5V or less. The PWRGD is in a defined state once the VIN input voltage is greater than 1V but with reduced current sinking capability. The PWRGD achieves full current sinking capability once the VIN input voltage is above 4.5V. The PWRGD pin is pulled low when VSENSE is lower than 91% or greater than 109% of the nominal internal reference voltage. Also, the PWRGD is pulled low, if the input UVLO or thermal shutdown are asserted, the EN pin is pulled low or the SS/TR pin is below 1.4V. Bootstrap Voltage (BOOT) and Low Dropout Operation The device has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH pins to provide the gate drive voltage for the high-side MOSFET. The boot capacitor is charged when the BOOT pin voltage is less than VIN and BOOT-PH voltage is below regulation. The value of this ceramic capacitor should be 0.1mF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10V or higher is recommended because of the stable characteristics over temperature and voltage. To improve drop out, the device is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is greater than the BOOT-PH UVLO threshold which is typically 2.1V. When the voltage between BOOT and PH drops below the BOOT-PH UVLO threshold the high-side MOSFET is turned off and the low-side MOSFET is turned on allowing the boot capacitor to be recharged. In applications with split input voltage rails 100% duty cycle operation can be achieved as long as (VIN – PVIN) > 4V. Sequencing (SS/TR) Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD pins. The sequential method is illustrated in Figure 22 using two TPS54620 devices. The power good of the first device is coupled to the EN pin of the second device which enables the second power supply once the primary supply reaches regulation. Figure 23 shows the results of Figure 22. 14 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 TPS54620 www.ti.com SLVS949A – MAY 2009 – REVISED JANUARY 2010 PWRGD = 2 V / div TPS54620 TPS54620 EN PWRGD EN EN = 2 V / div Vout1 = 1 V / div SS/TR SS/TR Vout2 = 1 v / div PWRGD Time = 20 msec / div Figure 22. Sequential Start Up Sequence Figure 23. Sequential Start Up using EN and PWRGD Figure 24 shows the method implementing ratio-metric sequencing by connecting the SS/TR pins of two devices together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow start time the pull-up current source must be doubled in Equation 5. Figure 25 shows the results of Figure 24. . TPS54620 EN EN = 2 V / div SS/TR PWRGD Vout1 = 1 V / div Vout2 = 1 v / div TPS54620 EN Time = 20 msec / div SS/TR Figure 25. Ratio-metric Startup using Coupled SS/TR Pins PWRGD . Figure 24. Ratiometric Start Up Sequence Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 26 to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 6 and Equation 7, the tracking resistors can be calculated to initiate the Vout2 slightly before, after or at the same time as Vout1. Equation 8 is the voltage difference between Vout1 and Vout2. To design a ratio-metric start up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2 reaches regulation, use a negative number in Equation 6 and Equation 7 for deltaV. Equation 8 results in a positive number for applications where the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved. Figure 27 and Figure 28 show the results for positive deltaV and negative deltaV respectively. The deltaV variable is zero volt for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE offset (Vssoffset, 29mV) in the slow start circuit and the offset created by the pull-up current source (Iss, 2.3mA) and tracking resistors, the Vssoffset and Iss are included as variables in the equations. Figure 29 shows the result when deltaV = 0V. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 15 TPS54620 SLVS949A – MAY 2009 – REVISED JANUARY 2010 www.ti.com To ensure proper operation of the device, the calculated R1 value from Equation 6 must be greater than the value calculated in Equation 9. R1 = Vout2 + D V Vssoffset ´ Vref Iss (6) Vref ´ R1 R2 = Vout2 + DV - Vref DV = Vout1 - Vout2 R1 > 2800 ´ Vout1- 180 ´ DV (7) (8) (9) TPS54620 EN VOUT1 SS/TR PWRGD TPS54620 EN VOUT 2 R1 SS/TR R2 PWRGD R4 R3 Figure 26. Ratiometric and Simultaneous Startup Sequence EN = 2 V / div Vout1 = 1 V / div Vout2 = 1 V / div Time = 20 msec / div Figure 27. Ratio-metric Startup with Vout1 Leading Vout2 16 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 TPS54620 www.ti.com SLVS949A – MAY 2009 – REVISED JANUARY 2010 EN = 2 V / div Vout1 = 1 V / div Vout2 = 1 V / div Time = 20 msec / div Figure 28. Ratio-metric Startup with Vout2 Leading Vout1 EN = 2 V / div Vout1 = 1 V / div Vout2 = 1 V / div Time = 20 msec / div Figure 29. Simultaneous Startup Output Overvoltage Protection (OVP) The device incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot. For example, when the power supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier demands maximum output current. Once the condition is removed, the regulator output rises and the error amplifier output transitions to the steady state voltage. In some applications with small output capacitance, the power supply output voltage can respond faster than the error amplifier. This leads to the possibility of an output overshoot. The OVP feature minimizes the overshoot by comparing the VSENSE pin voltage to the OVP threshold. If the VSENSE pin voltage is greater than the OVP threshold the high-side MOSFET is turned off preventing current from flowing to the output and minimizing output overshoot. When the VSENSE voltage drops lower than the OVP threshold, the high-side MOSFET is allowed to turn on at the next clock cycle. Overcurrent Protection The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side MOSFET and the low-side MOSFET. High-side MOSFET overcurrent protection The device implements current mode control which uses the COMP pin voltage to control the turn off of the high-side MOSFET and the turn on of the low-side MOSFET on a cycle by cycle basis. Each cycle the switch current and the current reference generated by the COMP pin voltage are compared, when the peak switch current intersects the current reference the high-side switch is turned off. Low-side MOSFET overcurrent protection Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 17 TPS54620 SLVS949A – MAY 2009 – REVISED JANUARY 2010 www.ti.com While the low-side MOSFET is turned on its conduction current is monitored by the internal circuitry. During normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side sourcing current is exceeded the high-side MOSFET is not turned on and the low-side MOSFET stays on for the next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing current limit at the start of a cycle. The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded the low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are off until the start of the next cycle. Thermal Shutdown The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds 175°C typically. The device reinitiates the power up sequence when the junction temperature drops below 165°C typically. Small Signal Model for Loop Response Figure 30 shows an equivalent model for the device control loop which can be modeled in a circuit simulation program to check frequency response and transient responses. The error amplifier is a transconductance amplifier with a gm of 1300mA/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor Roea (2.38 MΩ) and capacitor Coea (20.7 pF) model the open loop gain and frequency response of the error amplifier. The 1-mV ac voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. Plotting a/c and c/b show the small signal responses of the power stage and frequency compensation respectively. Plotting a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by replacing the RL with a current source with the appropriate load step amplitude and step rate in a time domain analysis. PH VOUT Power Stage 16 A/V a b c 0.8 V R3 Coea C2 R1 RESR VSENSE CO COMP C1 Roea gm 1300 mA/V RL R2 Figure 30. Small Signal Model for Loop Response Simple Small Signal Model for Peak Current Mode Control Figure 31 is a simple small signal model that can be used to understand how to design the frequency compensation. The device power stage can be approximated to a voltage controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 10 and consists of a dc gain, one dominant pole and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 30) is the power stage transconductance (gmps) which is 16 A/V for the device. The DC gain of the power stage is the product of gmps and the load resistance ®L) as shown in Equation 11 with resistive loads. As the load current increases, the DC gain decreases. This variation with load may seem problematic at first glance, but fortunately the dominant pole moves with load current (see Equation 12). The combined effect is highlighted by the dashed line in Figure 32. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions which makes it easier to design the frequency compensation. 18 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 TPS54620 www.ti.com SLVS949A – MAY 2009 – REVISED JANUARY 2010 VOUT VC RESR RL gm ps CO Figure 31. Simplified Small Signal Model for Peak Current Mode Control VOUT Adc VC RESR fp RL gm ps CO fz Figure 32. Simplified Frequency Response for Peak Current Mode Control æ ç1+ 2p VOUT = Adc ´ è VC æ ç1+ è 2p ö s ÷ ´ ¦z ø ö s ÷ ´ ¦p ø (10) Adc = gmps ´ RL (11) 1 ¦p = C O ´ R L ´ 2p ¦z = (12) 1 CO ´ RESR ´ 2p (13) Where gmea is the GM amplifier gain ( 1300mA/V) gmps is the power stage gain (16A/V). RL is the load resistance CO is the output capacitance. RESR is the equivalent series resistance of the output capacitor. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 19 TPS54620 SLVS949A – MAY 2009 – REVISED JANUARY 2010 www.ti.com Small Signal Model for Frequency Compensation The device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used frequency compensation circuits shown in Figure 33. In Type 2A, one additional high frequency pole is added to attenuate high frequency noise. The design guideline below are provided for advanced users who prefer to compensate using the general method. The step-by-step design procedure described in the application section may also be used. VOUT R1 VSENSE COMP Type 2A Type 2B Vref R2 gm ea Roea R3 Coea R3 C2 C1 C1 Figure 33. Types of Frequency Compensation The general design guidelines for device loop compensation are as follows 1. Determine the crossover frequency fc 2. R3 can be determined by 2p ´ ¦ c ´ VOUT ´ Co R3 = gmea ´ Vref ´ gmps (14) Where gmea is the GM amplifier gain ( 1300mA/V) gmps is the power stage gain (16A/V). Vref is the reference voltage (0.8V) æ ö 1 ç ¦p = ÷ CO ´ RL ´ 2p ø . 3. Place a compensation zero at the dominant pole è C1 can be determined by R ´ Co C1 = L R3 (15) 4. C2 is optional. It can be used to cancel the zero from the ESR (Equivalent Series Resistance) of the output capacitor Co. R ´ Co C2 = ESR R3 (16) 20 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 TPS54620 www.ti.com SLVS949A – MAY 2009 – REVISED JANUARY 2010 APPLICATION INFORMATION Design Guide – Step-By-Step Design Procedure This example details the design of a high frequency switching regulator design using ceramic output capacitors. A few parameters must be known in order to start the design process. These parameters are typically determined at the system level. For this example, we start with the following known parameters: Table 1. Parameter Value Output Voltage 3.3 V Output Current 6A Transient Response 1A load step ΔVout = 5 % Input Voltage 12 V nominal, 8 V to 17 V Output Voltage Ripple 33 mV p-p Start Input Voltage (Rising Vin) 6.528 V Stop Input Voltage (Falling Vin) 6.190 V Switching Frequency 480 kHz Typical Application Schematic The application schematic of Figure 34 was developed to meet the requirements above. This circuit is available as the TPS54620EVM-374 evaluation module. The design procedure is given in this section. Figure 34. Typical Application Circuit Operating Frequency The first step is to decide on a switching frequency for the regulator. There is a trade off between higher and lower switching frequencies. Higher switching frequencies may produce smaller a solution size using lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. However, the higher switching frequency causes extra switching losses, which hurt the converter’s efficiency and thermal performance. In this design, a moderate switching frequency of 480 kHz is selected to achieve both a small solution size and a high efficiency operation. Output Inductor Selection To calculate the value of the output inductor, use Equation 17. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer; however, KIND is normally from 0.1 to 0.3 for the majority of applications. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 21 TPS54620 SLVS949A – MAY 2009 – REVISED JANUARY 2010 L1 = www.ti.com Vinm ax - Vout Vout × Io × Kind Vinm ax × f sw (17) For this design example, use KIND = 0.3 and the inductor value is calculated to be 3.08 µH. For this design, a nearest standard value was chosen: 3.3 µH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation 19 and Equation 20. Vinmax - Vout Vout × Iripple = L1 Vinmax × f sw (18) ILrms = Io2 + 1 æ Vo × (Vinmax - Vo ) ö ×ç ÷ 12 çè Vinmax × L1× f sw ÷ø 2 Iripple ILpeak = Iout + 2 (19) (20) For this design, the RMS inductor current is 6.02 A and the peak inductor current is 6.84 A. The chosen inductor is a Coilcraft MSS1048 series 3.3 µH. It has a saturation current rating of 7.38 A and a RMS current rating of 7.22 A. The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current. Output Capacitor Selection There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance needs to be selected based on the more stringent of these three criteria The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the load with current when the regulator can not. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator is also temporarily not able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 21 shows the minimum output capacitance necessary to accomplish this. 2 × DIout Co > f sw × DVout (21) Where ΔIout is the change in output current, Fsw is the regulators switching frequency and ΔVout is the allowable change in the output voltage. For this example, the transient load response is specified as a 5% change in Vout for a load step of 1A. For this example, ΔIout = 1.0 A and ΔVout= 0.05 x 3.3 = 0.165 V. Using these numbers gives a minimum capacitance of 25 mF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Equation 22 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where fsw is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the inductor ripple current. In this case, the maximum output voltage ripple is 33mV. Under this requirement, Equation 22 yields 13.2µF. 22 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 TPS54620 www.ti.com Co > SLVS949A – MAY 2009 – REVISED JANUARY 2010 1 1 × 8 × f sw Voripple Iripple (22) Equation 23 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 23 indicates the ESR should be less than 19.7 mΩ. In this case, the ceramic caps’ ESR is much smaller than 19.7 mΩ. Voripple Resr < Iripple (23) Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this minimum value. For this example, a 47 mF 6.3V X5R ceramic capacitor with 3 mΩ of ESR is be used. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 24 can be used to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 24 yields 485mA. Vout × (Vinmax - Vout ) Icorms = 12 × Vinmax × L1× f sw (24) Input Capacitor Selection The TPS54620 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7 µF of effective capacitance on the PVIN input voltage pins and 4.7 µF on the Vin input voltage pin. In some applications additional bulk capacitance may also be required for the PVIN input. The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54620. The input ripple current can be calculated using Equation 25. Icirms = Iout × Vout (Vinmin - Vout ) × Vinmin Vinmin (25) The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at least a 25 V voltage rating is required to support the maximum input voltage. For this example, one 10 mF and one 4.7 µF 25 V capacitors in parallel have been selected as the VIN and PVIN inputs are tied together so the TPS54620 may operate from a single supply. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 26. Using the design example values, Ioutmax=6 A, Cin=14.7 mF, Fsw=480 kHz, yields an input voltage ripple of 213 mV and a RMS input ripple current of 2.95 A. Ioutmax × 0.25 DVin = Cin × f sw (26) Slow Start Capacitor Selection The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is very large and would require large amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the TPS54620 reach the current limit or excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The soft start capacitor value can be calculated using Equation 27. For the example circuit, the soft start time is not too critical since the output capacitor value is 47 mF which does not require much current to charge to 3.3 V. The example circuit has the soft start time set to an arbitrary value of 3.5 ms which requires a 10 nF capacitor. In TPS54620, Iss is 2.3 uA and Vref is 0.8V. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 23 TPS54620 SLVS949A – MAY 2009 – REVISED JANUARY 2010 C7(nF) = www.ti.com Tss(ms) × Iss( m A ) Vref ( V ) (27) Bootstrap Capacitor Selection A 0.1 µF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10V or higher voltage rating. Under Voltage Lockout Set Point The Under Voltage Lock Out (UVLO) can be adjusted using the external voltage divider network of R3 and R4. R3 is connected between VIN and the EN pin of the TPS54620 and R4 is connected between EN and GND . The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage increases above 6.528V (UVLO start or enable). After the regulator starts switching, it should continue to do so until the input voltage falls below 6.190 V (UVLO stop or disable). Equation 2 and Equation 3 can be used to calculate the values for the upper and lower resistor values. For the stop voltages specified the nearest standard resistor value for R3 is 35.7 kΩ and for R4 is 8.06 kΩ. Output Voltage Feedback Resistor Selection The resistor divider network R5 and R6 is used to set the output voltage. For the example design, 10 kΩ was selected for R6. Using Equation 28, R5 is calculated as 31.25 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Vo - Vref R5 = R6 Vref (28) Minimum Output Voltage Due to the internal design of the TPS54620, there is a minimum output voltage limit for any given input voltage. The output voltage can never be lower than the internal voltage reference of 0.8 V. Above 0.8 V, the output voltage may be limited by the minimum controllable on time. The minimum output voltage in this case is given by Equation 29 Voutmin = Ontimemin × Fsmax (Vinmax + Ioutmin (RDS2min - RDS1min ))- Ioutmin (RL + RDS2min ) Where: Voutmin = minimum achievable output voltage Ontimemin = minimum controllable on-time (135 nsec maximum) Fsmax = maximum switching frequency including tolerance Vinmax = maximum input voltage Ioutmin = minimum load current RDS1min = minimum high side MOSFET on resistance (36-32 mΩ typical) RDS2min = minimum low side MOSFET on resistance (19 mΩ typical) RL = series resistance of output inductor (29) Compensation Component Selection There are several industry techniques used to compensate DC/DC regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54620. Since the slope compensation is ignored, the actual cross over frequency is usually lower than the cross over frequency used in the calculations. Use SwitcherPro software for a more accurate design. First, the modulator pole, fpmod, and the esr zero, fzmod must be calculated using Equation 30 and Equation 31. For Cout, use a derated value of 22.4 µF. use Equation 32 and Equation 33 to estimate a starting point for the closed loop crossover frequency fco. Then the required compensation components may be derived. For this 24 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 TPS54620 www.ti.com SLVS949A – MAY 2009 – REVISED JANUARY 2010 design example, fpmod is 12.9 kHz and fzmod is 2730 kHz. Equation 32 is the geometric mean of the modulator pole and the esr zero and Equation 33 is the geometric mean of the modulator pole and one half the switching frequency. Use a frequency near the lower of these two values as the intended crossover frequency fco. In this case Equation 32 yields 175 kHz and Equation 33 yields 55.7 kHz. The lower value is 55.7 kHz. A slightly higher frequency of 60.5 kHz is chosen as the intended crossover frequency. Iout f pmod = 2 × p × Vout × Cout (30) f zm od = 1 2 × p × RESR × Cout f co = f pmod × f zmod f co = f pmod × (31) (32) f sw 2 (33) Now the compensation components can be calculated. First calculate the value for R2 which sets the gain of the compensated network at the crossover frequency. Use Equation 34 to determine the value of R2. 2p × f c × Vout × Cout R2 = gmea × Vref × gmps (34) Next calculate the value of C3. Together with R2, C3 places a compensation zero at the modulator pole frequency. Equation 35 to determine the value of C3. Vout × Cout C3 = Iout × R2 (35) Using Equation 34 and Equation 35 the standard values for R2 and C3 are 1.69 kΩ and 8200 pF. An additional high frequency pole can be used if necessary by adding a capacitor in parallel with the series combination of R2 and C3. The pole frequency is given by Equation 36. This pole is not used in this design. 1 fp = 2 × p × R2 × Cp (36) Application Curves LOAD TRANSIENT STARTUP with VIN Vin = 10 V / div Vout = 50 mV / div (ac coupled) EN = 2 V / div Iout = 2A / div (1.5 A to 4.5 load step) SS/TR = 1 V / div Vout = 2 V / div Time = 500 μsec / div Time = 2 msec / div Figure 35. Figure 36. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 25 TPS54620 SLVS949A – MAY 2009 – REVISED JANUARY 2010 www.ti.com STARTUP with EN STARTUP with PRE-BIAS Vin = 5 V / div Vin = 10 V / div EN = 2 V / div Vout = 2 V / div SS/TR = 1 V / div Vout starting from pre-bias voltage Vout = 2 V / div Time = 2 msec / div Time = 20 msec / div Figure 37. Figure 38. SHUTDOWN with VIN SHUTDOWN with EN Vin = 10 V / div Vin = 10 V / div EN = 2 V / div EN = 2 V / div SS/TR = 1 V / div SS/TR = 1 V / div Vout = 2 V / div Vout = 2 V / div Time = 2 msec / div Time = 2 msec / div Figure 39. Figure 40. OUTPUT VOLTAGE RIPPLE with NO LOAD OUTPUT VOLTAGE RIPPLE with FULL LOAD Vout = 10 mV / div (ac coupled) Vout = 10 mV / div (ac coupled) PH = 5 V / div PH = 5 V / div Time = 1 μsec / div Time = 1 μsec / div Figure 41. 26 Figure 42. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 TPS54620 www.ti.com SLVS949A – MAY 2009 – REVISED JANUARY 2010 INPUT VOLTAGE RIPPLE with NO LOAD INPUT VOLTAGE RIPPLE with FULL LOAD Vin = 200 mV / div (ac coupled) Vin = 200 mV / div (ac coupled) PH = 5 V / div PH = 5 V / div Time = 1 μsec / div Time = 1 μsec / div Figure 43. Figure 44. CLOSED LOOP RESPONSE LINE REGULATION 0.05 180 60 150 50 40 0.04 120 Phase 60 Gain 10 30 0 0 -30 -10 -60 -20 -30 -90 -40 -120 -50 -150 -60 -180 Percent Regulation - % 90 20 Phase - Deg Gain - dB 0.03 30 0.02 0.01 0 Io = 0A Io = 3A -0.01 -0.02 -0.03 Io = 6A -0.04 1000000 100000 10000 1000 100 10 Frequency - Hz -0.05 8 9 10 11 12 13 14 15 16 17 Input Voltage - V Figure 45. Figure 46. LOAD REGULATION TRACKING PERFORMANCE 10 0.05 10 Vin = 12 V Vout 0.04 1 1 0.02 0.01 0 -0.01 0.1 0.1 Ideal Vsense Vsense 0.01 0.01 0.001 0.001 0.0001 0.0001 Vsense Voltage - V Output Voltage - V Percent Regulation - % 0.03 -0.02 -0.03 -0.04 0.00001 0.001 -0.05 0 1 2 3 4 5 Output Current - A 6 7 8 Figure 47. 0.00001 0.01 0.1 1 10 Track In Voltage - V Figure 48. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 27 TPS54620 SLVS949A – MAY 2009 – REVISED JANUARY 2010 www.ti.com MAXIMUM AMBIENT TEMPERATURE vs LOAD CURRENT MAXIMUM AMBIENT TEMPERATURE vs IC POWER DISSIPATION 150 TA - Maximum Ambient Temperature - °C TA - Maximum Ambient Temperature - °C 150 125 125 100 100 75 VIN = 12 V, VOUT = 3.3 V, Fsw = 480 kHz, room temp, no air flow 50 75 50 25 25 0 1 2 3 4 Load Current - A 5 0 6 0.5 1 1.5 2 2.5 3 3.5 PD - IC Power Dissipation - W Figure 49. Figure 50. JUNCTION TEMPERATURE vs IC POWER DISSIPATION EFFICIENCY vs LOAD CURRENT 150 4 100 TA = room temperature, no air flow 95 125 90 85 Efficiency - % TJ - Junction Temperature - °C Tjmax = 150 °C, no air flow 100 75 80 VOUT = 5 V 75 VOUT = 3.3 V 70 VOUT = 1.8 V 65 VOUT = 1.2 V 50 60 VIN = 12 V Fsw = 500 kHz 55 25 VOUT = 0.8 V 50 0 0.5 1 1.5 2 2.5 3 3.5 Pic - IC Power Dissipation - W 4 Figure 51. 0 1 3 2 4 Load Current - A 5 6 Figure 52. Thermal Performance Figure 53. Thermal Signature of TPS54620EVM-374 Operating at VIN=12V,VOUT=3.3V/6A, TA = Room Temperature 28 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 TPS54620 www.ti.com SLVS949A – MAY 2009 – REVISED JANUARY 2010 Fast Transient Considerations In applications where fast transient responses are very important, the application circuit in Figure 34 can be modified as shown in Figure 54 which is a customized reference design (PMP4854-2, REV.B). The frequency responses of Figure 54 is shown in Figure 55. The crossover frequency is pushed much higher to 118kHz and the phase margin is about 57Deg. Figure 54. 3.3V Output Power Supply Design (PMP4854-2) with Fast Transients Figure 55. Closed Loop Response for PMP4854-2 PCB Layout Guidelines Layout is a critical portion of good power supply design. See Figure 56 for a PCB layout example. The top layer contains the main power traces for VIN, VOUT, and VPHASE. Also on the top layer are connections for the remaining pins of the TPS54620 and a large top side area filled with ground. The top layer ground area should be connected to the internal ground layer(s) using vias at the input bypass capacitor, the output filter capacitor and directly under the TPS54620 device to provide a thermal path from the exposed thermal pad land to ground. The GND pin should be tied directly to the power pad under the IC and the power pad. For operation at full rated load, the top side ground area together with the internal ground plane, must provide adequate heat dissipating area. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the PVIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the PVIN pins, and the ground connections. The VIN pin must also be bypassed to ground using a Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 29 TPS54620 SLVS949A – MAY 2009 – REVISED JANUARY 2010 www.ti.com low ESR ceramic capacitor with X5R or X7R dielectric. Make sure to connect this capacitor to the quite analog ground trace rather than the power ground trace of the PVIn bypass capacitor. Since the PH connection is the switching node, the output inductor should be located close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The output filter capacitor ground should use the same power ground trace as the PVIN input bypass capacitor. Try to minimize this conductor length while maintaining adequate width. The small signal components should be grounded to the analog ground path as shown. The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce good results and is meant as a guideline. Land pattern and stencil information is provided in the data sheet addendum. The dimension and outline information is for the standard RGY (S-PVQFN-N14) package. There may be slight differences between the provided data and actual lead frame used on the TPS54620RGY package. TOPSIDE GROUND AREA FREQUENCY SET RESISTOR PVIN INPUT BYPASS CAPACITOR RT/CLK OUTPUT FILTER CAPACITOR PWRGD GND BOOT CAPACITOR BOOT EXPOSED THERMAL PAD AREA GND OUTPUT INDUCTOR PH PVIN PH PVIN EN VIN SS/TR VOUT PH VSENSE PVIN COMP VIN SLOW START CAPACITOR UVLO SET RESISTORS VIN INPUT BYPASS CAPACITOR FEEDBACK RESISTORS COMPENSATION NETWORK ANALOG GROUND TRACE 0.010 in. Diameter Thermal VIA to Ground Plane VIA to Ground Plane Etch Under Component Figure 56. PCB Layout 30 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 TPS54620 www.ti.com SLVS949A – MAY 2009 – REVISED JANUARY 2010 Figure 57. Ultra-Small PCB layout Using TPS54620 (PMP4854-2) Estimated Circuit Area The estimated printed circuit board area for the components used in the design of Figure 34 is 0.58. in2 (374 mm2). This area does not include test points or connectors. The board area can be further reduced if size is a big concern in an application. Figure 57 shows the printed circuit board layout for PMP4854-2 as shown in Figure 54 whose board area is as small as 17.27 mm x 11.30 mm. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 31 TPS54620 SLVS949A – MAY 2009 – REVISED JANUARY 2010 www.ti.com REVISION HISTORY Changes from Original (May 2009) to Revision A Page • Changed title from 17V Input, 6A Output, Synchronous Step Down Switcher with Integrated FET (SWIFT) ...................... 1 • Changed EN max value from 3V to 6V ................................................................................................................................ 2 • Added thermal impedance junction to power pad parameter ............................................................................................... 3 • Added thermal via measurement for foot note d .................................................................................................................. 3 • Changed minimum switching frequency min value from 180 to 160 .................................................................................... 4 • Changed minimum switching frequency max value from 220 to 240 ................................................................................... 4 • Changed PO graphic label from PowerPAD to Exposed Thermal Pad ................................................................................ 5 • Changed PowerPAD to Exposed Thermal Pad .................................................................................................................... 5 • Changed PCB Layout graphic ............................................................................................................................................ 30 32 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPS54620 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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