TI TPS54160DGQR

TPS54160
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SLVS795C – OCTOBER 2008 – REVISED OCTOBER 2010
1.5-A, 60-V, STEP-DOWN
SWIFT™ DC/DC CONVERTER WITH ECO-MODE™
Check for Samples: TPS54160
FEATURES
1
•
•
•
2
•
•
•
•
•
•
•
3.5-V to 60-V Input Voltage Range
200-mΩ High-Side MOSFET
High Efficiency at Light Loads with a Pulse
Skipping Eco-Mode™
116-mA Operating Quiescent Current
1.3-mA Shutdown Current
100-kHz to 2.5-MHz Switching Frequency
Synchronizes to External Clock
Adjustable Slow Start/Sequencing
UV and OV Power Good Output
Adjustable UVLO Voltage and Hysteresis
•
•
•
•
0.8-V Internal Voltage Reference
MSOP-10 Package With PowerPAD™
Supported by SwitcherPro™ Software Tool
(http://focus.ti.com/docs/toolsw/folders/print/s
witcherpro.html)
For SWIFT™ Documentation, See the TI
Website at http://www.ti.com/swift
APPLICATIONS
•
•
12-V, 24-V and 48-V Industrial and Commercial
Low Power Systems
Aftermarket Auto Accessories: Video, GPS,
Entertainment
DESCRIPTION
The TPS54160 device is a 60-V, 1.5-A, step down regulator with an integrated high-side MOSFET. Current mode
control provides simple external compensation and flexible component selection. A low ripple pulse skip mode
reduces the no load, regulated output supply current to 116 mA. Using the enable pin, shutdown supply current is
reduced to 1.3 mA.
Under voltage lockout is internally set at 2.5 V, but can be increased using the enable pin. The output voltage
startup ramp is controlled by the slow start pin that can also be configured for sequencing/tracking. An open
drain power good signal indicates the output is within 93% to 107% of its nominal voltage.
A wide switching frequency range allows efficiency and external component size to be optimized. Frequency fold
back and thermal shutdown protects the part during an overload condition.
The TPS54160 is available in 10-pin thermally enhanced MSOP PowerPAD package.
SIMPLIFIED SCHEMATIC
90
VIN
PWRGD
85
TPS54160
80
BOOT
PH
SS /TR
RT /CLK
COMP
Efficiency (%)
EN
75
70
65
VSENSE
60
GND
VIN = 12 V
VOUT = 3.3 V
fSW = 1200 kHz
55
0
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
Load Current (A)
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Eco-Mode, PowerPAD, SwitcherPro, SWIFT are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2010, Texas Instruments Incorporated
TPS54160
SLVS795C – OCTOBER 2008 – REVISED OCTOBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1. ORDERING INFORMATION (1)
(1)
TJ
PACKAGE
–40°C to 150°C
10-Pin MSOP
TRANSPORT MEDIA
QUANTITY
PART NUMBER
Tube
80
TPS54160DGQ
Tape and Reel
2500
TPS54160DGQR
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating temperature range (unless otherwise noted).
VALUE
VIN
–0.3 to 65
EN (2)
–0.3 to 5
BOOT
Input voltage
73
VSENSE
–0.3 to 3
COMP
–0.3 to 3
PWRGD
–0.3 to 6
SS/TR
–0.3 to 3.6
BOOT-PH
8
PH
–0.6 to 65
PH, 10-ns Transient
Voltage Difference
Source current
V
–2 to 65
PAD to GND
±200
EN
100
mA
BOOT
100
mA
VSENSE
10
mA
PH
RT/CLK
VIN
Sink current
V
–0.3 to 3
RT/CLK
Output voltage
UNIT
mV
Current Limit
A
100
mA
Current Limit
A
COMP
100
mA
PWRGD
10
mA
SS/TR
200
mA
1
kV
Electrostatic Discharge (HBM) QSS 009-105 (JESD22-A114A)
Electrostatic Discharge (CDM) QSS 009-147 (JESD22-C101B.01)
500
V
Operating junction temperature
–40 to 150
°C
Storage temperature
–65 to 150
°C
(1)
(2)
2
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
See the Enable section and Adjusting Undervoltage Lockout section of this datasheet for details.
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SLVS795C – OCTOBER 2008 – REVISED OCTOBER 2010
THERMAL INFORMATION
TPS54160
THERMAL METRIC (1) (2)
DGQ
UNITS
10 PINS
Junction-to-ambient thermal resistance (standard board)
qJA
62.5
(3)
qJA
Junction-to-ambient thermal resistance (custom board)
qJCtop
Junction-to-case (top) thermal resistance
83
qJB
Junction-to-board thermal resistance
28
yJT
Junction-to-top characterization parameter
1.7
yJB
Junction-to-board characterization parameter
20.1
qJCbot
Junction-to-case (bottom) thermal resistance
21
(1)
(2)
(3)
57
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information
Test boards conditions:
(a) 3 inches x 3 inches, 2 layers, thickness: 0.062 inch
(b) 2 oz. copper traces located on the top of the PCB
(c) 2 oz. copper ground plane, bottom layer
(d) 6 thermal vias (13mil) located under the device package
ELECTRICAL CHARACTERISTICS
TJ = –40°C to 150°C, VIN = 3.5 to 60V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
3.5
60
Internal undervoltage lockout
threshold
No voltage hysteresis, rising and falling
2.5
Shutdown supply current
EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 60 V
1.3
4
Operating : nonswitching supply
current
VSENSE = 0.83 V, VIN = 12 V, 25°C
116
136
1.25
1.55
V
V
mA
ENABLE AND UVLO (EN PIN)
Enable threshold voltage
Input current
No voltage hysteresis, rising and falling, 25°C
0.9
Enable threshold +50 mV
–3.8
Enable threshold –50 mV
–0.9
Hysteresis current
V
mA
–2.9
mA
VOLTAGE REFERENCE
Voltage reference
TJ = 25°C
0.792
0.8
0.808
0.784
0.8
0.816
V
HIGH-SIDE MOSFET
On-resistance
VIN = 3.5 V, BOOT-PH = 3 V
300
VIN = 12 V, BOOT-PH = 6 V
200
410
mΩ
ERROR AMPLIFIER
Input current
50
nA
Error amplifier transconductance (gM) –2 mA < ICOMP < 2 mA, VCOMP = 1 V
97
mMhos
Error amplifier transconductance (gM) –2 mA < ICOMP < 2 mA, VCOMP = 1 V,
during slow start
VVSENSE = 0.4 V
26
mMhos
Error amplifier dc gain
VVSENSE = 0.8 V
Error amplifier bandwidth
Error amplifier source/sink
V(COMP) = 1 V, 100-mV overdrive
COMP to switch current
transconductance
10,000
V/V
2700
kHz
±7
mA
6
A/V
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ELECTRICAL CHARACTERISTICS (continued)
TJ = –40°C to 150°C, VIN = 3.5 to 60V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.8
2.7
A
182
°C
CURRENT LIMIT
Current limit threshold
VIN = 12 V, TJ = 25°C
THERMAL SHUTDOWN
Thermal shutdown
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using RT
mode
fSW
Switching frequency
100
RT = 200 kΩ
450
Switching frequency range using
CLK mode
581
300
Minimum CLK input pulse width
40
RT/CLK high threshold
1.9
RT/CLK low threshold
0.5
RT/CLK falling edge to PH rising
edge delay
Measured at 500 kHz with RT resistor in series
PLL lock in time
Measured at 500 kHz
2500
kHz
720
kHz
2200
kHz
ns
2.2
V
0.7
V
60
ns
100
ms
SLOW START AND TRACKING (SS/TR)
Charge current
VSS/TR = 0.4 V
2
mA
SS/TR-to-VSENSE matching
VSS/TR = 0.4 V
45
mV
SS/TR-to-reference crossover
98% nominal
1.0
V
SS/TR discharge current (overload)
VSENSE = 0 V, V(SS/TR) = 0.4 V
112
mA
SS/TR discharge voltage
VSENSE = 0 V
54
mV
VSENSE falling
92%
VSENSE rising
94%
VSENSE rising
109%
VSENSE falling
107%
Hysteresis
VSENSE falling
2%
Output high leakage
VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C
On resistance
I(PWRGD) = 3 mA, VSENSE < 0.79 V
Minimum VIN for defined output
V(PWRGD) < 0.5 V, II(PWRGD) = 100 mA
POWER GOOD (PWRGD PIN)
VVSENSE
4
VSENSE threshold
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10
nA
Ω
50
0.95
1.5
V
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS54160
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SLVS795C – OCTOBER 2008 – REVISED OCTOBER 2010
DEVICE INFORMATION
PIN CONFIGURATION
DGQ PowerPAD PACKAGE
(Top View)
BOOT
1
10
PG
VIN
2
9
GND
EN
3
8
COMP
SS/TR
4
7
VSENSE
RT/CLK
5
6
PWRGD
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
BOOT
1
O
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
minimum required by the output device, the output is forced to switch off until the capacitor is refreshed.
COMP
8
O
Error amplifier output, and input to the output switch current comparator. Connect frequency compensation
components to this pin.
EN
3
I
Enable pin, internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Adjust the input
undervoltage lockout with two resistors.
GND
9
–
Ground
PH
10
I
The source of the internal high-side power MOSFET.
Thermal Pad
11
–
GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation.
PWRGD
6
O
An open drain output, asserts low if output voltage is low due to thermal shutdown, dropout, over-voltage or
EN shut down.
RT/CLK
5
I
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold,
a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and
the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is
re-enabled and the mode returns to a resistor set function.
SS/TR
4
I
Slow-start and Tracking. An external capacitor connected to this pin sets the output rise time. Since the
voltage on this pin overrides the internal reference, it can be used for tracking and sequencing.
VIN
2
I
Input supply voltage, 3.5 V to 60 V.
VSENSE
7
I
Inverting node of the transconductance (gM) error amplifier.
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FUNCTIONAL BLOCK DIAGRAM
PWRGD
6
EN
3
VIN
2
Shutdown
UV
Thermal
Shutdown
Enable
Comparator
Logic
UVLO
Shutdown
Shutdown
Logic
OV
Enable
Threshold
Boot
Charge
Voltage
Reference
Boot
UVLO
Minimum
Clamp
Pulse
Skip
ERROR
AMPLIFIER
PWM
Comparator
VSENSE 7
Current
Sense
1 BOOT
Logic
And
PWM Latch
SS/TR 4
Shutdown
Slope
Compensation
10 PH
COMP 8
11 POWERPAD
Frequency
Shift
Overload
Recovery
Maximum
Clamp
Oscillator
with PLL
TPS54160 Block Diagram
9 GND
5
RT/CLK
6
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SLVS795C – OCTOBER 2008 – REVISED OCTOBER 2010
TYPICAL CHARACTERISTICS
VOLTAGE REFERENCE vs JUNCTION TEMPERATURE
0.816
500
VI = 12 V
VI = 12 V
375
Vref - Voltage Reference - V
RDSON - Static Drain-Source On-State Resistance - mW
ON RESISTANCE vs JUNCTION TEMPERATURE
BOOT-PH = 3 V
250
BOOT-PH = 6 V
125
0
-50
0.808
0.800
0.792
0.784
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
-25
0
150
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 1.
Figure 2.
SWITCH CURRENT LIMIT vs JUNCTION TEMPERATURE
SWITCHING FREQUENCY vs JUNCTION TEMPERATURE
3.5
610
VI = 12 V,
RT = 200 kW
VI = 12 V
fs - Switching Frequency - kHz
Switch Current - A
600
3
2.5
590
580
570
560
2
-50
-25
0
25
50
75
100
125
550
-50
150
-25
0
TJ - Junction Temperature - °C
25
50
75
100
TJ - Junction Temperature - °C
150
Figure 3.
Figure 4.
SWITCHING FREQUENCY vs RT/CLK RESISTANCE HIGH
FREQUENCY RANGE
SWITCHING FREQUENCY vs RT/CLK RESISTANCE LOW
FREQUENCY RANGE
2500
500
VI = 12 V,
TJ = 25°C
2000
fs - Switching Frequency - kHz
fs - Switching Frequency - kHz
125
1500
1000
500
0
0
25
50
75
100
125
RT/CLK - Resistance - kW
150
175
200
VI = 12 V,
TJ = 25°C
400
300
200
100
0
200
300
Figure 5.
400
500
600 700
800
900
RT/CLK - Resistance - kW
1000 1100
1200
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
EA TRANSCONDUCTANCE DURING SLOW START vs
JUNCTION TEMPERATURE
EA TRANSCONDUCTANCE vs JUNCTION TEMPERATURE
150
40
VI = 12 V
VI = 12 V
130
gm - mA/V
gm - mA/V
30
110
90
20
70
10
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
50
-50
150
-25
0
25
50
75
100
125
150
TJ - Junction Temperature - °C
Figure 7.
Figure 8.
EN PIN VOLTAGE vs JUNCTION TEMPERATURE
EN PIN CURRENT vs JUNCTION TEMPERATURE
1.40
-3.25
VI = 12 V,
VI(EN) = Threshold +50 mV
VI = 12 V
I(EN) - mA
EN - Threshold - V
-3.5
1.30
-3.75
1.20
-4
1.10
-50
-25
0
25
50
75
100
125
150
-4.25
-50
25
50
75
100
125
150
Figure 9.
Figure 10.
EN PIN CURRENT vs JUNCTION TEMPERATURE
SS/TR CHARGE CURRENT vs JUNCTION TEMPERATURE
-1
VI = 12 V,
VI(EN) = Threshold -50 mV
VI = 12 V
-0.85
I(SS/TR) - mA
-1.5
-0.9
-0.95
-1
-50
-2
-2.5
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
-3
-50
-25
Figure 11.
8
0
TJ - Junction Temperature - °C
-0.8
I(EN) - mA
-25
TJ - Junction Temperature - °C
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
SS/TR DISCHARGE CURRENT vs JUNCTION
TEMPERATURE
SWITCHING FREQUENCY vs VSENSE
120
100
VI = 12 V
VI = 12 V,
TJ = 25°C
80
% of Nominal fsw
II(SS/TR) - mA
115
110
60
40
105
20
100
-50
0
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
0
SHUTDOWN SUPPLY CURRENT vs INPUT VOLTAGE (Vin)
2
TJ = 25°C
I(VIN) - mA
1.5
1
0.5
1
0.5
0
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
0
10
20
30
40
VI - Input Voltage - V
Figure 15.
50
60
Figure 16.
VIN SUPPLY CURRENT vs JUNCTION TEMPERATURE
VIN SUPPLY CURRENT vs INPUT VOLTAGE
140
140
VI = 12 V,
VI(VSENSE) = 0.83 V
o
TJ = 25 C,
VI(VSENSE) = 0.83 V
130
130
120
120
I(VIN) - mA
I(VIN) - mA
0.8
SHUTDOWN SUPPLY CURRENT vs JUNCTION
TEMPERATURE
1.5
110
100
90
-50
0.6
Figure 14.
VI = 12 V
I(VIN) - mA
0.4
VSENSE - V
Figure 13.
2
0
-50
0.2
110
100
90
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
150
0
Figure 17.
20
40
VI - Input Voltage - V
60
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
PWRGD ON RESISTANCE vs JUNCTION TEMPERATURE
PWRGD THRESHOLD vs JUNCTION TEMPERATURE
115
100
VI = 12 V
PWRGD Threshold - % of Vref
VI = 12 V
RDSON - W
80
60
40
20
VSENSE Rising
110
VSENSE Falling
105
100
VSENSE Rising
95
VSENSE Falling
90
0
-50
-25
0
25
50
75
125
100
85
-50
150
-25
0
BOOT-PH UVLO vs JUNCTION TEMPERATURE
INPUT VOLTAGE (UVLO) vs JUNCTION TEMPERATURE
2.5
3
2.3
2.75
2
2.50
2.25
1.5
-50
-25
0
25
50
75
100
TJ - Junction Temperature - °C
125
2
-50
150
-25
0
25
50
75
100
TJ - Junction Temperature - °C
Figure 21.
125
150
Figure 22.
SS/TR TO VSENSE OFFSET vs VSENSE
SS/TR TO VSENSE OFFSET vs TEMPERATURE
600
60
V(SS/TR) = 0.2 V
VI = 12 V
VIN = 12 V
TJ = 25°C
500
55
50
400
Offset - mV
Offset Voltage Threshold (mV)
150
Figure 20.
1.8
300
45
40
200
35
100
30
-50
0
0
200
400
600
Voltage Sense (mV)
-25
800
Figure 23.
10
125
Figure 19.
VI(VIN) - V
VI(BOOT-PH) - V
TJ - Junction Temperature - °C
25
50
75
100
TJ - Junction Temperature - °C
0
25
50
75
100
125
150
TJ - Junction Temperature - °C
Figure 24.
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OVERVIEW
The TPS54160 device is a 60-V, 1.5-A, step-down (buck) regulator with an integrated high-side n-channel
MOSFET. To improve performance during line and load transients the device implements a constant frequency,
current mode control which reduces output capacitance and simplifies external frequency compensation design.
The wide switching frequency of 100kHz to 2500kHz allows for efficiency and size optimization when selecting
the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin.
The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power
switch turn on to a falling edge of an external system clock.
The TPS54160 has a default start up voltage of approximately 2.5V. The EN pin has an internal pull-up current
source that can be used to adjust the input voltage under voltage lockout (UVLO) threshold with two external
resistors. In addition, the pull up current provides a default condition. When the EN pin is floating the device
operates. The operating current is 116 mA when not switching and under no load. When the device is disabled,
the supply current is 1.3 mA.
The integrated 200mΩ high-side MOSFET allows for high efficiency power supply designs capable of delivering
1.5 A of continuous current to a load. The TPS54160 reduces the external component count by integrating the
boot recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor on the
BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and turns on the high-side
MOSFET off when the boot voltage falls below a preset threshold. The TPS54160 can operate at high duty
cycles because of the boot UVLO. The output voltage can be stepped down to as low as the 0.8V reference.
The TPS54160 has a power good comparator (PWRGD) which asserts when the regulated output voltage is less
than 92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open drain output which
deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage allowing the
pin to transition high when a pull-up resistor is used.
The TPS54160 minimizes excessive output overvoltage (OV) transients by taking advantage of the OV power
good comparator. When the OV comparator is activated, the high-side MOSFET is turned off and masked from
turning on until the output voltage is lower than 107%.
The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor should be coupled to the pin to adjust the slow start time. A resistor
divider can be coupled to the pin for critical power supply sequencing requirements. The SS/TR pin is discharged
before the output powers up. This discharging ensures a repeatable restart after an over-temperature fault,
UVLO fault or a disabled condition.
The TPS54160, also, discharges the slow start capacitor during overload conditions with an overload recovery
circuit. The overload recovery circuit will slow start the output from the fault voltage to the nominal regulation
voltage once a fault condition is removed. A frequency foldback circuit reduces the switching frequency during
startup and overcurrent fault conditions to help control the inductor current.
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DETAILED DESCRIPTION
Fixed Frequency PWM Control
The TPS54160 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared
through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives
the COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output
is compared to the high-side power switch current. When the power switch current reaches the level set by the
COMP voltage, the power switch is turned off. The COMP pin voltage will increase and decrease as the output
current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a
maximum level. The Eco-Mode™ is implemented with a minimum clamp on the COMP pin.
Slope Compensation Output Current
The TPS54160 adds a compensating ramp to the switch current signal. This slope compensation prevents
sub-harmonic oscillations. The available peak inductor current remains constant over the full duty cycle range.
Pulse Skip Eco-Mode
The TPS54160 operates in a pulse skip Eco mode at light load currents to improve efficiency by reducing
switching and gate drive losses. The TPS54160 is designed so that if the output voltage is within regulation and
the peak switch current at the end of any switching cycle is below the pulse skipping current threshold, the
device enters Eco mode. This current threshold is the current level corresponding to a nominal COMP voltage or
500mV.
When in Eco-mode, the COMP pin voltage is clamped at 500mV and the high-side MOSFET is inhibited. Further
decreases in load current or in output voltage can not drive the COMP pin below this clamp voltage level.
Since the device is not switching, the output voltage begins to decay. As the voltage control loop compensates
for the falling output voltage, the COMP pin voltage begins to rise. At this time, the high-side MOSFET is enabled
and a switching pulse initiates on the next switching cycle. The peak current is set by the COMP pin voltage. The
output voltage re-charges the regulated value (see Figure 25), then the peak switch current starts to decrease,
and eventually falls below the Eco mode threshold at which time the device again enters Eco mode.
For Eco mode operation, the TPS54160 senses peak current, not average or load current, so the load current
where the device enters Eco mode is dependent on the output inductor value. For example, the circuit in
Figure 51 enters Eco mode at about 18mA of output current. When the load current is low and the output voltage
is within regulation, the device enters a sleep mod,e and draws only 116mA input quiescent current. The internal
PLL remains operating when in sleep mode. When operating at light load currents in the pulse skip mode, the
switching transitions occur synchronously with the external clock signal.
VOUT(ac)
IL
PH
Figure 25. Pulse Skip Mode Operation
12
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DETAILED DESCRIPTION (continued)
Low Dropout Operation and Bootstrap Voltage (BOOT)
The TPS54160 has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and
PH pins to provide the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the
high-side MOSFET is off and the low-side diode conducts. The value of this ceramic capacitor should be 0.1mF.
A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10V or higher is recommended
because of the stable characteristics overtemperature and voltage.
To improve drop out, the TPS54160 is designed to operate at 100% duty cycle as long as the BOOT to PH pin
voltage is greater than 2.1V. When the voltage from BOOT to PH drops below 2.1V, the high-side MOSFET is
turned off using an UVLO circuit which allows the low-side diode to conduct and refresh the charge on the BOOT
capacitor. Since the supply current sourced from the BOOT capacitor is low, the high-side MOSFET can remain
on for more switching cycles than are required to refresh the capacitor, thus the effective duty cycle of the
switching regulator is high.
The effective duty cycle during dropout of the regulator is mainly influenced by the voltage drops across the
power MOSFET, inductor resistance, low-side diode and printed circuit board resistance. During operating
conditions in which the input voltage drops and the regulator is operating in continuous conduction mode, the
high-side MOSFET can remain on for 100% of the duty cycle to maintain output regulation, until the BOOT to PH
voltage falls below 2.1V.
Attention must be taken in maximum duty cycle applications which experience extended time periods with light
loads or no load. When the voltage across the BOOT capacitor falls below the 2.1V UVLO threshold, the
high-side MOSFET is turned off, but there may not be enough inductor current to pull the PH pin down to
recharge the BOOT capacitor. The high-side MOSFET of the regulator stops switching because the voltage
across the BOOT capacitor is less than 2.1V. The output capacitor then decays until the difference in the input
voltage and output voltage is greater than 2.1V, at which point the BOOT UVLO threshold is exceeded, and the
device starts switching again until the desired output voltage is reached. This operating condition persists until
the input voltage and/or the load current increases. It is recommended to adjust the VIN stop voltage greater
than the BOOT UVLO trigger condition at the minimum load of the application using the adjustable VIN UVLO
feature with resistors on the EN pin.
The start and stop voltages for typical 3.3V and 5V output applications are shown in Figure 26 and Figure 27.
The voltages are plotted versus load current. The start voltage is defined as the input voltage needed to regulate
the output within 1%. The stop voltage is defined as the input voltage at which the output drops by 5% or stops
switching.
During high duty cycle conditions, the inductor current ripple increases while the BOOT capacitor is being
recharged resulting in an increase in ripple voltage on the output. This is due to the recharge time of the boot
capacitor being longer than the typical high-side off time when switching occurs every cycle.
4
5.6
VO = 3.3 V
VO = 5 V
5.4
VI - Input Voltage - V
VI - Input Voltage - V
3.8
3.6
Start
3.4
Stop
5.2
Start
5
Stop
3.2
4.8
3
4.6
0
0.05
0.10
IO - Output Current - A
0.15
0.20
Figure 26. 3.3V Start/Stop Voltage
0
0.05
0.10
IO - Output Current - A
0.15
0.20
Figure 27. 5.0V Start/Stop Voltage
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DETAILED DESCRIPTION (continued)
Error Amplifier
The TPS54160 has a transconductance amplifier for the error amplifier. The error amplifier compares the
VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8-V voltage reference. The
transconductance (gM) of the error amplifier is 97mA/V during normal operation. During the slow start operation,
the transconductance is a fraction of the normal operating transconductance. When the voltage of the VSENSE
pin is below 0.8 V and the device is regulating using the SS/TR voltage, the transconductance is 25 mA/V.
The frequency compensation components (capacitor, series resistor and capacitor) are added to the COMP pin
to ground.
Voltage Reference
The voltage reference system produces a precise ±2% voltage reference over temperature by scaling the output
of a temperature stable bandgap circuit.
Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to
use 1% tolerance or better divider resistors. Start with a 10 kΩ for the R2 resistor and use the Equation 1 to
calculate R1. To improve efficiency at light loads consider using larger value resistors. If the values are too high,
the regulator becomes more susceptible to noise and voltage errors from the VSENSE input current are
noticeable.
æ (VOUT - 0.8 V ) ö
R1 = R2 ´ ç
÷
ç
÷
0.8 V
è
ø
(1)
Enable and Adjusting Undervoltage Lockout
The TPS54160 is disabled when the VIN pin voltage falls below 2.5 V. If an application requires a higher
undervoltage lockout (UVLO), use the EN pin as shown in Figure 28 to adjust the input voltage UVLO by using
the two external resistors. Though it is not necessary to use the UVLO adjust registers, for operation it is highly
recommended to provide consistent power up behavior. The EN pin has an internal pull-up current source, I1, of
0.9mA that provides the default condition of the TPS54160 operating when the EN pin floats. Once the EN pin
voltage exceeds 1.25V, an additional 2.9 mA of hysteresis, Ihys, is added. This additional current facilitates input
voltage hysteresis. Use Equation 2 to set the external hysteresis for the input voltage. Use Equation 3 to set the
input start voltage.
TPS54160
VIN
Ihys
I1
0.9 mA
R1
2.9 mA
+
R2
EN
1.25 V
-
Figure 28. Adjustable Undervoltage Lockout (UVLO)
14
V
- VSTOP
R1 = START
IHYS
(2)
VENA
R2 =
VSTART - VENA
+ I1
R1
(3)
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DETAILED DESCRIPTION (continued)
Another technique to add input voltage hysteresis is shown in Figure 29. This method may be used, if the
resistance values are high from the previous method and a wider voltage hysteresis is needed. The resistor R3
sources additional hysteresis current into the EN pin.
TPS54160
VIN
Ihys
R1
I1
0.9 mA
2.9 mA
+
R2
EN
1.25 V
-
VOUT
R3
Figure 29. Adding Additional Hysteresis
R1 =
R2 =
VSTART - VSTOP
V
IHYS + OUT
R3
(4)
VENA
VSTART - VENA
V
+ I1 - ENA
R1
R3
(5)
Do not place a low-impedance voltage source with greater than 5 V directly on the EN pin. Do not place a
capacitor directly on the EN pin if VEN > 5 V when using a voltage divider to adjust the start and stop voltage.
The node voltage, (see Figure 30) must remain equal to or less than 5.8 V. The zener diode can sink up to 100
µA. The EN pin voltage can be greater than 5 V if the VIN voltage source has a high impedance and does not
source more than 100 µA into the EN pin.
VIN
R1
Node
ENA
10kohm
R2
5.8V
Figure 30. Node Voltage
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DETAILED DESCRIPTION (continued)
Slow Start/Tracking Pin (SS/TR)
The TPS54160 effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as
the power-supply's reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to
ground implements a slow start time. The TPS54160 has an internal pull-up current source of 2mA that charges
the external slow start capacitor. The calculations for the slow start time (10% to 90%) are shown in Equation 6.
The voltage reference (VREF) is 0.8 V and the slow start current (ISS) is 2mA. The slow start capacitor should
remain lower than 0.47mF and greater than 0.47nF.
CSS (nF ) =
tSS (ms )´ ISS (mA )
VREF (V )´ 0.8
(6)
At power up, the TPS54160 does not start switching until the slow start pin is discharged to less than 40 mV to
ensure a proper power up, see Figure 31.
Also, during normal operation, the TPS54160 stops switching and the SS/TR must be discharged to 40 mV,
when the VIN UVLO is exceeded, EN pin pulled below 1.25V, or a thermal shutdown event occurs.
The VSENSE voltage follows the SS/TR pin voltage with a 45mV offset up to 85% of the internal voltage
reference. When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as
the effective system reference transitions from the SS/TR voltage to the internal voltage reference (see
Figure 23). The SS/TR voltage ramps linearly until clamped at 1.7V.
EN
SS/TR
VSENSE
VOUT
Figure 31. Operation of SS/TR Pin when Starting
Overload Recovery Circuit
The TPS54160 has an overload recovery (OLR) circuit. The OLR circuit slow starts the output from the overload
voltage to the nominal regulation voltage once the fault condition is removed. The OLR circuit discharges the
SS/TR pin to a voltage slightly greater than the VSENSE pin voltage using an internal pull down of 100 mA when
the error amplifier is changed to a high voltage from a fault condition. When the fault condition is removed, the
output slow-starts from the fault voltage to nominal output voltage.
16
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DETAILED DESCRIPTION (continued)
Sequencing
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD
pins. The sequential method can be implemented using an open drain output of a power on reset pin of another
device. The sequential method is illustrated in Figure 32 using two TPS54160 devices. The power good is
coupled to the EN pin on the TPS54160 which enables the second power supply once the primary supply
reaches regulation. If needed, a 1nF ceramic capacitor on the EN pin of the second power supply provides a
1-ms start-up delay. Figure 33 shows the results of Figure 32.
TPS54160
EN
PWRGD
EN
EN1
SS /TR
SS /TR
PWRGD1
PWRGD
VOUT1
VOUT2
Figure 32. Schematic for Sequential Start-Up
Sequence
Figure 33. Sequential Startup using EN and
PWRGD
TPS54160
3
EN
4
SS/TR
6
PWRGD
EN1, EN2
VOUT1
TPS54160
VOUT2
3
EN
4
SS/TR
6
PWRGD
Figure 34. Schematic for Ratiometric Start-Up
Using Coupled SS/TR Pins
Figure 35. Ratio-Metric Startup using Coupled
SS/TR pins
Figure 34 shows a method for ratio-metric start up sequence by connecting the SS/TR pins together. The
regulator outputs ramp up to reach regulation at the same time. When calculating the slow start time the pull up
current source must be doubled in Equation 6. Figure 35 shows the results of Figure 34.
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DETAILED DESCRIPTION (continued)
TPS54160
EN
VOUT 1
SS/TR
PWRGD
TPS54160
VOUT 2
EN
R1
SS/ TR
R2
PWRGD
R3
R4
Figure 36. Schematic for Ratiometric and Simultaneous Start-Up Sequence
Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network
of R1 and R2 shown in Figure 36 to the output of the power supply that needs to be tracked or another voltage
reference source. Using Equation 7 and Equation 8, the tracking resistors can be calculated to initiate the VOUT2
slightly before, after or at the same time as VOUT1. Equation 9 is the voltage difference between VOUT1 and VOUT2
at the 95% of nominal output regulation.
The ΔV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR to
VSENSE offset (VSS(offset)) in the slow start circuit and the offset created by the pull-up current source (ISS) and
tracking resistors, the VSS(offset) and ISS are included as variables in the equations.
To design a ratio-metric start up in which the VOUT2 voltage is slightly greater than the VOUT1 voltage when VOUT2
reaches regulation, use a negative number in Equation 7 through Equation 9 for ΔV. Equation 9 results in a
positive number for applications which the VOUT2 is slightly lower than VOUT1 when VOUT2 regulation is achieved.
Since the SS/TR pin must be pulled below 40 mV before starting after an EN, UVLO or thermal shutdown fault,
careful selection of the tracking resistors is needed to ensure the device restarts after a fault. Make sure the
calculated R1 value from Equation 7 is greater than the value calculated in Equation 10 to ensure the device can
recover from a fault.
As the SS/TR voltage becomes more than 85% of the nominal reference voltage the VSS(offset) becomes larger as
the slow start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR pin
voltage needs to be greater than 1.3 V for a complete handoff to the internal voltage reference as shown in
Figure 23.
V
+ DV VSS(offset )
R1 = OUT2
+
VREF
ISS
(7)
R2 =
VREF ´ R1
VOUT2 + DV - VREF
(8)
DV = VOUT1 - VOUT2
18
(9)
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DETAILED DESCRIPTION (continued)
R1 > 2800 ´ VOUT1 - 180 ´ DV
(10)
EN
EN
VOUT1
VOUT1
VOUT2
Figure 37. Ratiometric Startup with VOUT2 Leading
VOUT1
VOUT2
Figure 38. Ratiometric Startup with VOUT1 Leading
VOUT2
EN
VOUT1
VOUT2
Figure 39. Simultaneous Startup With Tracking Resistor
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DETAILED DESCRIPTION (continued)
Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS54160 is adjustable over a wide range from approximately 100kHz to
2500kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5V and must have a
resistor to ground to set the switching frequency. To determine the timing resistance for a given switching
frequency, use Equation 11 or the curves in Figure 40 or Figure 41. To reduce the solution size one would
typically set the switching frequency as high as possible, but tradeoffs of the supply efficiency, maximum input
voltage and minimum controllable on time should be considered.
The minimum controllable on time is typically 130ns and limits the maximum operating input voltage.
The maximum switching frequency is also limited by the frequency shift circuit. More discussion on the details of
the maximum switching frequency is located below.
206033
RRT (kW ) =
1.0888
fSW (kHz )
(11)
SWITCHING FREQUENCY
vs
RT/CLK RESISTANCE HIGH FREQUENCY RANGE
SWITCHING FREQUENCY
vs
RT/CLK RESISTANCE LOW FREQUENCY RANGE
2500
500
2000
fs - Switching Frequency - kHz
fs - Switching Frequency - kHz
VI = 12 V,
TJ = 25°C
1500
1000
500
0
0
25
50
75
100
125
150
RT/CLK - Clock Resistance - kW
175
200
VI = 12 V,
TJ = 25°C
400
300
200
100
0
200
300
Figure 40. High Range Timing Resistance
400
500
600 700
800
900
RT/CLK - Resistance - kW
1000 1100
1200
Figure 41. Low Range RT
Overcurrent Protection and Frequency Shift
The TPS54160 implements current mode control which uses the COMP pin voltage to turn off the high-side
MOSFET on a cycle by cycle basis. Each cycle the switch current and COMP pin voltage are compared, when
the peak switch current intersects the COMP voltage, the high-side switch is turned off. During overcurrent
conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high, increasing
the switch current. The error amplifier output is clamped internally, which functions as a switch current limit.
To increase the maximum operating switching frequency at high input voltages the TPS54160 implements a
frequency shift. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on
VSENSE pin.
The device implements a digital frequency shift to enable synchronizing to an external clock during normal
startup and fault conditions. Since the device can only divide the switching frequency by 8, there is a maximum
input voltage limit in which the device operates and still have frequency shift protection.
During short-circuit events (particularly with high input voltage applications), the control loop has a finite minimum
controllable on time and the output has a low voltage. During the switch on time, the inductor current ramps to
the peak current limit because of the high input voltage and minimum on time. During the switch off time, the
inductor would normally not have enough off time and output voltage for the inductor to ramp down by the ramp
up amount. The frequency shift effectively increases the off time allowing the current to ramp down.
20
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DETAILED DESCRIPTION (continued)
Selecting the Switching Frequency
The switching frequency that is selected should be the lower value of the two equations, Equation 12 and
Equation 13. Equation 12 is the maximum switching frequency limitation set by the minimum controllable on time.
Setting the switching frequency above this value causes the regulator to skip switching pulses.
Equation 13 is the maximum switching frequency limit set by the frequency shift protection. To have adequate
output short circuit protection at high input voltages, the switching frequency should be set to be less than the
fSW(maxshift) frequency. In Equation 13, to calculate the maximum switching frequency, consider that the output
voltage decreases from the nominal voltage to 0 V, the fDIV integer increases from 1 to 8 corresponding to the
frequency shift.
In Figure 42, the solid line illustrates a typical safe operating area regarding frequency shift and assumes the
output voltage is 0 V, and the resistance of the inductor is 0.1Ω, FET on-resistance of 0.2 Ω and the diode
voltage drop is 0.5 V. The dashed line is the maximum switching frequency to avoid pulse skipping. Enter these
equations in a spreadsheet or other software or use the SwitcherPro design software to determine the switching
frequency.
fSW (max skip ) =
fSWshift =
fDIV
tON
1
tON
æ I ´R + V
dc
OUT + Vd
´ç L
ç VIN - IL ´ RDS(on ) + Vd
è
æ IL ´ Rdc + VOUT(sc ) + Vd
´ç
ç VIN - IL ´ RDS(on ) + Vd
è
ö
÷
÷
ø
(12)
ö
÷
÷
ø
IL
inductor current
Rdc
inductor resistance
VIN
maximum input voltage
VOUT
output voltage
VOUT(sc)
output voltage during short
Vd
diode voltage drop
RDS(on)
switch on resistance
tON
controllable on time
fDIV
frequency divide equals (1, 2, 4, or 8)
(13)
2500
fs - Switching Frequency - kHz
VO = 3.3 V
2000
Shift
1500
Skip
1000
500
0
10
20
30
40
VI - Input Voltage - V
50
60
Figure 42. Maximum Switching Frequency vs. Input Voltage
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DETAILED DESCRIPTION (continued)
How to Interface to RT/CLK Pin
The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the
synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in
Figure 43. The square wave amplitude must transition lower than 0.5V and higher than 2.2V on the RT/CLK pin
and have an on time greater than 40 ns and an off time greater than 40 ns. The synchronization frequency range
is 100 kHz to 2200 kHz. The rising edge of the PH is synchronized to the falling edge of RT/CLK pin signal. The
external synchronization circuit should be designed in such a way that the device has the default frequency set
resistor connected from the RT/CLK pin to ground should the synchronization signal turn off. It is recommended
to use a frequency set resistor connected as shown in Figure 43 through a 50Ω resistor to ground. The resistor
should set the switching frequency close to the external CLK frequency. It is recommended to ac couple the
synchronization signal through a 10 pF ceramic capacitor to RT/CLK pin and a 4kΩ series resistor. The series
resistor reduces PH jitter in heavy load applications when synchronizing to an external clock and in applications
which transition from synchronizing to RT mode. The first time the CLK is pulled above the CLK threshold the
device switches from the RT resistor frequency to PLL mode. The internal 0.5V voltage source is removed and
the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. Since there is a PLL on
the regulator the switching frequency can be higher or lower than the frequency set with the external resistor.
The device transitions from the resistor mode to the PLL mode and then will increase or decrease the switching
frequency until the PLL locks onto the CLK frequency within 100 microseconds.
When the device transitions from the PLL to resistor mode the switching frequency will slow down from the CLK
frequency to 150 kHz, then reapply the 0.5V voltage and the resistor will then set the switching frequency. The
switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin. The
device implements a digital frequency shift to enable synchronizing to an external clock during normal startup
and fault conditions. Figure 44, Figure 45 and Figure 46 show the device synchronized to an external system
clock in continuous conduction mode (ccm) discontinuous conduction (dcm) and pulse skip mode (psm).
TPS54160
10 pF
4 kW
PLL
Rfset
EXT
Clock
Source
RT/CLK
50 W
Figure 43. Synchronizing to a System Clock
22
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DETAILED DESCRIPTION (continued)
EXT
EXT
VOUT
IL
PH
PH
IL
Figure 44. Plot of Synchronizing in ccm
Figure 45. Plot of Synchronizing in dcm
EXT
IL
PH
Figure 46. Plot of Synchronizing in PSM
Power Good (PWRGD Pin)
The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 107% of the internal
voltage reference the PWRGD pin is de-asserted and the pin floats. It is recommended to use a pull-up resistor
between the values of 10 and 100kΩ to a voltage source that is 5.5V or less. The PWRGD is in a defined state
once the VIN input voltage is greater than 1.5V but with reduced current sinking capability. The PWRGD will
achieve full current sinking capability as VIN input voltage approaches 3V.
The PWRGD pin is pulled low when the VSENSE is lower than 92% or greater than 109% of the nominal internal
reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin
pulled low.
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DETAILED DESCRIPTION (continued)
Overvoltage Transient Protection
The TPS54160 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot
when recovering from output fault conditions or strong unload transients on power supply designs with low value
output capacitance. For example, when the power supply output is overloaded the error amplifier compares the
actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal
reference voltage for a considerable time, the output of the error amplifier will respond by clamping the error
amplifier output to a high voltage. Thus, requesting the maximum output current. Once the condition is removed,
the regulator output rises and the error amplifier output transitions to the steady state duty cycle. In some
applications, the power supply output voltage can respond faster than the error amplifier output can respond, this
actuality leads to the possibility of an output overshoot. The OVTP feature minimizes the output overshoot, when
using a low value output capacitor, by implementing a circuit to compare the VSENSE pin voltage to OVTP
threshold which is 109% of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP
threshold, the high-side MOSFET is disabled preventing current from flowing to the output and minimizing output
overshoot. When the VSENSE voltage drops lower than the OVTP threshold, the high-side MOSFET is allowed
to turn on at the next clock cycle.
Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 182°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. Once the die temperature decreases below 182°C, the device reinitiates the power up sequence
by discharging the SS/TR pin.
Small Signal Model for Loop Response
Figure 47 shows an equivalent model for the TPS54160 control loop which can be modeled in a circuit simulation
program to check frequency response and dynamic load response. The error amplifier is a transconductance
amplifier with a gmEA of 97 mA/V. The error amplifier can be modeled using an ideal voltage controlled current
source. The resistor Ro and capacitor Co model the open loop gain and frequency response of the amplifier. The
1mV ac voltage source between the nodes a and b effectively breaks the control loop for the frequency response
measurements. Plotting c/a shows the small signal response of the frequency compensation. Plotting a/b shows
the small signal response of the overall loop. The dynamic loop response can be checked by replacing RL with a
current source with the appropriate load step amplitude and step rate in a time domain analysis. This equivalent
model is only valid for continuous conduction mode designs.
PH
VO
Power Stage
gmps 6 A/V
a
b
R1
RESR
RL
COMP
c
0.8 V
R3
C2
C1
CO
VSENSE
COUT
RO
gmea
97 mA/V
R2
Figure 47. Small Signal Model for Loop Response
Simple Small Signal Model for Peak Current Mode Control
Figure 48 describes a simple small signal model that can be used to understand how to design the frequency
compensation. The TPS54160 power stage can be approximated to a voltage-controlled current source (duty
24
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DETAILED DESCRIPTION (continued)
cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer
function is shown in Equation 14 and consists of a dc gain, one dominant pole, and one ESR zero. The quotient
of the change in switch current and the change in COMP pin voltage (node c in Figure 47) is the power stage
transconductance. The gmPS for the TPS54160 is 6 A/V. The low-frequency gain of the power stage frequency
response is the product of the transconductance and the load resistance as shown in Equation 15.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 16). The combined effect is highlighted by the dashed line in the right half of
Figure 48. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same for the varying load conditions which makes it easier to design the frequency
compensation. The type of output capacitor chosen determines whether the ESR zero has a profound effect on
the frequency compensation design. Using high ESR aluminum electrolytic capacitors may reduce the number
frequency compensation components needed to stabilize the overall loop because the phase margin increases
from the ESR zero at the lower frequencies (see Equation 17).
VO
Adc
VC
RESR
fp
RL
gmps
COUT
fz
Figure 48. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
æ
s ö
ç1 +
÷
2
p
´ fZ ø
VOUT
= Adc ´ è
VC
æ
s ö
ç1 +
÷
2p ´ fP ø
è
(14)
Adc = gmps ´ RL
(15)
1
fP =
COUT ´ RL ´ 2p
(16)
1
fZ =
COUT ´ RESR ´ 2p
(17)
Small Signal Model for Frequency Compensation
The TPS54160 uses a transconductance amplifier for the error amplifier and readily supports three of the
commonly-used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are
shown in Figure 49. Type 2 circuits most likely implemented in high bandwidth power-supply designs using low
ESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum
electrolytic or tantalum capacitors.. Equation 18 and Equation 19 show how to relate the frequency response of
the amplifier to the small signal model in Figure 49. The open-loop gain and bandwidth are modeled using the RO
and CO shown in Figure 49. See the application section for a design example using a Type 2A network with a
low ESR output capacitor.
Equation 18 through Equation 27 are provided as a reference for those who prefer to compensate using the
preferred methods. Those who prefer to use prescribed method use the method outlined in the application
section or use switched information.
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DETAILED DESCRIPTION (continued)
VO
R1
VSENSE
gmea
Type 2A
COMP
Type 2B
Type 1
Vref
R2
R3
RO
C2
R3
C2
CO
C1
C1
Figure 49. Types of Frequency Compensation
Aol
A0
P1
Z1
P2
A1
BW
Figure 50. Frequency Response of the Type 2A and Type 2B Frequency Compensation
Ro =
COUT
Aol(V/V)
gmea
gmea
=
2p ´ BW (Hz)
(18)
(19)
æ
ö
s
ç1 +
÷
2p ´ fZ1 ø
è
EA = A0 ´
æ
ö æ
ö
s
s
ç1 +
÷ ´ ç1 +
÷
2
2
p
´
p
´
f
f
P1 ø è
P2 ø
è
A0 = gmea
A1 = gmea
P1 =
26
R2
´ Ro ´
R1 + R2
R2
´ Ro| | R3 ´
R1 + R2
(20)
(21)
(22)
1
2p ´ Ro ´ C1
(23)
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DETAILED DESCRIPTION (continued)
Z1 =
1
2p ´ R3 ´ C1
(24)
1
P2 =
type 2a
2p ´ R3 | | Ro ´ (C2 + Co)
(25)
1
type 2b
2p ´ R3 | | Ro ´ Co
(26)
P2 =
1
P2 =
type 1
2 p ´ Ro ´ (C2 + Co)
(27)
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APPLICATION INFORMATION
Design Guide — Step-By-Step Design Procedure
This example details the design of a high frequency switching regulator design using ceramic output capacitors.
A few parameters must be known in order to start the design process. These parameters are typically determined
at the system level. For this example, we will start with the following known parameters:
Output Voltage
3.3 V
Transient Response 0 to 1.5A load step
ΔVOUT= 4%
Maximum Output Current
1.5 A
Input Voltage
12 V nom. 8 V to 18 V
Output Voltage Ripple
< 33 mVpp
Start Input Voltage (rising VIN)
7.25 V
Stop Input Voltage (falling VIN)
6.25 V
Selecting the Switching Frequency
The first step is to decide on a switching frequency for the regulator. Typically, the user will want to choose the
highest switching frequency possible since this will produce the smallest solution size. The high switching
frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that
switches at a lower frequency. The switching frequency that can be selected is limited by the minimum on-time of
the internal power switch, the input voltage and the output voltage and the frequency shift limitation.
Equation 12 and Equation 13 must be used to find the maximum switching frequency for the regulator, choose
the lower value of the two equations. Switching frequencies higher than these values will result in pulse skipping
or the lack of overcurrent protection during a short circuit.
The typical minimum on time, tonmin, is 130 ns for the TPS54160. For this example, the output voltage is 3.3 V
and the maximum input voltage is 18 V, which allows for a maximum switch frequency up to 1600 kHz when
including the inductor resistance, on resistance and diode voltage in Equation 12. To ensure overcurrent
runaway is not a concern during short circuits in your design use Equation 13 or the solid curve in Figure 42 to
determine the maximum switching frequency. With a maximum input voltage of 20 V, for some margin above 18
V, assuming a diode voltage of 0.5 V, inductor resistance of 100 mΩ, switch resistance of 200mΩ, a current limit
value of 2.7 A, the maximum switching frequency is approximately 2500kHz.
Choosing the lower of the two values and adding some margin a switching frequency of 1200 kHz is used. To
determine the timing resistance for a given switching frequency, use Equation 11 or the curve in Figure 40.
The switching frequency is set by resistor Rt shown in Figure 51.
L1
10 mH
U1
TPS54160DGQ
BOOT
VIN
C2
C3
C4
2.2 mF 2.2 mF 0.1 mF
R3
EN
SS/TR
RT/CLK
332 kW
CSS
RT
0.01 mF
90.9 kW
R4
61.9 kW
D1
B220A
COMP
VSNS
PWRGD
CF
6.8 pF
COUT
+
47 mF/6.3 V
PH
GND
PwPd
8 - 18 V
3.3 V at 1.5 A
0.1 mF
C1
RC
76.8 kW
CC
2700 pF
R1
31.6 kW
R2
10 kW
Figure 51. High Frequency, 3.3V Output Power Supply Design with Adjusted UVLO.
28
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Output Inductor Selection (LO)
To calculate the minimum value of the output inductor, use Equation 28.
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
The inductor ripple current will be filtered by the output capacitor. Therefore, choosing high inductor ripple
currents will impact the selection of the output capacitor since the output capacitor must have a ripple current
rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion
of the designer; however, the following guidelines may be used.
For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be used.
When using higher ESR output capacitors, KIND = 0.2 yields better results. Since the inductor ripple current is
part of the PWM control system, the inductor ripple current should always be greater than 100 mA for
dependable operation. In a wide input voltage regulator, it is best to choose an inductor ripple current on the
larger side. This allows the inductor to still have a measurable ripple current with the input voltage at its
minimum.
For this design example, use KIND = 0.2 and the minimum inductor value is calculated to be 7.6mH. For this
design, a nearest standard value was chosen: 10mH. For the output filter inductor, it is important that the RMS
current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from
Equation 30 and Equation 31.
For this design, the RMS inductor current is 1.506 A and the peak inductor current is 1.62 A. The chosen
inductor is a MSS6132-103. It has a saturation current rating of 1.64 A and an RMS current rating of 1.9A.
As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but
will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of
the regulator but allow for a lower inductance value.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
VIN(max ) - VOUT
VOUT
LO(min ) =
´
IOUT ´ KIND
VIN(max ) ´ fSW
(28)
IRIPPLE £ IOUT ´ KIND
IL(rms ) =
2
(IOUT )
IL(peak ) = IOUT
(29)
(
æ
1 ç VOUT ´ VIN(max ) - VOUT
+
´
12 çç
VIN(max ) ´ LO ´ fSW
è
)ö÷
2
÷
÷
ø
(30)
I
+ RIPPLE
2
(31)
Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor will
determine the modulator pole, the output voltage ripple, and how the regulators responds to a large change in
load current. The output capacitance needs to be selected based on the more stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator can not. This situation would occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator also will temporarily not be able to
supply sufficient output current if there is a large, fast increase in the current needs of the load such as
transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop
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to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output
capacitor must be sized to supply the extra current to the load until the control loop responds to the load change.
The output capacitance must be large enough to supply the difference in current for twoclock cycles while only
allowing a tolerable amount of droop in the output voltage. Equation 32 shows the minimum output capacitance
necessary to accomplish this.
Where ΔIOUT is the change in output current, ƒsw is the regulators switching frequency and ΔVout is the
allowable change in the output voltage. For this example, the transient load response is specified as a 4%
change in VOUT for a load step from 0 A (no load) to 1.5 A (full load). For this example, ΔIOUT = 1.5-0 = 1.5 A and
ΔVOUT = 0.04 × 3.3 = 0.132 V. Using these numbers gives a minimum capacitance of 18.9 mF. This value does
not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the
ESR is usually small enough to ignore in this calculation. Aluminum electrolytic and tantalum capacitors have
higher ESR that should be taken into account.
The catch diode of the regulator cannot sink current so any stored energy in the inductor produces an output
voltage overshoot when the load current rapidly decreases, see Figure 52. The output capacitor must also be
sized to absorb energy stored in the inductor when transitioning from a high load current to a lower load current.
The excess energy that gets stored in the output capacitor increases the voltage on the capacitor. The capacitor
must be sized to maintain the desired output voltage during these transient periods. Equation 33 is used to
calculate the minimum capacitance to keep the output voltage overshoot to a desired value. Where L is the value
of the inductor, IOH is the output current under heavy load, IOL is the output under light load, Vf is the final peak
output voltage, and Vi is the initial capacitor voltage. For this example, the worst case load step will be from 1.5
A to 0 A. The output voltage increases during this load transition and the stated maximum in our specification is
4% of the output voltage. This will make Vf = 1.04 × 3.3 = 3.432. Vi is the initial capacitor voltage which is the
nominal output voltage of 3.3 V. Using these numbers in Equation 33 yields a minimum capacitance of 25.3 mF.
Equation 34 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fSW is the switching frequency, VOUT(ripple) is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. Equation 34 yields 0.7 mF.
Equation 35 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 35 indicates the ESR should be less than 147 mΩ.
The most stringent criteria for the output capacitor is 25.3 mF of capacitance to keep the output voltage in
regulation during an unload transient.
Additional capacitance de-ratings for aging, temperature and dc bias should be factored in which increases this
minimum value. For this example, a 47 mF 6.3V X7R ceramic capacitor with 5 mΩ of ESR is used.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the Root Mean Square (RMS) value of the maximum ripple current. Equation 36 can be used
to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 36 yields
64.8 mA.
2 ´ DIOUT
COUT =
fSW ´ DVOUT
(32)
((I ) - (I ) )
´
((V ) - (V ) )
2
OH
COUT > LO
2
f
COUT >
30
2
OL
2
i
(33)
1
1
´
8 ´ fSW æ VOUT(ripple ) ö
ç
÷
ç IRIPPLE ÷
è
ø
(34)
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VOUT(ripple )
RESR =
IRIPPLE
ICOUT(rms) =
(35)
(
VOUT ´ VIN(max ) - VOUT
)
12 ´ VIN(max ) ´ LO ´ fSW
(36)
Catch Diode
The TPS54160 requires an external catch diode between the PH pin and GND. The selected diode must have a
reverse voltage rating equal to or greater than Vinmax. The peak current rating of the diode must be greater than
the maximum inductor current. The diode should also have a low forward voltage. Schottky diodes are typically a
good choice for the catch diode due to their low forward voltage. The lower the forward voltage of the diode, the
higher the efficiency of the regulator.
Typically, the higher the voltage and current ratings the diode has, the higher the forward voltage will be. Since
the design example has an input voltage up to 18 V, a diode with a minimum of 20V reverse voltage will be
selected.
For the example design, the B220A Schottky diode is selected for its lower forward voltage and it comes in a
larger package size which has good thermal characteristics over small devices. The typical forward voltage of the
B220A is 0.50 V.
The diode must also be selected with an appropriate power rating. The diode conducts the output current during
the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by
the forward voltage of the diode which equals the conduction losses of the diode. At higher switch frequencies,
the ac losses of the diode need to be taken into account. The ac losses of the diode are due to the charging and
discharging of the junction capacitance and reverse recovery. Equation 37 is used to calculate the total power
dissipation, conduction losses plus ac losses, of the diode.
The B220A has a junction capacitance of 120pF. Using Equation 37, the selected diode will dissipate 0.632 W.
This power dissipation, depending on mounting techniques, should produce a 16°C temperature rise in the diode
when the input voltage is 18 V and the load current is 1.5 A.
If the power supply spends a significant amount of time at light load currents or in sleep mode consider using a
diode which has a low leakage current and slightly higher forward voltage drop.
PD =
(V
IN(max ) - VOUT
)´ I
OUT
2
´ Vfd
VIN(max )
+
C j ´ fSW ´ (VIN + Vfd)
2
(37)
Input Capacitor
The TPS54160 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 3 mF of
effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any dc
bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The
capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54160.
The input ripple current can be calculated using Equation 38.
The value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the dc bias taken into account. The capacitance value of a capacitor
decreases as the dc bias across a capacitor increases.
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For this example design, a ceramic capacitor with at least a 20 V voltage rating is required to support the
maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25
V, 50 V or 100 V, so a 25 V capacitor should be selected. For this example, two 2.2 mF, 25 V capacitors in
parallel have been selected. Table 2 shows a selection of high voltage capacitors. The input capacitance value
determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 39.
Using the design example values
• IOUT(max) = 1.5 A
• CIN = 4.4 mF
• ƒSW = 1200 kHz
yields an input voltage ripple of 71 mV and a rms input ripple current of 0.701A.
ICI(rms ) = IOUT ´
DVIN =
(
VIN(min ) - VOUT
VOUT
´
VIN(min )
VIN(min )
)
(38)
IOUT(max ) ´ 0.25
CIN ´ fSW
(39)
Table 2. Capacitor Types
VENDOR
VALUE (mF)
1.0 to 2.2
1.0 to 4.7
Murata
1.0
1.0 to 2.2
1.0 10 1.8
1.0 to 1.2
Vishay
1.0 to 3.9
1.0 to 1.8
1.0 to 2.2
TDK
1.5 to 6.8
1.0. to 2.2
1.0 to 3.3
1.0 to 4.7
AVX
1.0
1.0 to 4.7
1.0 to 2.2
EIA Size
1210
1206
2220
2225
1812
1210
1210
1812
VOLTAGE (V)
DIALECTRIC
100
COMMENTS
GRM32 series
50
100
GRM31 series
50
50
100
VJ X7R series
50
100
100
50
100
50
X7R
C series C4532
C series C3225
50
100
50
X7R dielectric series
100
Slow Start Capacitor
The slow start capacitor determines the minimum amount of time it will take for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is large and would require large amounts of current to quickly charge the
capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS54160 reach the current limit or excessive current draw from the input power supply may cause the input
voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.
The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output
voltage without drawing excessive current. Equation 40 can be used to find the minimum slow start time, tss,
necessary to charge the output capacitor, Cout, from 10% to 90% of the output voltage, Vout, with an average
slow start current of Issavg. In the example, to charge the 47mF output capacitor up to 3.3V while only allowing
the average input current to be 0.125A would require a 1 ms slow start time.
32
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Once the slow start time is known, the slow start capacitor value can be calculated using Equation 6. For the
example circuit, the slow start time is not too critical since the output capacitor value is 47mF which does not
require much current to charge to 3.3V. The example circuit has the slow start time set to an arbitrary value of
1ms which requires a 3.3 nF capacitor.
´ VOUT ´ 0.8
C
tSS > OUT
ISS(avg)
(40)
Bootstrap Capacitor Selection
A 0.1-mF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10V
or higher voltage rating.
Under Voltage Lock Out Set Point
The Under Voltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54160. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power
down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 7.25V (enabled). After the regulator starts switching, it should
continue to do so until the input voltage falls below 6.25V (UVLO stop).
The programmable UVLO and enable voltages are set using a resistor divider between Vin and ground to the EN
pin. Equation 2 through Equation 3 can be used to calculate the resistance values necessary. For the example
application, a 332kΩ between Vin and EN and a 61.9kΩ between EN and ground are required to produce the
7.25 and 6.25 volt start and stop voltages.
Output Voltage and Feedback Resistors Selection
For the example design, 10.0 kΩ was selected for R2. Using Equation 1, R1 is calculated as 31.25 kΩ. The
nearest standard 1% resistor is 31.6 kΩ. Due to current leakage of the VSENSE pin, the current flowing through
the feedback network should be greater than 1 mA in order to maintain the output voltage accuracy. This
requirement makes the maximum value of R2 equal to 800 kΩ. Choosing higher resistor values will decrease
quiescent current and improve efficiency at low output currents but may introduce noise immunity problems.
Compensation
There are several industry techniques used to compensate DC/DC regulators. The method presented here yields
high phase margins. For most conditions, the regulator will have a phase margin between 60 and 90 degrees.
The method presented here ignores the effects of the slope compensation that is internal to the TPS54160.
Since the slope compensation is ignored, the actual crossover frequency is usually lower than the crossover
frequency used in the calculations.
Use SwitcherPro software for a more accurate design.
The uncompensated regulator will have a dominant pole, typically located between 300 Hz and 3 kHz, due to the
output capacitor and load resistance and a pole due to the error amplifier. One zero exists due to the output
capacitor and the ESR. The zero frequency is higher than either of the two poles.
If left uncompensated, the double pole created by the error amplifier and the modulator would lead to an unstable
regulator. To stabilize the regulator, one pole must be canceled out. One design approach is to locate a
compensating zero at the modulator pole. Then select a crossover frequency that is higher than the modulator
pole. The gain of the error amplifier can be calculated to achieve the desired crossover frequency. The capacitor
used to create the compensation zero along with the output impedance of the error amplifier form a low
frequency pole to provide a minus one slope through the crossover frequency. Then a compensating pole is
added to cancel the zero due to the output capacitors ESR. If the ESR zero resides at a frequency higher than
the switching frequency then it can be ignored.
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To compensate the TPS54160 using this method, first calculate the modulator pole and zero using the following
equations:
IOUT(max )
fP(mod) >
2 ´ p ´ VOUT ´ COUT
where
•
•
•
IOUT(max) is the maximum output current
COUT is the output capacitance
VOUT is the nominal output voltage
fZ(mod) >
(41)
1
2 ´ p ´ RESR ´ COUT
(42)
For the example design, the modulator pole is located at 1.5 kHz and the ESR zero is located at 338 kHz.
Next, the designer selects a crossover frequency which will determine the bandwidth of the control loop. The
crossover frequency must be located at a frequency at least five times higher than the modulator pole. The
crossover frequency must also be selected so that the available gain of the error amplifier at the crossover
frequency is high enough to allow for proper compensation.
Equation 47 is used to calculate the maximum crossover frequency when the ESR zero is located at a frequency
that is higher than the desired crossover frequency. This will usually be the case for ceramic or low ESR
tantalum capacitors. Aluminum Electrolytic and Tantalum capacitors will typically produce a modulator zero at a
low frequency due to their high ESR.
The example application is using a low ESR ceramic capacitor with 10mΩ of ESR making the zero at 338 kHz.
This value is much higher than typical crossover frequencies so the maximum crossover frequency is calculated
using both Equation 43 and Equation 46.
Using Equation 46 gives a minimum crossover frequency of 7.6 kHz and Equation 43 gives a maximum
crossover frequency of 45.3 kHz.
A crossover frequency of 45 kHz is arbitrarily selected from this range.
For ceramic capacitors use Equation 43:
fC(max ) £ 2100
fP(mod)
VOUT
(43)
For tantalum or aluminum capacitors use Equation 44:
51442
fC(max ) £
VOUT
For all cases use Equation 45 and Equation 46:
f
fC(max ) £ SW
5
fC(min ) ³ 5 ´ fP(mod)
(44)
(45)
(46)
Once a crossover frequency, fC, has been selected, the gain of the modulator at the crossover frequency is
calculated. The gain of the modulator at the crossover frequency is calculated using Equation 47 .
gm(PS ) ´ RLOAD ´ (2p ´ fC ´ COUT ´ RESR + 1)
GMOD(fc ) =
2p ´ fC ´ COUT ´ (RLOAD ´ RESR ) + 1
(47)
34
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For the example problem, the gain of the modulator at the crossover frequency is 0.542. Next, the compensation
components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A
capacitor in parallel to these two components forms the compensating pole. However, calculating the values of
these components varies depending on if the ESR zero is located above or below the crossover frequency. For
ceramic or low ESR tantalum output capacitors, the zero will usually be located above the crossover frequency.
For aluminum electrolytic and tantalum capacitors, the modulator zero is usually located lower in frequency than
the crossover frequency. For cases where the modulator zero is higher than the crossover frequency (ceramic
capacitors).
VOUT
RC =
GMOD(fc ) ´ gm(EA ) ´ VREF
(48)
1
CC =
p ´ RC ´ fP(mod)
(49)
´ RESR
C
Cf = OUT
RC
(50)
For cases where the modulator zero is less than the crossover frequency (Aluminum or Tantalum capacitors), the
equations are:
VOUT
RC =
GMOD(fc ) ´ fZ(mod) ´ gm(EA ) ´ VREF
(51)
1
CC =
p ´ RC ´ fP(mod)
Cf =
(52)
1
2 ´ p ´ RC ´ fZ(mod)
(53)
For the example problem, the ESR zero is located at a higher frequency compared to the crossover frequency so
Equation 50 through Equation 53 are used to calculate the compensation components. In this example, the
calculated components values are:
• RC= 76.2 kΩ
• CC= 2710 pF
• Cf =6.17 pF
The calculated value of the Cf capacitor is not a standard value so a value of 2700 pF is used. 6.8 pF is used for
CC. The RC resistor sets the gain of the error amplifier which determines the crossover frequency. The calculated
RC resistor is not a standard value, so 76.8 kΩ is used.
APPLICATION CURVES
VIN
VO
VOUT
EN
IO
IL
Figure 52. Load Transmit
Figure 53. Startup With EN
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VOUT
VOUT
IL
PH
VIN
IL
Figure 54. VIN Power Up
Figure 55. Output Ripple CCM
VOUT
VOUT
IL
IL
PH
Figure 56. Output Ripple, DCM
PH
Figure 57. Output Ripple, PSM
VIN
VIN
IL
IL
PH
PH
Figure 58. Input Ripple CCM
36
Figure 59. Input Ripple DCM
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95
VO = 3.3 V,
fsw = 1200 kHz
VI = 8 V
90
85
VIN
Efficiency - %
80
IL
VI = 12 V
VI = 16 V
75
70
65
PH
60
55
50
0
Figure 60. Input Ripple PSM
0.25
0.50
0.75
1
1.25
IL - Load Current - A
1.5
1.75
2
Figure 61. Efficiency vs Load Current
1.015
60
150
VI = 12 V
1.010
40
100
1.005
Phase - o
Gain - dB
50
20
0
Gain
0
-50
Regulation (%)
Phase
1.000
0.995
-100
-20
0.990
-150
-40
100
1-103
1-104
f - Frequency - Hz
1-105
0.985
0.00
1-106
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
Load Current - A
Figure 62. Overall Loop Frequency Response
Figure 63. Regulation vs Load Current
1.015
IO = 0.5 A
1.010
Regulation (%)
1.005
1.000
0.995
0.990
0.985
5
10
15
20
VI - Input Voltage - V
Figure 64. Regulation vs Input Voltage
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Power Dissipation Estimate
The following formulas show how to estimate the device power dissipation under continuous conduction mode
(CCM) operation. These equations should not be used if the device is working in discontinuous conduction mode
(DCM).
The power dissipation of the device includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd)
and supply current (Pq).
æV
ö
2
PCOND = (IOUT ) ´ RDS(on ) ´ ç OUT ÷
è VIN ø
(54)
2
PSW = (VIN ) ´ fSW ´ IOUT ´ 0.25 ´ 10-9
PGD = VIN ´ 3 ´ 10
PQ = 116 ´ 10
-6
-9
´ fSW
(55)
(56)
´ VIN
where
•
•
•
•
•
IOUT is the output current (A)
RDS(on) is the on-resistance of the high-side MOSFET (Ω)
VOUT is the output voltage (V)
VIN is the input voltage (V)
fSW is the switching frequency (Hz)
PTOT = PCOND ´ PSW ´ PGD ´ PQ
(57)
(58)
For given TA,
TJ = TA + RTH ´ PTOT
(59)
For given TJMAX = 150°C
TA (max ) = TJ(max ) - RTH ´ PTOT
where
•
•
•
•
•
•
PTOT s the total device power dissipation (W)
TA is the ambient temperature (°C)
TJ is the junction temperature (°C)
RTH is the thermal resistance of the package (°C/W)
TJ(max) is maximum junction temperature (°C)
TA(max) is maximum ambient temperature (°C).
(60)
There are additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode
and trace resistance that will impact the overall efficiency of the regulator.
38
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Layout
Layout is a critical portion of good power supply design. There are several signals paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed
to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to
minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch
diode. See Figure 65 for a PCB layout example. The GND pin should be tied directly to the power pad under the
device and the power pad.
The power pad should be connected to any internal PCB ground planes using multiple vias directly under the
device. The PH pin should be routed to the cathode of the catch diode and to the output inductor. Since the PH
connection is the switching node, the catch diode and output inductor should be located close to the PH pins,
and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated
load, the top side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise
so the RT resistor should be located as close as possible to the device and routed with minimal lengths of trace.
The additional external components can be placed approximately as shown. It may be possible to obtain
acceptable performance with alternate PCB layouts, however this layout has been shown to produce good
results and is meant as a guideline.
Vout
Output
Capacitor
Topside
Ground
Area
Output
Inductor
Route Boot Capacitor
Trace on another layer to
provide wide path for
topside ground
Input
Bypass
Capacitor
BOOT
Catch
Diode
PH
Vin
UVLO
Adjust
Resistors
Slow Start
Capacitor
VIN
GND
EN
COMP
SS/TR
VSENSE
RT/CLK
PWRGD
Frequency
Set Resistor
Compensation
Network
Resistor
Divider
Thermal VIA
Signal VIA
Figure 65. PCB Layout Example
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Figure 66. Wide Input Voltage Design
40
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SLVS795C – OCTOBER 2008 – REVISED OCTOBER 2010
REVISION HISTORY
Changes from Revision B (October 2009) to Revision C
Page
•
Added Note 2 ........................................................................................................................................................................ 2
•
Changed Updated characterization data ............................................................................................................................ 10
•
Added paragraph "Do not place a low-impedance voltage source..." ................................................................................ 15
•
Added Figure 30 ................................................................................................................................................................. 15
•
Changed from: "indicates the ESR should be less than 144 mΩ" to: "indicates the ESR should be less than 147
mΩ" ..................................................................................................................................................................................... 30
•
Changed from :" Equation 36 yields 66 mA" to: "Equation 36 yields 64.8 mA" .................................................................. 30
•
Changed corrected typrgraphical error in Equation 37 ....................................................................................................... 31
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41
PACKAGE OPTION ADDENDUM
www.ti.com
1-Apr-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
TPS54160DGQ
ACTIVE
MSOPPowerPAD
DGQ
10
80
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
TPS54160DGQG4
ACTIVE
MSOPPowerPAD
DGQ
10
80
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
TPS54160DGQR
ACTIVE
MSOPPowerPAD
DGQ
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
TPS54160DGQRG4
ACTIVE
MSOPPowerPAD
DGQ
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
TPS54160DRCR
PREVIEW
SON
DRC
10
3000
TBD
Call TI
Call TI
TPS54160DRCT
PREVIEW
SON
DRC
10
250
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Apr-2011
OTHER QUALIFIED VERSIONS OF TPS54160 :
• Automotive: TPS54160-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Apr-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS54160DGQR
MSOPPower
PAD
DGQ
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
TPS54160DGQR
MSOPPower
PAD
DGQ
10
2500
330.0
12.4
5.3
3.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Apr-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS54160DGQR
MSOP-PowerPAD
DGQ
10
2500
364.0
364.0
27.0
TPS54160DGQR
MSOP-PowerPAD
DGQ
10
2500
346.0
346.0
35.0
Pack Materials-Page 2
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