SCES624 − FEBRUARY 2005
D Member of the Texas Instruments
D
D
D
D
D
DBB PACKAGE
(TOP VIEW)
Widebus Family
Output Ports Have Series Damping
Resistors, So No External Resistors Are
Required
Diodes on Inputs Clamp Overshoot
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
2Y2
1Y2
GND
2Y1
1Y1
VCC
A1
A2
GND
A3
A4
GND
A5
A6
VCC
A7
A8
GND
A9
OE1
OE2
A10
GND
A11
A12
VCC
A13
A14
GND
A15
A16
GND
A17
A18
VCC
2Y18
1Y18
GND
2Y17
1Y17
description/ordering information
This 1-bit to 2-bit address driver is designed for
2.3-V to 3.6-V VCC operation.
Diodes to VCC have been added on the inputs to
clamp overshoot.
Active bus-hold circuitry holds unused or undriven
inputs at a valid logic state. Use of pullup or
pulldown resistors with the bus-hold circuitry is not
recommended.
The outputs, which are designed to sink up to
12 mA, include series damping resistors to reduce
overshoot and undershoot.
The ALVCHS162830A is an improved version of
the LVCHS162830 (non-A version) and has been
optimized for lower power consumption and
higher AC drive. Higher AC drive provides
capability to drive loads with a faster edge rate.
To ensure the high-impedance state during power
up or power down, the output-enable (OE) input
should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the
current-sinking capability of the driver.
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31
50
32
49
33
48
34
47
35
46
36
45
37
44
38
43
39
42
40
41
1Y3
2Y3
GND
1Y4
2Y4
VCC
1Y5
2Y5
GND
1Y6
2Y6
GND
1Y7
2Y7
VCC
1Y8
2Y8
GND
1Y9
2Y9
1Y10
2Y10
GND
1Y11
2Y11
VCC
1Y12
2Y12
GND
1Y13
2Y13
GND
1Y14
2Y14
VCC
1Y15
2Y15
GND
1Y16
2Y16
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright 2005, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
POST OFFICE BOX 655303
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1
SCES624 − FEBRUARY 2005
description/ordering information
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING
−40°C to 85°C TVSOP − DBB
Tape and reel
74ALVCHS162830AGR
ALVCHS162830A
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OUTPUTS
OE1
OE2
A
1Yn
2Yn
L
H
H
H
Z
L
H
L
L
Z
H
L
H
Z
H
H
L
L
Z
L
L
L
H
H
H
L
L
L
L
L
H
H
X
Z
Z
logic diagram (positive logic)
VCC
21
OE2
VCC
20
OE1
VCC
A1
5
7
4
To 17 Other Channels
2
1Y1
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2Y1
SCES624 − FEBRUARY 2005
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0, VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
MIN
MAX
2.3
3.6
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
VO
Input voltage
0
Output voltage
0
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
V
1.7
V
2
0.7
VCC = 2.7 V to 3.6 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
UNIT
0.8
VCC
VCC
V
V
V
−6
−8
mA
−12
6
8
mA
12
10
ns/V
TA
Operating free-air temperature
−40
85
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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3
SCES624 − FEBRUARY 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
II = −18 mA
II = 18 mA
VIK
IOH = −100 µA
IOH = −4 mA,
VOH
IOH = −8 mA,
IOH = −12 mA,
IOL = 100 µA
IOL = 4 mA,
IOL = 8 mA,
IOL = 12 mA,
II(hold)
VCC + 1.2
2.3 V
VCC − 0.2
1.9
2.3 V
1.7
3V
2.4
2.7 V
2
VIH = 2 V
3V
2
0.4
2.3 V
0.55
VIL = 0.8 V
VIL = 0.8 V
3V
0.55
2.7 V
0.6
VIL = 0.8 V
3V
0.8
±5
3.6 V
2.3 V
45
VI = 1.7 V
VI = 0.8 V
2.3 V
−45
One input at VCC − 0.6 V,
3V
75
3V
−75
Data inputs
V
µA
µA
3.6 V
±500
3.6 V
±10
µA
3.6 V
20
µA
500
µA
3 V to 3.6 V
Control inputs
Ci
V
0.2
2.3 V
IO = 0
Other inputs at VCC or GND
UNIT
V
VIL = 0.7 V
VIL = 0.7 V
VI = VCC or GND
VI = 0.7 V
VO = VCC or GND
VI = VCC or GND,
∆ICC
−1.2
2.3 V
VIH = 2 V
VIH = 2 V
VI = 2 V
VI = 0 to 3.6 V‡
IOZ
ICC
MAX
2.3 V to 3.6 V
IOL = 6 mA
II
TYP†
2.3 V
2.3 V to 3.6 V
VIH = 1.7 V
VIH = 1.7 V
IOH = −6 mA
VOL
MIN
VCC
3.5
VI = VCC or GND
3.3 V
pF
4.5
Co
Outputs
VO = VCC or GND
3.3 V
4.5
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
ten
tdis
PARAMETER
VCC = 2.5 V
± 0.2 V
MIN
MAX
Y
1.2
OE
Y
OE
Y
VCC = 2.7 V
MIN
VCC = 3.3 V
± 0.3 V
UNIT
MAX
MIN
MAX
3.8
4
1.7
3.5
ns
1
5.7
5.7
1
4.8
ns
1
4.9
5.4
1.7
5.2
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
4
Power dissipation capacitance
per bit (one output switching)
TEST CONDITIONS
One OE enabled
All outputs disabled
POST OFFICE BOX 655303
CL = 0,
f = 10 MHz
• DALLAS, TEXAS 75265
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
17
17.5
0.4
0.5
UNIT
pF
SCES624 − FEBRUARY 2005
PARAMETER MEASUREMENT INFORMATION
RL
From Output
Under Test
VLOAD
Open
S1
GND
CL
(see Note A)
RL
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUT
VCC
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
2.7 V
2.7 V
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
1.5 V
1.5 V
2 × VCC
6V
6V
30 pF
50 pF
50 pF
500 Ω
500 Ω
500 Ω
0.15 V
0.3 V
0.3 V
tw
VI
Timing
Input
VM
VM
VM
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VM
VM
0V
tPLH
Output
Control
(low-level
enabling)
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLZ
VLOAD/2
VM
tPZH
tPHL
VOH
VM
VI
VM
tPZL
VI
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VI
Data
Input
VM
0V
0V
tsu
Output
VI
VM
Input
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VOH
VM
VOH − V∆
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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5
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74ALVCHS162830AGR
ACTIVE
TSSOP
DBB
80
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ALVCHS162830AGRE4
ACTIVE
TSSOP
DBB
80
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ALVCHS162830AGRG4
ACTIVE
TSSOP
DBB
80
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS005D – JANUARY 1995 – REVISED MARCH 2002
DBB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
80 PINS SHOWN
0,23
0,13
0,40
80
0,07 M
41
6,20
6,00
8,30
7,90
0,20
0,09
1
Gage Plane
40
A
0,25
0°–ā8°
0,75
0,45
Seating Plane
1,20 MAX
0,15
0,05
PINS**
0,08
80
100
A MAX
17,10
20,90
A MIN
16,90
20,70
DIM
4040212 / E 03/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC : 80 Pin – MO-153 Variation FF
100 Pin – MO-194 Variation BB
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1
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