LTC2978 Octal Digital Power Supply Manager with EEPROM FEATURES DESCRIPTION I2C/SMBus Serial Interface n PMBus Compliant Command Set n Configuration EEPROM with CRC n Black Box Fault Logging to Internal EEPROM n Differential Input, 16-Bit ΔΣ ADC with Less Than ±0.25% of Total Unadjusted Error n Eight Voltage Servos Precisely Adjust Output Voltages Using Eight 10-Bit DACs with Soft-Connect n Monitors Eight Output Voltages and One Input Voltage and Internal Die Temperature n 8-Channel Sequencer n Programmable Watchdog Timer n Eight UV/OV V OUT and One VIN Supervisor n Supports Multi-Channel Fault Management n Operates Autonomously without Additional Software n LTC2978 Can Be Powered from 3.3V or 4.5V to 15V n Available in 64-pin 9mm × 9mm QFN package The LTC®2978 is an octal, digital power-supply monitor, supervisor, sequencer, and margin controller. Eight output channels can be managed per user defined configuration settings. Supervisory functions include fault OV/UV threshold limits for eight output channels and one input channel. Programmable fault dependencies and responses allow the power supplies to be disabled with optional retry after a fault has been detected. Serial bus telemetry allows eight output voltages, one input voltage, die temperature and fault status to be monitored. In addition, odd numbered channels can be configured to measure the voltage across a current sense resistor. Power supply sequencing, precision point-of-load voltage adjustment and margining are supported with PMBus commands. A programmable watchdog timer monitors microprocessor activity for a stalled condition and resets the microprocessor if necessary. The 1-wire synchronization bus supports power supply sequencing across multiple LTC digital power devices. User programmable parameters can be stored in EEPROM. Faults and telemetry data can be logged to EEPROM for diagnostic analysis. n APPLICATIONS Computers Network Servers n Industrial Test and Measurement n High Reliability Systems n Medical Imaging nVideo n n L, LT, LTC, LTM, PolyPhase, Linear Technology and the Linear logo are registered trademarks and LTpowerPlay ia a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 7382303 and 7420359. TYPICAL APPLICATION Typical ADC Total Unadjusted Error vs Temperature Octal Power Supply Controller with PMBus Interface 0.035 VIN 4.5V < VIBUS < 15V VIN_SNS VDD33 VDACP0 TO INTERMEDIATE BUS CONVERTER ENABLE VIN_EN SDA PMBus INTERFACE VOUT VSENSEP0 LTC2978* SCL R30 R20 VFB LOAD VDACM0 DIGITALLY MANAGED POWER SUPPLY R10 ALERTB VSENSEM0 SGND CONTROL0 VOUT_EN0 RUN/SS GND WRITE-PROTECT WP TO/FROM OTHER LTC2978s FAULTB00 PWRGD WDI/RESETB ASEL0 SHARE_CLK ASEL1 GND 2978 TA01a 0.025 ERROR (%) VPWR 3.3V** ADC VIN = 1.8V 0.030 0.020 0.015 0.010 0.005 TO µP RESETB INPUT WATCHDOG TIMER INTERRUPT *SOME DETAILS OMITTED FOR CLARITY ONLY ONE OF EIGHT CHANNELS SHOWN 0 –50 –35 –20 –5 10 25 40 55 70 85 100 TEMPERATURE (°C) 2978 TA01b **LTC2978 MAY BE POWERED FROM EITHER AN EXTERNAL 3.3V SUPPLY OR THE INTERMEDIATE BUS 2978fc 1 LTC2978 TABLE OF CONTENTS Features...................................................... 1 Applications................................................. 1 Typical Application......................................... 1 Description.................................................. 1 Absolute Maximum Ratings............................... 4 Order Information........................................... 4 Pin Configuration........................................... 4 Electrical Characteristics.................................. 5 PMBus Timing Diagram.................................... 9 Typical Performance Characteristics................... 10 Pin Functions............................................... 14 Block Diagram.............................................. 16 Operation................................................... 17 Operation Overview................................................. 17 EEPROM.............................................................. 17 Reset....................................................................... 18 Write-Protect Pin..................................................... 18 Other Operations..................................................... 18 Clock Sharing...................................................... 18 PMBus Serial Digital Interface................................. 19 PMBus................................................................. 19 Device Address....................................................22 Processing Commands........................................23 PMBus Command Summary............................. 24 Summary Table.................................................... 24 Data Formats....................................................... 28 PMBus Command Description........................... 29 Operation, Mode and EEPROM Commands.............29 PAGE...................................................................29 OPERATION.........................................................30 ON_OFF_CONFIG................................................. 31 CLEAR_FAULTS.................................................. 31 WRITE_PROTECT................................................ 32 STORE_USER_ALL and RESTORE_USER_ALL.. 32 CAPABILITY......................................................... 32 VOUT_MODE.......................................................33 Output Voltage Related Commands.........................33 VOUT_COMMAND, VOUT_MAX, VOUT_MARGIN_ HIGH, VOUT_MARGIN_LOW, VOUT_OV_FAULT_ LIMIT, VOUT_OV_WARN_LIMIT, VOUT_UV_ WARN_LIMIT, VOUT_UV_FAULT_LIMIT, POWER_ GOOD_ON and POWER_GOOD_OFF...................33 Input Voltage Related Commands............................33 VIN_ON, VIN_OFF, VIN_OV_FAULT_LIMIT, VIN_ OV_WARN_LIMIT, VIN_UV_WARN_LIMIT and VIN_UV_FAULT_LIMIT........................................33 Temperature Related Commands.............................34 OT_FAULT_LIMIT, OT_WARN_LIMIT, UT_WARN_ LIMIT and UT_FAULT_LIMIT................................34 Timer Limits............................................................34 TON_DELAY, TON_RISE, TON_MAX_FAULT_ LIMIT and TOFF_DELAY......................................34 Fault Response for Voltages Measured by the High Speed Supervisor....................................................35 VOUT_OV_FAULT_RESPONSE and VOUT_UV_ FAULT_RESPONSE..............................................35 Fault Response for Values Measured by the ADC....36 OT_FAULT_RESPONSE, UT_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE and VIN_UV_FAULT_ RESPONSE..........................................................36 Timed Fault Response.............................................36 TON_MAX_FAULT_RESPONSE...........................36 Status Commands................................................... 37 STATUS_BYTE:.................................................... 37 STATUS_WORD:..................................................38 STATUS_VOUT....................................................38 STATUS_INPUT...................................................39 STATUS_TEMPERATURE..................................... 39 STATUS_CML......................................................40 STATUS_MFR_SPECIFIC.....................................40 ADC Monitoring Commands.................................... 41 READ_VIN........................................................... 41 READ_VOUT........................................................ 41 READ_TEMPERATURE_1 ................................... 41 PMBUS_REVISION.............................................. 41 Manufacturer Specific Commands........................... 42 MFR_CONFIG_LTC2978...................................... 42 MFR_CONFIG_ALL_LTC2978.............................43 MFR_FAULTz0_PROPAGATE, MFR_FAULTz1_ PROPAGATE........................................................44 MFR_PWRGD_EN...............................................45 MFR_FAULTB00_RESPONSE, MFR_FAULTB01_ RESPONSE, MFR_FAULTB10_RESPONSE and MFR_FAULTB11_RESPONSE...............................46 MFR_VINEN_OV_FAULT_RESPONSE.................. 47 MFR_VINEN_UV_FAULT_RESPONSE..................48 2978fc 2 LTC2978 TABLE OF CONTENTS MFR_RETRY_DELAY...........................................48 MFR_RESTART_DELAY....................................... 49 MFR_VOUT_PEAK............................................... 49 MFR_VIN_PEAK.................................................. 49 MFR_TEMPERATURE_PEAK............................... 49 MFR_DAC............................................................50 MFR_POWERGOOD_ASSERTION_DELAY..........50 Watchdog Operation................................................50 MFR_WATCHDOG_T_FIRST and MFR_ WATCHDOG_T.....................................................50 MFR_PAGE_FF_MASK........................................ 51 MFR_PADS.......................................................... 52 MFR_I2C_BASE_ADDRESS................................ 52 MFR_SPECIAL_ID............................................... 52 MFR_SPECIAL_LOT............................................53 MFR_VOUT_DISCHARGE_THRESHOLD..............53 MFR_COMMON...................................................53 MFR_SPARE0......................................................53 MFR_SPARE2......................................................53 MFR_VOUT_MIN.................................................54 MFR_VIN_MIN....................................................54 MFR_TEMPERATURE_MIN.................................54 Fault Log Operation.................................................54 MFR_FAULT_LOG_STORE..................................55 MFR_FAULT_LOG_RESTORE..............................55 MFR_FAULT_LOG_CLEAR...................................55 MFR_FAULT_LOG_STATUS.................................55 MFR_FAULT_LOG................................................56 Applications Information................................. 62 Overview..................................................................62 Powering the LTC2978.............................................62 Setting Command Register Values..........................62 Sequence, Servo, Margin and Restart Operations...62 Command Units On or Off...................................62 On Sequencing....................................................63 On State Operation..............................................63 Servo Modes.......................................................63 DAC Modes..........................................................63 Margining............................................................64 Off Sequencing....................................................64 VOUT Off Threshold Voltage.................................64 Automatic Restart Via MFR_RESTART_DELAY Command and CONTROLn pin............................64 Fault Management...................................................64 Output Overvoltage and Undervoltage Faults......64 Output Overvoltage and Undervoltage Warnings.65 Configuring the VIN_EN Output.............................65 Multichannel Fault Management ......................... 67 Interconnect Between Multiple LTC2978s................ 67 Application Circuits..................................................69 Trimming and Margining DC/DC Converters with External Feedback Resistors...............................69 Four-Step Resistor Selection Procedure for DC/DC Converters with External Feedback Resistors.....69 Trimming and Margining DC/DC Converters with a TRIM Pin............................................................. 70 Two-Step Resistor and DAC Full-Scale Voltage Selection Procedure for DC/DC Converters with a TRIM Pin............................................................. 70 Measuring Current............................................... 71 Measuring Current with a Sense Resistor........... 71 Measuring Current with Inductor DCR................. 71 Single Phase Design Example.............................72 Measuring Multiphase Currents..........................72 Multiphase Design Example................................ 72 Anti-aliasing Filter Considerations.......................73 Sensing Negative Voltages..................................73 Connecting the USB to I2C/SMBus/PMBus Controller to the LTC2978 in System........................................ 74 LTpowerPlay: An Interactive GUI for Digital Power.. 76 PCB Assembly and Layout Suggestions..................77 Bypass Capacitor Placement...............................77 Exposed Pad Stencil Design................................77 PC Board Layout.................................................77 Unused ADC Sense Inputs...................................77 Package Description...................................... 78 Revision History........................................... 79 Typical Application........................................ 80 Related Parts............................................... 80 2978fc 3 LTC2978 Supply Voltages: VPWR to GND.......................................... –0.3V to 15V VIN_SNS to GND...................................... –0.3V to 15V VDD33 to GND........................................ –0.3V to 3.6V VDD25 to GND...................................... –0.3V to 2.75V Digital Input/Output Voltages: ALERTB, SDA, SCL, CONTROL0, CONTROL1............................................. –0.3V to 5.5V PWRGD, SHARE_CLK, WDI/RESETB, WP.....................–0.3V to VDD33 + 0.3V FAULTB00, FAULTB01, FAULTB10, FAULTB11.................................–0.3V to VDD33 + 0.3V ASEL0, ASEL1...........................–0.3V to VDD33 + 0.3V Analog Voltages: REFP.................................................... –0.3V to 1.35V REFM to GND......................................... –0.3V to 0.3V VSENSEP[7:0] to GND.................................. –0.3V to 6V VSENSEM[7:0] to GND................................. –0.3V to 6V VOUT_EN[3:0], VIN_EN to GND................... –0.3V to 15V VOUT_EN[7:4] to GND.................................. –0.3V to 6V VDACP[7:0] to GND..................................... –0.3V to 6V VDACM[7:0] to GND ................................. –0.3V to 0.3V Operating Junction Temperature Range: LTC2978C................................................. 0°C to 70°C LTC2978I..............................................–40°C to 85°C Storage Temperature Range................... –65°C to 125°C PIN CONFIGURATION TOP VIEW 64 VSENSEP6 63 VSENSEM5 62 VSENSEP5 61 VDACM7 60 VDACP7 59 VDACP6 58 VDACM6 57 VDACM5 56 VDACP5 55 VDACP4 54 VDACM4 53 VSENSEM4 52 VSENSEP4 51 VDACM3 50 VDACP3 49 VSENSEM3 (Notes 1, 2) VSENSEM6 1 VSENSEP7 2 VSENSEM7 3 VOUT_EN0 4 VOUT_EN1 5 VOUT_EN2 6 VOUT_EN3 7 VOUT_EN4 8 VOUT_EN5 9 VOUT_EN6 10 VOUT_EN7 11 VIN_EN 12 DNC 13 VIN_SNS 14 VPWR 15 VDD33 16 65 48 VSENSEP3 47 VSENSEM2 46 VSENSEP2 45 VDACM2 44 VDACP2 43 VSENSEM1 42 VSENSEP1 41 VDACM1 40 VDACP1 39 VDACP0 38 VDACM0 37 VSENSEM0 36 VSENSEP0 35 REFM 34 REFP 33 ASEL1 VDD33 17 VDD25 18 WP 19 PWRGD 20 SHARE_CLK 21 WDI/RESETB 22 FAULTB00 23 FAULTB01 24 FAULTB10 25 FAULTB11 26 SDA 27 SCL 28 ALERTB 29 CONTROL0 30 CONTROL1 31 ASEL0 32 ABSOLUTE MAXIMUM RATINGS UP PACKAGE 64-LEAD (9mm × 9mm) PLASTIC QFN TJMAX = 125°C, θJC-TOP = 7°C/W, θJC-BOTTOM = 1°C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE JUNCTION LTC2978CUP#PBF LTC2978CUP#TRPBF LTC2978UP 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C LTC2978IUP#PBF LTC2978IUP#TRPBF LTC2978UP 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2978fc 4 LTC2978 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C. VPWR = VIN_SNS = 12V, VDD33, VDD25 and REF pins floating, unless otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 15 V 10 13 mA 10 13 mA 2.55 2.8 V Power-Supply Characteristics VPWR VPWR Supply Input Operating Range IPWR VPWR Supply Current 4.5V ≤ VPWR ≤ 15V, VDD33 Floating l IVDD33 VDD33 Supply Current 3.13V ≤ VDD33 ≤ 3.47V, VPWR = VDD33 l VUVLO_VDD33 VDD33 Undervoltage Lockout VDD33 Ramping Up, VPWR = VDD33 l l 4.5 2.35 VDD33 Undervoltage Lockout Hysteresis VDD33 VDD25 120 Supply Input Operating Range VPWR = VDD33 l 3.13 Regulator Output Voltage 4.5V ≤ VPWR ≤ 15V mV 3.47 V l 3.13 3.26 3.47 V Regulator Output Short-Circuit Current VPWR = 4.5V, VDD33 = 0V l 75 90 140 mA Regulator Output Voltage l 2.35 2.5 2.6 V l 30 55 80 mA 3.13V ≤ VDD33 ≤ 3.47V Regulator Output Short-Circuit Current VPWR = VDD33 = 3.47V, VDD25 = 0V Voltage Reference Characteristics VREF Output Voltage 1.232 Temperature Coefficient Hysteresis V 3 ppm/°C 100 (Note 3) ppm ADC Characteristics VIN_ADC Voltage Sense Input Range Current Sense Input Range (Odd Numbered Channels Only) N_ADC Differential Voltage: VIN_ADC = (VSENSEPn – VSENSEMn) l 0 6 V Single-Ended Voltage: VSENSEMn l –0.1 0.1 V Single-Ended Voltage: VSENSEPn, VSENSEMn l –0.1 6 V Differential Voltage: VIN_ADC l –170 170 mV Voltage Sense Resolution Uses L16 Format 0V ≤ VIN_ADC ≤ 6V Current Sense Resolution (Odd Numbered Channels Only) 0mV ≤ |VIN_ADC| < 16mV (Note13) 16mV ≤ |VIN_ADC| < 32mV 32mV ≤ |VIN_ADC| < 63.9mV 63.9mV ≤ |VIN_ADC| < 127.9mV 127.9mV ≤ |VIN_ADC| TUE_ADC Total Unadjusted Error VIN_ADC ≥ 1.8V (Note 4 ) l ±0.25 % INL_ADC Integral Nonlinearity Voltage Sense Mode (Note 5) l ±854 µV Current Sense Mode, Odd Numbered Channels Only, 15.6µV/LSB (Note 5) l ±31.3 µV Voltage Sense Mode l ±400 µV Current Sense Mode, Odd Numbered Channels Only l ±31.3 µV Voltage Sense Mode l ±250 µV Current Sense Mode, Odd Numbered Channels Only l ±35 µV Voltage Sense Mode, VIN_ADC = 6V l ±0.2 % Current Sense Mode, Odd Numbered Channels Only, VIN_ADC = ±0.17V l ±0.2 % DNL_ADC VOS_ADC GAIN_ADC Differential Nonlinearity Offset Error Gain Error 122 µV/LSB 15.625 31.25 62.5 125 250 µV/LSB µV/LSB µV/LSB µV/LSB µV/LSB 2978fc 5 LTC2978 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C. VPWR = VIN_SNS = 12V; VDD33, VDD25 and REF pins floating, unless otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF. SYMBOL PARAMETER CONDITIONS MIN tCONV_ADC Conversion Time Voltage Sense Mode (Note 6) 6.15 ms Current Sense Mode (Note 6) 24.6 ms Temperature Input (Note 6) 24.6 ms 1 pF 62.5 kHz CIN_ADC Input Sampling Capacitance fIN_ADC Input Sampling Frequency IIN_ADC Input Leakage Current VIN_ADC = 0V, 0V ≤ VCOMMONMODE ≤ 6V, Current Sense Mode l Differential Input Current VIN_ADC = 0.17V, Current Sense Mode l VIN_ADC = 6V, Voltage Sense Mode l TYP MAX UNITS ±0.5 µA 80 250 nA 10 15 µA Voltage Buffered IDAC Output Characteristics N_VDACP Resolution VFS_VDACP Full-Scale Output Voltage (Programmable) DAC Code = 0x3FF Buffer Gain Setting_0 DAC Polarity = 1 Buffer Gain Setting_1 l l 10 INL_VDACP Integral Nonlinearity (Note 7) l ±2 LSB DNL_VDACP Differential Nonlinearity (Note 7) l ±2.4 LSB VOS_VDACP Offset Voltage (Note 7) l VDACP Load Regulation (VDACPn – VDACMn) VDACPn = 2.65V, IVDACPn Sourcing = 2mA 100 ppm/mA VDACPn = 0.1V, IVDACPn Sinking = 2mA 100 ppm/mA PSRR (VDACPn – VDACMn) DC: 3.13V ≤ VDD33 ≤ 3.47V, VPWR = VDD33 60 dB 100mV Step in 20ns with 50pF Load 40 dB 1.32 2.53 1.38 2.65 Bits 1.44 2.77 ±10 DC CMRR (VDACPn – VDACMn) –0.1V ≤ VDACMn ≤ 0.1V Leakage Current VDACPn Hi-Z, 0V ≤ VDACPn ≤ 6V l 60 Short-Circuit Current Low VDACPn Shorted to GND l –10 l 4 V V mV dB ±100 nA –4 mA 10 mA Short-Circuit Current High VDACPn Shorted to VDD33 COUT Output Capacitance VDACPn Hi-Z 10 pF tS_VDACP DAC Output Update Rate Fast Servo Mode 250 µs Voltage Supervisor Characteristics VIN_VS N_VS TUE_VS tS_VS Input Voltage Range (Programmable) Voltage Sensing Resolution Total Unadjusted Error VIN_VS = (VSENSEPn Low Resolution Mode – VSENSEMn) High Resolution Mode l l 0 0 6 3.8 V V Single-Ended Voltage: VSENSEMn l –0.1 0.1 V 0V to 3.8V Range: High Resolution Mode 4 mV/LSB 0V to 6V Range: Low Resolution Mode 8 mV/LSB 2V ≤ VIN_VS ≤ 6V, Low Resolution Mode l ±1.25 % 1.5V < VIN_VS ≤ 3.8V, High Resolution Mode l ±1.0 % 0.8V ≤ VIN_VS ≤ 1.5V, High Resolution Mode l ±1.5 % Update Rate 12.21 µs VIN_SNS Input Characteristics VVIN_SNS VIN_SNS Input Voltage Range l 0 RVIN_SNS VIN_SNS Input Resistance l 70 90 15 V 110 kΩ 2978fc 6 LTC2978 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C. VPWR = VIN_SNS = 12V; VDD33, VDD25 and REF pins floating, unless otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF. SYMBOL PARAMETER CONDITIONS MAX UNITS 3V ≤ VVIN_SNS ≤ 8V l TUEVIN_SNS VIN_ON, VIN_OFF Threshold Total Unadjusted Error READ_VIN Total Unadjusted Error MIN TYP ±2.0 % VVIN_SNS > 8V l ±1.0 % 3V ≤ VVIN_SNS ≤ 8V l ±1.5 % VVIN_SNS > 8V l ±1.0 % ±18 mV Voltage Buffered IDAC Soft-Connect Comparator Characteristics VOS_CMP Offset Voltage ±3 l Temperature Sensor Characteristics TUE_TS Total Unadjusted Error ±1 °C VOUT Enable Output (VOUT_EN [3:0]) Characteristics VVOUT_ENn Output High Voltage (Note 12) IVOUT_ENn = –5µA, VDD33 = 3.3V IVOUT_ENn Output Sourcing Current Output Sinking Current Output Leakage Current 11.6 12.5 14.7 VVOUT_ENn Pull-Up Enabled, VVOUT_ENn = 1V l –5 –6 –8 µA Strong Pull-Down Enabled, VVOUT_ENn = 0.4V l 3 5 8 mA Weak Pull-Down Enabled, VVOUT_ENn = 0.4V l 33 50 60 µA ±1 µA 9 mA ±1 µA V l Internal Pull-Up Disabled, 0V ≤ VVOUT_ENn ≤ 15V l Output Sinking Current Strong Pull-Down Enabled, VOUT_ENn = 0.1V l Output Leakage Current 0V ≤ VVOUT_ENn ≤ 6V l V VOUT Enable Output (VOUT_EN [7:4]) Characteristics IVOUT_ENn 3 6 VIN Enable Output (VIN_EN) Characteristics VVIN_EN Output High Voltage IVIN_EN = –5µA, VDD33 = 3.3V l 11.6 12.5 14.7 IVIN_EN Output Sourcing Current VIN_EN Pull-Up Enabled, VVIN_EN = 1V l –5 –6 –8 µA Output Sinking Current VVIN_EN = 0.4V l 3 5 8 mA Leakage Current Internal Pull-Up Disabled, 0V ≤ VVIN_EN ≤ 15V l ±1 µA 0°C < TJ < 85°C During EEPROM Write Operations l 10,000 l 10 EEPROM Characteristics Endurance (Notes 8, 11) Retention (Notes 8, 11) TJ < 85°C Mass_Write Mass Write Operation Time (Note 9) STORE_USER_ALL, 0°C < TJ < 85°C During l EEPROM Write Operations Cycles Years 440 4100 ms Digital Inputs SCL, SDA, CONTROL0, CONTROL1, WDI/RESETB, FAULTB00, FAULTB01, FAULTB10, FAULTB11, WP VIH High Level Input Voltage l VIL Low Level Input Voltage l VHYST Input Hysteresis ILEAK Input Leakage Current tSP tFAULT_MIN Pulse Width of Spike Suppressed Minimum Low Pulse Width for Externally Generated Faults 2.1 V 1.5 20 V mV 0V ≤ VPIN ≤ 5.5V, SDA, SCL, CONTROLx Pins Only l ±2 µA 0V ≤ VPIN ≤ VDD33 + 0.3V, FAULTBxx, WDI/RESETB, WP Pins Only l ±2 µA FAULTBxx, CONTROLx Pins Only 10 µs SDA, SCL Pins Only 98 ns 110 ms 2978fc 7 LTC2978 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25°C. VPWR = VIN_SNS = 12V; VDD33, VDD25 and REF pins floating, unless otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF. SYMBOL PARAMETER CONDITIONS MIN tRESETB Pulse Width to Assert Reset VWDI/RESETB ≤ 1.5V l 300 tWDI Pulse Width to Reset Watchdog Timer VWDI/RESETB ≤ 1.5V l 0.3 fWDI Watchdog Interrupt Input Frequency CIN Digital Input Capacitance TYP MAX UNITS µs 200 1 l 10 µs MHz pF Digital Input SHARE_CLK VIH High Level Input Voltage l VIL Low Level Input Voltage l fSHARE_CLK_IN Input Frequency Operating Range 1.6 l 90 0.825 V 0.8 V 110 kHz tLOW Assertion Low Time VSHARE_CLK < 0.8V l 1.1 µs tRISE Rise Time VSHARE_CLK < 0.8V to VSHARE_CLK > 1.6V l 450 ns ILEAK Input Leakage Current 0V ≤ VSHARE_CLK ≤ VDD33 + 0.3V l ±1 µA CIN Input Capacitance 10 pF Digital Outputs SDA, ALERTB, PWRGD, SHARE_CLK, FAULTB00, FAULTB01, FAULTB10, FAULTB11 VOL Digital Output Low Voltage fSHARE_CLK_OUT Output Frequency Operating Range ISINK = 3mA l 5.49kΩ Pull-Up to VDD33 l 90 VDD33 – 0.5 100 0.4 V 110 kHz Digital Inputs ASEL0,ASEL1 VIH Input High Threshold Voltage l VIL Input Low Threshold Voltage l 0.5 V IIH,IL High, Low Input Current l ±95 µA IIH, Z Hi-Z Input Current l ±24 µA CIN Input Capacitance ASEL[1:0] = 0, VDD33 V 10 pF Serial Bus Timing Characteristics fSCL Serial Clock Frequency (Note 10) l 10 400 tLOW Serial Clock Low Period (Note 10) l 1.3 µs tHIGH Serial Clock High Period (Note 10) l 0.6 µs tBUF Bus Free Time Between Stop and Start (Note 10) l 1.3 µs tHD,STA Start Condition Hold Time (Note 10) l 600 ns tSU,STA Start Condition Setup Time (Note 10) l 600 ns tSU,STO Stop Condition Setup Time (Note 10) l 600 ns tHD,DAT Data Hold Time (LTC2978 Receiving Data) (Note 10) l 0 ns Data Hold Time (LTC2978 Transmitting Data) (Note 10) l 300 tSU,DAT Data Setup Time (Note 10) l 100 tSP Pulse Width of Spike Suppressed (Note 10) tTIMEOUT_BUS Time Allowed to Complete any PMBus Longer Timeout = 0 Command After Which Time SDA Will Longer Timeout = 1 Be Released and Command Terminated 900 ns ns 98 l l kHz 25 200 ns 35 280 ms ms 2978fc 8 LTC2978 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating for extended periods may affect device reliability and lifetime. Note 2: All currents into device pins are positive. All currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified. If power is supplied to the chip via the VDD33 pin only, connect VPWR and VDD33 pins together. Note 3: Hysteresis in the output voltage is created by package stress that differs depending on whether the IC was previously at a higher or lower temperature. Output voltage is always measured at 25°C, but the IC is cycled to 85°C or –40°C before successive measurements. Hysteresis is roughly proportional to the square of the temperature change. Note 4: TUE(%) is defined as: Gain Error (%) + 100 • (INL + VOS)/VIN. Note 5: Integral nonlinearity (INL) is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve (0V and 6V). The deviation is measured from the center of the quantization band. Note 6: The time between successive ADC conversions (latency of the ADC) for any given channel is given as: 36.9ms + (6.15ms • number of ADC channels configured in Low Resolution mode) + (24.6ms • number of ADC channels configured in High Resolution mode). Note 7: Nonlinearity is defined from the first code that is greater than or equal to the maximum offset specification to full-scale code, 1023. Note 8: EEPROM endurance and retention are guaranteed by design, characterization and correlation with statistical process controls. The minimum retention specification applies for devices whose EEPROM has been cycled less than the minimum endurance specification. Note 9: The LTC2978 will not acknowledge any PMBus commands while a mass write operation is being executed. This includes the STORE_USER_ALL and MFR_FAULT_LOG_STORE commands or a fault log store initiated by a channel faulting off. Note 10: Maximum capacitive load, CB, for SCL and SDA is 400pF. Data and clock rise time (tr) and fall time (tf) are: (20 + 0.1 • CB) (ns) < tr < 300ns and (20 + 0.1 • CB) (ns) < tf < 300ns. CB = capacitance of one bus line in pF. SCL and SDA external pull-up voltage, VIO, is 3.13V < VIO < 5.5V. Note 11: EEPROM endurance and retention will be degraded when TJ > 85°C. Note 12: Output enable pins are charge pumped from VDD33. Note 13: The current sense resolution is determined by the L11 format and the mV units of the returned value. For example a full scale value of 170mV returns a L11 value of 0xF2A8 = 680 • 2–2 = 170. This is the lowest range that can represent this value without overflowing the L11 mantissa and the resolution for 1LSB in this range is 2–2 mV = 250µV. Each successively lower range improves resolution by cutting the LSB size in half. PMBUS TIMING DIAGRAM SDA tf tLOW tr tSU(DAT) tHD(SDA) tf tSP tr tBUF SCL tHD(STA) START CONDITION tHD(DAT) tHIGH tSU(STA) tSU(STO) 2978 TD REPEATED START CONDITION STOP CONDITION START CONDITION 2978fc 9 LTC2978 TYPICAL PERFORMANCE CHARACTERISTICS ADC Total Unadjusted Error vs Temperature Temperature Sensor Error vs Temperature Reference Voltage vs Temperature 1.6 0.035 1.2350 1.4 0.030 REFERENCE OUTPUT VOLTAGE (V) 1.2355 1.2345 1.2 1.2340 ERROR (%) 1.2330 0.025 1.0 ERROR (°C) 1.2335 0.8 0.6 1.2325 THREE TYPICAL PARTS 1.2310 –50 –35 –20 –5 10 25 40 55 70 85 100 TEMPERATURE (°C) 0 –50 –35 –20 –5 10 25 40 55 70 85 100 TEMPERATURE (°C) ADC Zero Code Center Offset Voltage vs Temperature VOLTAGE SENSE MODE ADC-DNL 0.8 122µV/LSB 0.6 2.5 –40 2.0 0.4 –60 1.5 0.2 –80 –100 ERROR (LSBs) –20 ERROR (LSBs) VOS (µV) 2978 G03 ADC-INL 3.0 –120 1.0 0 –0.4 0 –140 –0.5 –0.6 –160 –1.0 –0.8 –180 –50 –35 –20 –5 10 25 40 55 70 85 100 TEMPERATURE (°C) –1.5 –0.2 0 0.8 1.8 2.8 3.8 4.8 INPUT VOLTAGE (V) 5.8 –1.0 –0.2 0 ADC Rejection vs Frequency at VIN (Zoom) 0 –40 –40 –40 –120 REJECTION (dB) –20 REJECTION (dB) –20 –100 –60 –80 12500 25000 37500 50000 FREQUENCY (Hz) 62500 2978 G07 –120 5.8 ADC Rejection vs Frequency at VIN (Current Sense Mode) –60 –80 –100 –100 0 1.8 2.8 3.8 4.8 INPUT VOLTAGE (V) 2978 G06 –20 –80 0.8 2978 G05 ADC Rejection vs Frequency at VIN –60 122µV/LSB –0.2 0.5 2978 G04 REJECTION (dB) 0 –50 –35 –20 –5 10 25 40 55 70 85 100 TEMPERATURE (°C) 2978 G02 2978 G01 0 0.015 0.005 0.2 1.2315 0.020 0.010 0.4 1.2320 ADC VIN = 1.8V 0 3125 6250 9375 FREQUENCY (Hz) 12500 2978 G08 –120 0 12500 25000 37500 50000 FREQUENCY (Hz) 62500 2978 G09 2978fc 10 LTC2978 TYPICAL PERFORMANCE CHARACTERISTICS 1200 NUMBER OF READINGS REJECTION (dB) –60 –80 3125 0 6250 9375 FREQUENCY (Hz) –0.10 800 600 400 –0.25 –10 0 10 READ_VOUT (µV) –0.40 –50 –35 –20 –5 10 25 40 55 70 85 100 TEMPERATURE (°C) 20 2978 G11 Input Sampling Current vs Differential Input Voltage 2978 G12 DAC Full-Scale Output Voltage vs Temperature ADC High Resolution Mode Differential Input Current 9 90 2.698 8 80 2.696 7 6 5 4 3 2 1 0 0 1 2 3 4 INPUT VOLTAGE (V) 5 60 50 40 30 2.692 2.690 2.688 2.686 2.684 20 2.682 10 2.680 0 6 2.694 70 OUTPUT VOLTAGE (V) DIFFERENTIAL INPUT CURRENT (nA) INPUT SAMPLING CURRENT (µA) –0.20 –0.35 2978 G10 0 2.678 –50 –35 –20 –5 10 25 40 55 70 85 100 TEMPERATURE (°C) 20 40 60 80 100 120 140 160 180 DIFFERENTIAL INPUT VOLTAGE (mV) 2978 G13 2978 G15 2978 G14 DAC Offset Voltage vs Temperature DAC-INL DAC DNL 1.0 1.0 2.3 0.8 0.8 2.1 0.6 0.6 1.9 0.4 0.4 1.7 1.5 1.3 ERROR (LSBs) 2.5 ERROR (LSBs) OFFSET ERROR (mV) –0.15 –0.30 0 –20 12500 VIN = 0.8V HIGH RESOLUTION MODE –0.05 200 –100 –120 0 VIN = 0V HIGH RESOLUTION MODE 1000 –20 –40 Voltage Supervisor Total Unadjusted Error vs Temperature ADC Noise Histogram ERROR (%) 0 ADC Rejection vs Frequency at VIN (Current Sense Mode, Zoom) 0.2 0 –0.2 0.2 0 –0.2 1.1 –0.4 –0.4 0.9 –0.6 –0.6 0.7 –0.8 –0.8 0.5 –50 –35 –20 –5 10 25 40 55 70 85 100 TEMPERATURE (°C) –1.0 2978 G16 0 200 600 400 DAC CODE 800 1000 2978 G17 –1.0 0 200 600 400 DAC CODE 800 1000 2978 G18 2978fc 11 LTC2978 TYPICAL PERFORMANCE CHARACTERISTICS DAC Load Regulation (Sourcing) 85°C 2.696 25°C 2.692 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 2.694 2.690 2.688 2.686 2.684 2.682 2.678 9.00 0.1036 8.95 85°C 0.1034 25°C 0.1032 0.1030 –40°C 0.1028 –40°C 2.680 0.1038 0 –0.25 –0.5 –0.75 –1 –1.25 –1.50 1.75 CURRENT (mA) –2 SHORT-CIRCUIT CURRENT (mA) 2.698 DAC Short-Circuit Current vs Temperature DAC Load Regulation (Sinking) 0.1026 0 0.25 0.5 0.75 1 1.25 1.5 1.75 CURRENT (mA) 2978 G19 8.90 8.85 8.80 8.75 8.70 –50 –35 –20 –5 10 25 40 55 70 85 100 TEMPERATURE (°C) 2 2978 G21 2978 G20 DAC Soft Connect Transient Response when Transitioning from Hi-Z State to ON State DAC Transient Response to 1LSB DAC Code Change DAC Soft Connect Transient Response when Transitioning from ON State to Hi-Z State CODE ‘h200 HI-Z 500µV/DIV HI-Z 10mV/DIV 10mV/DIV CONNECTED CODE ‘h1FF 2978 G22 3.275 400 3.270 300 –86 85°C 200 3.265 3.260 3.255 3.250 3.245 25°C 100 –40°C 0 –100 –200 –300 3.240 –400 3.235 –50 –35 –20 –5 10 25 40 55 70 85 100 TEMPERATURE (°C) –500 2978 G25 2978 G24 VDD33 Regulator Short-Circuit Current vs Temperature VDD33 Regulator Line Regulation ∆VDD33 (ppm) VDD33 OUTPUT VOLTAGE (V) VDD33 Regulator Output Voltage vs Temperature 500µs/DIV 100k SERIES RESISTANCE ON CODE: ‘h1FF 2978 G23 500µs/DIV 100k SERIES RESISTANCE ON CODE: ‘h1FF SHORT-CIRCUIT CURRENT (mA) 2µs/DIV CONNECTED –88 –90 –92 –94 –96 –98 –100 4.5 6 7.5 9 10.5 VPWR (V) 12 13.5 15 2978 G26 –102 –50 –35 –20 –5 10 25 40 55 70 85 100 TEMPERATURE (°C) 2978 G27 2978fc 12 LTC2978 TYPICAL PERFORMANCE CHARACTERISTICS 10.16 VPWR = VDD33 10.14 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 10.4 10.3 10.2 10.1 10.0 9.9 9.8 14.0 VPWR = 12V CHARGE PUMP OUTUPT HIGH VOLTAGE (V) 10.5 10.12 10.10 10.08 10.06 3 3.1 3.2 3.4 3.3 3.5 3.6 13.5 11.5 11.0 10.0 9.5 100 0.6 1.2 0.5 VOLTS (V) VOLTS (V) 0.8 25°C 1000 0.6 0 –40°C –40°C 0.1 0 2 4 8 6 ISINK (mA) 0 12 10 0 4 8 12 16 ISINK (mA) 20 24 2978 G33 2978 G32 PWRGD and FAULTBzn VOL vs Current ALERTB VOL vs Current 1.2 1.4 1.0 1.2 1.0 VOLTS (V) 0.8 VOLTS (V) 25°C 0.2 2978 G31 0.6 0.4 85°C 0.8 25°C 0.6 –40°C 0.4 85°C 25°C –40°C 0.2 0 7 85°C 0.3 0.2 100 6 0.4 85°C 0.4 0.1 10 1 FREQUENCY (kHz) 2 3 4 5 CURRENT SOURCING (µA) 1 VOUT_EN[7:4] VOL vs Current 1.4 1.0 0.1 0 2978 G30 VOUT_EN[3:0] and VIN_EN VOL vs Current 1000 0.01 0.01 –40°C 12.0 2978 G29 DAC Output Impedance vs Frequency 1 25°C 12.5 10.02 –50 –35 –20 –5 10 25 40 55 70 85 100 TEMPERATURE (°C) 2978 G28 10 85°C 13.0 10.5 10.04 VDD33 (V) OUTPUT IMPEDANCE (Ω) VOUT_EN[3:0] and VIN_EN Output High Voltage vs Load Current Supply Current vs Temperature Supply Current vs Supply Voltage 0 2 4 6 8 ISINK (mA) 10 0.2 12 2978 G34 0 0 2 4 8 6 ISINK (mA) 10 12 2978 G35 2978fc 13 LTC2978 PIN FUNCTIONS PIN NAME VSENSEM6 VSENSEP7 VSENSEM7 VOUT_EN0 VOUT_EN1 VOUT_EN2 VOUT_EN3 VOUT_EN4 VOUT_EN5 VOUT_EN6 VOUT_EN7 VIN_EN DNC VIN_SNS PIN NUMBER PIN TYPE 1* In 2* In 3* In 4 Out 5 Out 6 Out 7 Out 8 Out 9 Out 10 Out 11 Out 12 0ut 13 Do Not Connect 14 In VPWR 15 In VDD33 16 In/Out VDD33 VDD25 WP PWRGD 17 18 19 20 In In/Out In Out SHARE_CLK WDI/RESETB 21 22 In/Out In FAULTB00 23 In/Out FAULTB01 24 In/Out FAULTB10 25 In/Out FAULTB11 26 In/Out SDA SCL ALERTB CONTROL0 CONTROL1 ASEL0 ASEL1 REFP REFM VSENSEP0 VSENSEM0 VDACM0 VDACP0 VDACP1 27 28 29 30 31 32 33 34 35 36* 37* 38 39 40 In/Out In Out In In In In Out Out In In Out Out Out DESCRIPTION DC/DC Converter Differential (–) Output Voltage-6 Sensing Pin DC/DC Converter Differential (+) Output Voltage or Current-7 Sensing Pin DC/DC Converter Differential (–) Output Voltage or Current-7 Sensing Pin DC/DC Converter Enable-0 Pin. Output High Voltage Optionally Pulled Up to 12V by 5µA DC/DC Converter Enable-1 Pin. Output High Voltage Optionally Pulled Up to 12V by 5µA DC/DC Converter Enable-2 Pin. Output High Voltage Optionally Pulled Up to 12V by 5µA DC/DC Converter Enable-3 Pin. Output High Voltage Optionally Pulled Up to 12V by 5µA DC/DC Converter Open-Drain Pull-Down Output-4 DC/DC Converter Open-Drain Pull-Down Output-5 DC/DC Converter Open-Drain Pull-Down Output-6 DC/DC Converter Open-Drain Pull-Down Output-7 DC/DC Converter VIN ENABLE Pin. Output High Voltage Optionally Pulled Up to 12V by 5µA Do Not Connect to This Pin VIN SENSE Input. This Voltage is Compared Against the VIN On and Off Voltage Thresholds in Order to Determine When to Enable and Disable, Respectively, the Downstream DC/DC Converters VPWR Serves as the Unregulated Power Supply Input to the Chip (4.5V to 15V). If a 4.5V to 15V Supply Voltage is Unavailable, Short VPWR to VDD33 and Power the Chip Directly from a 3.3V Supply. Bypass to GND with 0.1µF Capacitor. If Shorted to VPWR, it Serves as 3.13V to 3.47V Supply Input Pin. Otherwise it is a 3.3V Internally Regulated Voltage Output (Use 100nF Decoupling Capacitor to GND) Input for Internal 2.5V Sub-Regulator. Short This Pin to Pin 16 2.5V Internally Regulated Voltage Output. Bypass to GND with a 0.1µF Capacitor Digital Input. Write-Protect Input Pin, Active High Power Good Open-Drain Output. Indicates When Outputs are Power Good. Can be Used as System Power-On Reset. The Latency of This Signal May Be as Long as the ADC Latency. See Note 6. Bidirectional Clock Sharing Pin. Connect a 5.49k Pull-Up Resistor to VDD33 Watchdog Timer Interrupt and Chip Reset Input. Connect a 10k Pull-Up Resistor to VDD33. Rising Edge Resets Watchdog Counter. Holding This Pin Low for More Than tRESETB Resets the Chip Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-00. Connect a 10k Pull-Up Resistor to VDD33 Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-01. Connect a 10k Pull-Up Resistor to VDD33 Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-10. Connect a 10k Pull-Up Resistor to VDD33 Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-11. Connect a 10k Pull-Up Resistor to VDD33 PMBus Bidirectional Serial Data Pin PMBus Serial Clock Input Pin (400kHz Maximum) Open-Drain Output. Generates an Interrupt Request in a Fault/Warning Situation Control Pin 0 Input Control Pin 1 Input Ternary Address Select Pin 0 Input. Connect to VDD33, GND or Float to Encode 1 of 3 Logic States Ternary Address Select Pin 1 Input. Connect to VDD33, GND or Float to Encode 1 of 3 Logic States Reference Voltage Output. Needs 0.1µF Decoupling Capacitor to REFM Reference Return Pin. Needs 0.1µF Decoupling Capacitor to REFP. DC/DC Converter Differential (+) Output Voltage-0 Sensing Pin DC/DC Converter Differential (–) Output Voltage-0 Sensing Pin DAC0 Return. Connect to Channel 0 DC/DC Converter’s GND Sense or Return to GND DAC0 Output DAC1 Output 2978fc 14 LTC2978 PIN FUNCTIONS PIN NAME PIN NUMBER PIN TYPE DESCRIPTION 41 Out DAC1 Return. Connect to Channel 1 DC/DC Converter’s GND Sense or Return to GND VDACM1 42* In DC/DC Converter Differential (+) Output Voltage or Current-1 Sensing Pins VSENSEP1 43* In DC/DC Converter Differential (–) Output Voltage or Current-1 Sensing Pins VSENSEM1 44 Out DAC2 Output VDACP2 45 Out DAC2 Return. Connect to Channel 2 DC/DC Converter’s GND Sense or Return to GND VDACM2 46* In DC/DC Converter Differential (+) Output Voltage-2 Sensing Pin VSENSEP2 47* In DC/DC Converter Differential (–) Output Voltage-2 Sensing Pin VSENSEM2 48* In DC/DC Converter Differential (+) Output Voltage or Current-3 Sensing Pins VSENSEP3 49* In DC/DC Converter Differential (–) Output Voltage or Current-3 Sensing Pins VSENSEM3 50 Out DAC3 Output VDACP3 51 Out DAC3 Return. Connect to Channel 3 DC/DC Converter’s GND Sense or Return to GND VDACM3 52* In DC/DC Converter Differential (+) Output Voltage-4 Sensing Pin VSENSEP4 53* In DC/DC Converter Differential (–) Output Voltage-4 Sensing Pin VSENSEM4 54 Out DAC4 Return. Connect to Channel 4 DC/DC Converter’s GND Sense or Return to GND VDACM4 55 Out DAC4 Output VDACP4 56 Out DAC5 Output VDACP5 57 Out DAC5 Return. Connect to Channel 5 DC/DC Converter’s GND Sense or Return to GND VDACM5 58 Out DAC6 Return. Connect to Channel 6 DC/DC Converter’s GND Sense or Return to GND VDACM6 59 Out DAC6 Output VDACP6 60 Out DAC7 Output VDACP7 61 Out DAC7 Return. Connect to Channel 7 DC/DC Converter’s GND Sense or Return to GND VDACM7 62* In DC/DC Converter Differential (+) Output Voltage or Current-5 Sensing Pins VSENSEP5 63* In DC/DC Converter Differential (–) Output Voltage or Current-5 Sensing Pins VSENSEM5 64* In DC/DC Converter Differential (+) Output Voltage-6 Sensing Pin VSENSEP6 GND 65 Ground Exposed Pad, Must be Soldered to PCB *Any unused VSENSEPn or VSENSEMn or VDACMn pins must be tied to GND. 2978fc 15 LTC2978 BLOCK DIAGRAM 3.3V REGULATOR VOUT VIN VPWR 15 VDD VDD33 16 2.5V REGULATOR VIN VOUT VIN_SNS 14 3R VSENSEM0 VSENSEP0 R VSENSEM1 GND 65 INTERNAL TEMP SENSOR VSENSEP1 36 VSENSEP0 VSENSEM2 37 VSENSEM0 VSENSEP2 42 VSENSEP1 VSENSEM3 43 VSENSEM1 VSENSEP3 46 VSENSEP2 VSENSEM4 MUX VSENSEP4 CMP0 VSENSEM5 VSENSEP5 + – + – VDD33 17 VDD25 18 47 VSENSEM2 + – 48 VSENSEP3 10-BIT VDAC 49 VSENSEM3 52 VSENSEP4 VSENSEM6 53 VSENSEM4 VSENSEP6 62 VSENSEP5 VSENSEM7 63 VSENSEM5 VSENSEP7 64 VSENSEP6 + 16-BIT – ∆∑ ADC 1 VSENSEM6 +SC 2 VSENSEP7 CMP0 ADC CLOCKS DAC0 10 BITS 3 VSENSEM7 – + 39 VDACP0 VBUF0 – 40 VDACP1 VDD 44 VDACP2 50 VDACP3 REFERENCE 1.232V (TYP) REFP 34 55 VDACP4 56 VDACP5 REFM 35 59 VDACP6 60 VDACP7 38 VDACM0 41 VDACM1 SDA 27 ALERTB 29 ASEL0 32 45 VDACM2 NONVOLATILE MEMORY SCL 28 PMBus INTERFACE (400kHz I2C COMPATIBLE) ASEL1 33 51 VDACM3 EEPROM 54 VDACM4 RAM 57 VDACM5 ADC_RESULTS MONITOR LIMITS SERVO TARGETS 58 VDACM6 61 VDACM7 WP 19 4 VOUT_EN0 OUTPUT CONFIG CONTROL0 30 CONTROL1 31 OSCILLATOR WDI/RESETB 22 FAULTB00 23 FAULTB01 24 FAULTB10 25 FAULTB11 26 PWRGD 20 SHARE_CLK 21 CONTROLLER PMBus ALGORITHM FAULT PROCESSOR WATCHDOG SEQUENCER CLOCK GENERATION 6 VOUT_EN2 7 VOUT_EN3 12 VIN_EN VDD UVLO 5 VOUT_EN1 8 VOUT_EN4 OPEN-DRAIN OUTPUT 9 VOUT_EN5 10 VOUT_EN6 11 VOUT_EN7 2978 BD 2978fc 16 LTC2978 OPERATION OPERATION OVERVIEW n The LTC2978 is a PMBus programmable power supply controller, monitor, sequencer and voltage supervisor that can perform the following operations: n Accept PMBus compatible programming commands. n Provide DC/DC converter input voltage and output voltage/current read back through the PMBus interface. n Control the output of DC/DC converters that set the output voltage with a trim pin or DC/DC converters that set the output voltage using an external resistor feedback network. n Restore EEPROM contents through PMBus programming or when VDD33 is applied on power-up. Report the DC/DC converter output voltage status through the PMBus interface and the power good output. Generate interrupt requests by asserting the ALERTB pin in response to supported PMBus faults and warnings. n Coordinate system wide fault responses for all DC/DC converters connected to the FAULTBz0 and FAULTBz1 pins. n Synchronize sequencing delays or shutdown for multiple devices using the SHARE_CLK pin. Sequence the start-up of DC/DC converters via PMBus programming and the CONTROL input pins. n Trim the DC/DC converter output voltage (typically in 0.2% steps), in closed-loop servo operating mode, through PMBus programming. n n n Margin the DC/DC converter output voltage to PMBus programmed limits. n Allow the user to trim or margin the DC/DC converter output voltage in a manual operating mode by providing direct access to the margin DAC. n Software and hardware write protect the command registers. Disable the input voltage to the supervised DC/DC converters in response to output voltage OV and UV faults. n Log telemetry and status data to EEPROM in response to a faulted-off condition n Supervise an external microcontroller’s activity for a stalled condition with a programmable watchdog timer and reset it if necessary. n Supervise the DC/DC converter output voltage, input voltage, and the LTC2978 die temperature for overvalue/undervalue conditions with respect to PMBus programmed limits and generate appropriate faults and warnings. n Respond to a fault condition by either continuing operation indefinitely, latching off after a programmable deglitch period or latching off immediately. A retry mode may be used to automatically recover from a latched-off condition. n n n Optionally stop trimming the DC/DC converter output voltage after it reached the initial margin or nominal target. Optionally allow servo to resume if target drifts outside of VOUT warning limits. n Store command register contents with CRC to EEPROM through PMBus programming. n Prevent a DC/DC converter from re-entering the ON state after a power cycle until a programmable interval (MFR_RESTART_DELAY) has elapsed and its output has decayed below a programmable threshold voltage (MFR_VOUT_DISCHARGE_THRESHOLD). Record minimum and maximum observed values of input voltage, output voltages and temperature. EEPROM The LTC2978 contains internal EEPROM (nonvolatile memory) to store configuration settings and fault log information. EEPROM endurance, retention, and mass write operation time are specified over the operating temperature range. See Electrical Characteristics and Absolute Maximum Ratings sections. 2978fc 17 LTC2978 OPERATION Nondestructive operation above TJ = 85°C is possible although the Electrical Characteristics are not guaranteed and the EEPROM will be degraded. Operating the EEPROM above 85°C may result in a degradation of retention characteristics. The fault logging function, which is useful in debugging system problems that may occur at high temperatures, only writes to fault log EEPROM locations. If occasional writes to these registers occur above 85°C, a slight degradation in the data retention characteristics of the fault log may occur. It is recommended that the EEPROM not be written using STORE_USER_ALL or bulk programming when TJ > 85°C. The degradation in EEPROM retention for temperatures >85°C can be approximated by calculating the dimensionless acceleration factor using the following equation. AF = e Ea 1 1 − • k TUSE + 273 TSTRESS + 273 RESET Holding the WDI/RESETB pin low for more than tRESETB will cause the LTC2978 to enter the power-on reset state. Following the subsequent rising-edge of the WDI/RESETB pin, the LTC2978 will execute its power-on sequence per the user configuration stored in EEPROM. WRITE-PROTECT PIN The WP pin allows the user to write-protect the LTC2978’s configuration registers. The WP pin is active high, and when asserted it provides Level 2 protection: all writes are disabled except to the WRITE_PROTECT, PAGE, STORE_USER_ALL, OPERATION, MFR_PAGE_FF_MASK and CLEAR_FAULTS commands. The most restrictive setting between the WP pin and WRITE_PROTECT command will override. For example if WP = 1 and WRITE_PROTECT = 0x80, then the WRITE_PROTECT command overrides, since it is the most restrictive. Where: OTHER OPERATIONS AF = acceleration factor Clock Sharing Ea = activation energy = 1.4 eV Multiple LTC PMBus devices can synchronize their clocks in an application by connecting together the open-drain SHARE_CLK input/outputs to a pull-up resistor as a wired OR. In this case the fastest clock will take over and synchronize all LTC2978s. k = 8.625×10−5 eV/°K TUSE = 85°C specified junction temperature TSTRESS = actual junction temperature °C Example: Calculate the effect on retention when operating at a junction temperature of 95°C for 10 hours. TSTRESS = 95°C TUSE = 85°C AF = 3.4 Equivalent operating time at 85°C = 34 hours. So the overall retention of the EEPROM was degraded by 34 hours as a result of operation at a junction temperature of 95°C for 10 hours. Note that the effect of this overstress is negligible when compared to the overall EEPROM retention rating of 87,600 hours at a maximum junction temperature of 85°C. SHARE_CLK can optionally be used to synchronize ON/OFF dependency on VIN across multiple chips by setting bit 3 (Mfr_config_all_vin_share_enable) of the MFR_CONFIG_ ALL register. When configured this way the chip will hold SHARE_CLK low when the unit is off for insufficient input voltage and upon detecting that SHARE_CLK is held low the chip will disable all channels after a brief deglitch period. When the SHARE_CLK pin is allowed to rise, the chip will respond by beginning a soft-start requence. In this case the slowest VIN_ON detection will take over and synchronize other chips to its soft-start sequence. 2978fc 18 LTC2978 OPERATION PMBus SERIAL DIGITAL INTERFACE The LTC2978 communicates with a host (master) using the standard PMBus serial bus interface. The PMBus Timing Diagram shows the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The LTC2978 is a slave device. The master can communicate with the LTC2978 using the following formats: Master transmitter, slave receiver n Master receiver, slave transmitter n The following SMBus protocols are supported: The PMBus two wire interface is an incremental extension of the SMBus. SMBus is built upon I2C with some minor differences in timing, DC parameters and protocol. The SMBus protocols are more robust than simple I2C byte commands because they provide timeouts to prevent bus hangs and optional packet error checking (PEC) to ensure data integrity. In general, a master device that can be configured for I2C communication can be used for PMBus communication with little or no change to hardware or firmware. For a description of the minor extensions and exceptions PMBus makes to SMBus, refer to PMBus Specification Part 1 Revision 1.1: paragraph 5: Transport. This can be found at: Write Byte, Write Word, Send Byte www.pmbus.org. Read Byte, Read Word, Block Read For a description of the differences between SMBus and I2C, refer to system management bus (SMBus) specification version 2.0: Appendix B – Differences Between SMBus and I2C. This can be found at: n n Alert Response Address n Figures 1-12 illustrate the aforementioned SMBus protocols. All transactions support PEC (parity error check) and GCP (group command protocol). The Block Read supports 255 bytes of returned data. For this reason, the PMBus timeout may be extended using the Mfr_config_all_ longer_pmbus_timeout setting. The LTC2978 will not acknowledge any PMBus command if it is still busy with a STORE_USER_ALL, RESTORE_ USER_ALL, MFR_CONFIG_LTC2978 or if fault log data is being written to the EEPROM. Status_word_busy will also be set. www.smbus.org. When using an I2C controller to communicate with a PMBus part it is important that the controller be able to write a byte of data without generating a stop. This will allow the controller to properly form the repeated start of the PMBus read command by concatenating a start command byte write with an I2C read. PMBus PMBus is an industry standard that defines a means of communication with power conversion devices. It is comprised of an industry standard SMBus serial interface and the PMBus command language. 2978fc 19 LTC2978 OPERATION 1 S 1 1 SLAVE ADDRESS Wr A COMMAND CODE A x x 7 1 1 8 P S Sr Rd Wr x START CONDITION REPEATED START CONDITION READ (BIT VALUE OF 1) WRITE (BIT VALUE OF 0) SHOWN UNDER A FIELD INDICATES THAT THE FIELD IS REQUIRED TO HAVE THE VALUE OF x A ACKNOWLEDGE (THIS BIT POSITION MAY BE 0 FOR AN ACK OR 1 FOR A NACK) P STOP CONDITION PEC PACKET ERROR CODE MASTER TO SLAVE SLAVE TO MASTER ... CONTINUATION OF PROTOCOL 2978 F01a Figure 1a. PMBus Packet Protocol Diagram Element Key 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 1 DATA BYTE A P 2978 F01b Figure 1b. Write Byte Protocol 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 8 1 1 DATA BYTE LOW A DATA BYTE HIGH A P 2978 F02 Figure 2. Write Word Protocol 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 8 1 1 DATA BYTE A PEC A P 2978 F03 Figure 3. Write Byte Protocol with PEC 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 8 1 8 1 1 DATA BYTE LOW A DATA BYTE HIGH A PEC A P 2978 F04 Figure 4. Write Word Protocol with PEC 1 S 7 1 1 8 1 1 SLAVE ADDRESS Wr A COMMAND CODE A P 2978 F05 Figure 5. Send Byte Protocol 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 PEC A 1 P 2978 F06 Figure 6. Send Byte Protocol with PEC 2978fc 20 LTC2978 OPERATION 1 S 1 1 SLAVE ADDRESS Wr A COMMAND CODE A 7 1 1 8 S 7 1 1 SLAVE ADDRESS Rd A 8 1 DATA BYTE LOW A 1 1 DATA BYTE HIGH A 8 P 1 2978 F07 Figure 7. Read Word Protocol 1 S 7 1 1 8 1 1 SLAVE ADDRESS Wr A COMMAND CODE A S 7 1 1 SLAVE ADDRESS Rd A 8 1 DATA BYTE LOW A 8 1 DATA BYTE HIGH A 8 1 1 PEC A P 1 2978 F08 Figure 8. Read Word Protocol with PEC 1 S 1 1 SLAVE ADDRESS Wr A COMMAND CODE A 7 1 1 8 S 7 1 1 SLAVE ADDRESS Rd A 8 1 1 DATA BYTE A P 1 2978 F09 Figure 9. Read Byte Protocol 1 S 7 1 8 1 1 SLAVE ADDRESS Wr A COMMAND CODE A 1 S 7 1 1 SLAVE ADDRESS Rd A 8 1 DATA BYTE A PEC 1 1 A P 1 2978 F10 Figure 10. Read Byte Protocol with PEC 1 S 7 1 8 1 1 7 1 1 1 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A 8 1 8 1 DATA BYTE 1 A DATA BYTE 2 A 8 1 BYTE COUNT = N A ... 2978 F11 ... ... 8 1 1 DATA BYTE N A P 1 Figure 11. Block Read 1 S 7 1 8 1 1 7 1 1 1 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A 8 1 8 1 DATA BYTE 1 A DATA BYTE 2 A ... ... 8 1 BYTE COUNT = N A ... 2978 F12 8 1 DATA BYTE N A 8 1 1 PEC A P 1 Figure 12. Block Read with PEC 2978fc 21 LTC2978 OPERATION Device Address The I2C/SMBus address of the LTC2978 equals the base address + N where N is a number from 0 to 8. N can be configured by setting the ASEL0 and ASEL1 pins to VDD33, GND or FLOAT. See Table 1. Using one base address and the nine values of N, nine LTC2978s can be connected together to control 72 outputs. The base address is stored in the MFR_I2C_BASE_ADDRESS register. The base address can be written to any value, but generally should not be changed unless the desired range of addresses overlap existing addresses. Watch that the address range does not overlap with other I2C/SMBus device or global addresses, including I2C/SMBus multiplexers and bus buffers. This will bring you great happiness. The LTC2978 always responds to its global address and the SMBus Alert Response address regardless of the state of its ASEL pins and the MFR_I2C_BASE_ADDRESS register. Table 1. LTC2978 Device Address Look-Up Table ADDRESS DESCRIPTION HEX DEVICE ADDRESS BINARY DEVICE ADDRESS BITS ADDRESS PINS 7-Bit 8-Bit 6 5 4 3 2 1 0 R/W ASEL1 ASEL0 Alert Response 0C 19 0 0 0 1 1 0 0 1 X X Global 5B B6 1 0 1 1 0 1 1 0 X X N=0 5C* B8 1 0 1 1 1 0 0 0 L L N=1 5D BA 1 0 1 1 1 0 1 0 L NC N=2 5E BC 1 0 1 1 1 1 0 0 L H N=3 5F BE 1 0 1 1 1 1 1 0 NC L N=4 60 C0 1 1 0 0 0 0 0 0 NC NC N=5 61 C2 1 1 0 0 0 0 1 0 NC H N=6 62 C4 1 1 0 0 0 1 0 0 H L N=7 63 C6 1 1 0 0 0 1 1 0 H NC N=8 64 C8 1 1 0 0 1 0 0 0 H H H = Tie to VDD33, NC = No Connect = Open or Float, L = Tie to GND, X = Don’t Care *MFR_I2C_BASE_ADDRESS = 7bit 5C (Factory Default) 2978fc 22 LTC2978 OPERATION Processing Commands The LTC2978 uses a dedicated processing block to ensure quick response to all of its commands. There are a few exceptions where the part will NACK a subsequent command because it is still processing the previous command. These are summarized in the following tables. EEPROM Related Commands COMMAND STORE_USER_ALL TYPICAL DELAY* Mass_write COMMENT See Electrical Characterization table. The LTC2978 will not accept any commands while it is transferring register contents to the EEPROM. The command byte will be NACKed. RESTORE_USER_ALL 30ms The LTC2978 will not accept any commands while it is transferring EEPROM data to command registers. The command byte will be NACKed. MFR_DATA_LOG_CLEAR 175ms The LTC2978 will not accept any commands while it is initializing the fault log EEPROM space. The command byte will be NACKed. MFR_DATA_LOG_STORE 20ms The LTC2978 will not accept any commands while it is transferring the fault log RAM buffer to EEPROM space. The command byte will be NACKed. Internal Fault log 10ms An internal fault log event is a one time event that uploads the contents of the fault log to EEPROM in response to a fault. Internal fault logging may be disabled. Commands received during this EEPROM write are NACKed. MFR_DATA_LOG_ RESTORE 2ms The LTC2978 will not accept any commands while it is transferring EEPROM data to the fault log RAM buffer. The command byte will be NACKed. *The typical delay is measured from the command’s stop to the next command’s start. COMMAND MFR_CONFIG_LTC2978 TYPICAL DELAY* COMMENT <50µs The LTC2978 will not accept any commands while it is completing this command. The command byte will be NACKed. *The delay is measured from the command’s stop to the next command’s start. Other PMBus Timing Notes COMMAND CLEAR_FAULTS COMMENT The LTC2978 will accept commands while it is completing this command but the affected status flags will not be cleared for up to 500µs. 2978fc 23 LTC2978 PMBus COMMAND SUMMARY Summary Table COMMAND NAME CMD CODE DESCRIPTION TYPE DATA PAGED FORMAT UNITS NVM DEFAULT VALUE FLOAT HEX REF PAGE 0x00 29 PAGE 0x00 Channel or page currently selected for any R/W Byte command that supports paging. N Reg OPERATION 0x01 Operating mode control. On/Off, Margin High and Margin Low. R/W Byte Y Reg Y 0x00 30 ON_OFF_CONFIG 0x02 CONTROL pin & PMBus bus on/off command setting. R/W Byte Y Reg Y 0x12 31 CLEAR_FAULTS 0x03 Clear any fault bits that have been set. Send Byte Y NA 31 WRITE_PROTECT 0x10 Level of protection provided by the device against accidental changes. R/W Byte N Y 0x00 32 STORE_USER_ALL 0x15 Store entire operating memory to EEPROM. Send Byte N NA 32 RESTORE_USER_ALL 0x16 Restore entire operating memory from EEPROM. Send Byte N NA 32 CAPABILITY 0x19 Summary of PMBus optional communication protocols supported by this device. R Byte N Reg 0xE0 32 VOUT_MODE 0x20 Output voltage data format and mantissa exponent. (2–13) R Byte Y Reg 0x13 33 VOUT_COMMAND 0x21 Servo Target. Nominal DC/DC converter output voltage setpoint. R/W Word Y L16 V Y 1.0 0x2000 33 VOUT_MAX 0x24 Upper limit on the output voltage the unit can command regardless of any other commands. R/W Word Y L16 V Y 4.0 0x8000 33 VOUT_MARGIN_HIGH 0x25 Margin high DC/DC converter output voltage setting. R/W Word Y L16 V Y 1.05 0x219A 33 VOUT_MARGIN_LOW 0x26 Margin low DC/DC converter output voltage setting. R/W Word Y L16 V Y 0.95 0x1E66 33 VIN_ON 0x35 Input voltage above which power conversion can be enabled. R/W Word N L11 V Y 10.0 0xD280 33 VIN_OFF 0x36 Input voltage below which power conversion is disabled. All VOUT_EN pins go off immediately. R/W Word N L11 V Y 9.0 0xD240 33 VOUT_OV_FAULT_LIMIT 0x40 Output overvoltage fault limit R/W Word Y L16 V Y 1.1 0x2333 33 VOUT_OV_FAULT_ RESPONSE 0x41 Action to be taken by the device when an output overvoltage fault is detected. R/W Byte Y Reg Y 0x80 35 VOUT_OV_WARN_LIMIT 0x42 Output overvoltage warning limit . R/W Word Y L16 V Y 1.075 0x2266 33 VOUT_UV_WARN_LIMIT 0x43 Output undervoltage warning limit R/W Word Y L16 V Y 0.925 0x1D9A 33 VOUT_UV_FAULT_LIMIT 0x44 Output undervoltage fault limit. Limit used to determine if TON_MAX_FAULT has been met and the unit is on. R/W Word Y L16 V Y 0.9 0x1CCD 33 VOUT_UV_FAULT_ RESPONSE 0x45 Action to be taken by the device when an output undervoltage fault is detected. R/W Byte Y Reg Y 0x7F 35 OT_FAULT_LIMIT 0x4F Overtemperature fault limit setting. R/W Word N L11 Y 85.0 0xEAA8 34 Reg °C 2978fc 24 LTC2978 PMBus COMMAND SUMMARY Summary Table COMMAND NAME CMD CODE DESCRIPTION TYPE DATA PAGED FORMAT UNITS NVM DEFAULT VALUE FLOAT HEX REF PAGE Y 0xB8 36 OT_FAULT_RESPONSE 0x50 Action to be taken by the device when an overtemperature fault is detected. R/W Byte N Reg OT_WARN_LIMIT 0x51 Overtemperature warning limit setting. R/W Word N L11 °C Y 75.0 0xEA58 34 UT_WARN_LIMIT 0x52 Undertemperature warning limit. R/W Word N L11 °C Y 0 0x8000 34 UT_FAULT_LIMIT 0x53 Undertemperature fault limit. R/W Word N L11 °C Y –5.0 0xCD80 34 UT_FAULT_RESPONSE 0x54 Action to be taken by the device when an undertemperature fault is detected. R/W Byte N Reg Y 0xB8 36 VIN_OV_FAULT_LIMIT 0x55 Input overvoltage fault limit measured at VIN_SNS pin R/W Word N L11 Y 15.0 0xD3C0 33 VIN_OV_FAULT_RESPONSE 0x56 Action to be taken by the device when an input overvoltage fault is detected. R/W Byte N Reg Y 0x80 36 VIN_OV_WARN_LIMIT 0x57 Input overvoltage warning limit measured R/W Word at VIN_SNS pin N L11 V Y 14.0 0xD380 33 VIN_UV_WARN_LIMIT 0x58 Input undervoltage warning limit measured at VIN_SNS pin. R/W Word N L11 V Y 0 0x8000 33 VIN_UV_FAULT_LIMIT 0x59 Input undervoltage fault limit measured at R/W Word VIN_SNS pin N L11 V Y 0 0x8000 33 R/W Byte N Reg Y 0x00 36 POWER_GOOD_ON 0x5E Output voltage at or above which a power R/W Word good should be asserted. Y L16 V Y 0.96 0x1EB8 33 POWER_GOOD_OFF 0x5F Output voltage at or below which a power R/W Word good should be deasserted. Y L16 V Y 0.94 0x1E14 33 TON_DELAY 0x60 Time from CONTROL pin and/or OPERATION command = ON to VOUT_EN pin = ON. R/W Word Y L11 ms Y 1.0 0xBA00 34 TON_RISE 0x61 Time from when the output starts to rise R/W Word until the LTC2978 optionally soft-connects its DAC and begins to servo the output voltage to the desired value. Y L11 ms Y 10.0 0xD280 34 TON_MAX_FAULT_LIMIT 0x62 Maximum time from VOUT_EN = ON assertion that an UV condition will be tolerated before a TON_MAX_FAULT condition results. R/W Word Y L11 ms Y 15.0 0xD3C0 34 TON_MAX_FAULT_ RESPONSE 0x63 Action to be taken by the device when a TON_MAX_FAULT event is detected. R/W Byte Y Reg Y 0xB8 36 TOFF_DELAY 0x64 Time from CONTROL pin and/or OPERATION command = OFF to VOUT_EN pin = OFF. R/W Word Y L11 Y 1.0 0xBA00 34 STATUS_BYTE 0x78 One byte summary of the unit's fault condition. R Byte Y Reg NA 37 STATUS_WORD 0x79 Two byte summary of the unit's fault condition. R Word Y Reg NA 38 STATUS_VOUT 0x7A Output voltage fault and warning status. R Byte Y Reg NA 38 VIN_UV_FAULT_RESPONSE 0x5A Action to be taken by the device when an input undervoltage fault is detected. V ms 2978fc 25 LTC2978 PMBus COMMAND SUMMARY Summary Table COMMAND NAME CMD CODE DESCRIPTION TYPE DATA PAGED FORMAT UNITS NVM DEFAULT VALUE FLOAT HEX REF PAGE STATUS_INPUT 0x7C Input voltage fault and warning status measured at VIN_SNS pin. R Byte N Reg NA 39 STATUS_TEMPERATURE 0x7D Temperature fault and warning status for READ_TEMPERATURE_1. R Byte N Reg NA 39 STATUS_CML 0x7E Communication and memory fault and warning status. R Byte N Reg NA 40 STATUS_MFR_SPECIFIC 0x80 Manufacturer specific fault and state information. R Byte Y Reg NA 40 READ_VIN 0x88 Input voltage measured at VIN_SNS pin.. R Word N L11 V NA 41 READ_VOUT 0x8B DC/DC converter output voltage. R Word Y L16 V NA 41 READ_TEMPERATURE_1 0x8D Internal junction temperature. R Word N L11 °C PMBUS_REVISION 0x98 PMBus revision supported by this device. Current revision is 1.1. R Byte N Reg MFR_CONFIG_LTC2978 0xD0 Configuration bits that are channel specific. R/W Word Y Reg MFR_CONFIG_ALL_ LTC2978 0xD1 Configuration bits that are common to all pages. R/W Byte N MFR_FAULTBz0_ PROPAGATE 0xD2 Configuration that determines if a channel’s faulted off state is propagated to the FAULTB00 and FAULTB10 pins. R/W Byte MFR_FAULTBz1_ PROPAGATE 0xD3 Manufacturer configuration that Configuration that determines if a channel’s faulted off state is propagated to the FAULTB01 and FAULTB11 pins. MFR_PWRGD_EN NA 41 0x11 41 Y 0x0080 42 Reg Y 0x7B 43 Y Reg Y 0x00 44 R/W Byte Y Reg Y 0x00 44 0xD4 Configuration for mapping PWRGD and WDI/RESETB status to the PWRGD pin. R/W Word N Reg Y 0x0000 45 MFR_FAULTB00_ RESPONSE 0xD5 Action to be taken by the device when the FAULTB00 pin is asserted low. R/W Byte N Reg Y 0x00 46 MFR_FAULTB01_ RESPONSE 0xD6 Action to be taken by the device when the FAULTB01 pin is asserted low. R/W Byte N Reg Y 0x00 46 MFR_FAULTB10_ RESPONSE 0xD7 Action to be taken by the device when the FAULTB10 pin is asserted low. R/W Byte N Reg Y 0x00 46 MFR_FAULTB11_ RESPONSE 0xD8 Action to be taken by the device when the FAULTB11 pin is asserted low. R/W Byte N Reg Y 0x00 46 MFR_VINEN_OV_FAULT_ RESPONSE 0xD9 Action to be taken by the VIN_EN pin in response to a VOUT_OV_FAULT R/W Byte N Reg Y 0x00 47 MFR_VINEN_UV_FAULT_ RESPONSE 0xDA Action to be taken by the VIN_EN pin in response to a VOUT_UV_FAULT R/W Byte N Reg Y 0x00 48 MFR_RETRY_DELAY 0xDB Retry interval during FAULT retry mode. R/W Word N L11 ms Y 200.0 0xF320 48 MFR_RESTART_DELAY 0xDC Delay from actual CONTROL active edge to virtual CONTROL active edge. R/W Word N L11 ms Y 400.0 0xFB20 49 MFR_VOUT_PEAK 0xDD Maximum measured value of READ_ VOUT. R Word Y L16 V NA 49 MFR_VIN_PEAK 0xDE Maximum measured value of READ_VIN. R Word N L11 V NA 49 2978fc 26 LTC2978 PMBus COMMAND SUMMARY Summary Table COMMAND NAME CMD CODE DESCRIPTION MFR_TEMPERATURE_ PEAK 0xDF Maximum measured value of READ_ TEMPERATURE_1. MFR_DAC MFR_POWERGOOD_ ASSERTION_DELAY TYPE DATA PAGED FORMAT UNITS DEFAULT VALUE FLOAT HEX REF PAGE NA 49 Y 0x0000 50 NVM R Word N L11 0xE0 Manufacturer register that contains the code of the 10-bit DAC. R/W Word Y U16 0xE1 Power good output assertion delay. R/W Word N L11 ms Y 100.0 0xEB20 50 MFR_WATCHDOG_T_FIRST 0xE2 First watchdog timer interval. R/W Word N L11 ms Y 0 0x8000 50 MFR_WATCHDOG_T 0xE3 Watchdog timer interval. R/W Word N L11 ms Y 0 0x8000 50 MFR_PAGE_FF_MASK 0xE4 Configuration defining which channels respond to global page commands (PAGE=0xFF). R/W Byte N Reg Y 0xFF 51 MFR_PADS 0xE5 Current state of selected digital I/O pads. R Word N Reg N/A 52 R/W Byte N U16 Y 0x5C 52 0x0121 52 Base value of the I2C/SMBus address °C MFR_I2C_BASE_ADDRESS 0xE6 MFR_SPECIAL_ID 0xE7 Manufacturer code for identifying the LTC2978 R Word N Reg Y MFR_SPECIAL_LOT 0xE8 Customer dependent codes that identify the factory programmed user configuration stored in EEPROM. Contact factory for default value. R Byte Y Reg Y MFR_VOUT_DISCHARGE_ THRESHOLD R/W Word 0xE9 Coefficient used to multiply VOUT_ COMMAND in order to determine VOUT off threshold voltage. Y L11 Y MFR_FAULT_LOG_STORE 0xEA Command a transfer of the fault log from RAM to EEPROM. This causes the part to behave as if a channel has faulted off. Send Byte MFR_FAULT_LOG_ RESTORE 0xEB Command a transfer of the fault log previously stored in EEPROM back to RAM. MFR_FAULT_LOG_CLEAR 0xEC Initialize the EEPROM block reserved for fault logging and clear any previous fault logging locks. byte. 53 2.0 0xC200 53 N NA 55 Send Byte N NA 55 Send Byte N NA 55 MFR_FAULT_LOG_STATUS 0xED Fault logging status. R Byte N Reg Y NA 55 MFR_FAULT_LOG 0xEE Fault log data bytes. This sequentially retrieved data is used to assemble a complete fault log. 256 Bytes. R Block N Reg Y NA 56 MFR_COMMON 0xEF Manufacturer status bits that are common across multiple LTC chips. R Byte N Reg NA 53 MFR_SPARE_0 0xF7 Scratchpad register R/W Word N Reg Y 0x0000 53 MFR_SPARE_2 0xF9 Paged scratchpad register R/W Word Y Reg Y 0x0000 53 MFR_VOUT_MIN 0xFB Minimum measured value of READ_VOUT. R Word Y L16 NA 54 V MFR_VIN_MIN 0xFC Minimum measured value of READ_VIN. R Word N L11 V NA 54 MFR_TEMPERATURE_MIN 0xFD Minimum measured value of READ_ TEMPERATURE_1. R Word N L11 °C NA 54 2978fc 27 LTC2978 PMBus COMMAND SUMMARY Data Formats L11 Linear_5s_11s L16 Linear_16u Reg Register U16 Integer Word CF Custom Format PMBus data field b[15:0] Value = Y • 2N where N = b[15:11] is a 5-bit two’s complement integer and Y = b[10:0] is an 11-bit two’s complement integer Example: READ_VIN = 10V For b[15:0] = 0xD280 = 1101_0010_1000_0000b Value = 640 • 2–6 = 10 See PMBus Spec Part II: Paragraph 7.1 PMBus data field b[15:0] Value = Y • 2N where Y = b[15:0] is an unsigned integer and N = Vout_mode_parameter is a 5-bit two’s complement exponent that is hardwired to –13 decimal. Example: VOUT_COMMAND = 4.75V For b[15:0] = 0x9800 = 1001_1000_0000_0000b Value = 38912 • 2–13 = 4.75 See PMBus Spec Part II: Paragraph 8.3.1 PMBus data field b[15:0] or b[7:0]. Bit field meaning is defined in detailed PMBus Command Register Description. PMBus data field b[15:0] Value = Y where Y = b[15:0] is a 16-bit unsigned integer Example: For b[15:0] = 0x9807 = 1001_1000_0000_0111b Value = 38919 PMBus data field b[15:0] Value is defined in detailed PMBus Command Register Description. This is often an unsigned or two’s complement integer scaled by an MFR specific constant. 2978fc 28 LTC2978 PMBus COMMAND DESCRIPTION OPERATION, MODE AND EEPROM COMMANDS PAGE The LTC2978 has eight pages that correspond to the eight DC/DC converter channels that can be managed. Each DC/DC converter channel can be uniquely programmed by first setting the appropriate page. The PAGE command provides the ability to configure, control and monitor multiple outputs on one unit. Setting PAGE = 0xFF allows a simultaneous write to all pages for PMBus commands that support global page programming. The only commands that support PAGE = 0xFF are OPERATION and ON_OFF_CONFIG. See MFR_PAGE_FF_MASK for additional options. Reading any paged PMBus register with PAGE = 0xFF returns unpredictable data and will trigger a CML fault. PAGE Data Contents BIT(S) SYMBOL PURPOSE b[7:0] Page Page operation. 0x00: All PMBus commands address channel/page 0. 0x01: All PMBus commands address channel/page 1. • • • 0x07: All PMBus commands address channel/page 7. 0xXX: All nonspecified values reserved. 0xFF: A single PMBus write/send to commands that support this mode will simultaneously address all channels/pages with MFR_PAGE_FF_MASK enabled. 2978fc 29 LTC2978 PMBus COMMAND DESCRIPTION OPERATION The OPERATION command is used to turn the unit on and off in conjunction with the CONTROLn pin and ON_OFF_CONFIG. This command register responds to the global page command (PAGE=0xFF). The contents and functions of the data byte are shown in the following tables. OPERATION Data Contents (On_off_config_use_pmbus=1) SYMBOL Action BITS Turn off immediately Operation_control[1:0] Operation_margin[1:0] Operation_fault[1:0] Reserved (read only) b[7:6] b[5:4] b[3:2] b[1:0] 00 XX XX 00 Turn on 10 00 XX 00 Margin Low (Ignore Faults and Warnings) 10 01 01 00 Margin Low 10 01 10 00 Margin High (Ignore Faults and Warnings 10 10 01 00 10 10 10 00 01 00 XX 00 Sequence off and Margin Low (Ignore Faults and Warnings) 01 01 01 00 Sequence off and Margin Low 01 01 10 00 Sequence off and Margin High (Ignore Faults and Warnings) 01 10 01 00 Sequence off and Margin High 01 10 10 00 FUNCTION Margin High Sequence off and margin to nominal Reserved All remaining combinations OPERATION Data Contents (On_off_config_use_pmbus=0) SYMBOL Action BITS FUNCTION Operation_control[1:0] Operation_margin[1:0] Operation_fault[1:0] Reserved (read only) b[7:6] b[5:4] b[3:2] b[1:0] Output at Nominal 00, 01 or 10 00 XX 00 Margin Low (Ignore faults and Warnings) 00, 01 or 10 01 01 00 Margin Low 00, 01 or 10 01 10 00 Margin High (Ignore Faults and Warnings 00, 01 or 10 10 01 00 Margin High 00, 01 or 10 10 10 00 Reserved All remaining combinations 2978fc 30 LTC2978 PMBus COMMAND DESCRIPTION ON_OFF_CONFIG The ON_OFF_CONFIG command configures the combination of CONTROLn pin input and PMBus bus commands needed to turn the LTC2978 on/off, including the power-on behavior, as shown in the following table. This command register responds to the global page command (PAGE=0xFF). After the part has initialized, an additional comparator monitors VIN_SNS. The VIN_ON threshold must be exceeded before the output power sequencing can begin. After VIN is initially applied, the part will typically require 135ms to initialize and begin the TON_DELAY timer. The readback of voltages and currents may require an additional 160ms. ON_OFF_CONFIG Data Contents BITS(S) SYMBOL OPERATION b[7:5] Reserved Don’t care. Always returns 0. b[4] On_off_config_controlled_on Controls default autonomous power-up operation. 0: Unit powers up regardless of the CONTROLn pin or OPERATION value. Unit always powers up with sequencing. To turn unit on without sequencing, set TON_DELAY = 0. 1: Unit does not power up unless commanded by the CONTROLn pin and/or the OPERATION command on the serial bus. If On_off_config[3:2] = 00, the unit never powers up. b[3] On_off_config_use_pmbus Controls how the unit responds to commands received via the serial bus. 0: Unit ignores the Operation_control[1:0] bits. 1: Unit responds to Operation_control[1:0]. Depending on On_off_config_use_control, the unit may also require the CONTROLn pin to be asserted for the unit to start. b[2] On_off_config_use_control Controls how unit responds to the CONTROLn pin. 0: Unit ignores the CONTROLn pin. 1: Unit requires the CONTROLn pin to be asserted to start the unit. Depending on On_off_config_use_ pmbus the OPERATION command may also be required to instruct the device to start. b[1] Reserved Not supported. Always returns 1. b[0] On_off_config_control_fast_off CONTROLn pin turn off action when commanding the unit to turn off 0: Use the programmed TOFF_DELAY. 1: Turn off the output and stop transferring energy as quickly as possible, i.e. pull VOUTENn low immediately. CLEAR_FAULTS The CLEAR_FAULTS command is used to clear any status faults that have been set. This command clears all bits in all unpaged status registers, and the paged status registers selected by the current PAGE setting. At the same time, the device negates (clears, releases) its contribution to ALERTB. The CLEAR_FAULTS command does not cause a unit that has latched off for a fault condition to restart. See Clearing Latched Faults for more information. If the fault condition is present after the fault status is cleared, the fault status bit shall be set again and the host notified by the usual means. Note: this command register does not respond to the global page command (PAGE=0xFF). 2978fc 31 LTC2978 PMBus COMMAND DESCRIPTION WRITE_PROTECT The WRITE_PROTECT command provides protection against accidental programming of the LTC2978 command registers. All supported commands may have their parameters read, regardless of the WRITE_PROTECT setting. There are two levels of write protection: • Level 1: Nothing can be changed except the level of write protection itself. Values can be read from all pages. This setting can be stored to EEPROM. • Level 2: Nothing can be changed except for the level of protection, channel on/off state and clearing of faults. Values can be read from all pages. This setting can be stored to EEPROM. WRITE_PROTECT Data Contents BITS(S) SYMBOL b[7:0] Write_protect[7:0] OPERATION Level 1: 1000_0000b: Disable all writes except to the WRITE_PROTECT, PAGE, and STORE_USER_ALL commands. Level 2: 0100_0000b: Disable all writes except to the WRITE_PROTECT, PAGE, STORE_USER_ALL, OPERATION, MFR_ PAGE_FF_MASK, and CLEAR_FAULTS. 0000_0000b: Enable writes to all commands. xxxx_xxxxb: All other values reserved. STORE_USER_ALL and RESTORE_USER_ALL STORE_USER_ALL, RESTORE_USER_ALL commands provide access to User EEPROM space. Once a command is stored in User EEPROM, it will be restored with an explicit restore command or when the part emerges from poweron reset after power is applied. While either of these commands is being processed, the device will NACK I2C writes. STORE_USER_ALL. Issuing this command will store all operating memory commands with a corresponding EEPROM memory location. It is recommended that this command not be executed while a unit is enabled since all monitoring is suspended while the operating memory is transferred to EEPROM. RESTORE_USER_ALL. Issuing this command will restore all commands from EEPROM Memory. It is recommended that this command not be executed while a unit is enabled since all monitoring is suspended while the EEPROM is transferred to operating memory, and intermediate values from EEPROM may not be compatible with the values initially stored in operating memory. CAPABILITY The CAPABILITY command provides a way for a host system to determine some key capabilities of the LTC2978. This one byte command is read only. CAPABILITY Data Contents BITS(S) SYMBOL OPERATION b[7] Capability_pec Hard coded to 1 indicating Packet Error Checking is supported. Reading the Mfr_config_all_pec_en bit will indicate whether PEC is currently required. b[6] Capability_scl_max Hard coded to 1 indicating the maximum supported bus speed is 400kHz. b[5] Capability_smb_alert Hard coded to 1 indicating this device does have an ALERTB pin and does support the SMBus Alert Response Protocol. Reserved Always returns 0. b[4:0] 2978fc 32 LTC2978 PMBus COMMAND DESCRIPTION VOUT_MODE This command is read only and specifies the mode and exponent for all commands with a L16 data format. See Data Formats table on page 28. VOUT_MODE Data Contents BIT(S) SYMBOL OPERATION b[7:5] Vout_mode_type Reports linear mode. Hard wired to 000b. b[4:0] Vout_mode_parameter Linear mode exponent. 5-bit two’s complement integer. Hardwired to 0x13 (–13 decimal). OUTPUT VOLTAGE RELATED COMMANDS VOUT_COMMAND, VOUT_MAX, VOUT_MARGIN_HIGH, VOUT_MARGIN_LOW, VOUT_OV_FAULT_LIMIT, VOUT_OV_ WARN_LIMIT, VOUT_UV_WARN_LIMIT, VOUT_UV_FAULT_LIMIT, POWER_GOOD_ON and POWER_GOOD_OFF These commands all use the same format and provide various servo, margining, and supervising limits for a channel’s output voltage. When odd channels are configured to measure current, the OV_WARN_LIMIT, UV_WARN_LIMIT, OV_FAULT_LIMIT and UV_FAULT_LIMIT commands are not supported. Data Contents BIT(S) SYMBOL b[15:0] Vout_command[15:0], Vout_max[15:0], OPERATION These commands relate to output voltage. The data uses the L16 format. Units: V Vout_margin_high[15:0], Vout_margin_low[15:0], Vout_ov_fault_limit[15:0], Vout_ov_warn_limit[15:0], Vout_uv_warn_limit[15:0], Vout_uv_fault_limit[15:0], Power_good_on[15:0], Power_good_off[15:0] INPUT VOLTAGE RELATED COMMANDS VIN_ON, VIN_OFF, VIN_OV_FAULT_LIMIT, VIN_OV_WARN_LIMIT, VIN_UV_WARN_LIMIT and VIN_UV_FAULT_ LIMIT These commands use the same format and provide voltage supervising limits for VIN. Data Contents BIT(S) SYMBOL OPERATION b[15:0] Vin_on[15:0], These commands relate to input voltage. The data uses the L11 format. Vin_off[15:0], Units: V. Vin_ov_fault_limit[15:0], Vin_ov_warn_limit[15:0], Vin_uv_warn_limit[15:0], Vin_uv_fault_limit[15:0] 2978fc 33 LTC2978 PMBus COMMAND DESCRIPTION TEMPERATURE RELATED COMMANDS OT_FAULT_LIMIT, OT_WARN_LIMIT, UT_WARN_LIMIT and UT_FAULT_LIMIT These commands provide supervising limits for temperature. Data Contents BIT(S) SYMBOL OPERATION b[15:0] Ot_fault_limit[15:0], The data uses the L11 format. Ot_warn_limit[15:0], Units: °C. Ut_warn_limit[15:0], Ut_fault_limit[15:0] TIMER LIMITS TON_DELAY, TON_RISE, TON_MAX_FAULT_LIMIT and TOFF_DELAY These commands share the same format and provide sequencing and timer fault and warning delays in ms. TON_DELAY is the amount time in ms that elapses after the channel has been allowed on (usually due to CONTROLn pin or OPERATION command) until the channel enables the power supply. This delay is counted using SHARE_CLK only. TON_RISE is the amount of time in ms that elapses after the power supply has been enabled until the LTC2978’s DAC soft connects and servos the output voltage to the desired level if Mfr_dac_mode = 00b. This delay is counted using SHARE_CLK only. TON_MAX_FAULT_LIMIT is the maximum amount of time that the power supply being controlled by the LTC2978 can attempt to power up the output without reaching the VOUT_UV_FAULT_LIMIT. If the output reaches VOUT_UV_FAULT_ LIMIT prior to TON_MAX_FAULT_LIMIT, the LTC2978 unmasks the VOUT_UV_FAULT_LIMIT threshold. If it does not, then a TON_MAX_FAULT is declared. (Note that a value of zero means there is no limit to how long the power supply can attempt to bring up its output voltage.) This delay is counted using SHARE_CLK only. TOFF_DELAY is the amount of time that elapses after the CONTROLn pin and/or OPERATION command is deasserted until the channel is disabled (soft-off). This delay is counted using SHARE_CLK if available, otherwise the internal oscillator is used. Data Contents BIT(S) SYMBOL OPERATION b[15:0] Ton_delay[15:0], The data uses the L11 format. Ton_rise[15:0], The internal timers operate on a 10µs internal clock. The SHARE_CLK pin may be used to synchronize the Ton_max_fault_limit[15:0], 10µs timer. Delays are rounded to the nearest 10µs Toff_delay[15:0], Units: ms. Max value: 655ms 2978fc 34 LTC2978 PMBus COMMAND DESCRIPTION FAULT RESPONSE FOR VOLTAGES MEASURED BY THE HIGH SPEED SUPERVISOR VOUT_OV_FAULT_RESPONSE and VOUT_UV_FAULT_RESPONSE The fault response documented here is for voltages that are measured by the high speed supervisor. These voltages are measured over a short period of time and may require a deglitch period. Note that in addition to the response described by these commands, the LTC2978 will also: • Set the appropriate bit(s) in the STATUS_BYTE • Set the appropriate bit(s) in the STATUS_WORD • Set the appropriate bit in the corresponding STATUS_VOUT register, and • Notify the host by pulling the ALERTB pin low. Note: Odd numbered channels configured for high resolution ADC measurements (for current measurement) will not respond to OV/UV faults or warnings. Data Contents BIT(S) SYMBOL OPERATION b[7:6] Vout_ov_fault_response_action, Response action: Vout_uv_fault_response_action 00b: The unit continues operation without interruption. 01b: The unit continues operating for the delay time specified by bits[2:0] in increments of ts_vs. (See Electrical Characteristics Table, Voltage Supervisor Characteristics section). If the fault is still present at the end of the delay time, the unit shuts down and responds as programmed in the retry setting (bits [5:3]). 1Xb: The device shuts down and responds according to the retry setting in bits [5:3]. b[5:3] Vout_ov_fault_response_retry, Vout_uv_fault_response_retry Response retry behavior: 000b: A zero value for the retry setting means that the unit does not attempt to restart. The output remains disabled until the fault is cleared. 001b-111b: The PMBus device attempts to restart continuously, without limitation, at intervals of Mfr_retry_ delay, until it is commanded OFF (by the CONTROL pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down. b[2:0] Vout_ov_fault_response_delay, Vout_uv_fault_response_delay This sample count determines the amount of time a unit is to ignore a fault after it is first detected. Use this delay to deglitch fast faults. 000b: The unit turns off immediately. 001b-111b: The unit turns off after b[2:0] samples at the sampling period of ts_vs (12.2µs typical). 2978fc 35 LTC2978 PMBus COMMAND DESCRIPTION FAULT RESPONSE FOR VALUES MEASURED BY THE ADC OT_FAULT_RESPONSE, UT_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE and VIN_UV_FAULT_RESPONSE The fault response documented here is for values that are measured by the ADC. These values are measured over a longer period of time and are not deglitched. Note that in addition to the response described by these commands, the LTC2978 will also: • Set the appropriate bit(s) in the STATUS_BYTE • Set the appropriate bit(s) in the STATUS_WORD • Set the appropriate bit in the corresponding STATUS_VIN or STATUS_TEMPERATURE register, and • Notify the host by pulling the ALERTB pin low. Data Contents BIT(S) SYMBOL OPERATION b[7:6] Ot_fault_response_action, Response action: Ut_fault_response_action, 00b: The unit continues operation without interruption. Vin_ov_fault_response_action, 01b to 11b: The device shuts down and responds according to the retry setting in bits [5:3]. Vin_uv_fault_response_action b[5:3] Ot_fault_response_retry, Ut_fault_response_retry, Vin_ov_fault_response_retry, Vin_uv_fault_response_retry b[2:0] Ot_fault_response_delay, Response retry behavior: 000b: A zero value for the retry setting means that the unit does not attempt to restart. The output remains disabled until the fault is cleared. 001b-111b: The PMBus device attempts to restart continuously, without limitation, using Mfr_retry_delay, until it is commanded OFF (by the CONTROLn pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down. Hard coded to 000b. The unit turns off immediately. Ut_fault_response_delay, Vin_ov_fault_response_delay, Vin_uv_fault_response_delay TIMED FAULT RESPONSE TON_MAX_FAULT_RESPONSE This command defines the LTC2978 response to a TON_MAX_FAULT. It may be used to protect against a short-circuited output at start-up. After start-up use VOUT_UV_FAULT_RESPONSE to protect against a short-circuited output. The device also: • Sets the HIGH_BYTE bit in the STATUS_BYTE, • Sets the VOUT bit in the STATUS_WORD, • Sets the TON_MAX_FAULT bit in the STATUS_VOUT register, and • Notifies the host by asserting ALERTB. 2978fc 36 LTC2978 PMBus COMMAND DESCRIPTION TON_MAX_FAULT_RESPONSE Data Contents BIT(S) SYMBOL OPERATION b[7:6] Ton_max_fault_response_action Response action: 00b: The unit continues operation without interruption. 01b: The unit continues operating for the delay time specified which for this type of fault corresponds to an immediate shutdown. After shutting off, the device responds according to the retry settings in bits [5:3]. 1Xb: The device shuts down and responds according to the retry setting in bits [5:3]. b[5:3] Ton_max_fault_response_retry Response retry behavior: 000b: A zero value for the Retry Setting means that the unit does not attempt to restart. The output remains disabled until the fault is cleared. 001b-111b: The PMBus device attempts to restart continuously, without limitation, using Mfr_retry_delay, until it is commanded OFF (by the CONTROLn pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down. b[2:0] Ton_max_fault_response_delay Hard coded to 000b. The unit turns off immediately. Clearing Latched Faults Latched faults are reset by toggling the CONTROL pin, using the OPERATION command, or removing and reapplying the bias voltage to the VIN_SNS pin. All fault and warning conditions result in the ALERTB pin being asserted low and the corresponding bits being set in the status registers. The CLEAR_FAULTS command resets the contents of the status registers and de-asserts the ALERTB output, but it does not clear a faulted off state nor allow a channel to turn back on. STATUS COMMANDS STATUS_BYTE: The STATUS_BYTE command returns the summary of the most critical faults or warnings which have occurred, as shown in the following table. STATUS_BYTE is a subset of STATUS_WORD and duplicates the same information. STATUS_BYTE Data Contents BIT(S) SYMBOL OPERATION b[7] Status_byte_busy Same as Status_word_busy b[6] Status_byte_off Same as Status_word_off b[5] Status_byte_vout_ov Same as Status_word_vout_ov b[4] Status_byte_iout_oc Same as Status_word_iout_oc b[3] Status_byte_vin_uv Same as Status_word_vin_uv b[2] Status_byte_temp Same as Status_word_temp b[1] Status_byte_cml Same as Status_word_cml b[0] Status_byte_high_byte Same as Status_word_high_byte 2978fc 37 LTC2978 PMBus COMMAND DESCRIPTION STATUS_WORD: The STATUS_WORD command returns two bytes of information with a summary of the unit’s fault condition. Based on the information in these bytes, the host can get more information by reading detailed status register. The low byte of the STATUS_WORD is the same register as the STATUS_BYTE command. STATUS_WORD Data Contents BIT(S) SYMBOL OPERATION b[15] Status_word_vout An output voltage fault or warning has occurred. See STATUS_VOUT. b[14] Status_word_iout Not supported. Always returns 0. b[13] Status_word_input An input voltage fault or warning has occurred. See STATUS_INPUT. b[12] Status_word_mfr A manufacturer specific fault has occurred. See STATUS_MFR_SPECIFIC. b[11] Status_word_power_not_good The POWER_GOOD signal, if present is negated. Power is not good. b[10] Status_word_fans Not supported. Always returns 0. b[9] Status_word_other Not supported. Always returns 0. b[8] Status_word_unknown Not supported. Always returns 0. b[7] Status_word_busy Device busy when PMBus command received. See OPERATION: Processing Commands. b[6] Status_word_off This bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being enabled. The off bit is clear if unit is allowed to provide power to the output. b[5] Status_word_vout_ov An output overvoltage fault has occured. b[4] Status_word_iout_oc Not supported. Always returns 0. b[3] Status_word_vin_uv A VIN undervoltage fault has occurred. b[2] Status_word_temp A temperature fault or warning has occurred. See STATUS_TEMPERATURE. b[1] Status_word_cml A communication, memory or logic fault has occurred. See STATUS_CML. b[0] Status_word_high_byte A fault/warning not listed in b[7:1] has occurred. STATUS_VOUT The STATUS_VOUT command returns the summary of the output voltage faults or warnings which have occurred, as shown in the following table: STATUS_VOUT Data Contents BIT(S) SYMBOL OPERATION b[7] Status_vout_ov_fault Overvoltage fault. b[6] Status_vout_ov_warn Overvoltage warning. b[5] Status_vout_uv_warn Undervoltage warning b[4] Status_vout_uv_fault Undervoltage fault. b[3] Status_vout_max_fault VOUT_MAX fault. An attempt has been made to set the output voltage to a value higher than allowed by the VOUT_MAX command. b[2] Status_vout_ton_max_fault TON_MAX_FAULT sequencing fault. b[1] Status_vout_toff_max_warn Not supported. Always returns 0. b[0] Status_vout_tracking_error Not supported. Always returns 0. 2978fc 38 LTC2978 PMBus COMMAND DESCRIPTION STATUS_INPUT The STATUS_INPUT command returns the summary of the VIN faults or warnings which have occurred, as shown in the following table: STATUS_INPUT Data Contents BIT(S) SYMBOL OPERATION b[7] Status_input_ov_fault VIN Overvoltage fault b[6] Status_input_ov_warn VIN Overvoltage warning b[5] Status_input_uv_warn VIN Undervoltage warning b[4] Status_input_uv_fault VIN Undervoltage fault b[3] Status_input_off Unit is off for insufficient input voltage. b[2] IIN overcurrent fault Not supported. Always returns 0. b[1] IIN overcurrent warn Not supported. Always returns 0. b[0] PIN overpower warn Not supported. Always returns 0. STATUS_TEMPERATURE The STATUS_TEMPERATURE command returns the summary of the temperature faults or warnings which have occurred, as shown in the following table: STATUS_TEMPERATURE Data Contents Bit(s) Symbol Operation b[7] Status_temperature_ot_fault Overtemperature fault. b[6] Status_temperature_ot_warn Overtemperature warning. b[5] Status_temperature_ut_warn Undertemperature warning. b[4] Status_temperature_ut_fault Undertemperature fault. b[3] Reserved Reserved. Always returns 0. b[2] Reserved Reserved. Always returns 0. b[1] Reserved Reserved. Always returns 0. b[0] Reserved Reserved. Always returns 0. 2978fc 39 LTC2978 PMBus COMMAND DESCRIPTION STATUS_CML The STATUS_CML command returns the summary of the communication, memory and logic faults or warnings which have occurred, as shown in the following table: STATUS_CML Data Contents BIT(S) SYMBOL OPERATION b[7] Status_cml_cmd_fault Illegal or unsupported command fault has occurred. b[6] Status_cml_data_fault Illegal or unsupported data received. b[5] Status_cml_pec_fault A PEC fault has occurred. Note: PEC checking is always active in the LTC2978. Any extra byte received before a STOP will set Status_cml_pec_fault unless the extra byte is a matching PEC byte. b[4] Status_cml_memory_fault A fault has occurred in the NVM. (EEPROM). b[3] Status_cml_processor_fault Not supported, always returns 0. b[2] Reserved Reserved, always returns 0. b[1] Status_cml_pmbus_fault A communication fault other than ones listed in this table has occurred. This is a catch all category for illegally formed I2C/SMBus commands (Example: An address byte with read =1 received immediately after a START). b[0] Status_cml_unknown_fault Not supported, always returns 0. STATUS_MFR_SPECIFIC The STATUS_MFR_SPECIFIC command returns manufacturer specific status flags. Bits marked FAULT = No are intended to support polled handshaking; these are not latched nor do they assert ALERTB. Bits marked FAULT = Yes assert ALERTB low and are cleared by CLEAR_FAULTS. Bits marked Channel = All can be read from any page. STATUS_MFR_SPECIFIC Data Contents BIT(S) SYMBOL CHANNEL FAULT b[7] Status_mfr_discharge A VOUT discharge fault occurred while attempting to enter the ON state OPERATION Current Page Yes b[6] Status_mfr_fault1_in This channel attempted to turn on while the FAULTBz1 pin was asserted low, Current Page or this channel has shut down at least once in response to a FAULTBz1 pin asserting low since the last CONTROLn pin toggle, OPERATION command ON/OFF cycle or CLEAR_FAULTS command. Yes b[5] Status_mfr_fault0_in This channel attempted to turn on while the FAULTBz0 pin was asserted low, Current Page or this channel has shut down at least once in response to a FAULTBz0 pin asserting low since the last CONTROLn pin toggle, OPERATION command ON/OFF cycle or CLEAR_FAULTS command. Yes b[4] Status_mfr_servo_target_reached Servo target has been reached. No b[3] Status_mfr_dac_connected DAC is connected and driving VDACP pin. Current Page No b[2] Status_mfr_dac_saturated A previous servo operation terminated with maximum or minimum DAC value. Current Page Yes b[1] Status_mfr_vinen_faulted_off VIN_EN has been deasserted due to a VOUT fault. All No b[0] Status_mfr_watchdog_fault A watchdog fault has occurred. All Yes Current Page 2978fc 40 LTC2978 PMBus COMMAND DESCRIPTION ADC MONITORING COMMANDS READ_VIN This command returns the most recent ADC measured value of the voltage measured at the VIN_SNS pin. READ_VIN Data Contents BIT(S) SYMBOL OPERATION b[15:0] Read_vin[15:0] The data uses the L11 format. Units: V READ_VOUT This command returns the most recent ADC measured value of the channel’s output voltage. When odd channels are configured to measure current, the data contents use the L11 format with units in mV. READ_VOUT Data Contents BIT(S) SYMBOL OPERATION b[15:0] Read_vout[15:0] The data uses the L16 format. Units: V READ_VOUT Data Contents—for Odd Channels Configured to Measure Current Bit(s) Symbol Operation b[15:0] Read_vout[15:0] The data uses the L11 format. Units: mV READ_TEMPERATURE_1 This command returns the most recent ADC measured value of junction temperature in °C as determined by the LTC2978’s internal temperature sensor. READ_TEMPERATURE_1 Data Contents BIT(S) SYMBOL OPERATION b[15:0] Read_temperature_1 [15:0] The data uses the L11 format. Units: °C. PMBUS_REVISION The PMBUS_REVISION command register is read only and reports the LTC2978 compliance to the PMBus standard revision 1.1. PMBUS_REVISION Data Contents BIT(S) SYMBOL OPERATION b[7:0] PMBus_rev Reports the PMBus standard revision compliance. This is hard-coded to 0x11 for revision 1.1. 2978fc 41 LTC2978 PMBus COMMAND DESCRIPTION MANUFACTURER SPECIFIC COMMANDS MFR_CONFIG_LTC2978 This command is used to configure various manufacturer specific operating parameters for each channel. MFR_CONFIG_LTC2978 Data Contents BIT(S) SYMBOL b[15:12] Reserved b[11] Mfr_config_fast_servo_off b[10] b[9] b[8] b[7] b[6] b[5:4] OPERATION Don’t care. Always returns 0. Disables fast servo when margining or trimming output voltages: 0: fast-servo enabled. 1: fast-servo disabled. Mfr_config_supervisor_resolution Selects supervisor resolution: 0: high resolution – 4mV/LSB, range for VVSENSEPn – VVSENSEMn is 0V to 3.8V. 1: low resolution – 8mV/LSB, range for VVSENSEPn – VVSENSEMn is 0V to 6.0V. Mfr_config_adc_hires Selects ADC resolution for odd channels. This is typically used to measure current. Ignored for even channels (they always use low resolution). 0: low resolution – 122µV/LSB. 1: high resolution – 15.6µV/LSB. Mfr_config_controln_sel Selects the active control pin input (CONTROL0 or CONTROL1) for this channel. 0: Select CONTROL0 pin. 1: Select CONTROL1 pin. Mfr_config_servo_continuous Select whether the UNIT should continuously servo VOUT after it has reached a new margin or nominal target. Only applies when Mfr_config_dac_mode = 00b. 0: Do not continuously servo VOUT after reaching initial target. 1: Continuously servo VOUT to target. Mfr_config_servo_on_warn Control re-servo on warning feature. Only applies when Mfr_config_dac_mode = 00b and Mfr_config_servo_continuous = 0. 0: Do not allow the unit to re-servo when a VOUT warning threshold is met or exceeded. Mfr_config_dac_mode b[3] Mfr_config_vo_en_wpu_en b[2] Mfr_config_vo_en_wpd_en b[1] Mfr_config_dac_gain b[0] Mfr_config_dac_pol 1: Allow the unit to re-servo VOUT to nominal target if VOUT ≥ V(Vout_ov_warn_limit) or VOUT ≤ V(Vout_uv_warn_limit). Determines how DAC is used when channel enters ON state or is already in ON state. 00: Soft connect (if needed) and servo to target. Wait for TON_RISE if just entering ON state. 01: DAC not connected. 10: DAC connected using value from MFR_DAC command. 11: DAC is soft connected. After soft connect is complete MFR_DAC may be written. VOUT_EN pin charge pumped, current-limited pull-up enable. 0: Disable weak pull-up. VOUT_EN pin driver is three-stated when channel is on. 1: Use weak current-limited pull-up on VOUT_EN pin when the channel is on. For channels 4-7 this bit is treated as a 0 regardless of its value. VOUT_EN pin current-limited pull-down enable. 0: Use a fast N-channel device to pull down VOUT_EN pin when the channel is off for any reason. 1: Use weak current-limited pull-down to discharge VOUT_EN pin when channel is off due to soft stop by the CONTROLn pin and/or OPERATION command. If the channel is off due to a fault, use the fast pull-down on VOUT_EN pin. For channels 4-7 this bit is treated as a 0 regardless of its value. DAC buffer gain. 0: Select DAC buffer gain dac_gain_0 (1.38V full-scale) 1: Select DAC buffer gain dac_gain_1 (2.65V full-scale) DAC output polarity. 0: Encodes negative (inverting) DC/DC converter trim input. 1: Encodes positive (noninverting) DC/DC converter trim input. 2978fc 42 LTC2978 PMBus COMMAND DESCRIPTION MFR_CONFIG_ALL_LTC2978 This command is used to configure parameters that are common to all channels on the IC. They may be set or reviewed from any PAGE setting. MFR_CONFIG_ALL_LTC2978 Data Contents BIT(S) SYMBOL b[7] Mfr_config_fault_log_enable b[6] Mfr_vin_on_clr_faults_en b[5] Mfr_config_control1_pol b[4] Mfr_config_control0_pol b[3] Mfr_config_vin_share_enable b[2] Mfr_config_all_pec_en b[1] Mfr_config_all_longer_pmbus_ timeout b[0] Mfr_config_all_vinen_wpu_dis OPERATION Enable fault logging to NVM in response to Fault. 0: Fault logging to NVM is disabled 1: Fault logging to NVM is enabled VIN_ON rising edge to clear all latched faults 0: VIN_ON clear faults feature is disabled 1: VIN_ON clear faults feature is enabled Selects active polarity of control1 pin. 0: Active low (pull pin low to start unit) 1: Active high (pull pin high to start unit) Selects active polarity of control0 pin. 0: Active low (pull pin low to start unit) 1: Active high (pull pin high to start unit) Allow this unit to hold share-clock pin low when VIN_ON has fallen below VIN_OFF. When enabled, this unit will also turn all channels off in response to share-clock being held low. 0: Share-clock inhibit is disabled 1: Share-clock inhibit is enabled PMBus packet error checking enable. 0: PEC is accepted but not required 1: PEC is required Increase PMBus timeout internal by a factor of 8. Recommended for fault logging. 0: PMBus timeout is not multiplied by a factor of 8 1: PMBus timeout is multiplied by a factor of 8 VIN_EN charge pumped, current-limited pull-up disable. 0: Use weak current-limited pull-up on VIN_EN after power-up, as long as no faults have forced VIN_EN off. 1: Disable weak pull-up. VIN_EN driver is three-stated after power-up as long as no faults have forced VIN_EN off. 2978fc 43 LTC2978 PMBus COMMAND DESCRIPTION MFR_FAULTz0_PROPAGATE, MFR_FAULTz1_PROPAGATE These manufacturer specific commands enable channels that have faulted off to propagate that state to the appropriate fault pin. Faulted off states for pages 0 through 3 can only be propagated to pins FAULTB00 and FAULTB01; this is referred to as zone 0. Faulted off states for pages 4 through 7 can only be propagated to pins FAULTB10 and FAULTB11; this is referred to as zone 1. The z designator in the command name is used to indicate that this command affects different zones depending on the page. See Figure 19. Note that pulling a fault pin low will have no affect for channels that have MRF_FAULTBzn_RESPONSE set to 0. The channel continues operation without interruption. This fault response is called no action in LTpowerPlay™. MFR_FAULTz0_PROPAGATE Data Content BIT(S) SYMBOL OPERATION b[7:1] Reserved Don’t care. Always returns 0. b[0] Mfr_faultbz0_propagate Enable fault propagation. For pages 0 through 3, zone 0 0: Channel’s faulted off state does not assert FAULTB00 low. 1: Channel’s faulted off state asserts FAULTB00 low. For pages 4 through 7, zone 1 0: Channel’s faulted off state does not assert FAULTB10 low. 1: Channel’s faulted off state asserts FAULTB10 low. MFR_FAULTz1_PROPAGATE Data Content BIT(S) SYMBOL OPERATION b[7:1] Reserved Don’t care. Always returns 0. b[0] Mfr_faultbz1_propagate Enable fault propagation. For pages 0 through 3, zone 0 0: Channel’s faulted off state does not assert FAULTB01 low. 1: Channel’s faulted off state asserts FAULTB01 low. For pages 4 through 7, zone 1 0: Channel’s faulted off state does not assert FAULTB11 low. 1: Channel’s faulted off state asserts FAULTB11 low. 2978fc 44 LTC2978 PMBus COMMAND DESCRIPTION MFR_PWRGD_EN This command register controls the mapping of the watchdog and channel power good status to the PWRGD pin. Note that odd numbered channels whose ADC is in high res mode do not contribute to power good. MFR_PWRGD_EN Data Contents BIT(S) SYMBOL OPERATION b[15:9] Reserved Read only, always returns 0s. b[8] Mfr_pwrgd_en_wdog Watchdog 1 = Watchdog timer not-expired status is ANDed with PWRGD status for any similarly enabled channels to determine when the PWRGD pin gets asserted. 0 = Watchdog timer does not affect the PWRGD pin. b[7] Mfr_pwrgd_en_chan7 Channel 7 1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when the PWRGD pin gets asserted. 0 = PRWGD status for this channel does not affect the PWRGD pin. b[6] Mfr_pwrgd_en_chan6 Channel 6 1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when the PWRGD pin gets asserted. 0 = PRWGD status for this channel does not affect the PWRGD pin. b[5] Mfr_pwrgd_en_chan5 Channel 5 1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when the PWRGD pin gets asserted. 0 = PRWGD status for this channel does not affect the PWRGD pin. b[4] Mfr_pwrgd_en_chan4 Channel 4 1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when the PWRGD pin gets asserted. 0 = PRWGD status for this channel does not affect the PWRGD pin. b[3] Mfr_pwrgd_en_chan3 Channel 3 1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when the PWRGD pin gets asserted. 0 = PRWGD status for this channel does not affect the PWRGD pin. b[2] Mfr_pwrgd_en_chan2 Channel 2 1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when the PWRGD pin gets asserted. 0 = PRWGD status for this channel does not affect the PWRGD pin. b[1] Mfr_pwrgd_en_chan1 Channel 1 1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when the PWRGD pin gets asserted. 0 = PRWGD status for this channel does not affect the PWRGD pin. b[0] Mfr_pwrgd_en_chan0 Channel 0 1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when the PWRGD pin gets asserted. 0 = PRWGD status for this channel does not affect the PWRGD pin. 2978fc 45 LTC2978 PMBus COMMAND DESCRIPTION MFR_FAULTB00_RESPONSE, MFR_FAULTB01_RESPONSE, MFR_FAULTB10_RESPONSE and MFR_ FAULTB11_RESPONSE These manufacturer specific commands share the same format and specify the response to assertions of the FAULTB pins. For fault zone 0, MFR_FAULTB00_RESPONSE determines whether channels 0 to 3 shut off when the FAULTB00 pin is asserted, and MFR_FAULTB01_RESPONSE determines whether channels 0 to 3 shut off when the FAULTB01 pin is asserted. For fault zone 1, MFR_FAULTB10_RESPONSE determines whether channels 4 to 7 shut off when the FAULTB10 pin is asserted, and MFR_FAULTB11_RESPONSE determines whether channels 4 to 7 shut off when the FAULTB11 pin is asserted. When a channel shuts off in response to a FAULTB pin, the ALERTB pin is asserted low and the appropriate bit is set in the STATUS_MFR_SPECIFIC register. For a graphical explanation, see the switches on the left hand side of Figure 19, Channel Fault Management Block Diagram. Data Contents—Fault Zone 0 Response Commands BIT(S) SYMBOL b[7:4] Reserved b[3] Mfr_faultb00_response_chan3, Mfr_faultb01_response_chan3 b[2] Mfr_faultb00_response_chan2, Mfr_faultb01_response_chan2 b[1] Mfr_faultb00_response_chan1, Mfr_faultb01_response_chan1 b[0] Mfr_faultb00_response_chan0, Mfr_faultb01_response_chan0 OPERATION Read only, always returns 0s. Channel 3 response. 0: The channel continues operation without interruption. 1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10µs. When the FAULTBzn pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings. Channel 2 response. 0: The channel continues operation without interruption. 1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10µs. When the FAULTBzn pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings. Channel 1 response. 0: The channel continues operation without interruption. 1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10µs. When the FAULTBzn pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings. Channel 0 response. 0: The channel continues operation without interruption. 1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10µs. When the FAULTBzn pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings. Data Contents—Fault Zone 1 Response Commands BIT(S) SYMBOL b[7:4] Reserved b[3] Mfr_faultb10_response_chan7, Mfr_faultb11_response_chan7 b[2] Mfr_faultb10_response_chan6, Mfr_faultb11_response_chan6 b[1] Mfr_faultb10_response_chan5, Mfr_faultb11_response_chan5 b[0] Mfr_faultb10_response_chan4, Mfr_faultb11_response_chan4 OPERATION Read only, always returns 0s. Channel 7 response. 0: The channel continues operation without interruption. 1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10µs. When the FAULTBzn pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings. Channel 6 response. 0: The channel continues operation without interruption. 1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10µs. When the FAULTBzn pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings. Channel 5 response. 0: The channel continues operation without interruption. 1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10µs. When the FAULTBzn pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings. Channel 4 response. 0: The channel continues operation without interruption. 1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 10µs. When the FAULTBzn pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings. 2978fc 46 LTC2978 PMBus COMMAND DESCRIPTION MFR_VINEN_OV_FAULT_RESPONSE This command register determines whether VOUT over voltage faults from a given channel cause the VIN_EN pin to be forced off. MFR_VINEN_OV_FAULT_RESPONSE Data Contents BIT(S) SYMBOL b[7] Mfr_vinen_ov_fault_response_chan7 OPERATION Response to channel 7 VOUT_OV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[6] Mfr_vinen_ov_fault_response_chan6 Response to channel 6 VOUT_OV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[5] Mfr_vinen_ov_fault_response_chan5 Response to channel 5 VOUT_OV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[4] Mfr_vinen_ov_fault_response_chan4 Response to channel 4 VOUT_OV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[3] Mfr_vinen_ov_fault_response_chan3 Response to channel 3 VOUT_OV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[2] Mfr_vinen_ov_fault_response_chan2 Response to channel 2 VOUT_OV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[1] Mfr_vinen_ov_fault_response_chan1 Response to channel 1 VOUT_OV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[0] Mfr_vinen_ov_fault_response_chan0 Response to channel 0 VOUT_OV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. 2978fc 47 LTC2978 PMBus COMMAND DESCRIPTION MFR_VINEN_UV_FAULT_RESPONSE This command register determines whether VOUT undervoltage faults from a given channel cause the VIN_EN pin to be forced off. MFR_VINEN_UV_FAULT_RESPONSE Data Contents BIT(S) SYMBOL b[7] OPERATION Mfr_vinen_uv_fault_response_chan7 Response to channel 7 VOUT_UV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[6] Mfr_vinen_uv_fault_response_chan6 Response to channel 6 VOUT_UV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[5] Mfr_vinen_uv_fault_response_chan5 Response to channel 5 VOUT_UV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[4] Mfr_vinen_uv_fault_response_chan4 Response to channel 4 VOUT_UV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[3] Mfr_vinen_uv_fault_response_chan3 Response to channel 3 VOUT_UV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[2] Mfr_vinen_uv_fault_response_chan2 Response to channel 2 VOUT_UV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[1] Mfr_vinen_uv_fault_response_chan1 Response to channel 1 VOUT_UV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. b[0] Mfr_vinen_uv_fault_response_chan0 Response to channel 0 VOUT_UV_FAULT. 1 = Disable VIN_EN via fast pull-down. 0 = Leave VIN_EN as-is. MFR_RETRY_DELAY This command determines the retry interval when the LTC2978 is in retry mode in response to a fault condition. MFR_RETRY_DELAY Data Contents BIT(S) SYMBOL OPERATION b[15:0] Mfr_retry_delay The data uses the L11 format. This delay is counted using SHARE_CLK only. Delays are rounded to the nearest 200µs. Units: ms. Max delay is 13.1 sec. 2978fc 48 LTC2978 PMBus COMMAND DESCRIPTION MFR_RESTART_DELAY This command sets the minimum off time of a CONTROL initiated restart. If the CONTROL pin is toggled off for at least 10µs then on, all dependent channels are disabled, held off for a time = Mfr_restart_delay, then sequenced back on. CONTROLn pin transitions whose OFF time exceeds Mfr_restart_delay are not affected by this command. A value of all zeros disables this feature. MFR_RESTART_DELAY Data Contents BIT(S) SYMBOL OPERATION b[15:0] Mfr_restart_delay The data uses the L11 format. This delay is counted using SHARE_CLK only. Delays are rounded to the nearest 200µs. Units: ms. Max delay is 13.1 sec. MFR_VOUT_PEAK This command returns the maximum ADC measured value of the channel’s output voltage. This command is not supported for odd channels that are configured to measure current. This register is reset to 0xF800 (0.0) when the LTC2978 emerges from power-on reset or when a CLEAR_FAULTS command is executed. MFR_VOUT_PEAK Data Contents BIT(S) SYMBOL OPERATION b[15:0] Mfr_vout_peak[15:0] The data uses the L16 format. Units: V. MFR_VIN_PEAK This command returns the maximum ADC measured value of the input voltage. This register is reset to 0x7C00 (–225) when the LTC2978 emerges from power-on reset or when a CLEAR_FAULTS command is executed. MFR_VIN_PEAK Data Contents BIT(S) SYMBOL OPERATION b[15:0] Mfr_vin_peak[15:0] The data uses the L11 format. Units: V MFR_TEMPERATURE_PEAK This command returns the maximum ADC measured value of junction temperature in °C as determined by the LTC2978’s internal temperature sensor. This register is reset to 0x7C00 (–225) when the LTC2978 emerges from power-on reset or when a CLEAR_FAULTS command is executed. MFR_TEMPERATURE_PEAK Data Contents BIT(S) SYMBOL OPERATION b[15:0] Mfr_temperature_peak[15:0] The data uses the L11 format. Units: °C. 2978fc 49 LTC2978 PMBus COMMAND DESCRIPTION MFR_DAC This command register allows the user to directly program the 10-bit DAC. Manual DAC writes require the channel to be in the ON state,TON_RISE to have expired and MFR_CONFIG_LTC2978 b[5:4] = 10b or 11b. Writing MFR_CONFIG_ LTC2978 b[5:4] = 10b commands the DAC to hard connect with the value in Mfr_dac_direct_val. Writing b[5:4] = 11b commands the DAC to soft connect. Once the DAC has soft connected, Mfr_dac_direct_val returns the value that allowed the DAC to be connected without perturbing the power supply. MFR_DAC Data Contents BIT(S) SYMBOL b[15:10] Reserved b[9:0] OPERATION Read only, always returns 0. Mfr_dac_direct_val DAC code value. MFR_POWERGOOD_ASSERTION_DELAY This command register allows the user to program the delay from when the internal power good signal becomes valid until the power good output is asserted. This delay is counted using SHARE_CLK if available, otherwise the internal oscillator is used. This delay is internally limited to 13.1 seconds, and rounded to the nearest 200µs. The read value of this command always returns what was last written and does not reflect internal limiting. MFR_POWERGOOD_ASSERTION_DELAY Data Contents BIT(S) SYMBOL OPERATION b[15:0] Mfr_powergood_assertion_delay The data uses the L11 format. This delay is counted using SHARE_CLK if available, otherwise the internal oscillator is used. Delays are rounded to the nearest 200µs. Units: ms. Max delay is 13.1 sec. WATCHDOG OPERATION A non zero write to the MFR_WATCHDOG_T register will reset the watchdog timer. Low-to-high transitions on the WDI/ RESETB pin also reset the watchdog timer. If the timer expires, ALERTB is asserted and the PWRGD output is optionally deasserted and then reasserted after MFR_PWRGD_ASSERTION_DELAY ms. Writing 0 to either the MFR_WATCH_DOG_T or MFR_WATCHDOG_T_FIRST registers will disable the timer. MFR_WATCHDOG_T_FIRST and MFR_WATCHDOG_T The MFR_WATCHDOG_T_FIRST register allows the user to program the duration of the first watchdog timer interval following assertion of the POWER GOOD signal, assuming the POWER GOOD signal reflects the status of the watchdog timer. If assertion of POWER GOOD is not conditioned by the watchdog timer’s status, then MFR_WATCHDOG_T_FIRST applies to the first timing interval after the timer is enabled. Writing a value of 0ms to the MFR_WATCHDOG_T_FIRST register disables the watchdog timer. The MFR_WATCHDOG_T register allows the user to program watchdog time intervals subsequent to the MFR_ WATCHDOG_T_FIRST timing interval. Writing a value of 0ms to the MFR_WATCHDOG_T register disables the watchdog timer. A non-zero write to MFR_WATCHDOG_T will reset the watchdog timer. 2978fc 50 LTC2978 PMBus COMMAND DESCRIPTION MFR_WATCHDOG_T_POR and MFR_WATCHDOG_T Data Contents BIT(S) SYMBOL OPERATION b[15:0] Mfr_watchdog_t_first The data uses the L11 format. Mfr_watchdog_t These timers operate on an internal clock. The Mfr_watchdog_t timer will align to SHARE_CLK if it is running. Delays are rounded to the nearest 10µs for _t and 1ms for _t_first. Writing a zero value for Y to the Mfr_watchdog_t or Mfr_watchdog_t_first registers will disable the watchdog timer. Units: ms. Max timeout is 0.6 sec for _t and 65 sec for _t_first MFR_PAGE_FF_MASK The MFR_PAGE_FF_MASK command is used to select which channels respond when the global page command (PAGE=0xFF) is in use. MFR_PAGE_FF_MASK Data Contents BIT(S) SYMBOL b[7] Mfr_page_ff_mask_chan7 OPERATION Channel 7 masking of global page command (PAGE=0xFF) accesses 0 = ignore global page command accesses 1 = fully respond to global page command accesses b[6] Mfr_page_ff_mask_chan6 Channel 6 masking of global page command (PAGE=0xFF) accesses 0 = ignore global page command accesses 1 = fully respond to global page command accesses b[5] Mfr_page_ff_mask_chan5 Channel 5 masking of global page command (PAGE=0xFF) accesses 0 = ignore global page command accesses 1 = fully respond to global page command accesses b[4] Mfr_page_ff_mask_chan4 Channel 4 masking of global page command (PAGE=0xFF) accesses 0 = ignore global page command accesses 1 = fully respond to global page command accesses b[3] Mfr_page_ff_mask_chan3 Channel 3 masking of global page command (PAGE=0xFF) accesses 0 = ignore global page command accesses 1 = fully respond to global page command accesses b[2] Mfr_page_ff_mask_chan2 Channel 2 masking of global page command (PAGE=0xFF) accesses 0 = ignore global page command accesses 1 = fully respond to global page command accesses b[1] Mfr_page_ff_mask_chan1 Channel 1 masking of global page command (PAGE=0xFF) accesses 0 = ignore global page command accesses 1 = fully respond to global page command accesses b[0] Mfr_page_ff_mask_chan0 Channel 0 masking of global page command (PAGE=0xFF) accesses 0 = ignore global page command accesses 1 = fully respond to global page command accesses 2978fc 51 LTC2978 PMBus COMMAND DESCRIPTION MFR_PADS The MFR_PADS command provides read only access to slow frequency digital pads. The input values presented in bits[9:0] are before any deglitching logic. MFR_PADS_PWRGD_DRIVE Data Contents BIT(S) SYMBOL b[15] Mfr_pads_pwrgd_drive OPERATION 0 = PWRGD pad is being driven low by this chip b[14] 1 = PWRGD pad is not being driven low by this chip 0 = ALERTB pad is being driven low by this chip Mfr_pads_alertb_drive 1 = ALERTB pad is not being driven low by this chip b[13:10] Mfr_pads_faultb_drive[3.0] Bit[3] used for FAULTB00 pad, bit[2] used for FAULTB01 pad, bit[1] used for FAULTB10 pad, bit[0] used for FAULTB11 pad as follows: 0 = FAULTBzn pad is being driven low by this chip b[9:8] 1 = FAULTBzn pad is not being driven low by this chip 11: Logic high detected on ASEL1 input pad Mfr_pads_asel1[1:0] 10: ASEL1 input pad is floating 01: Reserved b[7:6] 00: Logic low detected on ASEL1 input pad 11: Logic high detected on ASEL0 input pad Mfr_pads_asel0[1:0] 10: ASEL0 input pad is floating 01: Reserved b[5] Mfr_pads_control1 00: Logic low detected on ASEL0 input pad 1: Logic high detected on CONTROL1 pad b[4] Mfr_pads_control0 0: Logic low detected on CONTROL1 pad 1: Logic high detected on CONTROL0 pad b[3:0] 0: Logic low detected on CONTROL0 pad Bit[3] used for FAULTB00 pad, bit[2] used for FAULTB01 pad, bit[1] used for FAULTB10 pad, bit[0] used for FAULTB11 pad as follows: Mfr_pads_faultb[3:0] 1: Logic high detected on FAULTBzn pad 0: Logic low detected on FAULTBzn pad MFR_I2C_BASE_ADDRESS The MFR_I2C_BASE_ADDRESS command determines the base value for the I2C/SMBus address byte. Offsets of 0 to 9 are added to this base address to make the device I2C/SMBus address. The part responds to the device address. MFR_I2C_BASE_ADDRESS Data Contents BIT(S) SYMBOL b[7] Reserved b[6:0] i2c_base_address OPERATION Read only, always returns 0. This 7-bit value determines the base value of the 7-bit I2C/SMBus address. See Operation Section: Device Address. MFR_SPECIAL_ID This register contains the manufacturer ID for the LTC2978. MFR_SPECIAL_ID Data Contents BIT(S) SYMBOL OPERATION b[15:0] Mfr_special_id Read only, always returns 0x0121 2978fc 52 LTC2978 PMBus COMMAND DESCRIPTION MFR_SPECIAL_LOT These paged registers contain information that identifies the user configuration that was programmed at the factory. MFR_SPECIAL_LOT Data Contents BIT(S) SYMBOL OPERATION b[7:0] Mfr_special_lot Contains the LTC default special lot number. Contact the factory to request a custom factory programmed user configuration and special lot number. MFR_VOUT_DISCHARGE_THRESHOLD This register contains the coefficient that multiplies VOUT_COMMAND in order to determine the OFF threshold voltage for the associated output. If the output voltage has not decayed below MFR_VOUT_DISCHARGE_ THRESHOLD • VOUT_COMMAND prior to the channel being commanded to enter/re-enter the ON state, bit [7] in the STATUS_MFR_SPECIFIC register will be set and the ALERTB pin will be asserted low. In addition, the channel will not enter the ON state until the output has decayed below its OFF threshold voltage. Other channels can be held off if a particular output has failed to discharge by using the bidirectional FAULTBzn pins (refer to the MFR_FAULTBzn_RESPONSE and MFR_FAULTBzn_PROPAGATE registers). MFR_VOUT_DISCHARGE_THRESHOLD Data Contents BIT(S) SYMBOL OPERATION b[15:0] Mfr_vout_discharge_ threshold The data uses the L11 format. Units: Dimensionless, this register contains a coefficient. MFR_COMMON This command returns status information for the share-clock pin (SHARE_CLK) and the write-protect pin (WP). MFR_COMMON Data Contents BIT(S) SYMBOL OPERATION b[7:2] Reserved Read only, always returns 0s b[1] Mfr_common_ share_clk Returns status of share-clock pin 1: Share-clock pin is being held low 0: Share-clock pin is active b[0] Mfr_common_ write_protect Returns status of write-protect pin 1: Write-protect pin is high 0: Write-protect pin is low MFR_SPARE0 This 16-bit wide register can be used to store miscellaneous information. The contents of this register may be stored and recalled from EEPROM using the STORE_USER_ALL and RESTORE_USER_ALL commands, respectively. MFR_SPARE2 These 16-bit wide, paged registers can be used to store miscellaneous information. The contents of these registers may be stored and recalled from EEPROM using the STORE_USER_ALL and RESTORE_USER_ALL commands, respectively. 2978fc 53 LTC2978 PMBus COMMAND DESCRIPTION MFR_VOUT_MIN This command returns the minimum ADC measured value of the channel’s output voltage. This register is reset to 0xFFFF (7.999) when the LTC2978 emerges from power-on reset or when a CLEAR_FAULTS command is executed. When odd channels are configured to measure current, this command is not supported. Updates are disabled when undervoltage detection is disabled. MFR_VOUT_MIN Data Contents BIT(S) SYMBOL OPERATION b[15:0] Mfr_vout_min The data uses the L16 format. Units: V. MFR_VIN_MIN This command returns the minimum ADC measured value of the input voltage. This register is reset to 0x7BFF (approximately 225) when the LTC2978 emerges from power-on reset or when a CLEAR_FAULTS command is executed. Updates are disabled when unit is off for insufficient input voltage. MFR_VIN_MIN Data Contents BIT(S) SYMBOL OPERATION b[15:0] Mfr_vin_min The data uses the L11 format. Units: V. MFR_TEMPERATURE_MIN This command returns the minimum ADC measured value of junction temperature in °C as determined by the LTC2978’s internal temperature sensor. This register is reset to 0x7BFF (approximately 225) when the LTC2978 emerges from power-on reset or when a CLEAR_FAULTS command is executed. MFR_TEMPERATURE_MIN Data Contents BIT(S) SYMBOL OPERATION b[15:0] Mfr_temperature_min The data uses the L11 format. Units: °C. FAULT LOG OPERATION A conceptual diagram of the fault log is shown in Figure 13. The fault log provides black box capability to the LTC2978. During normal operation, the contents of the status registers, the output voltage/current readings, temperature readings as well as peak and min values of these quantities are stored in a continuously updated buffer in RAM. You can think of the operation as being similar to a strip chart recorder. When a fault occurs, the contents are written into EEPROM for nonvolatile storage. The EEPROM fault log is then locked. The part can be powered down with the fault log being available for reading at a later time. 2978fc 54 LTC2978 PMBus COMMAND DESCRIPTION 8 ADC READINGS CONTINUOUSLY FILL BUFFER RAM 255 BYTES TIME OF FAULT TRANSFER TO EEPROM AND LOCK ... ... AFTER FAULT READ FROM EEPROM AND LOCK BUFFER EEPROM 255 BYTES 2978 F13 Figure 13. Fault Log Conceptual Diagram MFR_FAULT_LOG_STORE This command allows the user to transfer data from the RAM buffer to EEPROM. MFR_FAULT_LOG_RESTORE This command allows the user to transfer a copy of the fault-log data from the EEPROM to the RAM buffer. After a restore the RAM buffer is locked until a successful Mfr_fault_log read. MFR_FAULT_LOG_CLEAR This command initializes the EEPROM block reserved for fault logging. Any previous fault log stored in EEPROM will be erased by this operation. MFR_FAULT_LOG_STATUS Read only. This register is used to manage fault log events. Mfr_fault_log_status_eeprom is set after a MFR_FAULT_LOG_STORE command or a faulted-off event triggers a transfer of the fault log from RAM to EEPROM. This bit is cleared by a MFR_FAULT_LOG_CLEAR command. Mfr_fault_log_status_ram is set after a MFR_FAULT_LOG_RESTORE to indicate that the data in the RAM has been restored from EEPROM and not yet read using a MFR_FAULT_LOG command. This bit is cleared only by a successful execution of an MFR_FAULT_LOG command. MFR_FAULT_LOG_STATUS Data Contents BIT(S) SYMBOL b[1] Mfr_fault_log_status_ram OPERATION Fault log RAM status: 0: The fault log RAM allows updates. 1: The fault log RAM is locked until the next Mfr_fault_log read. b[0] Mfr_fault_log_status_eeprom Fault log EEPROM status: 0: The transfer of the fault log RAM to the EEPROM is enabled. 1: The transfer of the fault log RAM to the EEPROM is inhibited. 2978fc 55 LTC2978 PMBus COMMAND DESCRIPTION MFR_FAULT_LOG Read only. This 2040-bit data block contains a copy of the RAM buffer fault log. The RAM buffer is continuously updated after each ADC conversion as long as Mfr_fault_ log_status_ram is clear. With Mfr_config_fault_log_en = 1 and Mfr_fault_log_status_eeprom = 0, the RAM buffer is transferred to EEPROM whenever an LTC2978 fault causes a channel to latch off or a MFR_FAULT_LOG_STORE command is received. Mfr_fault_log_status_eeprom is set high after the RAM buffer is transferred to EEPROM and not cleared until a Mfr_fault_log_clear is received, even if the LTC2978 is reset or powered down. Fault log EEPROM transfers are not initiated as a result of Status_mfr_discharge, Status_mfr_fault1_in or Status_mfr_fault0_in events. During a Mfr_fault_log read, data is returned as defined by the following table. The fault log data is partitioned into two sections. The first section is referred to as the preamble and contains the Position-last pointer, time information and peak and minimum values. The second section contains a chronological record of telemetry and requires Position-last for proper interpretation. The fault log stores approximately 1 to 2 seconds of telemetry. To prevent timeouts during block reads, it is recommended that MFR_CONFIG_ALL_LTC2978 b[1] be set to 1. Table 2. Data Block Contents DATA Position_last[7:0] SharedTime[7:0] SharedTime[15:8] SharedTime[23:16] SharedTime[31:24] SharedTime[39:32] SharedTime[40] Mfr_vout_peak0[7:0] Mfr_vout_peak0[15:8] Mfr_vout_min0[7:0] Mfr_vout_min0[15:8] Mfr_vout_peak1[7:0] Mfr_vout_peak1[15:8] Mfr_vout_min1[7:0] Mfr_vout_min1[15:8] Mfr_vin_peak[7:0] Mfr_vin_peak[15:8] Mfr_vin_min[7:0] Mfr_vin_min[15:8] Mfr_vout_peak2[7:0] Mfr_vout_peak2[15:8] Mfr_vout_min2[7:0] Mfr_vout_min2[15:8] Mfr_vout_peak3[7:0] Mfr_vout_peak3[15:8] Mfr_vout_min3[7:0] Mfr_vout_min3[15:8] Mfr_temp_peak[7:0] Mfr_temp_peak[15:8] Mfr_ temp_min[7:0] Mfr_ temp_min[15:8] Mfr_vout_peak4[7:0] Mfr_vout_peak4[15:8] Mfr_vout_min4[7:0] Mfr_vout_min4[15:8] Mfr_vout_peak5[7:0] Mfr_vout_peak5[15:8] Mfr_vout_min5[7:0] Mfr_vout_min5[15:8] Mfr_vout_peak6[7:0] Mfr_vout_peak6[15:8] Mfr_vout_min6[7:0] Mfr_vout_min6[15:8] BYTE* 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 DESCRIPTION Position of fault log pointer when fault occurred. 41-bit share-clock counter value when fault occurred. Counter LSB is in 200µs increments. This counter is cleared at power-up or after the LTC2978 is reset 2978fc 56 LTC2978 PMBus COMMAND DESCRIPTION Table 2. Data Block Contents DATA Mfr_vout_peak7[7:0] Mfr_vout_peak7[15:8] Mfr_vout_min7[7:0] Mfr_vout_min7[15:8] BYTE* 43 44 45 46 DESCRIPTION 47 bytes for preamble Fault_log [Position_last] Fault_log . . . Fault_log Reserved 47 48 237 Last Valid Byte 238-254 Number of loops (238-47)/40 = 4.8 *Note: PMBus data byte numbers start at 1 rather than 0. Position_last is the first byte returned after BYTE COUNT = OxFF. See block read protocol. The data returned between bytes 47 and 237 of the previous table is interpreted using Position_last and the following table. The key to identifying byte 47 is to locate the DATA corresponding to POSITION = Position_last in the next table. Subsequent bytes are identified by decrementing the value of POSITION. For example: If Position_last = 9 then the first data returned in byte position 47 of a block read is Read_vin[15:8] followed by Read_vin[7:0] followed by Status_mfr of page 1. See Table 3. Table 3. Interpreting Cyclical Loop POSITION 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Table 3. Interpreting Cyclical Loop POSITION 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 DATA Read_vout3[15:8] Status_vout3 Status_mfr3 Read_temperature_1[7:0] Read_temperature_1[15:8] Status_temp Reserved Read_vout4[7:0] Read_vout4[15:8] Status_vout4 Status_mfr4 Read_vout5[7:0] Read_vout5[15:8] Status_vout5 Status_mfr5 Read_vout6[7:0] Read_vout6[15:8] Status_vout6 Status_mfr6 Read_vout7[7:0] Read_vout7[15:8] Status_vout7 Status_mfr7 Total Bytes =40 The following table fully decodes a sample fault log read to help clarify the cyclical nature of the operation. MFR_FAULT_LOG DATA BLOCK CONTENTS DATA Read_vout0[7:0] Read_vout0[15:8] Status_vout0 Status_mfr0 Read_vout1[7:0] Read_vout1[15:8] Status_vout1 Status_mfr1 Read_vin[7:0] Read_vin[15:8] Status_vin Reserved Read_vout2[7:0] Read_vout2[15:8] Status_vout2 Status_mfr2 Read_vout3[7:0] PREAMBLE INFORMATION BYTE BYTE NUMBER NUMBER DECIMAL HEX DATA DESCRIPTION 0 00 Position_last[7:0] = 9 Position of Fault-Log Pointer When Fault Occured. 1 01 SharedTime[7:0] 41-Bit ShareClock Counter Value When Fault Occurred. Counter LSB Is in 200µs Increments. 2 02 SharedTime[15:8] 3 03 SharedTime[23:16] 4 04 SharedTime[31:24] 2978fc 57 LTC2978 PMBus COMMAND DESCRIPTION BYTE BYTE NUMBER NUMBER DECIMAL HEX DATA DESCRIPTION BYTE BYTE NUMBER NUMBER DECIMAL HEX DATA 5 05 SharedTime[39:32] 44 2C Mfr_vout_peak7[15:8] 6 06 SharedTime[40] 45 2D Mfr_vout_min7[7:0] 7 07 Mfr_vout_peak0[7:0] 46 2E 8 08 Mfr_vout_peak0[15:8] Mfr_vout_min7[15:8] DESCRIPTION End of Preamble CYCLICAL DATA LOOPS 9 09 Mfr_vout_min0[7:0] 10 0A Mfr_vout_min0[15:8] 11 0B Mfr_vout_peak1[7:0] 12 0C Mfr_vout_peak1[15:8] 47 2F 9 Read_vin[15:8] 13 0D Mfr_vout_min1[7:0] 48 30 8 Read_vin[7:0] 14 0E Mfr_vout_min1[15:8] 49 31 7 Status_mfr1 15 0F Mfr_vin_peak[7:0] 50 32 6 Status_vout1 16 10 Mfr_vin_peak[15:8] 51 33 5 Read_vout1[15:8] 17 11 Mfr_vin_min[7:0] 52 34 4 Read_vout1[7:0] 18 12 Mfr_vin_min[15:8] 53 35 3 Status_mfr0 19 13 Mfr_vout_peak2[7:0] 54 36 2 Status_vout0 20 14 Mfr_vout_peak2[15:8] 55 37 1 Read_vout0[15:8] 21 15 Mfr_vout_min2[7:0] 56 38 0 Read_vout0[7:0] 22 16 Mfr_vout_min2[15:8] 23 17 Mfr_vout_peak3[7:0] 24 18 Mfr_vout_peak3[15:8] 25 19 Mfr_vout_min3[7:0] 26 1A Mfr_vout_min3[15:8] 57 39 39 Status_mfr7 27 1B Mfr_temp_peak[7:0] 58 3A 38 Status_vout7 28 1C Mfr_temp_peak[15:8] 59 3B 37 Read_vout7[15:8] 29 1D Mfr_ temp_min[7:0] 60 3C 36 Read_vout7[7:0] 30 1E Mfr_ temp_min[15:8] 61 3D 35 Status_mfr6 31 1F Mfr_vout_peak4[7:0] 62 3E 34 Status_vout6 32 20 Mfr_vout_peak4[15:8] 63 3F 33 Read_vout6[15:8] 33 21 Mfr_vout_min4[7:0] 64 40 32 Read_vout6[7:0] 34 22 Mfr_vout_min4[15:8] 65 41 31 Status_mfr5 35 23 Mfr_vout_peak5[7:0] 66 42 30 Status_vout5 36 24 Mfr_vout_peak5[15:8] 67 43 29 Read_vout5[15:8] 37 25 Mfr_vout_min5[7:0] 68 44 28 Read_vout5[7:0] 38 26 Mfr_vout_min5[15:8] 69 45 27 Status_mfr4 39 27 Mfr_vout_peak6[7:0] 70 46 26 Status_vout4 40 28 Mfr_vout_peak6[15:8] 71 47 25 Read_vout4[15:8] 41 29 Mfr_vout_min6[7:0] 72 48 24 Read_vout4[7:0] 42 2A Mfr_vout_min6[15:8] 73 49 23 Reserved 43 2B Mfr_vout_peak7[7:0] 74 4A 22 Status_temp LOOP BYTE BYTE BYTE NUMBER NUMBER NUMBER DECIMAL HEX DECIMAL LOOP BYTE BYTE BYTE NUMBER NUMBER NUMBER DECIMAL HEX DECIMAL DATA LOOP 0 DATA LOOP 1 40 BYTES PER LOOP Position_last 40 BYTES PER LOOP 2978fc 58 LTC2978 PMBus COMMAND DESCRIPTION LOOP BYTE BYTE BYTE NUMBER NUMBER NUMBER DECIMAL HEX DECIMAL 75 76 4B 4C 21 20 DATA LOOP 1 40 BYTES PER LOOP LOOP BYTE BYTE BYTE NUMBER NUMBER NUMBER DECIMAL HEX DECIMAL DATA LOOP 2 Read_ temperature_1[15:8] 109 6D 27 Status_mfr4 Read_ temperature_1[7:0] 110 6E 26 Status_vout4 111 6F 25 Read_vout4[15:8] 112 70 24 Read_vout4[7:0] 113 71 23 Reserved 114 72 22 Status_temp 115 73 21 Read_temperature_ 1[15:8] 116 74 20 Read_temperature_ 1[7:0] 77 4D 19 Status_mfr3 78 4E 18 Status_vout3 79 4F 17 Read_vout3[15:8] 80 50 16 Read_vout3[7:0] 81 51 15 Status_mfr2 82 52 14 Status_vout2 83 53 13 Read_vout2[15:8] 117 75 19 Status_mfr3 84 54 12 Read_vout2[7:0] 118 76 18 Status_vout3 85 55 11 Reserved 119 77 17 Read_vout3[15:8] 86 56 10 Status_vin 120 78 16 Read_vout3[7:0] 87 57 9 Read_vin[15:8] 121 79 15 Status_mfr2 88 58 8 Read_vin[7:0] 122 7A 14 Status_vout2 89 59 7 Status_mfr1 123 7B 13 Read_vout2[15:8] 90 5A 6 Status_vout1 124 7C 12 Read_vout2[7:0] 91 5B 5 Read_vout1[15:8] 125 7D 11 Reserved 92 5C 4 Read_vout1[7:0] 126 7E 10 Status_vin 93 5D 3 Status_mfr0 127 7F 9 Read_vin[15:8] 94 5E 2 Status_vout0 128 80 8 Read_vin[7:0] 95 5F 1 Read_vout0[15:8] 129 81 7 Status_mfr1 96 60 0 Read_vout0[7:0] 130 82 6 Status_vout1 131 83 5 Read_vout1[15:8] 132 84 4 Read_vout1[7:0] 133 85 3 Status_mfr0 134 86 2 Status_vout0 LOOP BYTE BYTE BYTE NUMBER NUMBER NUMBER DECIMAL HEX DECIMAL DATA LOOP 2 40 BYTES PER LOOP 97 61 39 Status_mfr7 135 87 1 Read_vout0[15:8] 98 62 38 Status_vout7 136 88 0 Read_vout0[7:0] 99 63 37 Read_vout7[15:8] 100 64 36 Read_vout7[7:0] 101 65 35 Status_mfr6 102 66 34 Status_vout6 103 67 33 Read_vout6[15:8] 137 89 39 Status_mfr7 104 68 32 Read_vout6[7:0] 138 8A 38 Status_vout7 105 69 31 Status_mfr5 139 8B 37 Read_vout7[15:8] 106 6A 30 Status_vout5 140 8C 36 Read_vout7[7:0] 107 6B 29 Read_vout5[15:8] 141 8D 35 Status_mfr6 108 6C 28 Read_vout5[7:0] LOOP BYTE BYTE BYTE NUMBER NUMBER NUMBER DECIMAL HEX DECIMAL DATA LOOP 3 40 BYTES PER LOOP 40 BYTES PER LOOP 2978fc 59 LTC2978 PMBus COMMAND DESCRIPTION LOOP BYTE BYTE BYTE NUMBER NUMBER NUMBER DECIMAL HEX DECIMAL DATA LOOP 3 40 BYTES PER LOOP LOOP BYTE BYTE BYTE NUMBER NUMBER NUMBER DECIMAL HEX DECIMAL DATA LOOP 4 142 8E 34 Status_vout6 177 B1 39 Status_mfr7 143 8F 33 Read_vout6[15:8] 178 B2 38 Status_vout7 144 90 32 Read_vout6[7:0] 179 B3 37 Read_vout7[15:8] 145 91 31 Status_mfr5 180 B4 36 Read_vout7[7:0] 146 92 30 Status_vout5 181 B5 35 Status_mfr6 147 93 29 Read_vout5[15:8] 182 B6 34 Status_vout6 148 94 28 Read_vout5[7:0] 183 B7 33 Read_vout6[15:8] 149 95 27 Status_mfr4 184 B8 32 Read_vout6[7:0] 150 96 26 Status_vout4 185 B9 31 Status_mfr5 151 97 25 Read_vout4[15:8] 186 BA 30 Status_vout5 152 98 24 Read_vout4[7:0] 187 BB 29 Read_vout5[15:8] 153 99 23 Reserved 188 BC 28 Read_vout5[7:0] 154 9A 22 Status_temp 189 BD 27 Status_mfr4 155 9B 21 Read_temperature_ 1[15:8] 190 BE 26 Status_vout4 Read_temperature_ 1[7:0] 191 BF 25 Read_vout4[15:8] 192 C0 24 Read_vout4[7:0] 193 C1 23 Reserved 194 C2 22 Status_temp 195 C3 21 Read_temperature_ 1[15:8] 196 C4 20 Read_temperature_ 1[7:0] 156 9C 20 157 9D 19 Status_mfr3 158 9E 18 Status_vout3 159 9F 17 Read_vout3[15:8] 160 A0 16 Read_vout3[7:0] 161 A1 15 Status_mfr2 162 A2 14 Status_vout2 197 C5 19 Status_mfr3 163 A3 13 Read_vout2[15:8] 198 C6 18 Status_vout3 164 A4 12 Read_vout2[7:0] 199 C7 17 Read_vout3[15:8] 165 A5 11 Reserved 200 C8 16 Read_vout3[7:0] 166 A6 10 Status_vin 201 C9 15 Status_mfr2 167 A7 9 Read_vin[15:8] 202 CA 14 Status_vout2 168 A8 8 Read_vin[7:0] 203 CB 13 Read_vout2[15:8] 169 A9 7 Status_mfr1 204 CC 12 Read_vout2[7:0] 170 AA 6 Status_vout1 205 CD 11 Reserved 171 AB 5 Read_vout1[15:8] 206 CE 10 Status_vin 172 AC 4 Read_vout1[7:0] 207 CF 9 Read_vin[15:8] 173 AD 3 Status_mfr0 208 D0 8 Read_vin[7:0] 174 AE 2 Status_vout0 209 D1 7 Status_mfr1 175 AF 1 Read_vout0[15:8] 210 D2 6 Status_vout1 176 B0 0 Read_vout0[7:0] 211 D3 5 Read_vout1[15:8] 40 BYTES PER LOOP 2978fc 60 LTC2978 PMBus COMMAND DESCRIPTION LOOP BYTE BYTE BYTE NUMBER NUMBER NUMBER DECIMAL HEX DECIMAL RESERVED BYTES DATA LOOP 4 212 D4 4 Read_vout1[7:0] 213 D5 3 Status_mfr0 214 D6 2 Status_vout0 215 D7 1 Read_vout0[15:8] 216 D8 0 Read_vout0[7:0] LOOP BYTE BYTE BYTE NUMBER NUMBER NUMBER DECIMAL HEX DECIMAL DATA LOOP 5 217 D9 39 Status_mfr7 218 DA 38 Status_vout7 219 DB 37 Read_vout7[15:8] 220 DC 36 Read_vout7[7:0] 221 DD 35 Status_mfr6 222 DE 34 Status_vout6 223 DF 33 Read_vout6[15:8] 224 E0 32 Read_vout6[7:0] 225 E1 31 Status_mfr5 226 E2 30 Status_vout5 227 E3 29 Read_vout5[15:8] 228 E4 28 Read_vout5[7:0] 229 E5 27 Status_mfr4 230 E6 26 Status_vout4 231 E7 25 Read_vout4[15:8] 232 E8 24 Read_vout4[7:0] 233 E9 23 Reserved 234 EA 22 Status_temp 235 EB 21 Read_temperature_ 1[15:8] 236 EC 20 Read_temperature_ 1[7:0] 237 ED 19 Status_mfr3 40 BYTES PER LOOP 40 BYTES PER LOOP 238 EE 0x00 239 EF 0x00 240 F0 0x00 241 F1 0x00 242 F2 0x00 243 F3 0x00 244 F4 0x00 245 F5 0x00 246 F6 0x00 247 F7 0x00 248 F8 0x00 249 F9 0x00 250 FA 0x00 251 FB 0x00 252 FC 0x00 253 FD 0x00 254 FE 0x00 Bytes EE - FE Return 0x00 But Must Be Read Use One Block Read Command to Read 255 Bytes Total, from 0x00 to 0xFE Last Valid Fault Log Byte 2978fc 61 LTC2978 APPLICATIONS INFORMATION OVERVIEW The LTC2978 is a power management IC that is capable of sequencing, margining, trimming, supervising output voltage for OV/UV conditions, providing fault management, and voltage read back for eight DC/DC converters. Input voltage and LTC2978 junction temperature read back are also available. Odd numbered channels can be configured to read back sense resistor voltages. Multiple LTC2978s can be synchronized to operate in unison using the SHARE_CLK, FAULTB and CONTROL pins. The LTC2978 utilizes a PMBus compliant interface and command set. POWERING THE LTC2978 The LTC2978 can be powered two ways. The first method requires that a voltage between 4.5V and 15V be applied to the VPWR pin. See Figure 14. An internal linear regula- tor converts VPWR down to 3.3V which drives all of the internal circuitry of the LTC2978. Alternatively, power from an external 3.3V supply may be applied directly to the VDD33 pins 16 and 17 using a voltage between 3.13V and 3.47V. Tie VPWR to VDD33 pins. See Figure 15. All functionality is available when using this alternate power method. The higher voltages needed for the VOUT_EN[0:3] pins and bias for the VSENSE pins are charge pumped from VDD33. SETTING COMMAND REGISTER VALUES The command register settings described herein are for the purpose of understanding and software development in a host processor. In actual practice, the LTC2978 can be completely configured for standalone operation with the LTC USB to I2C/SMBus/PMBus controller and software GUI using intuitive menu driven objects. 4.5V < VPWR < 15V 0.1µF 0.1µF VPWR SEQUENCE, SERVO, MARGIN AND RESTART OPERATIONS VIN_SNS VDD33 VDD33 VDD25 Command Units On or Off LTC2978 0.1µF GND 2978 F14 *SOME DETAILS OMITTED FOR CLARITY Figure 14. Powering LT2978 Directly from an Intermediate Bus EXTERNAL 3.3V 0.1µF Some examples of typical ON/OFF configurations are: VPWR VDD33 VDD33 1. A DC/DC converter may be configured to turn on anytime VIN exceeds VIN_ON. LTC2978 VDD25 0.1µF Three control parameters determine how a particular channel is turned on and off. The CONTROL pins, the OPERATION command and the value of the input voltage measured at the VIN_SNS pin (VIN). In all cases, VIN must exceed VIN_ON in order to enable a start. When VIN drops below VIN_OFF an immediate OFF of all channels will result. Refer to the OPERATION section in the data sheet for a detailed description of the ON_OFF_CONFIG command. GND 2978 F15 *SOME DETAILS OMITTED FOR CLARITY Figure 15. Powering LTC2978 from External 3.3V Supply 2. A DC/DC converter may be configured to turn on only when it receives an OPERATION command. 3. A DC/DC converter may be configured to turn on only via the CONTROL pin. 4. A DC/DC converter may be configured to turn on only when it receives an OPERATION command and the CONTROL pin is asserted. 2978fc 62 LTC2978 APPLICATIONS INFORMATION On Sequencing The TON_DELAY command sets the amount of time that a channel will wait following the start of an ON sequence before its VOUT_EN pin will enable a DC/DC converter. Once the DC/DC converter has been enabled, the TON_RISE command determines the amount of time the LTC2978 waits before soft connecting the VDACPn output and servoing the DC/DC converter output to VOUT_COMMAND. The TON_MAX_FAULT_LIMIT command determines the amount of time after the DC/DC converter has been enabled that an undervoltage condition will be tolerated before a fault occurs. If a TON_MAX_FAULT occurs, the channel can be configured to disable the DC/DC converter and propagate the fault to other channels using the bidirectional FAULTB pins. Figure 16 shows a typical on-sequence using the CONTROL pin. On State Operation Once a channel has reached the ON state, the OPERATION command can be used to command the DC/DC converter’s output to margin high, margin low, or return to a nominal output voltage indicated by VOUT_COMMAND. The user also has the option of configuring a channel to continuously trim the output of the DC/DC converter to the VOUT_COMMAND voltage, or the channel’s VDACPn output can be placed in a high impedance state thus allowing the DC/DC converter output voltage to go to its nominal value, VDCn (NOM). Refer VCONTROL VOUT_EN VOUT_0V_FAULT_LIMIT DAC SOFT-CONNECTS AND BEGINS ADJUSTING OUTPUT VOUT_COMMAND VOUT_UV_FAULT_LIMIT 2978 F16 TON_DELAY Servo Modes The ADC, DAC and internal processor comprise a digital servo loop that can be configured to operate in several useful modes. The servo target refers to the desired output voltage. Continuous/noncontinuous trim mode. MFR_CONFIG_ LTC2978 b[7]. In continuous trim mode, the servo will update the DAC in a closed loop fashion each time it takes a VOUT reading. The update rate is determined by the time it takes to step through the ADC MUX which is typically 100ms. See Electrical Characteristics Table Note 6. In noncontinuous trim mode, the servo will drive the DAC until the ADC measures the output voltage desired and then stop updating the DAC. Noncontinuous servo on warn mode. MFR_CONFIG_ LTC2978 b[7] = 0, b[6] = 1. When in noncontinuous mode, the LTC2978 can additionally retrim (reservo) the output if the output drifts beyond the OV or UV warn limits. DAC Modes The DACs that drive the VDACn pins can operate in several useful modes. See MFR_CONFIG_LTC2978. • Soft connect. Using the LTC patented soft connect feature, the DAC output is driven to within 1 LSB of the voltage at the DC/DC's feedback node before connecting to avoid introducing transients on the output. This mode is used when servoing the output voltage. During start-up, the LTC2978 waits until TON_RISE has expired before connecting the DAC. This is the most common operating mode. • Disconnected. DAC output is high Z. VDC(NOM) VOUT to the MFR_CONFIG_LTC2978 command for details on how to configure the output voltage servo. TON_RISE TON_MAX_FAULT_LIMIT • DAC manual with soft connect. Non servo mode. The DAC soft connects to the feedback node . The DAC code is driven to match the voltage at the feedback node. After connection, the DAC is moved by writing DAC codes to the device. Figure 16. Typical On Sequence Using Control Pin 2978fc 63 LTC2978 APPLICATIONS INFORMATION • DAC manual with hard connect. Non servo mode. The DAC hard connects to the feedback node at the value in MFR_DAC. After connection, the DAC is moved by writing DAC codes to the device. Margining The LTC2978 margins and trims the output of a DC/DC converter by driving current into or out of the feedback node or the trim pin. Preset limits for margining are stored in the VOUT_MARGIN_HIGH/LOW registers. Margining is actuated by writing the appropriate bits to the OPERATION register. Margining requires the DAC to be connected. Margin requests that occur when the DAC is disconnected will force the DAC to soft connect. When in the margin high/ low state, the DAC cannot be disconnected. The DAC can only be disconnected from the ON state. Off Sequencing An off sequence is initiated using the CONTROL pin or the OPERATION command. The TOFF_DELAY command determines the amount of time that elapses from the beginning of the off sequence until each channel’s VOUT_EN pin is pulled low thus disabling its DC/DC converter. VOUT Off Threshold Voltage The MFR_VOUT_DISCHARGE_THRESHOLD command register allows the user to specify the OFF threshold that the output voltage must decay below before the channel can enter/re-enter the ON state. The OFF threshold voltage is specified by multiplying MFR_VOUT_DISCHARGE_ THRESHOLD and VOUT_COMMAND. In the event that an output voltage has not decayed below its OFF threshold before attempting to enter the ON state, the channel will continue to be held off, the appropriate bit is set in the STATUS_MFR_SPECIFIC register, and the ALERTB pin will be asserted low. When the output voltage has decayed below its OFF threshold, the channel can enter the ON state. Automatic Restart Via MFR_RESTART_DELAY Command and CONTROLn pin An automatic restart sequence can be initiated by driving the CONTROL pin to the off state for >10μs then releasing it. The automatic restart disables all VOUT_EN pins that are mapped to a particular CONTROL pin for a time period = MFR_RESTART_DELAY and then starts all DC-DC Converters according to their respective TON_DELAYs. (see Figure 17). VOUT_ENn pins are mapped to one of the CONTROL pins by the MFR_CONFIG_LTC2978 command. This feature allows a host that is about to reset to restart the power in a controlled manner after it has recovered. CONTROL PIN BOUNCE VCONTROL VOUT_END 2978 F17 TOFF_DELAY0 MFR_RESTART_DELAY TON_DELAY0 Figure 17. Off Sequence with Automatic Restart FAULT MANAGEMENT Output Overvoltage and Undervoltage Faults The high speed voltage supervisor OV and UV fault thresholds are configured using the VOUT_OV_FAULT_LIMIT and VOUT_UV_FAULT_LIMIT commands, respectively. The VOUT_OV_FAULT_RESPONSE and VOUT_UV_FAULT_RESPONSE commands determine the responses to OV/ UV faults. Fault responses can range from disabling the DC/DC converter immediately, waiting to see if the fault condition persists for some interval before disabling the DC/DC converter, or allowing the DC/DC converter to continue operating in spite of the fault. If a DC/DC converter is disabled, the LTC2978 can be configured to retry or latch-off. The retry interval is specified using the 2978fc 64 LTC2978 APPLICATIONS INFORMATION MFR_RETRY_DELAY command. Latched faults are reset by toggling the CONTROL pin, using the OPERATION command, or removing and reapplying the bias voltage to the VIN_SNS pin. All fault and warning conditions result in the ALERTB pin being asserted low and the corresponding bits being set in the status registers. The CLEAR_FAULTS command resets the contents of the status registers and deasserts the ALERTB output. Output Overvoltage and Undervoltage Warnings OV and UV warning threshold voltages are processed by the LTC2978’s ADC. These thresholds are set by the VOUT_OV_WARN_LIMIT and VOUT_UV_WARN_LIMIT commands respectively. If a warning occurs, the corresponding bits are set in the status registers and the ALERTB output is asserted low. Note that a warning will never cause a VOUT_EN output pin to disable a DC/DC converter. RSENSE 0.007Ω VIN <15V Configuring the VIN_EN Output The VIN_EN output may be used to disable the intermediate bus voltage in the event of an output OV or UV fault. Use the MFR_VINEN_OV_FAULT_RESPONSE and MFR_VINEN_UV_FAULT_RESPONSE registers to configure the VIN_EN pin to assert low in response to VOUT_OV/ UV fault conditions. The VIN_EN output will stop pulling low when the LTC2978 is commanded to re-enter the ON state following a faulted-off condition. A charge-pumped 5µA pull-up to 12V is also available on the VIN_EN output. Refer to the MFR_CONFIG_ALL_LTC2978 register description in the OPERATION section for more information. Figure 18 shows an application circuit where the VIN_EN output is used to trigger a SCR crowbar on the intermediate bus in order to protect the DC/DC converter’s load from a catastrophic fault such as a stuck top gate. Q1 Si4894BDY VIN CBYPASS VIN_SNS VPWR VCC GATE LTC4210-3 24.3k 10k SENSE ON TIMER GND 100Ω LTC2978* LOAD VFB VDACM0 0.01µF 0.22µF VSENSEM0 SGND VOUT_EN0 RUN/SS GND 10k 2907 4.99k DC/DC CONVERTER VSENSEP0 0.1µF 68Ω 0.01µF VOUT VDACP0 2978 F18 MCR12DC 220Ω 0.1µF BAT54 REFP VIN_EN REFM VDD33 VDD33 VDD25 GND 0.1µF *SOME DETAILS OMITTED FOR CLARITY ONLY ONE OF EIGHT CHANNELS SHOWN 0.1µF Figure 18. LTC2978 Application Circuit with Crowbar Protection on Intermediate Bus 2978fc 65 LTC2978 APPLICATIONS INFORMATION Mfr_faultb00_response, page = 0 Mfr_faultb01_response, page = 0 CHANNEL 0 EVENT PROCESSOR PAGE = 0 Mfr_faultb00_response, page = 1 Mfr_faultb01_response, page = 1 CHANNEL 1 EVENT PROCESSOR PAGE = 1 Mfr_faultb00_response, page = 2 Mfr_faultb01_response, page = 2 CHANNEL 2 EVENT PROCESSOR PAGE = 2 Mfr_faultb00_response, page = 3 Mfr_faultb01_response, page = 3 CHANNEL 3 EVENT PROCESSOR PAGE = 3 Mfr_faultbz0_propagate_ch0 FAULTED_OFF Mfr_faultbz1_propagate_ch0 FAULTB00 Mfr_faultbz0_propagate_ch1 FAULTED_OFF Mfr_faultbz1_propagate_ch1 Mfr_faultbz0_propagate_ch2 FAULTED_OFF FAULTB01 Mfr_faultbz1_propagate_ch2 Mfr_faultbz0_propagate_ch3 FAULTED_OFF Mfr_faultbz1_propagate_ch3 ZONE 0 ZONE 0 ZONE 1 ZONE 1 Mfr_faultb10_response, page = 4 Mfr_faultb11_response, page = 4 CHANNEL 4 EVENT PROCESSOR PAGE = 4 Mfr_faultb10_response, page = 5 Mfr_faultb11_response, page = 5 CHANNEL 5 EVENT PROCESSOR PAGE = 5 Mfr_faultb10_response, page = 6 Mfr_faultb11_response, page = 6 CHANNEL 6 EVENT PROCESSOR PAGE = 6 Mfr_faultb10_response, page = 7 Mfr_faultb11_response, page = 7 CHANNEL 7 EVENT PROCESSOR PAGE = 7 Mfr_faultbz0_propagate_ch4 FAULTED_OFF Mfr_faultbz1_propagate_ch4 FAULTB10 Mfr_faultbz0_propagate_ch5 FAULTED_OFF Mfr_faultbz1_propagate_ch5 Mfr_faultbz0_propagate_ch6 FAULTED_OFF FAULTB11 Mfr_faultbz1_propagate_ch6 Mfr_faultbz0_propagate_ch7 FAULTED_OFF Mfr_faultbz1_propagate_ch7 2978 F19 Figure 19. Channel Fault Management Block Diagram 2978fc 66 LTC2978 APPLICATIONS INFORMATION Multichannel Fault Management • A FAULTBzn pin can also be asserted low by an external driver in order to initiate an immediate off-sequence after a 10µs deglitch delay. Multichannel fault management is handled using the bidirectional FAULTBzn pins. The “z” designates the fault zone which is either 0 or 1. There are two fault zones in the LTC2978. Each zone contains 4-channels. Figure 19 illustrates the connections between channels and the FAULTBzn pins. INTERCONNECT BETWEEN MULTIPLE LTC2978’S • The MFR_FAULTBz0_PROPAGATE command acts like a programmable switch that allows faulted-off conditions from a particular channel (PAGE) to propagate to either FAULTBzn output in that channel’s zone. The MFR_FAULTBzn_RESPONSE command controls similar switches on the inputs to each channel that allow any channel to shut down in response to any combination of the FAULTBzn pins within a zone. Channels responding to a FAULTBzn pin pulling low will attempt a new start sequence when the FAULTBzn pin in question is released by the faulted channel. • All VIN_SNS lines should be tied together in a star type connection at the point where VIN is to be sensed. This will minimize timing errors for the case where the ON_OFF_CONFIG is configured to start the LTC2978 based on VIN and ignore the CONTROL line and the OPERATION command. In multi-part applications that are sensitive to timing differences, it is recommended that the Vin_share_enable bit of the MFR_CONFIG_ALL register be set high in order to allow SHARE_CLK to synchronize on/off sequencing in response to the VIN_ON and VIN_OFF thresholds. • To establish dependencies across fault zones, tie the fault pins together, e.g., FAULTB01 to FAULTB10. Any channel can depend on any other. To disable all channels in response to any channel faulting off, short all the FAULTBzn pins together, and set MFR_FAULTBzn_ PROPAGATE = 0x01 and MFR_FAULTBzn_RESPONSE = 0x0F for all channels. • Connecting all VIN_EN lines together will allow selected faults on any DC/DC converter’s output in the array to shut off a common input switch. Figure 20 shows how to interconnect the pins in a typical multi-LTC2978 array. TO VIN OF DC/DCs TO HOST CONTROLLER LTC2978 N-1 VIN_SNS VIN_EN SDA SCL ALERTB CONTROL0 CONTROL1 WDI/RESETB FAULTB00 FAULTB01 FAULTB10 FAULTB11 SHARE_CLK PWRGD GND TO INPUT SWITCH LTC2978 N VIN_SNS VIN_EN SDA SCL ALERTB CONTROL0 CONTROL1 WDI/RESETB FAULTB00 FAULTB01 FAULTB10 FAULTB11 SHARE_CLK PWRGD GND TO OTHER LTC2978s–10k EQUIV PULL-UP RECOMMENDED ON EACH LINE EXCEPT SHARE_CLK (USE 5.49k) 2978 F20 Figure 20. Typical Connections Between Multiple LTC2978s 2978fc 67 LTC2978 APPLICATIONS INFORMATION • ALERTB is typically one line in an array of PMBus converters. The LTC2978 allows a rich combination of faults and warnings to be propagated to the ALERTB pin. • PWRGD reflects the status of the outputs that are mapped to it by the MFR_PWRGD_EN command. Figure 19 shows all the PWRGD pins connected together, but any combination may be used. Note that the latency of the PWRGD pin response may be in the range of 30ms to 185ms depending on ADC MUX settings. See Electrical Characteristics Table Note 6. • WDI/RESETB can be used to put the LTC2978 in the power-on reset state. Pull WDI/RESETB low for at least tRESETB to enter this state. A fast deassertion of PWRGD may be implemented by wire ANDing the VIN_EN pin with the PWRGD pin. When the UV fault threshold is crossed, VIN_EN will pull low if programmed to do so. See Figure 22. • The FAULTBzn lines can be connected together to create fault dependencies. Figure 20 shows a configuration where a fault on any FAULTBzn will pull all others low. This is useful for arrays where it is desired to abort a start-up sequence in the event any channel does not come up (see Figure 21). VCONTROLn VOUT0 VOUT1 VOUT2 VOUTn BUSSED VFAULTBzn PINS TON_DELAY0 TON_DELAY1 TON_DELAY2 • • • • • • TON_DELAYn 2978 F21 TON_MAX_FAULT1 Figure 21. Aborted On Sequence Due to Channel 1 Short VIN_EN 4.7k LTC2978 VDD33 PWRGD FAST PWRGD DEASSERT 2978 F22 Figure 22. PWRGD Deassert 2978fc 68 LTC2978 APPLICATIONS INFORMATION APPLICATION CIRCUITS Trimming and Margining DC/DC Converters with External Feedback Resistors Figure 23 shows a typical application circuit for trimming/ margining a power supply with an external feedback network. The VSENSEP0 and VSENSEM0 differential inputs sense the load voltage directly, and a correction voltage is developed between the VDACP0 and VDACM0 pins by the closed-loop servo algorithm. VDACM0 is Kelvin connected to the point-of-load GND in order to minimize the effects of load induced grounding errors. The VDACP0 output is connected to the DC/DC converter’s feedback node through resistor R30. For this configuration, set b[0] in MFR_CONFIG_LTC2978 = 0. Four-Step Resistor Selection Procedure for DC/DC Converters with External Feedback Resistors The following four-step procedure should be used to calculate the resistor values required for the application circuit shown in Figure 23. 1. Assume values for feedback resistor R20 and the nominal DC/DC converter output voltage VDC(NOM), and solve for R10. VDC(NOM) is the output voltage of the DC/DC converter when the LTC2978’s VDACP0 pin is in a high impedance state. R10 is a function of R20, VDC(NOM), the voltage at the feedback node (VFB) when the loop is in regulation, and the feedback node’s input current (IFB). R10 = R20 • VFB VDC(NOM) – IFB • R20 – VFB When VDACP0 is at 0V, the output of the DC/DC converter is at its maximum voltage. R30 ≤ R20 • VFB VDC(MAX) – VDC(NOM) (2) 3. Solve for the minimum value of VDACP0 that’s needed to yield the minimum required DC/DC converter output voltage VDC(MIN). The DAC has two full-scale settings, 1.38V and 2.65V. In order to select the appropriate full-scale setting, calculate the minimum required VDACP0(F/S) output voltage: ( ) VDACP0(F /S) > VDC(NOM) – VDC(MIN) • VIN 4.5V < VIBUS < 15V 0.1µF 2. Solve for the value of R30 that yields the maximum required DC/DC converter output voltage VDC(MAX). 0.1µF (1) R30 + VFB (3) R20 VIN VPWR VIN_SNS VOUT VDACP0 VDD33 VDD33 VDD25 R30 VSENSEP0 LTC2978* DC/DC CONVERTER VFB LOAD VDACM0 0.1µF R20 R10 VSENSEM0 SGND VOUT_EN0 RUN/SS GND 2978 F23 GND *SOME DETAILS OMITTED FOR CLARITY ONLY ONE OF EIGHT CHANNELS SHOWN Figure 23. Application Circuit for DC/DC Converters with External Feedback Resistors 2978fc 69 LTC2978 APPLICATIONS INFORMATION 4. Recalculate the minimum, nominal, and maximum DC/DC converter output voltages and the resulting margining resolution. R20 VDC(NOM) = VFB • 1+ + I • R20 R10 FB R20 • VDACP0(F /S) – VFB R30 R20 VDC(MAX) = VDC(NOM) + • VFB R30 R20 • VDACP0(F /S) VRES = R30 V/DAC LSB 1024 VDC(MIN) = VDC(NOM) – ( ) relationships between these resistors and the ∆% change in the output voltage of the DC/DC converter are typically expressed as: RTRIM • 50 – RTRIM ΔDOWN % (4) RTRIM_DOWN = (5) RTRIM_UP = (6) V • (100 + Δ %) 50 DC UP RTRIM • – – 1 2 • V • Δ ΔUP % REF UP % Figure 24 illustrates a typical application circuit for trimming/margining the output voltage of a DC/DC converter with a TRIM Pin. The LTC2978’s VDACP0 pin connects to the TRIM pin through resistor R30, and the VDACM0 pin is connected to the converter’s point-of-load ground. For this configuration, set the DAC polarity bit Mfr_config_ dac_pol in MFR_CONFIG_LTC2978 to 1. Two-Step Resistor and DAC Full-Scale Voltage Selection Procedure for DC/DC Converters with a TRIM Pin DC/DC converters with a TRIM pin are typically margined high or low by connecting an external resistor between the TRIM pin and either the VSENSEP or VSENSEM pin. The 1. Solve for R30: The following two-step procedure should be used to calculate the resistor value for R30 and the required full-scale DAC voltage (refer to Figure 24). 50 – Δ DOWN % R30 ≤ RTRIM • ΔDOWN % VIN 4.5V < VIBUS < 15V 0.1µF (9) where RTRIM is the resistance looking into the TRIM pin, VREF is the TRIM pin’s open-circuit output voltage and VDC is the DC/DC converter’s nominal output voltage. ∆UP% and ∆DOWN% denote the percentage change in the converter’s output voltage when margining up or down, respectively. (7) Trimming and Margining DC/DC Converters with a TRIM Pin 0.1µF (8) (10) VIN VPWR VIN_SNS VDD33 VSENSEP0 R30 VDACP0 VDD33 VDD25 LTC2978* GND TRIM VSENSE+ LOAD VDACM0 0.1µF VOUT+ DC/DC CONVERTER VSENSEM0 VSENSE– VOUT_EN0 ON/OFFB GND 2978 F24 *SOME DETAILS OMITTED FOR CLARITY ONLY ONE OF EIGHT CHANNELS SHOWN Figure 24. Application Circuit for DC/DC Converters with Trim Pin 2978fc 70 LTC2978 APPLICATIONS INFORMATION 2. Calculate the maximum required output voltage for VDACP0: Δ % VDACP0 ≥ 1+ UP • V ΔDOWN % REF (11) Note: Not all DC/DC’s converters follow these trim equations especially newer bricks. Consult LTC Field Application Engineering. Measuring Current Odd numbered ADC channels may be used to measure supply current. Set the ADC to high resolution mode to configure for current measuring and improve sensitivity. Note that no OV or UV faults or warnings are reported in this mode, but telemetry is available from the READ_VOUT command using the 11-bit signed mantissa plus 5-bit signed exponent L11 data format. Set the MFR_CONFIG_LTC2978 bit b[9] = 1 in order to enable high res mode. The VOUT_EN pin will assert low in this mode and cannot be used to control a DC/DC converter. The VDACP output pin is also unavailable. Measuring Current with a Sense Resistor A circuit for measuring current with a sense resistor is shown in Figure 25. The balanced filter rejects both common mode and differential mode noise from the output of the DC/DC converter. The filter is placed directly across the sense resistor in series with the DC/DC converter’s inductor. Note that the current sense inputs must be limited to less than 6V with respect to ground. Select RCM and CCM such that the filter’s corner frequency is < 1/10 the DC/DC converter’s switching frequency. This will result in a current sense waveform that offers a good compromise between the voltage ripple and the delay through the filter. A value 1kΩ for RCM is suggested in order to minimize gain errors due to the current sense inputs’ internal resistance. Measuring Current with Inductor DCR Figure 26 shows the circuit for applications that require DCR current sense. A second order RC filter is required in these applications in order to minimize the ripple voltage seen at the current sense inputs. A value of 1kΩ is suggested for RCM1 and RCM2 in order to minimize gain errors due the current sense inputs’ internal resistance. CCM1 should be selected to provide cancellation of the zero created by the DCR and inductance, i.e. CCM1 = L/(DCR • RCM1). CCM2 should be selected to provide a second stage corner frequency at < 1/10 of the DC/DC converter’s switching frequency. In addition, CCM2 needs to be much smaller than CCM1 in order to prevent significant loading of the filter’s first stage. RCM CCM RCM L CCM RSNS VSENSEP1 LTC2978 VSENSEM1 2978 F25 LOAD CURRENT Figure 25. Sense Resistor Current Sensing Circuits RCM2 CCM1 CCM1 CCM2 RCM2 CCM2 VSENSEP1 LTC2978 VSENSEM1 2978 F26 RCM1 SWX0 RCM1 L DCR Figure 26. Sense Resistor Current Sensing Circuits 2978fc 71 LTC2978 APPLICATIONS INFORMATION Single Phase Design Example Measuring Multiphase Currents As a design example for a DCR current sense application, assume L = 2.2μH, DCR = 10mΩ, and FSW = 500kHz. For current sense applications with more than one phase, RC averaging may be employed. Figure 27 shows an example of this approach for a 3-phase system with DCR current sensing. The current sense waveforms are averaged together prior to being applied to the second stage of the filter consisting of RCM2 and CCM2. Because the RCM1 resistors for the three phases are in parallel, the value of RCM1 must be multiplied by the number of phases. Also note that since the DCRs are effectively in parallel, the value for IOUT_CAL_GAIN will be equal to the inductor’s DCR divided by the number of phases. Care should to be taken in the layout of the multiphase inductors to keep the PCB trace resistance from the DC side of each inductor to the summing node balanced in order to provide the most accurate results. Let RCM1 = 1kΩ and solve for CCM1: CCM1 ≥ 2.2µH = 220nF 10mΩ • 1kΩ Let RCM2 = 1kΩ. In order to get a second pole at FSW/10 = 50kHz: CCM2 ≅ 1 = 3.18nF 2π • 50kHz • 1kΩ Let CCM2 = 3.3nF. Note that since CCM2 is much less than CCM1 the loading effects of the second stage filter on the matched first stage are not significant. Consequently, the delay time constant through the filter for the current sense waveform will be approximately 3μs. Multiphase Design Example Using the same values for inductance and DCR from the previous design example, the value for RCM1 will be 3kΩ for a three phase DC/DC converter if CCM1 is left at 220nF. Similarly, the value for IOUT_CAL_GAIN will be DCR/3 = 3.33mΩ. SWX1 RCM1 RCM1 RCM1 L RCM2 CCM1 CCM2 ISENSEP LTC2978 DCR ISENSEM RCM1/3 DCR DCR L SWX2 TO LOAD 2978 F27 RCM2 CCM1 CCM2 L SWX3 Figure 27. Multiphase DCR Current Sensing Circuits 2978fc 72 LTC2978 APPLICATIONS INFORMATION Anti-aliasing Filter Considerations Noisy environments require an anti-aliasing filter on the input to the LTC2978’s ADC. The R-C circuit shown in Figure 28 is adequate for most situations. Keep R40 = R50 ≤ 200Ω to minimize ADC gain errors, and select a value for capacitors C10 and C20 that doesn’t add too much additional response time to the OV/UV supervisor, e.g. τ ≅ 10µs (R = 100Ω, C = 0.10µF). while the VSENSEP1 input is tied to the REFP pin which has a typical output voltage of 1.23V. The voltage divider should be configured in order to present about 0.5V to the voltage sense inputs when the negative supply reaches its POWER_GOOD_ON threshold so that the current flowing out of the VSENSEMn pin is minimized to ~1µA. The relationship between the POWER_GOOD_ON register value and the corresponding negative supply value can be expressed as: Sensing Negative Voltages Figure 29 shows the LTC2978 sensing a negative power supply (VEE). The R1/R2 resistor divider translates the negative supply voltage to the LTC2978s VSENSEM1 input R2 VEE = VREFP – (READ_VOUT) • + 1 – 1µA • R2 R1 Where READ_VOUT returns VSENSEP – VSENSEM VIN 4.5V < VIBUS < 15V 0.1µF 0.1µF VIN VPWR VIN_SNS VOUT VDACP0 VDD33 VSENSEP0 VDD33 LTC2978* VDD25 VSENSEM0 0.1µF C10 R40 C20 R50 R30 R20 VFB LOAD R10 VDACM0 SGND VOUT_EN0 GND DC/DC CONVERTER *SOME DETAILS OMITTED FOR CLARITY ONLY ONE OF EIGHT CHANNELS SHOWN RUN/SS GND 2978 F28 Figure 28. Antialiasing Filter on VSENSE Lines 4.5V < VIBUS < 15V VIN_SNS VPWR LTC2978 REFP 1.23V TYP 0.1µF SDA PMBus INTERFACE SCL ALERTB CONTROL REFM VSENSEP1 1µA AT 0.5V VEE = –12V FAULTB SHARE_CLK PWRGD ASEL1 WP GND R1 = 4.99k R2 = 120k WDI/RESETB ASEL0 0.1µF VSENSEM1 WDI/RESETB POWER_GOOD_ON = 0.5V FOR VEE POWER_GOOD = –11.414V WHERE VEE POWER_GOOD = ONLY ONE OF EIGHT CHANNELS SHOWN, SOME DETAILS OMITTED FOR CLARITY 2978 F29 Figure 29. Sensing Negative Voltages 2978fc 73 LTC2978 APPLICATIONS INFORMATION Connecting the USB to I2C/SMBus/PMBus Controller to the LTC2978 in System Figures 30 and 31 illustrate application schematics for powering, programming and communicating with one or more LTC2978's via the LTC I2C/SMBus/PMBus controller regardless of whether or not system power is present. The LTC USB to I2C/SMBus/PMBus Controller can be interfaced to LTC2978s on the user's board for programming, telemetry and system debug. The controller, when used in conjunction with LTpowerPlay software, provides a powerful way to debug an entire power system. Failures are quickly diagnosed using telemetry, fault status registers and the fault log. The final configuration can be quickly developed and stored to the LTC2978's EEPROM. Figure 30 shows the recommended schematic to use when the LTC2978 is powered by the system intermediate bus through its VPWR pin. REPEAT OUTLINED CIRCUIT FOR EVERY LTC2978 150k 4.5V TO 15V 49.9k VPWR 0.1µF ISOLATED 3.3V SCL LTC2978 VDD33 Si1303 VDD33 GND 0.1µF SDA VDD25 0.1µF TO LTC USB TO I2C/SMBUS/PMBUS CONTROLLER 10k 10k PIN CONNECTIONS OMITTED FOR CLARITY 5.49k SCL SDA SHARE_CLK TO/FROM OTHER LTC2978s WP GND 2978 F30 Figure 30. LTC Controller Connections When VPWR is Used 2978fc 74 LTC2978 APPLICATIONS INFORMATION node because this will interfere with bus communication in the absence of system power. Figure 31 shows the recommended schematic to use when the LTC2978 is powered by the system 3.3V through its VDD33 and VPWR pins. The LTC4212 ideal OR'ing circuit allows either the controller or system to power the LTC2978. The LTC controller's I2C/SMBus connections are optoisolated from the PC's USB. The 3.3V from the controller and the LTC2978's VDD33 pin can be paralleled because the LTC LDOs that generate these voltages can be backdriven and draw <10μA. The controller's 3.3V current limit is 100mA. Because of the controller's limited current sourcing capability, only the LTC2978s, their associated pull up resistors and the I2C/SMBus pull-up resistors should be powered from the ORed 3.3V supply. In addition, any device sharing I2C/SMBus bus connections with the LTC2978 should not have body diodes between the SDA/SCL pins and its VDD TP0101K-SSOT23 SYSTEM 3.3V LTC4412 VIN IDEAL DIODE 0R’d 3.3V 10k 10k LTC2978_3.3V 5.49k VDD33 0.1µF VDD33 SENSE GND GATE CTL STAT VPWR 0.1µF VDD25 LTC2978 PIN CONNECTIONS OMITTED FOR CLARITY ISOLATED 3.3V SCL SCL GND SDA SHARE_CLK SDA WP TO LTC USB TO I2C/SMBUS/PMBUS CONTROLLER GND TO/FROM OTHER LTC2978s 2978 F31 NOTE: LTC CONTROLLER I2C CONNECTIONS ARE OPTO-ISOLATED ISOLATED 3.3V FROM CONTROLLER CAN BE BACK DRIVEN AND WILL ONLY DRAW < 10µA ISOLATED 3.3V CURRENT LIMIT = 100mA Figure 31. LTC Controller Connections When LTC2978 Powered Directly from 3.3V 2978fc 75 LTC2978 APPLICATIONS INFORMATION LTpowerPlay: AN INTERACTIVE GUI FOR DIGITAL POWER LTpowerPlay is a powerful Windows based development environment that supports Linear Technology digital power ICs with EEPROM, including the LTC2978 octal digital power supply manager. The software supports a variety of different tasks. You can use LTpowerPlay to evaluate Linear Technology ICs by connecting to a demo board system. LTpowerPlay can also be used in an offline mode (with no hardware present) in order to build a multi-chip configuration file that can be saved and reloaded at a later time. LTpowerPlay provides unprecedented diagnostic and debug features. It becomes a valuable diagnostic tool during board bring-up to program or tweak the power management scheme in a system or to diagnose power issues when bringing up rails. LTpowerPlay utilizes Linear Technology's USB-to-I2C/SMBus/PMBus Controller to communicate with one of many potential targets, including the DC1540 demo board set, the DC1508 socketed programming board, or a customer target system. The software also provides an automatic update feature to keep the software current with the latest set of device drivers and documentation. A great deal of context sensitive help is available within LTpowerPlay along with several tutorial demos. Complete information is available at: www.linear.com/ltpowerplay 2978fc 76 LTC2978 APPLICATIONS INFORMATION PCB ASSEMBLY AND LAYOUT SUGGESTIONS The proposed stencil design enables out-gassing of the solder paste during reflow as well as regulating the finished solder thickness. Bypass Capacitor Placement The LTC2978 requires 0.1µF bypass capacitors between the VDD33 pins and GND, the VDD25 pin and GND, and the REFP pin and REFM pin. If the chip is being powered from the VPWR input, then that pin should also be bypassed to GND by a 0.1µF capacitor. In order to be effective, these capacitors should be made of high quality ceramic dielectric such as X5R or X7R and be placed as close to the chip as possible. Exposed Pad Stencil Design The LTC2978’s package is thermally and electrically efficient. This is enabled by the exposed die attach pad on the under side of the package which must be soldered down to the PCB or mother board substrate. It is a good practice to minimize the presence of voids within the exposed pad inter-connection. Total elimination of voids is difficult, but the design of the exposed pad stencil is key. Figure 32 shows a suggested screen print pattern. PC Board Layout Mechanical stress on a PC board and soldering-induced stress can cause the LTC2978’s reference voltage and voltage drift to shift. A simple way to reduce these stressrelated shifts is to mount the IC near the short edge of the PC board, or in a corner. The board edge acts as a stress boundary, or a region where the flexure of the board is minimal. Unused ADC Sense Inputs Connect all unused ADC sense inputs (VSENSEPn or VSENSEMn) to GND. In a system where the inputs are connected to removable cards and may be left floating in certain situations, connect the inputs to GND using 100k resistors. Place the 100k resistors before any filter components, as shown in Figure 33, to prevent loading of the filter. VSENSEP 100k LTC2978 VSENSEP 100k 2978 F33 Figure 33. Connecting Unused Inputs to GND 2978 F32 Figure 32. Suggested Screen Pattern for Die Attach Pad 2978fc 77 LTC2978 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UP Package 64-Lead Plastic QFN (9mm × 9mm) (Reference LTC DWG # 05-08-1705 Rev C) 0.70 ±0.05 7.15 ±0.05 7.50 REF 8.10 ±0.05 9.50 ±0.05 (4 SIDES) 7.15 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 9 .00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.10 TYP R = 0.115 TYP 63 64 0.40 ± 0.10 PIN 1 TOP MARK (SEE NOTE 5) 1 2 PIN 1 CHAMFER C = 0.35 7.50 REF (4-SIDES) 7.15 ± 0.10 7.15 ± 0.10 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE (UP64) QFN 0406 REV C 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD 2978fc 78 LTC2978 REVISION HISTORY (Revision history begins at Rev B) REV DATE DESCRIPTION PAGE NUMBER B 10/11 All sections revised C 3/12 Change MFR_CONFIG name to MFR_CONFIG_LTC2978 1 - 80 19, 23,42 Changed text “data log” to “fault log” under EEPROM Related Commands DATA_LOG Comments 23 Elaborated on ON_OFF_CONFIG command description 31 Added Unused ADC Sense Inputs section 77 Renumbered Figure 33 to Figure 34 80 2978fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 79 LTC2978 TYPICAL APPLICATION 0.1µF 41 5 VIN VOUT 44 46 R32 R22 DC/DC CONVERTER VFB LOAD 47 R12 45 RUN/SS SGND GND 6 50 48 49 51 IN ASEL0 VIN_SNS VPWR ASEL1 VDD33 WP GND REFP VDD25 VSENSEP7 VSENSEM7 VDACM0 VDACM7 VOUT_EN0 VOUT_EN7 VDACP1 VDACP6 VSENSEP1 VSENSEP6 VSENSEM1 VSENSEM6 VDACM1 VDACM6 VOUT_EN1 VOUT_EN6 LTC2978 VDACP2 VDACP5 VSENSEP2 VSENSEP5 VSENSEM2 VSENSEM5 VDACM2 VDACM5 VOUT_EN2 VOUT_EN5 VDACP3 VDACP4 VSENSEP3 VSENSEP4 VSENSEM3 VSENSEM4 VDACM3 VOUT_EN3 VIN_EN 7 VDACP7 VSENSEM0 OUT INTERMEDIATE BUS CONVERTER 14 12 EN 3.3V 23 24 25 26 21 27 28 29 30 31 20 VDACM4 WDI/RESETB 43 32 PWRGD 42 33 CONTROL1 40 15 CONTROL0 4 16 ALERTB RUN/SS SGND GND 17 SCL 38 18 SDA 37 19 SHARE_CLK LOAD R10 65 FAULTB11 VFB VSENSEP0 34 FAULTB10 R30 R20 DC/DC CONVERTER VDACP0 REFM 36 FAULTB01 39 35 FAULTB00 VOUT DNC 13 VIN 3.3V 0.1µF VDD33 0.1µF VOUT_EN4 VOUT 60 2 3 R37 R27 VIN DC/DC CONVERTER VFB LOAD R17 61 SGND RUN/SS GND 11 VOUT 59 64 1 R36 R26 VIN DC/DC CONVERTER VFB LOAD R16 58 SGND RUN/SS GND 10 VOUT 56 62 63 R35 R25 VIN DC/DC CONVERTER VFB LOAD R15 57 SGND RUN/SS GND 9 VOUT 55 52 53 54 R34 R24 VIN DC/DC CONVERTER VFB LOAD R14 SGND RUN/SS GND 8 2978 F34 22 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 5.49k 10k 3.3V TO/FROM OTHER LTC2974s, LTC2978s AND MICROCONTROLLER Figure 34. LTC2978 Application Circuit with 3.3V Chip Power RELATED PARTS PART NUMBER DESCRIPTION LTC2970 Dual I2C Power Supply Monitor and Margining Controller COMMENTS LTC2974 Quad Digital Power Supply Manager with EEPROM LTC3880 Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management Accurate Current Measurement and Supervision ® 2978fc 80 Linear Technology Corporation LT 0412 REV C • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2009