SCLS191B − FEBRUARY 1993 − REVISED APRIL 1996
D EPIC (Enhanced-Performance Implanted
D
D
D
D
CMOS) 2-µ Process
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC, TA = 25°C
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
A
B
QA
QB
QC
QD
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
QH
QG
QF
QE
CLR
CLK
SN54LV164 . . . FK PACKAGE
(TOP VIEW)
B
A
NC
VCC
QH
D
SN54LV164 . . . J OR W PACKAGE
SN74LV164 . . . D, DB, OR PW PACKAGE
(TOP VIEW)
QA
NC
QB
NC
QC
description
These 8-bit parallel-out serial shift registers are
designed for 2.7-V to 5.5-V VCC operation.
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
QG
NC
QF
NC
QE
QD
GND
NC
CLK
CLR
The ’LV164 feature AND-gated serial (A and B)
inputs and an asynchronous clear (CLR) input.
The gated serial inputs permit complete control
NC − No internal connection
over incoming data as a low at either input inhibits
entry of the new data and resets the first flip-flop
to the low level at the next clock pulse. A high-level
input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can
be changed while the clock is high or low, provided the minimum setup time requirements are met. Clocking
occurs on the low-to-high-level transition of the clock (CLK) input.
The SN74LV164 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LV164 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74LV164 is characterized for operation from −40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
!"#$%& "!&'& (
&)!*$'!& "#**%& ' !) +#,-"'!& '%. *!#" "!&)!*$ !
+%")"'!& +%* % %*$ !) %/' &*#$%& '&'* 0'**'&1.
*!#"!& +*!"%&2 !% &! &%"%'*-1 &"-#% %&2 !) '-+'*'$%%*.
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1
SCLS191B − FEBRUARY 1993 − REVISED APRIL 1996
FUNCTION TABLE
OUTPUTS
INPUTS
CLR
CLK
A
B
QA
L
X
X
X
L
QB . . . QH
L
L
H
L
X
X
QA0
QB0
QH0
H
↑
H
H
H
QAn
QGn
H
↑
L
X
L
QAn
QGn
H
↑
X
L
L
QAn
QGn
QA0, QB0, QH0 = the level of QA, QB, or QH, respectively,
before the indicated steady-state inputs conditions were
established
QAn, QGn = the level of QA or QG before the most recent
↑ transition of the clock: indicates a 1-bit shift
logic symbol†
SRG8
9
CLR
R
8
CLK
C1/
1
A
&
3
2
B
1D
4
5
6
10
11
12
13
QA
QB
QC
QD
QE
QF
QG
QH
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for D, DB, J, PW, and W packages.
logic diagram (positive logic)
CLK
A
B
CLR
8
C1
1
2
C1
C1
C1
C1
C1
C1
1D
1D
1D
1D
1D
1D
1D
R
R
R
R
R
R
R
R
9
3
QA
2
C1
1D
4
QB
5
6
QC
10
QD
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QE
11
QF
12
QG
13
QH
SCLS191B − FEBRUARY 1993 − REVISED APRIL 1996
typical clear, shift, and clear sequences
Serial Inputs
CLK
A
B
CLR
QA
QB
Outputs
QC
QD
QE
QF
QG
QH
Clear
Clear
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 3): D package . . . . . . . . . . . . . . . . . . . 1.25 W
DB or PW package . . . . . . . . . . . . . 0.5 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
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3
SCLS191B − FEBRUARY 1993 − REVISED APRIL 1996
recommended operating conditions (see Note 4)
SN54LV164
VCC
Supply voltage
MIN
MAX
MIN
MAX
2.7
5.5
2.7
5.5
VIH
High-level input voltage
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VIL
Low-level input voltage
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VI
VO
Input voltage
0
Output voltage
0
IOH
High-level output current
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
IOL
Low-level output current
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
SN74LV164
2
2
3.15
3.15
0.8
0.8
1.65
0
0
V
V
1.65
VCC
VCC
UNIT
VCC
VCC
−6
−6
−12
−12
6
6
12
12
V
V
V
mA
mA
0
100
0
100
ns/V
−55
125
−40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
VCC†
TEST CONDITIONS
IOH = −100 µA
IOH = −6 mA
MIN to MAX
IOH = −12 mA
IOL = 100 µA
4.5 V
3V
SN54LV164
MIN
TYP
II
VI = VCC or GND
ICC
VI = VCC or GND,
nICC
One input at VCC − 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
MAX
MIN
VCC − 0.2
2.4
3.6
3.6
MAX
0.2
0.2
0.4
0.4
4.5 V
0.55
0.55
3.6 V
±1
±1
5.5 V
±1
±1
3.6 V
20
20
5.5 V
20
20
3 V to 3.6 V
500
500
IO = 0
3.3 V
2.5
2.5
5V
3
3
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%2& +'% !) %3%-!+$%&. ('*'"%*" '' '& !%*
+%")"'!& '*% %2& 2!'-. %/' &*#$%& *%%*3% % *2 !
"'&2% !* "!&&#% %% +*!#" 0!# &!"%.
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•
UNIT
V
3V
† For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
4
TYP
VCC − 0.2
2.4
MIN to MAX
IOL = 6 mA
IOL = 12 mA
SN74LV164
V
µA
A
µA
A
µA
pF
SCLS191B − FEBRUARY 1993 − REVISED APRIL 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN54LV164
VCC = 5.5 V
± 0.5 V
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time, data before CLK↑
th
Hold time, data after CLK↑
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MIN
MAX
MIN
MAX
MIN
MAX
0
40
0
35
0
30
CLR low
14
16
18
CLK high or low
14
16
18
Data
8
10
12
CLR inactive
5
6
7
3
3
3
UNIT
MHz
ns
ns
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN74LV164
VCC = 5.5 V
± 0.5 V
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time, data before CLK↑
th
Hold time, data after CLK↑
MIN
MAX
0
40
VCC = 3.3 V
± 0.3 V
MIN
MAX
0
35
VCC = 2.7 V
MIN
MAX
0
30
CLR low
14
16
18
CLK high or low
14
16
18
Data
8
10
12
CLR inactive
5
6
7
3
3
3
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN54LV164
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5.5 V ± 0.5 V
MIN
TYP
MAX
fmax
40
VCC = 3.3 V ± 0.3 V
MIN
TYP
MAX
90
35
75
VCC = 2.7 V
MIN
MAX
30
UNIT
MHz
tpd
CLK
Q
10
20
14
26
32
ns
tPHL
CLR
Q
12
20
16
26
32
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN74LV164
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5.5 V ± 0.5 V
MIN
TYP
MAX
fmax
40
tpd
CLK
tPHL
CLR
VCC = 3.3 V ± 0.3 V
MIN
TYP
MAX
90
35
75
VCC = 2.7 V
MIN
MAX
30
UNIT
MHz
Q
10
20
14
26
32
ns
Q
12
20
16
26
32
ns
( &)!*$'!& "!&"%*& +*!#" & % )!*$'3% !*
%2& +'% !) %3%-!+$%&. ('*'"%*" '' '& !%*
+%")"'!& '*% %2& 2!'-. %/' &*#$%& *%%*3% % *2 !
"'&2% !* "!&&#% %% +*!#" 0!# &!"%.
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5
SCLS191B − FEBRUARY 1993 − REVISED APRIL 1996
operating characteristics, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
TYP
TYP
3.3 V
74
5V
75
f = 10 MHz
UNIT
pF
PARAMETER MEASUREMENT INFORMATION
S1
1 kΩ
From Output
Under Test
Vz
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
Vz
GND
1 kΩ
WAVEFORM
CONDITION
Vm
Vi
Vz
LOAD CIRCUIT
VCC = 4.5 V
to 5.5 V
0.5 × VCC
VCC
2 × VCC
VCC = 2.7 V
to 3.6 V
1.5 V
2.7 V
6V
Vi
Vm
Timing Input
0V
tw
tsu
Vi
Input
Vm
th
Vi
Vm
Vm
Data Input
Vm
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Vi
Vm
Input
0V
Vm
Vm
VOL
Output
tPLH
tPHL
Output
Waveform 2
S1 at GND
(see Note B)
VOH
Vm
0V
tPLZ
Output
Waveform 1
S1 at Vz
(see Note B)
VOH
Output
Vm
Vm
tPZL
tPHL
tPLH
Vi
Output
Control
Vm
Vm
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Vm
tPZH
0.5 × Vz
VOL + 0.3 V
VOL
tPHZ
Vm
VOH − 0.3 V
VOH
[0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
SN74LV164D
OBSOLETE
SOIC
D
14
TBD
Call TI
Call TI
SN74LV164DR
OBSOLETE
SOIC
D
14
TBD
Call TI
Call TI
SN74LV164PWLE
OBSOLETE
TSSOP
PW
14
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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