LM25101A, LM25101B, LM25101C www.ti.com SNVS859B – JULY 2012 – REVISED APRIL 2013 LM25101A/B/C 3A, 2A, and 1A 80V Half-Bridge Gate Drivers Check for Samples: LM25101A, LM25101B, LM25101C FEATURES PACKAGES • • • • • • • • 1 2 • • • • • • Independent high and low driver logic inputs Bootstrap supply voltage up to 100V DC Drives both a high-side and low-side NChannel MOSFETs Fast propagation times (25 ns typical) Drives 1000 pF load with 8 ns rise and fall times Excellent propagation delay matching (3 ns typical) Supply rail under-voltage lockout Low power consumption Pin compatible with HIP2100/HIP2101 TYPICAL APPLICATIONS • • • • • • • Motor controlled drivers Half and Full Bridge power converters Synchronous buck converters Two switch forward power converters Forward with Active Clamp converters 48V server power Solar DC/DC and DC/AC converters SOIC-8 SO Power Pad-8 WSON-8 (4 mm x 4 mm) WSON-10 (4 mm x 4 mm) MSOP Power Pad-8 DESCRIPTION The LM25101A/B/C High Voltage Gate Drivers are designed to drive both the high-side and the low-side N-Channel MOSFETs in a synchronous buck or a half-bridge configuration. The “A” versions provide a full 3A of gate drive while the “B” and “C” versions provide 2A and 1A respectively. The outputs are independently controlled with TTL input thresholds. An integrated high voltage diode is provided to charge the high-side gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing clean level transitions from the control logic to the high-side gate driver. Under-voltage lockout is provided on both the low-side and the high-side power rails. These devices are available in the standard SOIC-8 pin, SO Power Pad-8, WSON-8 (4 mm x 4 mm), WSON-10 (4 mm x 4 mm), and MSOP Power Pad-8 packages. SIMPLIFIED BLOCK DIAGRAM HB HO UVLO LEVEL SHIFT DRIVER HS HI VDD UVLO LI LO DRIVER VSS 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012–2013, Texas Instruments Incorporated LM25101A, LM25101B, LM25101C SNVS859B – JULY 2012 – REVISED APRIL 2013 www.ti.com Table 1. Input/Output Options Part Number Input Thresholds Peak Output Current LM25101A TTL 3A LM25101B TTL 2A LM25101C TTL 1A Connection Diagrams VDD 1 HB 2 8 LO 7 VSS VDD 1 HB 2 HO 3 HS 4 SOIC-8 HO 3 6 LI HS 4 5 HI SO Power Pad-8 8 LO 7 VSS 6 LI 5 HI Exposed Pad Connect to VSS VDD 1 8 LO HB 2 7 VSS HO 3 6 LI WSON-8 HS 4 5 HI VDD HB HO HS 2 Submit Documentation Feedback LO VDD 1 10 HB 2 9 VSS HO 3 8 LI HS 4 7 HI NC 5 6 NC WSON-10 LO MSOPPowerPad-8 VSS LI HI Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM25101A LM25101B LM25101C LM25101A, LM25101B, LM25101C www.ti.com SNVS859B – JULY 2012 – REVISED APRIL 2013 PIN DESCRIPTIONS (1) Pin # SOIC-8 SO Power Pad-8 WSON8 (1) WSON10 (1) MSOPPowerPad -8 (1) Name 1 1 1 1 1 VDD 2 2 2 2 2 3 3 3 3 4 4 4 5 5 6 (1) Description Application Information Positive gate drive supply Locally decouple to VSS using low ESR/ESL capacitor located as close to the IC as possible. HB High-side gate driver bootstrap rail Connect the positive terminal of the bootstrap capacitor to HB and the negative terminal to HS. The bootstrap capacitor should be placed as close to the IC as possible. 3 HO High-side gate driver output Connect to the gate of high-side MOSFET with a short, low inductance path. 4 4 HS High-side MOSFET source connection Connect to the bootstrap capacitor negative terminal and the source of the high-side MOSFET. 5 7 5 HI High-side driver control input The LM25101A/B/C inputs have TTL type thresholds. Unused inputs should be tied to ground and not left open. 6 6 8 6 LI Low-side driver control input The LM25101A/B/C inputs have TTL type thresholds. Unused inputs should be tied to ground and not left open. 7 7 7 9 7 VSS Ground return All signals are referenced to this ground. 8 8 8 10 8 LO Low-side gate driver output Connect to the gate of the low-side MOSFET with a short, low inductance path. EP EP EP EP EP (WSON and SO PowerPad and MSOPPowerPad packages) Solder to the ground plane under the IC to aid in heat dissipation. Note: For SO Power Pad - 8, WSON-8, WSON-10 and MSOP-PowerPad-8 package, it is recommended that the exposed pad on the bottom of the package is soldered to ground plane on the PC board, and that ground plane should extend out from beneath the IC to help dissipate heat. For WSON-10 package, pins 5 and 6 have no connection. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) VDD to VSS −0.3V to +18V HB to HS −0.3V to +18V −0.3V to VDD +0.3V LI or HI Input LO Output −0.3V to VDD +0.3V HO Output VHS −0.3V to VHB +0.3V HS to VSS (2) −5V to +100V HB to VSS 100V Junction Temperature +150°C −55°C to +150°C Storage Temperature Range ESD Rating, HBM (1) (2) (3) (3) 2 kV Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test conditions, see the Electrical Characteristics tables. In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally not exceed -1V. However, in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur, the HS voltage must never be more negative than VDD-15V. For example if VDD = 10V, the negative transients at HS must not exceed -5V. The Human Body Model (HBM) is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. 2 kV for all pins except Pin 2, Pin 3 and Pin 4 which are rated at 1000V for HBM. Machine Model (MM) rating is 100V. Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM25101A LM25101B LM25101C Submit Documentation Feedback 3 LM25101A, LM25101B, LM25101C SNVS859B – JULY 2012 – REVISED APRIL 2013 www.ti.com Recommended Operating Conditions VDD +9V to +14V HS −1V to 100V - VDD HB VHS +8V to VHS +14V HS Slew Rate < 50 V/ns −40°C to +125°C Junction Temperature Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO (1). Symbol Parameter Conditions Min Typ Max Unit 0.25 0.4 mA SUPPLY CURRENTS IDD VDD Quiescent Current, LM25101A/B/C LI = HI = 0V IDDO VDD Operating Current f = 500 kHz 2.0 3 mA IHB Total HB Quiescent Current LI = HI = 0V 0.06 0.2 mA IHBO Total HB Operating Current f = 500 kHz 1.6 3 mA IHBS HB to VSS Current, Quiescent HS = HB = 100V 0.1 10 µA IHBSO HB to VSS Current, Operating f = 500 kHz 0.4 mA INPUT PINS VIL Input Voltage Threshold LM25101A/B/C VIHYS Input Voltage Hysteresis LM25101A/B/C RI Input Pulldown Resistance Rising Edge 1.3 1.8 2.3 100 200 400 kΩ 6.0 6.9 7.4 V 50 V mV UNDER VOLTAGE PROTECTION VDDR VDD Rising Threshold VDDH VDD Threshold Hysteresis VHBR HB Rising Threshold VHBH HB Threshold Hysteresis (1) 4 0.5 5.7 6.6 0.4 V 7.1 V V Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM25101A LM25101B LM25101C LM25101A, LM25101B, LM25101C www.ti.com SNVS859B – JULY 2012 – REVISED APRIL 2013 Electrical Characteristics (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO (1). Symbol Parameter Conditions Min Typ Max Unit BOOT STRAP DIODE VDL Low-Current Forward Voltage IVDD-HB = 100 µA 0.52 0.85 V VDH High-Current Forward Voltage IVDD-HB = 100 mA 0.8 1 V RD Dynamic Resistance LM25101A/B/C IVDD-HB = 100 mA 1.0 1.65 Ω IHO = ILO = 100 mA 0.12 0.25 LO & HO GATE DRIVER VOL VOH Low-Level Output Voltage LM25101A Low-Level Output Voltage LM25101B 0.16 0.4 Low-Level Output Voltage LM25101C 0.28 0.65 0.24 0.45 0.28 0.60 0.60 1.10 High-Level Output Voltage LM25101A High-Level Output Voltage LM25101B High-Level Output Voltage LM25101C IOHL Peak Pullup Current LM25101A IHO = ILO = 100 mA VOH = VDD– LO or VOH = HB - HO HO, LO = 0V Peak Pullup Current LM25101B Peak Pulldown Current LM25101A V 3 2 Peak Pullup Current LM25101C IOLL V A 1 HO, LO = 12V 3 Peak Pulldown Current LM25101B 2 Peak Pulldown Current LM25101C 1 A THERMAL RESISTANCE θJA (2) Junction to Ambient (2) SOIC-8 170 SO power Pad-8 40 WSON-8 40 WSON-10 40 Msop Power Pad-8 80 °C/W The θJA is not a given constant for the package and depends on the printed circuit board design and the operating environment. Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM25101A LM25101B LM25101C Submit Documentation Feedback 5 LM25101A, LM25101B, LM25101C SNVS859B – JULY 2012 – REVISED APRIL 2013 www.ti.com Switching Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO (1). Symbol Parameter Conditions Min Typ Max Unit tLPHL LO Turn-Off Propagation Delay LI Falling to LO Falling 22 56 ns tLPLH LO Turn-On Propagation Delay LI Rising to LO Rising 26 56 ns tHPHL HO Turn-Off Propagation Delay HI Falling to HO Falling 22 56 ns tHPLH LO Turn-On Propagation Delay HI Rising to HO Rising 26 56 ns tMON Delay Matching: LO on & HO Off 4 10 ns tMOFF Delay Matching: LO on & HO Off 4 10 ns tRC, tFC Either Output Rise/Fall Time CL = 1000 pF tR Output Rise Time (3V to 9V) LM25101A CL = 0.1 µF tF 8 Output Rise Time (3V to 9V) LM25101B 570 Output Rise Time (3V to 9V) LM25101C 990 Output Fall Time (3V to 9V) LM25101A ns 430 CL = 0.1 µF ns 260 Output Fall Time (3V to 9V) LM25101B 430 Output Fall Time (3V to 9V) LM25101C 715 tPW Minimum input pulse duration that changes the output 50 ns tBS Bootstrap diode reverse recovery time 37 ns (1) 6 IF = 100 mA, IR = 100 mA ns Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM25101A LM25101B LM25101C LM25101A, LM25101B, LM25101C www.ti.com SNVS859B – JULY 2012 – REVISED APRIL 2013 Typical Performance Characteristics Peak Sourcing Current vs VDD Peak Sinking Current vs VDD 5.0 5.0 4.5 4.5 4.0 4.0 3.5 LM25101A 3.0 CURRENT (A) CURRENT (A) 3.5 2.5 LM25101B 2.0 1.5 1.0 2.5 LM25101B 2.0 1.5 1.0 LM25101C 0.5 0.0 LM25101A 3.0 LM25101C 0.5 7 8 9 10 11 12 13 14 0.0 15 7 8 9 10 11 12 VDD (V) Figure 1. Figure 2. Sink Current vs Output Voltage Source Current vs Output Voltage 3.5 2.5 VDD = 12V 2.5 LM25101A CURRENT (A) CURRENT (A) 15 3.0 3.0 2.0 LM25101B 1.5 1.0 LM25101A 2.0 LM25101B 1.5 1.0 LM25101C 0.5 LM25101C 0.5 0 2 4 8 6 10 0.0 12 0 2 4 8 6 10 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 3. Figure 4. LM25101A/B/C IDD vs Frequency Operating Current vs Temperature 100000 12 2.3 VDD = 12V 2.1 CL = 4400 pF IDDO 1.9 10000 CURRENT (mA) CURRENT (PA) 14 3.5 VDD = 12V 0.0 13 VDD (V) CL = 1000 pF 1000 1.7 IHBO 1.5 1.3 1.1 CL = 0 pF 0.9 100 0.1 1 10 100 1000 0.7 -50 -25 FREQUENCY (kHz) Figure 5. Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM25101A LM25101B LM25101C 0 25 50 75 100 125 150 TEMPERATURE (oC) Figure 6. Submit Documentation Feedback 7 LM25101A, LM25101B, LM25101C SNVS859B – JULY 2012 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) IHB vs Frequency Quiescent Current vs Supply Voltage 100000 400 HB = 12V, HS = 0V 350 CL = 4400 pF IDD 300 CL = 1000 pF 1000 CL = 0 pF 100 CURRENT (PA) CURRENT (PA) 10000 250 200 150 100 IHB 50 10 0.1 1 10 100 0 1000 9 10 11 12 13 14 15 16 VDD, VHB (V) Figure 7. Figure 8. Quiescent Current vs Temperature Undervoltage Rising Thresholds vs Temperature 350 7.30 7.20 300 7.10 IDD THRESHOLD (V) 250 CURRENT (PA) 8 FREQUENCY (kHz) 200 150 100 7.00 VDDR 6.90 6.80 6.70 6.60 VHBR 6.50 50 6.40 IHB 0 -50 -25 0 25 50 75 6.30 -50 -25 100 125 150 TEMPERATURE (°C) 50 75 100 125 150 Figure 10. Undervoltage Threshold Hysteresis vs Temperature Bootstrap Diode Forward Voltage 0.60 1.00E-01 T = 150°C 0.55 1.00E-02 VDDH 0.50 1.00E-03 ID (A) HYSTERESIS (V) 25 TEMPERATURE (°C) Figure 9. 0.45 VHBH 0.40 0.30 -50 T = 25°C 1.00E-04 T = -40°C 1.00E-05 0.35 -25 0_ 25 50_ 75_100_125_150_ 1.00E-06 0.2 0.3 o TEMPERATURE ( C) Submit Documentation Feedback 0.4 0.5 0.6 0.7 0.8 0.9 VD (V) Figure 11. 8 0 Figure 12. Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM25101A LM25101B LM25101C LM25101A, LM25101B, LM25101C www.ti.com SNVS859B – JULY 2012 – REVISED APRIL 2013 Typical Performance Characteristics (continued) LM25101A/B/C Input Threshold vs VDD 1.92 1.92 1.91 1.91 1.90 THRESHOLD VOLTAGE (V) THRESHOLD VOLTAGE (V) LM25101A/B/C Input Threshold vs Temperature Rising 1.89 1.88 1.87 1.86 Falling 1.85 1.84 1.83 1.82 1.90 Rising 1.89 1.88 1.87 1.86 1.85 Falling 1.84 1.83 1.82 1.81 1.81 1.80 1.80 -50 -25 0 25 50 8 75 100 125 150 9 10 11 TEMPERATURE (°C) 13 14 15 16 Figure 13. Figure 14. LM25101A/B/C Propagation Delay vs Temperature LO & HO Gate Drive - High Level Output Voltage vs Temperature 1.0 40 VDD = 12V 0.9 0.8 35 30 VOH (V) 0.7 DELAY (ns) 12 VDD (V) T_PLH 25 LM25101C 0.6 0.5 0.4 LM25101B 0.3 T_PHL LM25101A 0.2 20 0.1 15 -50 -25 0 25 50 0.0 -50 -25 75 100 125 150 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 15. Figure 16. LO & HO Gate Drive - Low Level Output Voltage vs Temperature LO & HO Gate Drive - Output High Voltage vs VDD 0.50 0.8 VDD = 12V IOUT = -100 mA 0.45 0.7 0.40 0.6 0.30 LM25101C LM25101C VOH (V) VOL (V) 0.35 0.25 LM25101B 0.20 0.15 LM25101A 0.10 0.4 0.3 LM25101B 0.2 0.05 0.00 -50 -25 0.5 0 25 50 75 100 125 150 0.1 LM25101A 7 8 TEMPERATURE (°C) Figure 17. Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM25101A LM25101B LM25101C 9 10 11 12 13 14 15 VDD (V) Figure 18. Submit Documentation Feedback 9 LM25101A, LM25101B, LM25101C SNVS859B – JULY 2012 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) LO & HO Gate Drive - Output Low Voltage vs VDD 0.35 IOUT = 100 mA VOL (V) 0.30 LM25101C 0.25 0.20 LM25101B 0.15 LM25101A 0.10 7 8 9 10 11 12 13 14 15 VDD (V) Figure 19. 10 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM25101A LM25101B LM25101C LM25101A, LM25101B, LM25101C www.ti.com SNVS859B – JULY 2012 – REVISED APRIL 2013 TIMING DIAGRAM LI LI HI tHPLH tLPLH HI tHPHL tLPHL LO LO HO HO tMON tMOFF Figure 20. Layout Considerations The optimum performance of high and low-side gate drivers cannot be achieved without taking due considerations during circuit board layout. Following points are emphasized. 1. Low ESR / ESL capacitors must be connected close to the IC, between VDD and VSS pins and between the HB and HS pins to support the high peak currents being drawn from VDD during turn-on of the external MOSFET. 2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be connected between MOSFET drain and ground (VSS). 3. In order to avoid large negative transients on the switch node (HS pin), the parasitic inductances in the source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized. 4. Grounding Considerations: (a) The first priority in designing grounding connections is to confine the high peak currents that charge and discharge the MOSFET gate into a minimal physical area. This will decrease the loop inductance and minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as possible to the gate driver. (b) The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground referenced bypass capacitor and low-side MOSFET body diode. The bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation. A recommended layout pattern for the driver is shown in Figure 21. If possible a single layer placement is preferred. Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM25101A LM25101B LM25101C Submit Documentation Feedback 11 LM25101A, LM25101B, LM25101C SNVS859B – JULY 2012 – REVISED APRIL 2013 www.ti.com Recommended Layout for Driver IC and Passives VDD LO HB VSS SO Power Pad-8 HO LI HI HS To Hi-Side FET D Multi Layer Option LO N G HO HS HO Single Layer Option To Low-Side FET Figure 21. Recommended Layout Pattern Power Dissipation Considerations The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate driver losses are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply voltage (VDD) and can be roughly calculated as: PDGATES = 2 • f • CL • VDD2 (1) There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and HO outputs. Figure 22 shows the measured gate driver power dissipation versus frequency and load capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the power losses driving the output loads and agrees well with Equation 1. This plot can be used to approximate the power losses due to the gate drivers. 1.000 CL = 4400 pF POWER (W) 0.100 CL = 1000 pF 0.010 CL = 0 pF 0.001 0.1 1.0 10.0 100.0 1000.0 SWITCHING FREQUENCY (kHz) Figure 22. Gate Driver Power Dissipation (LO + HO) VDD = 12V, Neglecting Diode Losses 12 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM25101A LM25101B LM25101C LM25101A, LM25101B, LM25101C www.ti.com SNVS859B – JULY 2012 – REVISED APRIL 2013 The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these events happens once per cycle, the diode power loss is proportional to frequency. Larger capacitive loads require more energy to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to the half bridge result in higher reverse recovery losses. Figure 23 was generated based on calculations and lab measurements of the diode recovery time and current under several operating conditions. This can be useful for approximating the diode power dissipation. The total IC power dissipation can be estimated from the previous plots by summing the gate drive losses with the bootstrap diode losses for the intended application. 0.100 POWER (W) CL = 4400 pF CL = 0 pF 0.010 0.001 1 10 100 1000 SWITCHING FREQUENCY (kHz) Figure 23. Diode Power Dissipation VIN = 50V Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM25101A LM25101B LM25101C Submit Documentation Feedback 13 LM25101A, LM25101B, LM25101C SNVS859B – JULY 2012 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Original (March 2013) to Revision A • 14 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 13 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM25101A LM25101B LM25101C PACKAGE OPTION ADDENDUM www.ti.com 15-Jun-2013 PACKAGING INFORMATION Orderable Device Status (1) LM25101AM/NOPB ACTIVE Package Type Package Pins Package Drawing Qty SOIC Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L25101 AM LM25101AMR/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 L25101 AMR LM25101AMRX/NOPB ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 L25101 AMR LM25101AMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L25101 AM LM25101ASD-1/NOPB ACTIVE WSON NGT 8 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 25101A1 LM25101ASD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 25101A LM25101ASDX-1/NOPB ACTIVE WSON NGT 8 4500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 25101A1 LM25101ASDX/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 25101A LM25101BMA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L25101 BMA LM25101BMAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L25101 BMA LM25101BSD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 25101B LM25101BSDX/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 25101B LM25101CMA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L25101 CMA LM25101CMAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L25101 CMA LM25101CMY/NOPB ACTIVE MSOPPowerPAD DGN 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 CMYN LM25101CMYE/NOPB ACTIVE MSOPPowerPAD DGN 8 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 CMYN LM25101CMYX/NOPB ACTIVE MSOPPowerPAD DGN 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 CMYN Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 15-Jun-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) LM25101CSD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 25101C LM25101CSDX/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 25101C (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 2 Samples PACKAGE MATERIALS INFORMATION www.ti.com 20-Jun-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device LM25101AMRX/NOPB Package Package Pins Type Drawing SO Power PAD SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM25101AMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM25101ASD-1/NOPB WSON NGT 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM25101ASD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM25101ASDX-1/NOPB WSON NGT 8 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM25101ASDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM25101BMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM25101BSD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM25101BSDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM25101CMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM25101CMY/NOPB MSOPPower PAD DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM25101CMYE/NOPB MSOPPower PAD DGN 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM25101CMYX/NOPB MSOPPower DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jun-2013 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PAD LM25101CSD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM25101CSDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM25101AMRX/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0 LM25101AMX/NOPB SOIC D 8 2500 349.0 337.0 45.0 LM25101ASD-1/NOPB WSON NGT 8 1000 210.0 185.0 35.0 LM25101ASD/NOPB WSON DPR 10 1000 210.0 185.0 35.0 LM25101ASDX-1/NOPB WSON NGT 8 4500 367.0 367.0 35.0 LM25101ASDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0 LM25101BMAX/NOPB SOIC D 8 2500 349.0 337.0 45.0 LM25101BSD/NOPB WSON DPR 10 1000 210.0 185.0 35.0 LM25101BSDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0 LM25101CMAX/NOPB SOIC D 8 2500 349.0 337.0 45.0 LM25101CMY/NOPB MSOP-PowerPAD DGN 8 1000 210.0 185.0 35.0 LM25101CMYE/NOPB MSOP-PowerPAD DGN 8 250 210.0 185.0 35.0 LM25101CMYX/NOPB MSOP-PowerPAD DGN 8 3500 367.0 367.0 35.0 LM25101CSD/NOPB WSON DPR 10 1000 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jun-2013 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM25101CSDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0 Pack Materials-Page 3 MECHANICAL DATA DGN0008A MUY08A (Rev A) BOTTOM VIEW www.ti.com MECHANICAL DATA DDA0008B MRA08B (Rev B) www.ti.com MECHANICAL DATA NGT0008A SDC08A (Rev A) www.ti.com MECHANICAL DATA DPR0010A SDC10A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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