LP3982 www.ti.com SNVS185D – FEBRUARY 2002 – REVISED APRIL 2013 LP3982 Micropower, Ultra Low-Dropout, Low-Noise, 300 mA CMOS Regulator Check for Samples: LP3982 FEATURES DESCRIPTION • • • • • • • • • • • The LP3982 low-dropout (LDO) CMOS linear regulator is available in 1.8V, 2.5V, 2.77V, 2.82V, 3.0V, 3.3V, and adjustable versions. They deliver 300 mA of output current. Packaged in an 8-Pin VSSOP, the LP3982 is pin and package compatible with Maxim's MAX8860. The LM3982 is also available in the small footprint WSON package. 1 2 • • MAX8860 Pin, Package and Spec. Compatible WSON Space Saving Package 300 mA Output Current 120 mV Typical Dropout @ 300 mA 90 μA Typical Quiescent Current 1 nA Typical Shutdown Mode 60 dB Typical PSRR 2.5V to 6V Input Range 120μs Typical Turn-on Time Stable with Small Ceramic Output Capacitors 37 μV RMS Output Voltage Noise (10 Hz to 100 kHz) Over-Temperature/Over-Current Protection ±2% Output Voltage Tolerance The LP3982 suits battery-powered applications because of its shutdown mode (1nA typ), low quiescent current (90 μA typ), and LDO voltage (120 mV typ). The low dropout voltage allows for more utilization of a battery’s available energy by operating closer to its end-of-life voltage. The LP3982's PMOS output transistor consumes relatively no drive current compared to PNP LDO regulators. This PMOS regulator is stable with small ceramic capacitive loads (2.2 μF typ). These devices also include regulation fault detection, a bandgap voltage reference, constant current limiting and thermal overload protection. APPLICATIONS • • • • Wireless Handsets DSP Core Power Battery Powered Electronics Portable Information Appliances Application Circuit VO VIN OUT IN 2.2PF 100k SHDN 2.2PF CERAMIC FAULT GND CC 33n F 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2013, Texas Instruments Incorporated LP3982 SNVS185D – FEBRUARY 2002 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) (3) −0.3V to 6.5V VIN, VOUT, VSHDN, VSET, VCC, VFAULT Fault Sink Current 20mA Power Dissipation See (4) −65°C to 160°C Storage Temperature Range Junction Temperature (TJ) 150°C Lead Temperature (10 sec.) Human Body Model ESD Rating (2) (3) 2kV Machine Model Thermal Resistance (θJA) (1) 260°C (5) 200V 8-Pin VSSOP 223°C/W See (4) 8-Pin WSON Absolute Maximum ratings indicate limits beyond which damage may occur. Electrical specifications do not apply when operating the device outside of its rated operating conditions. All voltages are with respect to the potential at the ground pin. If Military/Aerospace specified devices are required, please contact Texas Instruments Sales Office/Distributors for availability and specifications. TJ(MAX) - TA (4) (5) PD = TJA Maximum Power dissipation for the device is calculated using the following equations: where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance. For example, for the VSSOP8 package θJA = 223°C/W, TJ(MAX) = 150°C and using TA = 25°C; the maximum power dissipation is found to be 561 mW. The derating factor (−1/θJA) = −4.5 mW/°C, thus below 25°C the power dissipation figure can be increased by 4.5 mW per degree, and similarity decreased by this factor for temperatures above 25°C. The value of the θJA for the WSON package is specifically dependent on the PCB trace area, trace material, and the number of layers and thermal vias. For improved thermal resistance and power dissipation for the WSON package, refer to Application Note AN-1187 SNOA401. Human body model: 1.5 kΩ in series with 100 pF. RECOMMENDED OPERATING CONDITIONS (1) (2) −40°C to 85°C Temperature Range Supply Voltage (1) (2) 2.5V to 6.0V Absolute Maximum ratings indicate limits beyond which damage may occur. Electrical specifications do not apply when operating the device outside of its rated operating conditions. All voltages are with respect to the potential at the ground pin. ELECTRICAL CHARACTERISTICS Unless otherwise specified, all limits specified for VIN = VO +0.5V (1), VSHDN = VIN, CIN = COUT = 2.2μF, CCC = 33nF, TJ = 25°C. Boldface limits apply for the operating temperature extremes: −40°C and 85°C. Symbol Parameter VIN Input Voltage ΔVO Output Voltage Tolerance Conditions 100 μA ≤ IOUT ≤ 300 mA VIN = VO +0.5V (1) SET = OUT for the Adjust Versions Min (2) Max (2) Units 2.5 6.0 V −2 +2 −3 +3 6 VO Output Adjust Range Adjust Version Only 1.25 IO Maximum Output Current Average DC Current Rating 300 ILIMIT Output Current Limit IQ Supply Current Shutdown Supply Current (1) (2) (3) 2 330 Typ (3) (NOM) V mA 770 IOUT = 0mA 90 IOUT = 300 mA 225 VO = 0V, SHDN = GND % of VOUT 0.001 mA 270 1 μA μA Condition does not apply to input voltages below 2.5V since this is the minimum input operating voltage. All limits are verified by testing or statistical analysis. Typical Values represent the most likely parametric norm. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3982 LP3982 www.ti.com SNVS185D – FEBRUARY 2002 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise specified, all limits specified for VIN = VO +0.5V(1), VSHDN = VIN, CIN = COUT = 2.2μF, CCC = 33nF, TJ = 25°C. Boldface limits apply for the operating temperature extremes: −40°C and 85°C. Symbol VDO Parameter Dropout Voltage ΔVO en VSHDN Min (2) Conditions (1) (4) IOUT = 1 mA Typ (3) Max (2) Units 220 mV 0.4 IOUT = 200 mA 80 IOUT = 300 mA 120 Line Regulation IOUT = 1 mA, (VO + 0.5V) ≤ VI ≤ 6V (1) Load Regulation 100 μA ≤ IOUT ≤ 300 mA Output Voltage Noise IOUT = 10 mA, 10 Hz ≤ f ≤ 100 kHz 37 μVRMS Output Voltage Noise Density 10 Hz ≤ f ≤ 100 kHz, COUT = 10 μF 190 nV/√Hz SHDN Input Threshold VIH, (VO + 0.5V) ≤ VI ≤ 6V (1) −0.1 0.01 0.1 0.002 VIL, (VO + 0.5V) ≤ VI ≤ 6V %/V %/mA 2 (1) 0.4 V ISHDN SHDN Input Bias Current SHDN = GND or IN 0.1 100 nA ISET SET Input Leakage SET = 1.3V, Adjust Version Only (5) 0.1 2.5 nA mV (6) FAULTDetection Voltage VO ≥ 2.5V, IOUT = 200 mA FAULT Output Low Voltage ISINK = 2 mA IFAULT FAULT Off-Leakage Current FAULT = 3.6V, SHDN = 0V TSD Thermal Shutdown Temperature 160 Thermal Shutdown Hysteresis 10 VFAULT TON (4) (5) (6) COUT = 10 μF, VO at 90% of Final Value Start-Up Time 120 280 0.115 0.25 V 0.1 100 nA 120 °C μs Dropout voltage is measured by reducing VIN until VO drops 100mV from its nominal value at VIN -VO = 0.5V. Dropout Voltage does not apply to the 1.8 version. The SET pin is not externally connected for the fixed versions. The FAULT detection voltage is specified for the input to output voltage differential at which the FAULT pin goes active low. FUNCTIONAL BLOCK DIAGRAM VIN VO FAST START-UP CIRCUIT CURRENT LIMIT FAULT FAULT COMPARATORS R1 + SET - CC ERROR AMP OFF SHDN R2 THERMAL PROTECTION 1.25V BANDGAP GND Figure 1. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3982 3 LP3982 SNVS185D – FEBRUARY 2002 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified, VIN = VO + 0.5V, CIN = COUT = 2.2 μF, CCC = 33 nF, TJ = 25°C, VSHDN = VIN. Dropout Voltage vs. Load Current (For Different Output Voltages) Dropout Voltage vs. Load Current (For Different Output Temperatures) 160 140 VO = 2.77V 140 25°C DROPOUT VOLTAGE (mV) DROPOUT VOLTAGE (mV) 120 100 VO = 2.5V 80 VO = 3.3V 60 40 120 85°C 100 80 -40°C 60 40 20 20 0 0 0 50 100 200 150 250 300 0 100 150 200 Figure 2. Figure 3. FAULT Detect Threshold vs. Load Current 300 250 LOAD CURRENT (mA) Supply Current vs. Input Voltage 240 180 IL = 0mA 220 160 200 140 SUPPLY CURRENT (PA) FAULT DETECT THRESHOLD (mV) 50 LOAD CURRENT (mA) FAULT = HIGH 120 100 80 FAULT = LOW 60 40 180 TA = 85°C 160 TA = 25°C 140 120 100 80 60 TA = -40°C 40 20 20 0 0 0 50 100 150 200 250 300 0 LOAD CURRENT (mA) 1 2 3 4 5 6 INPUT VOLTAGE (V) Figure 4. Figure 5. Supply Current vs. Load Current Power Supply Rejection Ratio vs. Frequency 0 250 85°C 25°C -20 PSRR (dB) SUPPLY CURRENT (PA) -10 200 150 -40°C 100 -30 -40 -50 50 -60 0 0 50 250 200 150 100 LOAD CURRENT (mA) 300 -70 10 Figure 6. 4 10k 100 1k FREQUENCY (Hz) 100k Figure 7. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3982 LP3982 www.ti.com SNVS185D – FEBRUARY 2002 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified, VIN = VO + 0.5V, CIN = COUT = 2.2 μF, CCC = 33 nF, TJ = 25°C, VSHDN = VIN. Output Noise Spectral Density Output Noise (10Hz to 100kHz) 1 100 PV/DIV NOISE (PV/ Hz) 10 COUT = 10PF 0.1 COUT = 2.2PF 0.01 100 10 k FREQUENCY (Hz) 1k 1 ms/DIV 100k Figure 8. Figure 9. Output Impedance vs. Frequency Line Transient Response 2 VIN (V) 1.6 1.4 IL = 300mA 4.3V 3.3V 1.2 1 VO (10 mV/DIV) OUTPUT IMPEDANCE (:) 1.8 0.8 0.6 0.4 0.2 0 10 100 1k 10k 500 Ps/DIV 100k Figure 10. Figure 11. Load Transient Shutdown Response IL = 300mA 2 V/DIV 20 mV/DIV FREQUENCY (Hz) VOUT VSHDN 0V 1 V/DIV 100 mA/DIV VOUT IOUT 0V 500 Ps/DIV 500Ps/DIV Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3982 5 LP3982 SNVS185D – FEBRUARY 2002 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified, VIN = VO + 0.5V, CIN = COUT = 2.2 μF, CCC = 33 nF, TJ = 25°C, VSHDN = VIN. VIN 1 V/DIV VIN VO 2 V/DIV FAULT Power-Down Response 1 V/DIV 2 V/DIV Power-Up Response FAULT VIN VO VIN VO VO 5 ms/DIV 5 mS/DIV Figure 14. 6 Figure 15. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3982 LP3982 www.ti.com SNVS185D – FEBRUARY 2002 – REVISED APRIL 2013 APPLICATION INFORMATION General Information The LP3982 is package, pin and performance compatible with Maxim's MAX8860 excluding reverse battery protection and Dual Mode function (fixed and adjustable combined). Figure 16 shows the functional block diagram for the LP3982. A 1.25V bandgap reference, an error amplifier and a PMOS pass transistor perform voltage regulation while being supported by shutdown, fault, and the usual Temperature and current protection circuitry The regulator's topology is the classic type with negative feedback from the output to one of the inputs of the error amplifier. Feedback resistors R1 and R2 are either internal or external to the IC, depending on whether it is the fixed voltage version or the adjustable version. The negative feedback and high open loop gain of the error amplifier cause the two inputs of the error amplifier to be virtually equal in voltage. If the output voltage changes due to load changes, the error amplifier provides the appropriate drive to the pass transistor to maintain the error amplifier's inputs as virtually equal. In short, the error amplifier keeps the output voltage constant in order to keep its inputs equal. VIN VO FAST START-UP CIRCUIT CURRENT LIMIT FAULT R1 + SET - CC ERROR AMP OFF FAULT COMPARATORS SHDN R2 THERMAL PROTECTION 1.25V BANDGAP GND Figure 16. Functional Block Diagram for the LP3982 Output Voltage Setting (Adj Version Only) The output voltage is set according to the amount of negative feedback (Note that the pass transistor inverts the feedback signal.) Figure 17 simplifies the topology of the LP3982. This type of regulator can be represented as an op amp configured as non-inverting amplifier and a fixed DC Voltage (VREF) for its input signal. The special characteristic of this op amp is its extra-large output transistor that only sources current. In terms of its noninverting configuration, the output voltage equals VREF times the closed loop gain: VO = VREF R1 R2 +1 (1) Utilize the following equation for adjusting the output to a particular voltage: é V ù R1 = R2 ê O - 1ú ë1.25V û (2) Choose R2 = 100k to optimize accuracy, power supply rejection, noise and power consumption. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3982 7 LP3982 SNVS185D – FEBRUARY 2002 – REVISED APRIL 2013 www.ti.com VIN VREF + VOUT - R1 R2 Figure 17. Regulator Topology Simplified Similarity in the output capabilities exists between op amps and linear regulators. Just as rail-to-rail output op amps allow their output voltage to approach the supply voltage, low dropout regulators (LDOs) allow their output voltage to operate close to the input voltage. Both achieve this by the configuration of their output transistors. Standard op amps and regulator outputs are at the source (or emitter) of the output transistor. Rail-to-rail op amp and LDO regulator outputs are at the drain (or collector) of the output transistor. This replaces the threshold (or diode drop) limitations on the output with the less restrictive source-to-drain (or VSAT) limitations. There is a tradeoff, of course. The output impedance become significantly higher, thus providing a critically lower pole when combined with the capacitive load. That's why rail-to-rail op amps are usually poor at driving capacitive loads and recommend a series output resistor when doing so. LDOs require the same series resistance except that the internal resistance of the output capacitor will usually suffice. Refer to the Output Capacitance section for more information. Output Capacitance The LP3982 is specifically designed to employ ceramic output capacitors as low as 2.2 μF. Ceramic capacitors below 10μF offer significant cost and space savings, along with high frequency noise filtering. Higher values and other types and of capacitor may be used, but their equivalent series resistance (ESR) should be maintained below 0.5Ω Ceramic capacitor of the value required by the LP3982 are available in the following dielectric types: Z5U, Y5V, X5R and X7R. The Z5U and Y5V types exhibit a 50% or more drop in capacitance value as their temperature increases from 25°C, an important consideration. The X5R generally maintain their capacitance value within ±20%. The X7R type are desirable for their tighter tolerance of 10% over temperature. Ceramic capacitors pose a challenge because of their relatively low ESR. Like most other LDOs, the LP3982 relies on a zero in the frequency response to compensate against excessive phase shift in the regulator's feedback loop. If the phase shift reaches 360° (i.e.; becomes positive), the regulator will oscillate. This compensation usually resides in the zero generated by the combination of the output capacitor with its equivalent series resistance (ESR). The zero is intended to cancel the effects of the pole generated by the load capacitance (CL) combined with the parallel combination of the load resistance (RL) and the output resistance (RO) of the regulator. The challenge posed by low ESR capacitors is that the zero it generates can be too high in frequency for the pole that it's intended to compensate. The LP3982 overcomes this challenge by internally generating a strategically placed zero. 8 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3982 LP3982 www.ti.com SNVS185D – FEBRUARY 2002 – REVISED APRIL 2013 LOOP GAIN - RO VREF ESR + CL RL Figure 18. Simplified Model of Regulator Loop Gain Components Figure 18 shows a basic model for the linear regulator that helps describe what happens to the output signal as it is processed through its feedback loop; that is, describe its loop gain (LG). The LG includes two main transfer functions: the error amplifier and the load. The error amplifier provides voltage gain and a dominant pole, while the load provides a zero and a pole. The LG of the model in Figure 18 is described by the following equation: LG (jω) = AO ω 1+j ω POLE 1 + jω (ESR x CL) * 1 + jω ((ESR + RO // RL) CL) (3) The first term of the above equation expresses the voltage gain (numerator) and a single pole role-off (denominator) of the error amplifier. The second term expresses the zero (numerator) and pole (denominator) of the load in combination with the RO of the regulator. Figure 19 shows a Bode plot that represents a case where the zero contributed by the load is too high to cancel the effect of the pole contributed by the load and RO. The solid line illustrates the loop gain while the dashed line illustrates the corresponding phase shift. Notice that the phase shift at unity gain is a total 360° -the criteria for oscillation. ERROR AMP POLE: ZPOLE 0 dB LOOP PHASE SHIFT LOOP GAIN -180° LOAD POLE 1/(2S (ESR + RO // RL)CL) -360° LOAD ZERO 1/(2S (ESR x CL) Figure 19. Loop Gain Bode Plot Illustrating Inadequately High Zero for Stability Compensation The LP3982 generates an internal zero that makes up for the inadequately high zero of the low ESR ceramic output capacitor. This internally generated zero is strategically placed to provide positive phase shift near unity gain, thus providing a stable phase margin. No-Load Stability The LP3982 remains stable during no-load conditions, a necessary feature for CMOS RAM keep-alive applications. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3982 9 LP3982 SNVS185D – FEBRUARY 2002 – REVISED APRIL 2013 www.ti.com Input Capacitor The LP3982 requires a minimum input capacitance of about 1μF. The value may be increased indefinitely. The type is not critical to stability. However, instability may occur with bench set-ups where long supply leads are used, particularly at near dropout and high current conditions. This is attributed to the lead inductance coupling to the output through the gate oxide of the pass transistor; thus, forming a pseudo LCR network within the Loopgain. A 10 μF tantalum input capacitor remedies this non-situ condition; its larger ESR acts to dampen the pseudo LCR network. This may only be necessary for some bench setups. 1 μF ceramic input capacitor are fine for most end-use applications. If a tantalum input capacitor is intended for the final application, it is important to consider their tendency to fail in short circuit mode, thus potentially damaging the part. Noise Bypass Capacitor The noise bypass capacitor (CC) significantly reduces output noise of the LP3982. It connects between pin 6 and ground. The optimum value for CC is 33 nF. Pin 6 directly connects to the high impedance output of the bandgap. The DC leakage of the CC capacitor should be considered; loading down the reference will reduce the output voltage. NPO and COG ceramic capacitors typically offer very low leakage. Polypropylene and polycarbonate film carbonate capacitor offer even lower leakage currents. CC does not affect the transient response; however, it does affect turn-on time. The smaller the CC value, the quicker the turn-on time. Power Dissipation Power dissipation refers to the part's ability to radiate heat away from the silicon, with packaging being a key factor. A reasonable analogy is the packaging a human being might wear, a jacket for example. A jacket keeps a person comfortable on a cold day, but not so comfortable on a hot day. It would be even worse if the person was exerting power (exercising). This is because the jacket has resistance to heat flow to the outside ambient air, like the IC package has a thermal resistance from its junctions to the ambient (θJA). θJA has a unit of temperature per power and can be used to calculate the IC's junction temperature as follows: TJ = θJA • • • • (PD) + TA TJ is the junction temperature of the IC θJA is the thermal resistance from the junction to the ambient air outside the package PD is the power exerted by the IC TA is the ambient temperature (4) PD is calculated as follows: PD = IOUT (VIN -VO) • θJA for the LP3982 package (VSSOP-8) is 223°C/W with no forced air flow • 182°C/W with 225 linear feet per minute (LFPM) of air flow • 163°C/W with 500 LFPM of air flow • 149°C/W with 900 LFPM of air flow (5) θJA can also be decreased (improved) by considering the layout of the PC board: heavy traces (particularly at VIN and the two VOUT pins), large planes, through-holes, etc. Improvements and absolute measurements of the θJA can be estimated by utilizing the thermal shutdown circuitry that is internal to the IC. The thermal shutdown turns off the pass transistor of the device when its junction temperature reaches 160°C (Typical). The pass transistor doesn't turn on again until the junction temperature drops about 10°C (hysteresis). Using the thermal shutdown circuit to estimate , θJA can be done as follows: With a low input to output voltage differential, set the load current to 300 mA. Increase the input voltage until the thermal shutdown begins to cycle on and off. Then slowly decrease VIN (100 mV increments) until the part stays on. Record the resulting voltage differential (VD) and use it in the following equation: 10 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3982 LP3982 www.ti.com TJA SNVS185D – FEBRUARY 2002 – REVISED APRIL 2013 (160 - TA) (0.300 x VD) (6) Fault Detection The LP3982 provides a FAULT pin that goes low during out of regulation conditions like current limit and thermal shutdown, or when it approaches dropout. The latter monitors the input-to-output voltage differential and compares it against a threshold that is slightly above the dropout voltage. This threshold also tracks the dropout voltage as it varies with load current. Refer to Figure 4 in the typical characteristics section. The FAULT pin requires a pull-up resistor since it is an open-drain output. This resistor should be large in value to reduce energy drain. A 100 kΩ pull-up resistor works well for most applications. Figure 20 shows the LP3985 with delay added to the FAULT pin for the reset pin of a microprocessor. The output of the comparator stays low for a preset amount of time after the regulator comes out of a fault condition. VIN VO = 3V OUT IN LP3982 SHDN + FAULT CDELAY GND CC 0.1PF LMC7225 RESET - MICROPROCESSOR RP 100k Figure 20. Power on Delayed Reset Application The delay time for the application of Figure 20 is set as follows: CDELAY = -t RPln 1 - VREF VO (7) The application is set for a reset delay time of 8.8 ms. Note that the comparator should have high impedance inputs so as to not load down the VREF at the CC pin of the LP3982. Shutdown The LP3982 goes into sleep mode when the SHDN pin is in a logic low condition. During this condition, the pass transistor, error amplifier, and bandgap are turned off, reducing the supply current to 1 nA typical. The maximum voltage for a logic low at the SHDN pin is 0.4V. A minimum voltage of 2V at the SHDN pin will turn the LP3982 back on. The SHDN pin may be directly tied to VIN to keep the part on. The SHDN pin may exceed VIN but not the ABS MAX of 6.5V. Figure 21 shows an application that uses the SHDN pin. It detects when the battery is too low and disconnects the load by turning off the regulator. A micropower comparator (LMC7215) and reference (LM385) are combined with resistors to set the minimum battery voltage. At the minimum battery voltage, the comparator output goes low and tuns off the LP3982 and corresponding load. Hysteresis is added to the minimum battery threshold to prevent the battery's recovery voltage from falsely indicating an above minimum condition. When the load is disconnected from the battery, it automatically increases in terminal voltage because of the reduced IR drop across its internal resistance. The Minimum battery detector of Figure 21 has a low detection threshold (VLT) of 3.6V that corresponds to the minimum battery voltage. The upper threshold (VUT) is set for 4.6V in order to exceed the recovery voltage of the battery. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3982 11 LP3982 SNVS185D – FEBRUARY 2002 – REVISED APRIL 2013 www.ti.com VB OUT IN R1 768k R4 180k + 4 Cells NiMH R2 2.2PF 2.74M 100k 2.2PF CERAMIC VB LMC7215 FAULT SHDN GND R3 301k LP3982 VREF LM385A-1.2V Figure 21. Minimum Battery Detector that Disconnects the Load Via the SHDN Pin of the LP3982 Resistor value for VUT and VLT are determined as follows: GT = 1 + 1 + R2 R1 1 R3 VUT = R1 (VREF) GT VLT = R1 // R2 (VREF) GT (8) (The application of Figure 21 used a GT of 5μ mho) R1 = VUT1 VREF (GT) 1 R2 = VREF (GT) VLT (9) - 1 R1 (10) 1 R3 = GT - 1 1 + R2 R1 (11) The above procedure assumes a rail-to-rail output comparator. Essentially, R2 is in parallel with R1 prior to reaching the lower threshold, then R2 becomes parallel with R3 for the upper threshold. Note that the application requires rail-to-rail input as well. The resistor values shown in Figure 21 are the closest practical to calculated values. Fast Start-Up The LP3982 provides fast start-up time for better system efficiency. The start-up speed is maintained when using the optional noise bypass capacitor. An internal 500 μA current source charges the capacitor until it reaches about 90% of its final value. 12 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3982 LP3982 www.ti.com SNVS185D – FEBRUARY 2002 – REVISED APRIL 2013 Connection Diagram The set pin is internally disconnected for the fixed versions. 1 8 FAULT OUT IN 2 3 GND OUT 4 7 6 5 SHD N OUT 1 IN 2 8 FAULT 7 SHDN GND GND 3 6 CC OUT 4 5 SET CC SET * Figure 22. 8-Pin VSSOP Top View Figure 23. 8-Pin WSON Surface Mount Top View Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3982 13 LP3982 SNVS185D – FEBRUARY 2002 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision C (April 2013) to Revision D • 14 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 13 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3982 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP3982ILD-1.8 NRND WSON NGM 8 1000 TBD Call TI Call TI -40 to 85 LNB LP3982ILD-1.8/NOPB ACTIVE WSON NGM 8 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LNB LP3982ILD-2.5/NOPB ACTIVE WSON NGM 8 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LPB LP3982ILD-3.0/NOPB ACTIVE WSON NGM 8 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LTB LP3982ILD-3.3/NOPB ACTIVE WSON NGM 8 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LUB LP3982ILD-ADJ/NOPB ACTIVE WSON NGM 8 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LVB LP3982ILDX-1.8/NOPB ACTIVE WSON NGM 8 4500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LNB LP3982ILDX-3.0/NOPB ACTIVE WSON NGM 8 4500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LTB LP3982ILDX-3.3/NOPB ACTIVE WSON NGM 8 4500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LUB LP3982ILDX-ADJ/NOPB ACTIVE WSON NGM 8 4500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LVB LP3982IMM-1.8 NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 85 LENB LP3982IMM-1.8/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LENB LP3982IMM-2.5 NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 85 LEPB LP3982IMM-2.5/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LEPB LP3982IMM-3.0 NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 85 LETB LP3982IMM-3.0/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LETB LP3982IMM-3.3 NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 85 LEUB LP3982IMM-3.3/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LEUB LP3982IMM-ADJ NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 85 LEVB Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 1-Nov-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP3982IMM-ADJ/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LEVB LP3982IMMX-1.8/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LENB LP3982IMMX-2.5/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LEPB LP3982IMMX-2.82/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LESB LP3982IMMX-ADJ NRND VSSOP DGK 8 3500 TBD Call TI Call TI -40 to 85 LEVB LP3982IMMX-ADJ/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LEVB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP3982ILD-1.8 WSON NGM 8 1000 178.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP3982ILD-1.8/NOPB WSON NGM 8 1000 178.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP3982ILD-2.5/NOPB WSON NGM 8 1000 178.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP3982ILD-3.0/NOPB WSON NGM 8 1000 178.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP3982ILD-3.3/NOPB WSON NGM 8 1000 178.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP3982ILD-ADJ/NOPB WSON NGM 8 1000 178.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP3982ILDX-1.8/NOPB WSON NGM 8 4500 330.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP3982ILDX-3.0/NOPB WSON NGM 8 4500 330.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP3982ILDX-3.3/NOPB WSON NGM 8 4500 330.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP3982ILDX-ADJ/NOPB WSON NGM 8 4500 330.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LP3982IMM-1.8 VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3982IMM-1.8/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3982IMM-2.5 VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3982IMM-2.5/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3982IMM-3.0 VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3982IMM-3.0/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3982IMM-3.3 VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3982IMM-3.3/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP3982IMM-ADJ VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3982IMM-ADJ/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3982IMMX-1.8/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3982IMMX-2.5/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3982IMMX-2.82/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3982IMMX-ADJ/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP3982IMMX-ADJ *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP3982ILD-1.8 WSON NGM 8 1000 210.0 185.0 35.0 LP3982ILD-1.8/NOPB WSON NGM 8 1000 213.0 191.0 55.0 LP3982ILD-2.5/NOPB WSON NGM 8 1000 213.0 191.0 55.0 LP3982ILD-3.0/NOPB WSON NGM 8 1000 213.0 191.0 55.0 LP3982ILD-3.3/NOPB WSON NGM 8 1000 213.0 191.0 55.0 LP3982ILD-ADJ/NOPB WSON NGM 8 1000 213.0 191.0 55.0 LP3982ILDX-1.8/NOPB WSON NGM 8 4500 367.0 367.0 35.0 LP3982ILDX-3.0/NOPB WSON NGM 8 4500 367.0 367.0 35.0 LP3982ILDX-3.3/NOPB WSON NGM 8 4500 367.0 367.0 35.0 LP3982ILDX-ADJ/NOPB WSON NGM 8 4500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP3982IMM-1.8 VSSOP DGK 8 1000 210.0 185.0 35.0 LP3982IMM-1.8/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP3982IMM-2.5 VSSOP DGK 8 1000 210.0 185.0 35.0 LP3982IMM-2.5/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP3982IMM-3.0 VSSOP DGK 8 1000 210.0 185.0 35.0 LP3982IMM-3.0/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP3982IMM-3.3 VSSOP DGK 8 1000 210.0 185.0 35.0 LP3982IMM-3.3/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP3982IMM-ADJ VSSOP DGK 8 1000 210.0 185.0 35.0 LP3982IMM-ADJ/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP3982IMMX-1.8/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LP3982IMMX-2.5/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LP3982IMMX-2.82/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LP3982IMMX-ADJ VSSOP DGK 8 3500 367.0 367.0 35.0 LP3982IMMX-ADJ/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 3 MECHANICAL DATA NGM0008C LDA08C (Rev B) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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