UCC27200, UCC27201 www.ti.com ....................................................................................................................................... SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008 120-V Boot, 3-A Peak, High Frequency, High-Side/Low-Side Driver FEATURES 1 CONTENTS • Specified from -40 °C to 140 °C • Drives Two N-Channel MOSFETs in High-Side/Low-Side Configuration • Maximum Boot Voltage 120 V • Maximum VDD Voltage 20 V • On-Chip 0.65-V VF, 0.6-Ω RD Bootstrap Diode • Greater than 1 MHz of Operation • 20-ns Propagation Delay Times • 3-A Sink, 3-A Source Output Currents • 8-ns Rise/7-ns Fall Time with 1000-pF Load • 1-ns Delay Matching • Under Voltage Lockout for High-Side and Low-Side Driver 2 • • • • • • 2 Electrical Characteristics 4 Device Information 11 Application Information 14 Additional References 22 DESCRIPTION The UCC27200/1 family of high frequency N-Channel MOSFET drivers include a 120-V bootstrap diode and high-side/low-side driver with independent inputs for maximum control flexibility. This allows for N-Channel MOSFET control in half-bridge, full-bridge, two-switch forward and active clamp forward converters. The low-side and the high-side gate drivers are independently controlled and matched to 1-ns between the turn-on and turn-off of each other. APPLICATIONS • Device Ratings Power Supplies for Telecom, Datacom, and Merchant Markets Half-Bridge Applications and Full-Bridge Converters Isolated Bus Architecture Two-Switch Forward Converters Active-Clamp Forward Converters High Voltage Synchronous-Buck Converters Class-D Audio Amplifiers Simplified Application Diagram +12V +100V SECONDARY SIDE CIRCUIT V DD HB DRIVE HI LI CONTROL HI PWM CONTROLLER HO HS DRIVE LO LO UCC27200/1 VSS ISOLATION AND FEEDBACK 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPad is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2008, Texas Instruments Incorporated UCC27200, UCC27201 SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008 ....................................................................................................................................... www.ti.com DESCRIPTION (CONT.) An on-chip bootstrap diode eliminates the external discrete diodes. Under-voltage lockout is provided for both the high-side and the low-side drivers forcing the outputs low if the drive voltage is below the specified threshold. Two versions of the UCC27200 are offered. The UCC27200 has high noise immune CMOS input thresholds while the UCC27201 has TTL compatible thresholds. Both devices are offered in 8-pin SOIC (D), PowerPad™ SOIC-8 (DDA) and SON-8 (DRM) packages. ORDERING INFORMATION PACKAGED DEVICES (1) TEMPERATURE RANGE TA = TJ INPUT COMPATIBILITY SOIC-8 (D) (2) PowerPad™ SOIC-8 (DDA) (2) SON-8 (DRM) (3) CMOS UCC27200D UCC27200DDA UCC27200DRMT TTL UCC27201D UCC27201DDA UCC27201DRMT -40°C to +140°C (1) (2) (3) These products are packaged in Lead (Pb)-Free and green lead finish of PdNiAu which is compatible with MSL level 1 at 255-260°C peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations. D (SOIC-8) and DDA (Power Pad™ SOIC-8) packages are available taped and reeled. Add R suffix to device type (e.g. UCC27200DR) to order quantities of 2,500 devices per reel. DRM (SON-8) package comes either in a small reel of 250 pieces as part number UCC27200DRMT, or larger reels of 3000 pieces as part number UCC27200 DRMR. DEVICE RATINGS ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature, unless noted, all voltages are with respect to VSS (1) PARAMETER Supply voltage range, (2) VALUE VDD Input voltages on LI and HI, VLI, VHI Output voltage on LO, VLO Output voltage on HO, VHO Voltage on HS, VHS UNIT -0.3 to 20 -0.3 to 20 DC -0.3 to VDD + 0.3, Repetitive pulse <100 ns -2 to VDD + 0.3 DC VHS – 0.3 to VHB + 0.3 Repetitive pulse <100 ns VHS - 2 to VHB + 0.3, (VHB - VHS <20) DC -1 to 120 Repetitive pulse <100 ns -5 to 120 Voltage on HB, VHB -0.3 to 120 Voltage On HB-HS -0.3 to 20 Operating virtual junction temperature range, TJ -40 to +150 Storage temperature, TSTG -65 to +150 Lead temperature (soldering, 10 sec.) Power dissipation at TA = 25°C (D package) Power dissipation at TA = 25°C (DRM package) (2) (3) 2 °C +300 (3) 1.3 Power dissipation at TA = 25°C (DDA package) (3) (1) V 2.7 (3) W 3.3 Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to Vss. Currents are positive into, negative out of the specified terminal. This data was taken using the JEDEC proposed high-K test PCB. See THERMAL CHARACTERISTICS section for details. Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200 UCC27201 UCC27200, UCC27201 www.ti.com ....................................................................................................................................... SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) PARAMETER MIN NOM VHS Voltage on HS -1 105 Voltage on HS, (repetitive pulse <100 ns) -5 110 VHS + 8, VDD –1 VHS + 17, 115 -40 +140 Voltage on HB 12 UNIT Supply voltage range VHB 8 MAX VDD Voltage slew rate on HS TJ 17 V 50 Operating junction temperature range V / ns °C ELECTROSTATIC DISCHARGE (ESD) PROTECTION METHOD MIN Human body model 2000 CDM 1000 UNIT V THERMAL CHARACTERISTICS over operating free-air temperature range, maximum power dissipation at ambient temperature: PDISS = (150-TA) / θJA, (unless otherwise noted) PACKAGE θJA (°C/W)(Junction to Ambient) θJC (°C/W)( Junction to Case) θJP (°C/W) ( Junction to PowerPad™) D 95 71 NA (1) 46 71 4.8 DRM (2) 38 56 4.1 DDA (1) (2) Test board conditions: a. 3in x 3in, four4 layers, thickness: 0.062 in. b. 2-oz copper traces located on the top and bottom of the PCB. c. 2-oz copper ground planes on the internal 2 layers. d. Six thermal vias in the PowerPad™ area under the device package. Test board conditions: a. 3in x 3in, 4 layers, thickness: 0.062 in. b. 2-oz copper traces located on the top and bottom of the PCB. c. 2-oz copper ground planes on the internal 2 layers. d. Four thermal vias in the PowerPad™ area under the device package. Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200 UCC27201 Submit Documentation Feedback 3 UCC27200, UCC27201 SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008 ....................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range, VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO, TA = TJ = -40°C to +140°C, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply Currents IDD VDD quiescent current VLI = VHI = 0 0.4 0.8 UCC27200 f = 500 kHz, CLOAD = 0 2.5 4 UCC27201 IDDO VDD operating current f = 500 kHz, CLOAD = 0 3.8 5.5 IHB Boot voltage quiescent current VLI = VHI = 0 V 0.4 0.8 IHBO Boot voltage operating current f = 500 kHz, CLOAD = 0 2.5 4 IHBS HB to VSS quiescent current VHS = VHB = 110 V 0.0005 1 IHBSO HB to VSS operating current f = 500 kHz, CLOAD = 0 0.1 mA uA mA Input VHIT Input rising threshold VLIT Input falling threshold 5.8 VIHYS Input voltage hysteresis 0.4 VHIT Input voltage threshold 1.7 VLIT Input voltage threshold VIHYS Input voltage Hysteresis RIN Input pulldown resistance UCC27200 3 UCC27201 0.8 8 5.4 V 2.5 1.6 100 mV 100 200 350 6.2 7.1 7.8 kΩ Undervoltage Protection (UVLO) VDD rising threshold VDD threshold hysteresis 0.5 VHB rising threshold 5.8 VHB threshold hysteresis 6.7 7.2 V 0.4 Bootstrap Diode VF Low-current forward voltage I VDD - HB = 100 µA 0.65 0.85 VFI High-current forward voltage I VDD - HB = 100 mA 0.85 1.1 RD Dynamic resistance, ΔVF/ΔI I VDD - HB = 100 mA and 80 mA 0.6 1.0 ILO = 100 mA 0.18 0.4 TJ = -40 to 125°C ILO = -100 mA, VLOH = VDD VLO 0.25 0.4 TJ = -40 to 140°C ILO = -100 mA, VLOH = VDD VLO 0.25 0.42 V Ω LO Gate Driver VLOL VLOH Low level output voltage High level output voltage Peak pull-up current VLO = 0 V 3 Peak pull-down current VLO = 12 V 3 V A HO Gate Driver VHOL Low level output voltage VHOH High level output voltage IHO = 100 mA 0.18 0.4 TJ = -40 to 125°C IHO = -100 mA, VHOH = VHBVHO 0.25 0.4 TJ = -40 to 140°C IHO = -100 mA, VHOH = VHBVHO 0.25 0.42 Peak pull-up current VHO = 0 V 3 Peak pull-down current VHO = 12 V 3 V A Propagation Delays 4 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200 UCC27201 UCC27200, UCC27201 www.ti.com ....................................................................................................................................... SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO, TA = TJ = -40°C to +140°C, (unless otherwise noted) PARAMETER TDLFF TDHFF VLI falling to VLO falling VHI falling to VHO falling TDLRR VLI rising to VLO rising TDHRR VHI rising to VHO rising TYP MAX TJ = -40 to 125°C CLOAD = 0 TEST CONDITIONS MIN 20 45 TJ = -40 to 140°C CLOAD = 0 20 50 TJ = -40 to 125°C CLOAD = 0 20 45 TJ = -40 to 140°C CLOAD = 0 20 50 TJ = -40 to 125°C CLOAD = 0 20 45 TJ = -40 to 140°C CLOAD = 0 20 50 TJ = -40 to 125°C CLOAD = 0 20 45 TJ = -40 to 140°C CLOAD = 0 20 50 UNIT ns Delay Matching TMON LI ON, HI OFF 1 7 TMOFF LI OFF, HI ON 1 7 ns Output Rise and Fall Time tR LO, HO CLOAD = 1000 pF 8 tF LO, HO CLOAD = 1000 pF 7 tR LO, HO (3 V to 9 V) CLOAD = 0.1 µF 0.35 0.6 tF LO, HO (3 V to 9 V) CLOAD = 0.1 µF 0.3 0.6 IF = 20 mA, IREV = 0.5 A (1) (2) 20 ns us Miscellaneous Minimum input pulse width that changes the output Bootstrap diode turn-off time (1) (2) 50 ns Typical values for TA = 25°C IF: Forward current applied to bootstrap diode, IREV: Reverse current applied to bootstrap diode. Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200 UCC27201 Submit Documentation Feedback 5 UCC27200, UCC27201 SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008 ....................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS UCC27200 IDD OPERATING CURRENT vs FREQUENCY UCC27201 IDD OPERATING CURRENT vs FREQUENCY 10.0 10.0 VDD = 12 V No Load on Outputs VDD = 12 V No Load on Outputs 150oC IDDO - Operating Current - mA IDDO - Operating Current - mA 25oC 150oC 125oC 1.0 25oC o -40 C 0.1 125oC 1.0 -40oC 0.1 100 10 1000 100 10 Frequency - kHz Figure 1. Figure 2. BOOT VOLTAGE OPERATING CURRENT vs FREQUENCY HB TO VSS OPERATING CURRENT vs FREQUENCY 10.0 1.0 HB = 12 V No Load on Outputs IHBSO - Operating Current - mA HB = 12 V No Load on Outputs IHBO - Operating Current - mA 1000 Frequency - kHz 150oC o 125 C 1.0 25oC -40oC 0.1 150oC 0.01 25oC 125oC 0.1 -40oC 0.001 10 100 1000 100 10 Frequency - kHz Figure 3. 6 Submit Documentation Feedback 1000 Frequency - kHz Figure 4. Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200 UCC27201 UCC27200, UCC27201 www.ti.com ....................................................................................................................................... SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008 TYPICAL CHARACTERISTICS (continued) UCC27200 INPUT THRESHOLD vs SUPPLY VOLTAGE UCC27201 INPUT THRESHOLD vs SUPPLY VOLTAGE 2.0 T = 25oC T = 25oC HI, LI - Input Threshold Voltage - V HI, LI - Input Threshold Voltage/VDD Voltage - % 50 Rising 48 46 Falling 44 42 1.8 Rising Falling 1.6 1.4 1.2 1.0 40 8 10 12 14 16 18 8 20 10 VDD - Supply Voltage - V 18 16 Figure 5. Figure 6. UCC27200 INPUT THRESHOLD vs TEMPERATURE UCC27201 INPUT THRESHOLD vs TEMPERATURE 50 20 2.0 VDD = 12 V VDD = 12 V HI, LI - Input Threshold Voltage - V HI, LI - Input Threshold Voltage/VDD Voltage - % 14 12 VDD - Supply Voltage - V 48 Rising 46 Falling 44 42 40 1.8 Rising 1.6 Falling 1.4 1.2 1.0 -50 -25 0 25 50 75 100 125 150 -50 -25 TA - Temperature - oC Figure 7. 0 25 50 75 TA - Temperature - 100 125 150 oC Figure 8. Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200 UCC27201 Submit Documentation Feedback 7 UCC27200, UCC27201 SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008 ....................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) LO AND HO HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE LO AND HO LOW LEVEL OUTPUT VOLTAGE vs TEMPERATURE 0.45 0.45 VDD = VHB = 16 V ILO = IHO = -100 mA 0.35 VDD = VHB = 12 V 0.30 VDD = VHB = 8 V 0.25 0.20 0.15 0.10 ILO = IHO = 100 mA 0.40 VOL - LO/HO Output Voltage - V VOH - LO/HO Output Voltage - V 0.40 VDD = VHB = 20 V 0.35 VDD = VHB = 16 V 0.30 VDD = VHB = 12 V 0.25 VDD = VHB = 8 V 0.20 0.15 0.10 0.05 0.05 VDD = VHB = 20 V 0.0 0.0 -50 -25 0 25 50 75 100 125 -50 150 -25 0 25 50 75 100 125 150 TA - Temperature - oC TA - Temperature - oC Figure 9. Figure 10. UNDERVOLTAGE LOCKOUT THRESHOLD vs TEMPERATURE UNDERVOLTAGE LOCKOUT THRESHOLD HYSTERESIS vs TEMPERATURE 7.8 0.8 7.6 0.7 7.4 Hysteresis - V Threshold - V 0.6 VDD Rising Threshold 7.2 7.0 6.8 6.6 VDD UVLO Hysteresis 0.5 0.4 0.3 HB UVLO Hysteresis HB Rising Threshold 6.4 0.2 6.2 0.1 6.0 5.8 0 -50 -25 0 25 50 75 100 125 150 -50 -25 TA - Temperature - oC Submit Documentation Feedback 25 50 75 100 125 150 TA - Temperature - oC Figure 11. 8 0 Figure 12. Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200 UCC27201 UCC27200, UCC27201 www.ti.com ....................................................................................................................................... SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008 TYPICAL CHARACTERISTICS (continued) UCC27200 PROPAGATION DELAYS vs TEMPERATURE UCC27201 PROPAGATION DELAYS vs TEMPERATURE 36 36 VDD = VHD = 12 V 34 32 TDHRR 28 26 24 22 20 Propagation Delay - ns 32 30 Propagation Delay - ns VDD = VHB = 12 V 34 TDHFF TDLFF 18 30 28 26 24 22 TDLFF TDLRR 20 18 16 TDHFF 16 TDLRR 14 TDHRR 14 -50 -25 0 50 75 25 100 TA - Temperature - oC 125 150 -50 -25 0 25 50 75 100 125 150 TA - Temperature - oC Figure 13. Figure 14. UCC27200 PROPAGATION DELAY vs SUPPLY VOLTAGE UCC27201 PROPAGATION DELAY vs SUPPLY VOLTAGE 26 26 T = 25oC T = 25oC 24 Propagation Delay - ns Propagation Delay - ns 24 22 LI Falling 20 LI Rising HI Falling LI Falling 22 LI Rising 20 HI Rising HI Rising 18 HI Falling 16 18 8 10 12 14 16 18 20 8 10 VDD = VHB - Supply Voltage - V Figure 15. 12 14 16 18 20 VDD = VHB - Supply Voltage - V Figure 16. Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200 UCC27201 Submit Documentation Feedback 9 UCC27200, UCC27201 SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008 ....................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) DELAY MATCHING vs TEMPERATURE OUTPUT CURRENT vs OUTPUT VOLTAGE 3.5 7 VDD = VHB = 12 V VDD = VHB = 12 V 3.0 Delay Matching - ns 5 4 UCC27200TMOFF 3 UCC27201TMOFF UCC27201TMON UCC27200TMON 2 ILO, IHO - Output Current - A 6 2.5 Pull-Down Current Pull-Up Current 2.0 1.5 1.0 0.5 1 0 0 0 -50 -25 0 25 50 75 100 125 2 4 150 8 6 10 12 VLO, VHO - Output Voltage - V TA - Temperature - oC Figure 17. Figure 18. DIODE CURRENT vs DIODE VOLTAGE QUIESCENT CURRENT vs SUPPLY VOLTAGE 100.0 700 Inputs Low T = 25oC 600 IDD, IHB - Supply Current - mA Diode Current - mA 10.0 1.0 0.1 500 IHB 400 300 IDD 200 0.01 100 0 0.001 0.5 0.6 0.7 0.8 0.9 0 4 Figure 19. 10 Submit Documentation Feedback 8 12 16 20 VDD, VHB - Supply Voltage - V Diode Voltage - V Figure 20. Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200 UCC27201 UCC27200, UCC27201 www.ti.com ....................................................................................................................................... SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008 DEVICE INFORMATION SOIC-8(D) TOP VIEW Power Pad TM SOIC-8(DDA) TOP VIEW VDD 1 8 HB 2 7 VSS HB 2 HO 3 6 LI HO 3 6 LI HS 4 5 HI HS 4 5 HI 8 LO VDD 1 LO Exposed Thermal Die Pad 7 VSS SON-8 (DRM) TOP VIEW 8 LO VDD 1 HB 2 Exposed Thermal Die Pad* 7 VSS HO 3 6 LI 4 5 HI HS NOTE: Pin VSS and the exposed thermal die pad are internally connected. Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200 UCC27201 Submit Documentation Feedback 11 UCC27200, UCC27201 SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008 ....................................................................................................................................... www.ti.com TERMINAL FUNCTIONS TERMINAL NAME NO. VDD 1 I/O DESCRIPTION I Positive supply to the lower gate driver. De-couple this pin to VSS (GND). Typical decoupling capacitor range is 0.22 µF to 1.0 µF. HB 2 I High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap capacitor is required. Connect positive side of the bootstrap capacitor to this pin. Typical range of HB bypass capacitor is 0.022 µF to 0.1 µF, the value is dependant on the gate charge of the high-side MOSFET however. HO 3 O High-side output. Connect to the gate of the high-side power MOSFET. HS 4 I High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. HI 5 I High-side input. LI 6 I Low-side input. VSS 7 O Negative supply terminal for the device which is generally grounded. LO 8 O Low-side output. Connect to the gate of the low-side power MOSFET. PAD - Utilized on the DDA and DRM packages only. Electrically referenced to VSS (GND). Connect to a large thermal mass trace or GND plane to dramatically improve thermal performance. PowerPAD™ 12 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200 UCC27201 UCC27200, UCC27201 www.ti.com ....................................................................................................................................... SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008 FUNCTIONAL BLOCK DIAGRAM 2 HB 3 HO 4 HS 8 LO 7 VSS UVLO LEVEL SHIFT HI 5 VDD 1 UVLO LI 6 Figure 21. TIMING DIAGRAMS LI Input (HI, LI) HI TDLRR, TDHRR LO Output (HO, LO) TDLFF, TDHFF HO TMON TMOFF Figure 22. Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200 UCC27201 Submit Documentation Feedback 13 UCC27200, UCC27201 SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008 ....................................................................................................................................... www.ti.com APPLICATION INFORMATION Functional Description The UCC27200 and UCC27201 are high-side/low-side drivers. The high-side and low-side each have independent inputs which allow maximum flexibility of input control signals in the application. The boot diode for the high-side driver bias supply is internal to the UCC27200 and UCC27201. The UCC27200 is the CMOS compatible input version and the UCC27201 is the TTL or logic compatible version. The high-side driver is referenced to the switch node (HS) which is typically the source pin of the high side MOSFET and drain pin of the low-side MOSFET. The low-side driver is referenced to VSS which is typically ground. The functions contained are the input stages, UVLO protection, level shift, boot diode, and output driver stages. NOTE: The term “UCC2720x” applies to both the UCC27200 and UCC27201. Input Stages The input stages provide the interface to the PWM output signals. The input impedance of the UCC27200 is 200 kΩ nominal and input capacitance is approximately 2 pF. The 200 kΩ is a pull-down resistance to Vss (ground). The CMOS compatible input of the UCC27200 provides a rising threshold of 48% of VDD and falling threshold of 45% of VDD. The inputs of the UCC27200 are intended to be driven from 0 to VDD levels. The input stages of the UCC27201 incorporate an open drain configuration to provide the lower input thresholds. The input impedance is 200 kΩ nominal and input capacitance is approximately 4 pF. The 200 kΩ is a pull-down resistance to VSS (ground). The logic level compatible input provides a rising threshold of 1.7 V and a falling threshold of 1.6 V. UVLO (Under Voltage Lockout) The bias supplies for the high-side and low-side drivers have UVLO protection. VDD as well as VHB to VHS differential voltages are monitored. The VDD UVLO disables both drivers when VDD is below the specified threshold. The rising VDD threshold is 7.1 V with 0.5-V hysteresis. The VHB UVLO disables only the high-side driver when the VHB to VHS differential voltage is below the specified threshold. The VHB UVLO rising threshold is 6.7 V with 0.4-V hysteresis. Level Shift The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides excellent delay matching with the low-side driver. Boot Diode The boot diode necessary to generate the high-side bias is included in the UCC2720x family of drivers. The diode anode is connected to VDD and cathode connected to VHB. With the VHB capacitor connected to HB and the HS pins, the VHB capacitor charge is refreshed every switching cycle when HS transitions to ground. The boot diode provides fast recovery times, low diode resistance, and voltage rating margin to allow for efficient and reliable operation. Output Stages The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance and high peak current capability of both output drivers allow for efficient switching of the power MOSFETs. The low-side output stage is referenced from VDD to VSS and the high-side is referenced from VHB to VHS. 14 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200 UCC27201 UCC27200, UCC27201 www.ti.com ....................................................................................................................................... SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008 Design Tips Switching the MOSFETs Achieving optimum drive performance at high frequency efficiently requires special attention to layout and minimizing parasitic inductances. Care must be taken at the driver die and package level as well as the PCB layout to reduce parasitic inductances as much as possible. Figure 23 shows the main parasitic inductance elements and current flow paths during the turn ON and OFF of the MOSFET by charging and discharging its CGS capacitance. L bond wire L pin L trace 1 VDD I SOURCE Rsource Driver Output Stage Cvdd L pin L trace L bond wire Rg 8 LO I sink Rsink L pin L trace L bond wire 7 Cgs L trace Vss Figure 23. MOSFET Drive Paths and Circuit Parasitics Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200 UCC27201 Submit Documentation Feedback 15 UCC27200, UCC27201 SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008 ....................................................................................................................................... www.ti.com The ISOURCE current charges the CGS gate capacitor and the ISINK current discharges it. The rise and fall time of the voltage across the gate to source defines how quickly the MOSFET can be switched. Based on actual measurements, the analytical curves in Figure 24 and Figure 25 indicate the output voltage and current of the drivers during the discharge of the load capacitor. Figure 24 shows voltage and current as a function of time. Figure 25 indicates the relationship of voltage and current during fast switching. These figures demonstrate the actual switching process and limitations due to parasitic inductances. 12 11 12 11 10 10 9 8 9 6 8 5 7 4 3 LO Voltage, V LO Falling, V or A 7 2 1 0 1 2 5 4 3 2 3 4 5 6 1 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 0 1 t, ns Voltage 2 Current 3 2 1 0 1 2 3 4 5 LO Current, A Figure 24. Turn-Off Voltage and Current vs Time 16 Submit Documentation Feedback Figure 25. Turn-Off Voltage and Current Switching Diagram Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200 UCC27201 UCC27200, UCC27201 www.ti.com ....................................................................................................................................... SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008 Turning off the MOSFET needs to be achieved as fast as possible to minimize switching losses. For this reason the UCC2720x drivers are designed for high peak currents and low output resistance. The sink capability is specified as 0.18 V at 100-mA dc current implying 1.8-Ω RDS(on). With 12-V drive voltage, no parasitic inductance and a linear resistance, one would expect initial sink current amplitude of 6.7 A for both high-side and low-side drivers. Assuming a pure R-C discharge circuit of the gate capacitor, one would expect the voltage and current waveforms to be exponential. Due to the parasitic inductances and non-linear resistance of the driver MOSFET’S, the actual waveforms have some ringing and the peak-sink current of the drivers is approximately 3.3 A as shown in Figure 18. The overall parasitic inductance of the drive circuit is estimated at 4 nH. The internal parasitic inductance of the SOIC-8 package is estimated to be 2 nH including bond wires and leads. The SON-8 package reduces the internal parasitic inductances by more than 50%. Actual measured waveforms are shown in Figure 26 and Figure 27. As shown, the typical rise time of 8 ns and fall time of 7 ns is conservatively rated. Figure 26. VLO and VHO Rise Time, 1-nF Load, 5 ns/Div Figure 27. VLO and VHO Fall Time, 1-nF Load, 5-ns/Div Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200 UCC27201 Submit Documentation Feedback 17 UCC27200, UCC27201 SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008 ....................................................................................................................................... www.ti.com Dynamic Switching of the MOSFETs The true behavior of MOSFETS presents a dynamic capacitive load primarily at the gate to source threshold voltage. Using the turn off case as the example, when the gate to source threshold voltage is reached the drain voltage starts rising, the drain to gate parasitic capacitance couples charge into the gate resulting in the turn off plateau. The relatively low threshold voltages of many MOSFETS and the increased charge that has to be removed (Miller charge) makes good driver performance necessary for efficient switching. An open loop half bridge power converter was utilized to evaluate performance in actual applications. The schematic of the half-bridge converter is shown in Figure 30. The turn off waveforms of the UCC27200 driving two MOSFETs in parallel is shown in Figure 28 and Figure 29. Figure 28. VLO Fall Time in Half-Bridge Converter 18 Submit Documentation Feedback Figure 29. VHO Fall Time in Half-Bridge Converter Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200 UCC27201 UCC27200, UCC27201 + + + www.ti.com ....................................................................................................................................... SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008 Figure 30. Open Loop Half-Bridge Converter Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200 UCC27201 Submit Documentation Feedback 19 UCC27200, UCC27201 SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008 ....................................................................................................................................... www.ti.com Delay Matching and Narrow Pulse Widths The total delays encountered in the PWM, driver and power stage need to be considered for a number of reasons, primarily delay in current limit response. Also to be considered are differences in delays between the drivers which can lead to various concerns depending on the topology. The sync-buck topology switching requires careful selection of dead-time between the high- and low-side switches to avoid 1) cross conduction and 2) excessive body diode conduction. Bridge topologies can be affected by a resulting volt-sec imbalance on the transformer if there is imbalance in the high and low side pulse widths in a steady state condition. Narrow pulse width performance is an important consideration when transient and short circuit conditions are encountered. Although there may be relatively long steady state PWM output-driver-MOSFET signals, very narrow pulses may be encountered in 1) soft start, 2) large load transients, and 3) short circuit conditions. The UCC2720x driver family offers excellent performance regarding high and low-side driver delay matching and narrow pulse width performance. The delay matching waveforms are shown in Figure 31 and Figure 32. The UCC2720x driver narrow pulse performance is shown in Figure 33 and Figure 34. 20 Figure 31. VLO and VHO Rising Edge Delay Matching Figure 32. VLO and VHO Falling Edge Delay Matching Figure 33. 20-ns Input Pulse Delay Matching Figure 34. 10-ns Input Pulse Delay Matching Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200 UCC27201 UCC27200, UCC27201 www.ti.com ....................................................................................................................................... SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008 Boot Diode Performance The UCC2720x family of drivers incorporates the bootstrap diode necessary to generate the high side bias internally. The characteristics of this diode are important to achieve efficient, reliable operation. The dc characteristics to consider are VF and dynamic resistance. A low VF and high dynamic resistance results in a high forward voltage during charging of the bootstrap capacitor. The UCC2720x has a boot diode rated at 0.65-V VF and dynamic resistance of 0.6 Ω for reliable charge transfer to the bootstrap capacitor. The dynamic characteristics to consider are diode recovery time and stored charge. Diode recovery times that are specified with no conditions can be misleading. Diode recovery times at no forward current (IF) can be noticeably less than with forward current applied. The UCC2720x boot diode recovery is specified at 20ns at IF = 20 mA, IREV = 0.5 A. At 0 mA IF the reverse recovery time is 15 ns. Another less obvious consideration is how the stored charge of the diode is affected by applied voltage. On every switching transition when the HS node transitions from low to high, charge is removed from the boot capacitor to charge the capacitance of the reverse biased diode. This is a portion of the driver power losses and reduces the voltage on the HB capacitor. At higher applied voltages, the stored charge of the UCC2720x PN diode is often less than a comparable Schottky diode. Layout Recommendations To improve the switching characteristics and efficiency of a design, the following layout rules should be followed. • Locate the driver as close as possible to the MOSFETs. • Locate the VDD and VHB (bootstrap) capacitors as close as possible to the driver. • Pay close attention to the GND trace. Use the thermal pad of the DDA and DRM package as GND by connecting it to the VSS pin (GND). Note: The GND trace from the driver goes directly to the source of the MOSFET but should not be in the high current path of the MOSFET(S) drain or source current. • Use similar rules for the HS node as for GND for the high side driver. • Use wide traces for LO and HO closely following the associated GND or HS traces. 60 mil to 100 mil width is preferable where possible. • Use as least two or more vias if the driver outputs or SW node needs to be routed from one layer to another. For GND the number of vias needs to be a consideration of the thermal pad requirements as well as parasitic inductance. • Avoid LI and HI (driver input) going close to the HS node or any other high dV/dT traces that can induce significant noise into the relatively high impedance leads. • Keep in mind that a poor layout can cause a significant drop in efficiency versus a good PCB layout and can even lead to decreased reliability of the whole system. Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200 UCC27201 Submit Documentation Feedback 21 UCC27200, UCC27201 SLUS746B – DECEMBER 2006 – REVISED NOVEMBER 2008 ....................................................................................................................................... www.ti.com Figure 35. Example Component Placement Additional References These references and links to additional information may be found at www.ti.com. 1. Additional layout guidelines for PCB land patterns may be found in Application Brief SLUA271 2. Additional thermal performance guidelines may be found in Application Reports SLMA002A and SLMA004 22 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): UCC27200 UCC27201 PACKAGE MATERIALS INFORMATION www.ti.com 19-Oct-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UCC27200DDAR SO Power PAD DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1 UCC27200DDAR SO Power PAD DDA 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC27200DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC27200DRMR VSON DRM 8 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 UCC27200DRMT VSON DRM 8 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 UCC27201DDAR SO Power PAD DDA 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC27201DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC27201DRMR VSON DRM 8 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 UCC27201DRMT VSON DRM 8 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Oct-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC27200DDAR SO PowerPAD DDA 8 2500 364.0 364.0 27.0 UCC27200DDAR SO PowerPAD DDA 8 2500 367.0 367.0 35.0 UCC27200DR SOIC D 8 2500 340.5 338.1 20.6 UCC27200DRMR VSON DRM 8 3000 367.0 367.0 35.0 UCC27200DRMT VSON DRM 8 250 210.0 185.0 35.0 UCC27201DDAR SO PowerPAD DDA 8 2500 367.0 367.0 35.0 UCC27201DR SOIC D 8 2500 340.5 338.1 20.6 UCC27201DRMR VSON DRM 8 3000 367.0 367.0 35.0 UCC27201DRMT VSON DRM 8 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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