TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 DUAL-OUTPUT, LOW DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS Check for Samples: TPS70445, TPS70448, TPS70451, TPS70458, TPS70402 FEATURES DESCRIPTION • The TPS704xx family of devices consists of dual-output, low-dropout voltage regulators with integrated SVS (RESET, POR, or power on reset) and power good (PG) functions. These devices are capable of supplying 1 A and 2 A by regulator 1 and regulator 2 respectively. Quiescent current is typically 185 mA at full load. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power on reset), manual reset input, and independent enable functions provide a complete system solution. 1 23 • • • • • • • • • • • • • • • Dual Output Voltages for Split-Supply Applications Independent Enable Functions (See Part Number TPS703xx for Sequenced Outputs) Output Current Range of 1 A on Regulator 1 and 2 A on Regulator 2 Fast Transient Response Voltage Options: 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and Dual Adjustable Outputs Open Drain Power-On Reset with 120-ms Delay Open Drain Power Good for Regulator 1 and Regulator 2 Ultralow 185mA (typ) Quiescent Current 2mA Input Current During Standby Low Noise: 78mVRMS Without Bypass Capacitor Quick Output Capacitor Discharge Feature One Manual Reset Input 2% Accuracy Over Load and Temperature Undervoltage Lockout (UVLO) Feature 24-Pin PowerPAD™ TSSOP Package Thermal Shutdown Protection PWP PACKAGE (TOP VIEW) GND/HEATSINK GND/HEATSINK 1 24 VIN1 2 23 VOUT1 VIN1 3 22 VOUT1 NC 4 21 VSENSE1/FB1 MR 5 20 NC EN1 6 19 PG1 EN2 7 18 PG2 RESET 8 17 NC GND 9 16 VSENSE2/FB2 VIN2 10 15 VOUT2 VIN2 11 14 VOUT2 GND/HEATSINK 12 13 GND/HEATSINK NC = No internal connection TPS70451 PWP 5V VIN1 0.22 mF 22 mF VSENSE1 250 kW PG1 PG1 VIN2 0.22 mF >2 V EN1 <0.7 V EN2 >2 V MR MR 250 kW >2 V <0.7 V 250 kW RESET RESET EN1 PG2 EN2 VSENSE2 I/O 3.3 V VOUT1 PG2 <0.7 V 1.8 V VOUT2 Core 47 mF 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2010, Texas Instruments Incorporated TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com The TPS704xx family of voltage regulators offers very low dropout voltage and dual outputs. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 47-mF low ESR capacitors. These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable voltage options. Regulator 1 can support up to 1 A, and regulator 2 can support up to 2 A. Separate voltage inputs allow the designer to configure the source power. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 160 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 250 mA over the full range of output current and full range of temperature). This LDO family also features a sleep mode; applying a high signal to EN1 or EN2 (enable) shuts down regulator 1 or regulator 2, respectively. When a high signal is applied to both EN1 and EN2, both regulators enter sleep mode, thereby reducing the input current to 2 mA at TJ = +25°C. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage condition at VOUT1. The PG1 pin can be used to implement a SVS (RESET, POR, or power on reset) for the circuitry supplied by regulator 1. The PG2 pin reports the voltage conditions at VOUT2. The PG2 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 2. The TPS704xx features a RESET (SVS, POR, or power on reset). RESET is an active low, open drain output and requires a pull-up resistor for normal operation. When pulled up, RESET goes into a high impedance state (that is, logic high) after a 120-ms delay when both of the following conditions are met. First, VIN1 must be above the undervoltage condition. Second, the manual reset (MR) pin must be in a high impedance state. To monitor VOUT1, the PG1 output pin can be connected to MR. To monitor VOUT2, the PG2 output pin can be connected to MR. RESET can be used to drive power on reset or a low-battery indicator. If RESET is not used, it can be left floating. Internal bias voltages are powered by VIN1 and require 2.7 V for full functionality. Each regulator input has an undervoltage lockout circuit that prevents each output from turning on until the respective input reaches 2.5 V. 2 Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) VOLTAGE (V) (1) (2) (2) PRODUCT VOUT1 VOUT2 PACKAGELEAD (DESIGNATOR) SPECIFIED TEMPERATURE RANGE (TJ) TPS70402 Adjustable Adjustable HTSSOP-24 (PWP) –40°C to +125°C TPS70445 3.3 V 1.2 V HTSSOP-24 (PWP) –40°C to +125°C TPS70448 3.3 V 1.5 V HTSSOP-24 (PWP) –40°C to +125°C TPS70451 3.3 V 1.8 V HTSSOP-24 (PWP) –40°C to +125°C TPS70458 3.3 V 2.5 V HTSSOP-24 (PWP) –40°C to +125°C ORDERING NUMBER TRANSPORT MEDIA, QUANTITY TPS70402PWP Tube, 60 TPS70402PWPR Tape and Reel, 2000 TPS70445PWP Tube, 60 TPS70445PWPR Tape and Reel, 2000 TPS70448PWP Tube, 60 TPS70448PWPR Tape and Reel, 2000 TPS70451PWP Tube, 60 TPS70451PWPR Tape and Reel, 2000 TPS70458PWP Tube, 60 TPS70458PWPR Tape and Reel, 2000 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at ti.com. For fixed 1.20 V operation, tie FB to OUT. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). Input voltage range: VIN1, VIN2 (2) Voltage range at EN1, EN2 TPS704xx UNIT –0.3 to +7 V –0.3 to +7 V Output voltage range (VOUT1, VSENSE1) 5.5 V Output voltage range (VOUT2, VSENSE2) 5.5 V Maximum RESET, PG1, PG2 voltage 7 V Maximum MR voltage VIN1 V Internally limited — See Dissipation Ratings Table — Operating virtual junction temperature range, TJ –40 to +150 °C Storage temperature range, Tstg –65 to +150 °C 2 kV Peak output current Continuous total power dissipation ESD rating, HBM (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are tied to network ground. Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com DISSIPATION RATINGS PACKAGE AIR FLOW (CFM) TA ≤ +25°C DERATING FACTOR TA = +70°C TA = +85°C 0 3.067W 30.67mW/°C 1.687W 1.227W 250 4.115W 41.15mW/°C 2.265W 1.646W PWP (1) (1) This parameter is measured with the recommended copper heat sink pattern on a 4-layer PCB, 1 oz. copper on a 4-in by 4-in ground layer. For more information, refer to TI technical brief SLMA002. RECOMMENDED OPERATING CONDITIONS Over operating temperature range (unless otherwise noted). Input voltage, VI (1) (regulator 1 and 2) Output current, IO (regulator 1) Output current, IO (regulator 2) MIN MAX 2.7 6 UNIT V 0 1 A A 0 2 Output voltage range (for adjustable option) 1.22 5.5 V Operating virtual junction temperature, TJ –40 +125 °C (1) 4 To calculate the minimum input voltage for maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load). Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 ELECTRICAL CHARACTERISTICS Over recommended operating junction temperature range (TJ = –40°C to +125°C), VIN1 or VIN2 = VOUT(nom) + 1 V, IO = 1 mA, EN = 0 V, COUT1 = 22 mF, and COUT2 = 47 mF (unless otherwise noted). PARAMETER 2.7 V < VIN < 6 V, TJ = +25°C FB connected to VO 2.7 V < VIN < 6 V, FB connected to VO 1.2 V Output (VOUT2) 2.7 V < VIN < 6 V, TJ = +25°C 1.5 V Output (VOUT2) 2.7 V < VIN < 6 V, 1.8 V Output (VOUT2) 2.8 V < VIN < 6 V, 2.5 V Output (VOUT2) 3.5 V < VIN < 6 V, 3.3 V Output (VOUT2) 4.3 V < VIN < 6 V, Reference voltage Output voltage VO (1) , TEST CONDITIONS (2) 2.7 V < VIN < 6 V, 2.7 V < VIN < 6 V, 4.3 V < VIN < 6 V, 2.55 3.3 3.234 VO + 1 V < VIN ≤ 6 V, TJ = +25°C (1) VO + 1 V < VIN ≤ 6 V (1) Load regulation for VOUT 1 and VOUT2 TJ = +25°C TJ = +25°C 3.366 185 250 0.01 0.1 1 Regulator 1 BW = 300 Hz to 50 kHz, CO = 33 mF, TJ = +25°C VOUT = 0 V mVRMS 1.75 2.2 3.8 4.5 +150 EN1 = VIN, EN2 = VIN Regulator 2 EN1 = VIN, EN2 = VIN Regulator 1 f = 1 kHz TJ = +25°C (1) 65 Regulator 2 f = 1 kHz TJ = +25°C (1) 60 Minimum input voltage for valid RESET IRESET = 300 mA, V(RESET) ≤ 0.8 V t (RESET) RESET pulse duration Output low voltage VIN = 3.5 V, Leakage current V(RESET) = 6 V PSRR %V mV 77 Regulator 1 Powersupply ripple rejection (TPS70451) mA 79 Thermal shutdown junction temperature II Standby (standby) current V 1.836 2.45 Output voltage line regulation (∆VO/VO) for regulator 1 and regulator 2 (3) Regulator 2 1.53 2.5 TJ = +25°C (2) Regulator 1 1.224 1.764 See Regulator 2 1.244 1.8 TJ = +25°C 3.5 V < VIN < 6 V, UNIT 1.5 TJ = +25°C 2.8 V < VIN < 6 V, MAX 1.2 1.47 (2) Output current limit 1.196 1.176 See Vn TYP 1.22 TJ = +25°C Quiescent current (GND current) for regulator 1 and regulator 2, EN1 = EN2 = 0 V (1) Output noise voltage (TPS70451) MIN TJ = +25°C 1 A °C 2 10 mA dB RESET Terminal (1) (2) (3) 80 I(RESET) = 1 mA 1.0 1.3 V 120 160 ms 0.15 0.4 V 1 mA Minimum input operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum input voltage = 6 V, minimum output current = 1 mA. IO = 1 mA to 1 A for Regulator 1 and 1 mA to 2 A for Regulator 2. (VImax - 2.7) x 1000 Line regulation (mV) = (%/V) x Vo 100 If VO < 1.8 V then VImax = 6 V, VImin = 2.7 V: [V - (Vo + 1) ] x 1000 Line regulation (mV) = (%/V) x Vo Imax 100 If VO > 2.5 V then VImax = 6 V, VImin = VO + 1 V: Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 5 TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over recommended operating junction temperature range (TJ = –40°C to +125°C), VIN1 or VIN2 = VOUT(nom) + 1 V, IO = 1 mA, EN = 0 V, COUT1 = 22 mF, and COUT2 = 47 mF (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2.65 V VIN1/VIN2 Terminal UVLO threshold 2.4 UVLO hysteresis 110 mV PG1/PG2 Terminal V(PGx) ≤ 0.8 V Minimum input voltage for valid PGx I(PGx) = 300 mA, Trip threshold voltage VO decreasing Hysteresis voltage Measured at VO tr(PGx) Rising edge deglitch 30 Output low voltage VIN = 2.7V, Leakage current V(PGx) = 6V 92 I(PGx) = 1 mA 1.0 1.3 95 98 %VOUT 0.5 %VOUT 0.15 V ms 0.4 V 1 mA EN1/EN2 Terminal High-level ENx input voltage 2 V Low-level ENx input voltage Input current (ENx) –1 0.7 V 1 mA MR Terminal High-level input voltage 2 V Low-level input voltage 0.7 Pull-up current source 6 V mA VOUT1 Terminal Dropout voltage (4) IO = 1 A, VIN1 = 3.2 V TJ = +25°C 160 IO = 1 A, VIN1 = 3.2 V 250 mV Peak output current 2 ms pulse width 1.2 A Discharge transistor current VOUT1 = 1.5 V 7.5 mA VOUT2 Terminal Peak output current 2 ms pulse width Discharge transistor current VOUT2 = 1.5 V 3 A 7.5 mA FB Terminal Input current: TPS70402 (4) 6 FB = 1.8 V 1 mA Input voltage (VIN1 or VIN2) = VO(typ) – 100 mV. For 1.5-V, 1.8-V, and 2.5-V regulators, the dropout voltage is limited by input voltage range. The 3.3-V regulator input is set to 3.2 V to perform this test. Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 DEVICE INFORMATION Fixed Voltage Version VIN1 (2 Pins) VOUT1 (2 Pins) 2.5 V UVLO1 Comp 10kW Current Sense + (see Note A) + GND VSENSE1 ENA_1 Reference Thermal Shutdown ENA_1 Vref Vref PG1 VSENSE1 - 0.95 x Vref + Rising Edge Deglitch VIN1 PG1 Comp MR RESET 120 ms Delay ENA_1 EN1 PG2 Comp VSENSE2 - 0.95 x Vref + ENA_2 PG2 Rising Edge Deglitch Vref FB2 EN2 - 2.5 V UVLO2 Comp + - ENA_2 VSENSE2 Current Sense ENA_2 (see Note A) 10kW VOUT2 (2 Pins) VIN2 (2 Pins) A. + For most applications, VSENSE1 and VSENSE2 should be externally connected to VOUT1 and VOUT2, respectively, as close as possible to the device. For other implementations, refer to SENSE terminal connection discussion in the Application Information section. Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 7 TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com Adjustable Voltage Version VOUT1 (2 Pins) VIN1 (2 Pins) 2.5 V UVLO1 Comp Current Sense + GND FB1 (see Note A) ENA_1 + Reference Thermal Shutdown ENA_1 Vref FB1 Vref PG1 FB1 - 0.95 x Vref + Rising Edge Deglitch VIN1 PG1 Comp MR RESET 120 ms Delay ENA_1 EN1 PG2 Comp FB2 - 0.95 x Vref + ENA_2 PG2 Rising Edge Deglitch Vref FB2 EN2 - 2.5 V UVLO2 Comp + - VIN2 (2 Pins) A. 8 + ENA_2 Current Sense ENA_2 FB2 (see Note A) VOUT2 (2 Pins) For most applications, FB1 and FB2 should be externally connected to resistor dividers as close as possible to the device. For other implementations, refer to FB terminals connection discussion in the Application Information section. Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 RESET Timing Diagram VIN1 VUVLO VUVLO VRES t VRES (see Note A) MR Input t RESET Output 120 ms Delay Output Undefined 120 ms Delay Output Undefined t NOTE A: VRES is the minimum input voltage for a valid RESET. The symbol VRES is not currently listed within EIA or JEDEC standards for semiconductor symbology. PG1 Timing Diagram VIN1 VUVLO VUVLO VPG VPG1 (see Note A) t VOUT1 VIT+ (see Note B) Threshold Voltage VIT(see Note B) t PG1 Output PG1 Output Undefined Output Undefined t NOTES A: VPG1 is the minimum input voltage for a valid PG. The symbol VPG1 is not currently listed within EIA or JEDEC standards for semiconductor symbology. NOTES B: VIT- trip voltage is typically 5% lower than the output voltage (95%VO). VIT- to VIT+ is the hysteresis voltage. Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 9 TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com PG2 Timing Diagram (assuming VIN1 already powered up) VIN2 t VOUT2 VIT+ (see Note A) Threshold Voltage VIT(see Note A) t PG2 Output t NOTE A: VIT- trip voltage is typically 5% lower than the output voltage (95%VO). VIT- to VIT+ is the hysteresis voltage. TERMINAL FUNCTIONS TERMINAL NAME NO. EN1 6 EN2 GND GND/HEATSI NK I/O DESCRIPTION I Active low enable for VOUT1 7 I Active low enable for VOUT2 9 — Ground 1, 12, 13, 24 — Ground/heatsink MR 5 I NC 4, 17, 20 — No connection PG1 19 O Open drain output, low when VOUT1 voltage is less than 95% of the nominal regulated voltage PG2 18 O Open drain output, low when VOUT2 voltage is less than 95% of the nominal regulated voltage RESET 8 O Open drain output, SVS (power-on reset) signal, active low VIN1 2, 3 I Input voltage of regulator 1 VIN2 10, 11 I Input voltage of regulator 2 VOUT1 22, 23 O Output voltage of regulator 1 VOUT2 14, 15 O Output voltage of regulator 2 VSENSE1/FB1 21 I Regulator 1 output voltage sense/regulator 1 feedback for adjustable VSENSE2/FB2 16 I Regulator 2 output voltage sense/regulator 2 feedback for adjustable 10 Submit Documentation Feedback Manual reset input, active low, pulled up internally Copyright © 2000–2010, Texas Instruments Incorporated TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 Detailed Description The TPS704xx low dropout regulator family provides dual regulated output voltages with independent enable functions. These devices provide fast transient response and high accuracy with small output capacitors, while drawing low quiescent current. Other features are integrated SVS (power-on reset, RESET) and power good (PG1, PG2) that monitor output voltages and provide logic output to the system. These differentiated features provide a complete power solution. The TPS704xx, unlike many other LDOs, features very low quiescent current that remains virtually constant even with varying loads. Conventional LDO regulators use a PNP pass element, the base current of which is directly proportional to the load current through the regulator (IB = IC/b). The TPS704xx uses a PMOS transistor to pass current; because the gate of the PMOS is voltage-driven, operating current is low and stable over the full load range. Pin Functions Enable (EN1, EN2) The EN terminals are inputs that enable or shut down each respective regulator. If EN is at a voltage high signal, the respective regulator is in shutdown mode. When EN goes to voltage low, the respective regulator is enabled. Power-Good (PG1, PG2) The PG terminals are open drain, active high output terminals that indicate the status of each respective regulator. When VOUT1 reaches 95% of its regulated voltage, PG1 goes to a high impedance state. When VOUT2 reaches 95% of its regulated voltage, PG2 goes to a high impedance state. Each PG goes to a low impedance state when its respective output voltage is pulled below 95% (that is, goes to an overload condition) of its regulated voltage. The open drain outputs of the PG terminals require a pull-up resistor. Manual Reset Pin MR is an active low input terminal used to trigger a reset condition. When MR is pulled to logic low, a POR (RESET) occurs. The terminal has a 6-mA pull-up current to VIN1; however, it is recommended that the pin be pulled high to VIN1 when it is not used. Sense (VSENSE1, VSENSE2) The sense terminals of fixed-output options must be connected to the regulator outputs, and the connection should be as short as possible. Internally, the sense terminal connects to high-impedance, wide-bandwidth amplifiers through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential to route the sense connection in such a way as to minimize or avoid noise pickup. Adding RC networks between sense terminals and VOUT terminals to filter noise is not recommended because these networks can cause the regulators to oscillate. Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 11 TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com FB1 and FB2 FB1 and FB2 are input terminals used for adjustable-output devices and must be connected to the external feedback resistor divider. FB1 and FB2 connections should be as short as possible. It is essential to route them in such a way as to minimize or avoid noise pickup. Adding RC networks between FB terminals and VOUT terminals to filter noise is not recommended because these networks can cause the regulators to oscillate. RESET Indicator RESET is an active low, open drain output and requires a pullup resistor for normal operation. When pulled up, RESET goes into a high impedance state (that is, logic high) after a 120-ms delay when both of the following conditions are met. First, VIN1 must be above the undervoltage condition. Second, the manual reset (MR) pin must be in a high impedance state. To monitor VOUT1, the PG1 output pin can be connected to MR. To monitor VOUT2, the PG2 output pin can be connected to MR. If RESET is not used, it can be left floating. VIN1 and VIN2 VIN1 and VIN2 are inputs to each regulator. Internal bias voltages are powered by VIN1. VOUT1 and VOUT2 VOUT1 and VOUT2 are output terminals of each regulator. 12 Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VO vs Output current Output voltage PSRR ZO Figure 1 and Figure 2 vs Junction temperature Figure 3 to Figure 4 Ground current vs Junction temperature Figure 5 Power-supply rejection ratio vs Frequency Figure 6 to Figure 9 Output spectral noise density vs Frequency Figure 10 to Figure 13 Output impedance vs Frequency Dropout voltage Figure 14 to Figure 17 vs Temperature Figure 18 and Figure 19 vs Input voltage Figure 20 and Figure 21 Load transient response Figure 22 and Figure 23 Line transient response (VOUT1) Figure 24 Line transient response (VOUT2) VO Figure 25 Output voltage vs Time (start-up) Figure 26 and Figure 27 Equivalent series resistance (ESR) vs Output current Figure 29 to Figure 32 TPS70451 OUTPUT VOLTAGE vs OUTPUT CURRENT TPS70451 OUTPUT VOLTAGE vs OUTPUT CURRENT 1.815 3.33 VIN2 = 2.8 V VIN1 = 4.3 V VOUT2 VOUT1 3.31 3.30 3.29 1.805 1.8 1.795 1.79 3.28 3.27 TJ = 25°C 1.81 TJ = 25°C VO - Output Voltage - V VO - Output Voltage - V 3.32 1.785 0 200 400 600 800 IO - Output Current - mA Figure 1. Copyright © 2000–2010, Texas Instruments Incorporated 1000 0 500 1000 1500 IO - Output Current - mA 2000 Figure 2. Submit Documentation Feedback 13 TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) TPS70451 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE TPS70451 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE 1.834 VOUT1 VIN2 = 2.8 V VOUT2 1.824 3.334 3.314 VO - Output Voltage - V VO - Output Voltage - V 3.354 VIN1 = 4.3 V IO = 1 mA 3.294 IO = 1 A 3.274 3.254 1.814 IO = 2 A 1.804 IO = 1 mA 1.794 1.784 1.774 3.234 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ - Junction Temperature - °C 1.764 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ - Junction Temperature - °C Figure 3. Figure 4. TPS70451 GROUND CURRENT vs JUNCTION TEMPERATURE 210 Regulator 1 and Regulator 2 Ground Current - mA 200 IOUT1 = 1 mA IOUT2 = 1 mA 190 IOUT1 = 1 A 180 IOUT2 = 2 A 170 160 150 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ - Junction Temperature - °C Figure 5. 14 Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) TPS70451 POWER-SUPPLY REJECTION RATIO vs FREQUENCY TPS70451 POWER-SUPPLY REJECTION RATIO vs FREQUENCY 0 VIN1 = 4.3 V PSRR - Power Supply Rejection Ratio - dB PSRR - Power Supply Rejection Ratio - dB -10 VOUT1 = 3.3 V -20 IO = 10 mA CO = 22 mF -30 -40 -50 -60 -70 -80 -90 10 100 1k 10 k 100 k VIN1 = 4.3 V -10 VOUT1 = 3.3 V -20 IO = 1 A -40 -50 -60 -70 -80 -90 -100 1M CO = 22 mF -30 10 100 f - Frequency - Hz Figure 7. TPS70451 POWER-SUPPLY REJECTION RATIO vs FREQUENCY TPS70451 POWER-SUPPLY REJECTION RATIO vs FREQUENCY 1M 0 VIN2 = 2.8 V -10 PSRR - Power Supply Rejection Ratio - dB PSRR - Power Supply Rejection Ratio - dB 100 k Figure 6. 0 VOUT2 = 1.8 V IO = 10 mA -20 CO = 47 mF -30 -40 -50 -60 -70 -80 -90 -100 1k 10 k f - Frequency - Hz 10 100 1k 10 k f - Frequency - Hz Figure 8. Copyright © 2000–2010, Texas Instruments Incorporated 100 k 1M VIN2 = 2.8 V -10 VOUT2 = 1.8 V IO = 2 A -20 CO = 47 mF -30 -40 -50 -60 -70 -80 -90 -100 10 100 1k 10 k 100 k 1M f - Frequency - Hz Figure 9. Submit Documentation Feedback 15 TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 10 VIN1 = 4.3 V VIN2 = 2.8 V VOUT1 = 3.3 V VOUT2 = 1.8 V Output Spectral Noise Density - mV/ÖHz Output Spectral Noise Density - mV/ÖHz 10 COUT1 = 22 mF IO = 10 mA TJ = 25°C 1 0.1 0.01 100 1k 10 k 0.1 1k 10 k f - Frequency - Hz Figure 10. Figure 11. OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 100 k 10 VIN1 = 4.3 V VIN2 = 2.8 V VOUT1 = 3.3 V VOUT2 = 1.8 V Output Spectral Noise Density - mV/ÖHz Output Spectral Noise Density - mV/ÖHz TJ = 25°C 1 f - Frequency - Hz COUT1 = 22 mF IO = 1 mA TJ = 25°C 1 0.1 1k 10 k f - Frequency - Hz Figure 12. 16 IO = 10 mA 0.01 100 100 k 10 0.01 100 COUT2 = 47 mF Submit Documentation Feedback 100 k COUT2 = 47 mF IO = 2 A TJ = 25°C 1 0.1 0.01 100 1k 10 k f - Frequency - Hz 100 k Figure 13. Copyright © 2000–2010, Texas Instruments Incorporated TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) OUTPUT IMPEDANCE vs FREQUENCY OUTPUT IMPEDANCE vs FREQUENCY VOUT1 = 3.3 V VOUT1 = 3.3 V IO = 1 A CO = 22 mF CO = 22 mF ZO - Output Impedance - W ZO - Output Impedance - W IO = 10 mA 1 0.1 0.01 10 100 1k 10 k 100 k 1M 1 0.1 0.01 10 10 M 100 1k f - Frequency - Hz Figure 15. OUTPUT IMPEDANCE vs FREQUENCY OUTPUT IMPEDANCE vs FREQUENCY VOUT2 = 1.8 V IO = 10 mA IO = 2 A 10 M 1M 10 M CO = 47 mF ZO - Output Impedance - W ZO - Output Impedance - W 1M f - Frequency - Hz VOUT2 = 1.8 V 1 0.1 0.01 100 100 k Figure 14. CO = 47 mF 10 10 k 1k 10 k 100 k f - Frequency - Hz Figure 16. Copyright © 2000–2010, Texas Instruments Incorporated 1M 10 M 1 0.1 0.01 10 100 1k 10 k 100 k f - Frequency - Hz Figure 17. Submit Documentation Feedback 17 TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) TPS70451 DROPOUT VOLTAGE vs TEMPERATURE TPS70451 DROPOUT VOLTAGE vs TEMPERATURE 250 25 VOUT1 VOUT1 VIN1 = 3.2 V VIN1 = 3.2 V 20 IO = 1 A Dropout Voltage - mV Dropout Voltage - mV 200 150 100 50 IO = 100 mA 15 10 5 IO = 10 mA 0 -40 -25 -10 5 20 35 50 65 80 0 -40 -25 -10 95 110 125 T - Temperature - °C 5 20 IO = 1 mA 35 50 65 Figure 19. TPS70402 DROPOUT VOLTAGE vs INPUT VOLTAGE TPS70402 DROPOUT VOLTAGE vs INPUT VOLTAGE 300 VOUT1 VOUT2 IO = 1 A IO = 2 A 250 TJ = 125°C Dropout Voltage - mV Dropout Voltage - mV 250 200 TJ = 25°C 150 100 TJ = -40°C 50 0 2.5 TJ = 125°C 200 TJ = 25°C 150 TJ = -40°C 100 50 3 3.5 4 4.5 VI - Input Voltage - V Figure 20. 18 95 110 125 T - Temperature - °C Figure 18. 300 80 Submit Documentation Feedback 5 5.5 0 2.5 3 3.5 4 4.5 VI - Input Voltage - V 5 5.5 Figure 21. Copyright © 2000–2010, Texas Instruments Incorporated TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) IO - Output Current - A LOAD TRANSIENT RESPONSE VIN1 = 4.3 V VOUT1 = 3.3 V 1 CO = 22 mF 0.5 0 DVO - Change in 50 0 -50 -100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Output Voltage - mV DVO - Change in Output Voltage - mV IO - Output Current - A LOAD TRANSIENT RESPONSE VOUT2 = 1.8 V IO = 2 A 2 CO = 47 mF 1 0 50 0 -50 0 2 0.2 LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE VI - Input Voltage - V VOUT1 = 3.3 V IO = 1 A CO = 22 mF DVO - Change in 4.3 50 0 50 0 20 1.4 1.6 Figure 23. 5.3 100 0.4 0.6 0.8 1 1.2 t - Time - ms Figure 22. 40 60 80 100 120 140 160 180 200 t - Time - ms Figure 24. Copyright © 2000–2010, Texas Instruments Incorporated Output Voltage - mV DVO - Change in Output Voltage - mV VI - Input Voltage - V t - Time - ms 1.8 2 VOUT2 = 1.8 V IO = 2 A 3.8 CO = 47 mF 2.8 100 0 100 200 0 20 40 60 80 100 120 140 160 180 20 t - Time - ms Figure 25. Submit Documentation Feedback 19 TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT VOLTAGE AND ENABLE VOLTAGE vs TIME (START-UP) OUTPUT VOLTAGE AND ENABLE VOLTAGE vs TIME (START-UP) VO - Output Voltage - V 3 VOUT1 = 3.3 V IO = 1 A 2 CO = 22 mF VIN1 = 4.3 V 1 EN2 = High 0 Enable Voltage - V Enable Voltage - V VO - Output Voltage - V 4 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2 1 0 VOUT2 = 1.8 V IO = 2 A CO = 47 mF VIN2 = 2.8 V 5 EN1 = High 0 0 0.2 0.4 0.6 t - Time - ms Figure 26. VIN 0.8 1 1.2 1.4 1.6 1.8 2 t - Time - ms Figure 27. To Load IN OUT + COUT EN RL GND ESR Figure 28. Test Circuit for Typical Regions of Stability 20 Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(1) vs OUTPUT CURRENT TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(1) vs OUTPUT CURRENT 10 10 VOUT1 = 3.3 V CO = 22 mF ESR - Equivalent Series Resistance - W ESR - Equivalent Series Resistance - W VOUT1 = 3.3 V REGION OF INSTABILITY 1 0.1 50 mW CO = 220 mF REGION OF INSTABILITY 1 0.1 15 mW 0.01 0.01 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 1 0.1 0.2 0.4 0.5 0.6 0.7 0.8 0.9 Figure 29. Figure 30. TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(1) vs OUTPUT CURRENT TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(1) vs OUTPUT CURRENT 10 1 10 REGION OF INSTABILITY ESR - Equivalent Series Resistance - W REGION OF INSTABILITY ESR - Equivalent Series Resistance - W 0.3 IO - Output Current - A IO - Output Current - A VOUT2 = 1.8 V CO = 47 mF 1 0.1 50 mW 0.01 VOUT2 = 1.8 V CO = 680 mF 1 0.1 15 mW 0.01 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 IO - Output Current - A Figure 31. 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 IO - Output Current - A Figure 32. (1) Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 21 TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com THERMAL INFORMATION Thermally-Enhanced TSSOP-24 (PWP— PowerPAD™) The thermally-enhanced PWP package is based on the 24-pin TSSOP, but includes a thermal pad [see Figure 33(c)] to provide an effective thermal contact between the IC and the printed wiring board (PWB). Traditionally, surface mount and power have been mutually exclusive terms. A variety of scaled-down TO220-type packages have leads formed as gull wings to make them applicable for surface-mount applications. These packages, however, suffer from several shortcomings: they do not address the very low profile requirements (<2 mm) of many of today’s advanced systems, and they do not offer a pin-count high enough to accommodate increasing integration. On the other hand, traditional low-power surface-mount packages require power-dissipation derating that severely limits the usable range of many high-performance analog circuits. The PWP package (thermally-enhanced TSSOP) combines fine-pitch surface-mount technology with thermal performance comparable to much larger power packages. The PWP package is designed to optimize the heat transfer to the PWB. Because of the very small size and limited mass of a TSSOP package, thermal enhancement is achieved by improving the thermal conduction paths that remove heat from the component. The thermal pad is formed using a lead-frame design (patent pending) and manufacturing technique to provide the user with direct connection to the heat-generating IC. When this pad is soldered or otherwise coupled to an external heat dissipator, high power dissipation in the ultrathin, fine-pitch, surface-mount package can be reliably achieved. DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) Figure 33. Views of Thermally-Enhanced PWP Package Because the conduction path has been enhanced, power-dissipation capability is determined by the thermal considerations in the PWB design. For example, simply adding a localized copper plane (heat-sink surface), which is coupled to the thermal pad, enables the PWP package to dissipate 2.5 W in free air (reference Figure 35(a), 8 cm2 of copper heat sink and natural convection). Increasing the heat-sink size increases the power dissipation range for the component. The power dissipation limit can be further improved by adding airflow to a PWB/IC assembly (see Figure 34 and Figure 35). The line drawn at 0.3 cm2 in Figure 34 and Figure 35 indicates performance at the minimum recommended heat-sink size, illustrated in Figure 36. 22 Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 The thermal pad is directly connected to the substrate of the IC, which for the TPS704xx series is a secondary electrical connection to device ground. The heat-sink surface that is added to the PWP can be a ground plane or left electrically isolated. In TO220-type surface-mount packages, the thermal connection is also the primary electrical connection for a given terminal which is not always ground. The PWP package provides up to 24 independent leads that can be used as inputs and outputs (Note: leads 1, 12, 13, and 24 are internally connected to the thermal pad and the IC substrate). THERMAL RESISTANCE vs COPPER HEATSINK AREA 150 RqJA - Thermal Resistance - °C/W 125 Natural Convection 50 ft/min 100 ft/min 100 150 ft/min 200 ft/min 75 50 250 ft/min 300 ft/min 25 0 0.3 1 2 3 4 6 5 Copper Heatsink Area - cm 7 8 2 Figure 34. Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 23 TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com 3.5 3.5 TA = 25°C TA = 55°C 300 ft/min 3 PD - Power Dissipation Limit - W PD - Power Dissipation Limit - W 3 150 ft/min 2.5 2 Natural Convection 1.5 1 0.5 0 300 ft/min 2.5 2 150 ft/min 1.5 Natural Convection 1 0.5 0 0.3 2 4 Copper Heatsink Size - cm 0 8 6 2 0 2 0.3 4 6 Copper Heatsink Size - cm (a) 8 2 (b) 3.5 TA = 105°C PD - Power Dissipation Limit - W 3 2.5 2 1.5 150 ft/min 300 ft/min 1 Natural Convection 0.5 0 0 0.3 2 4 6 Copper Heatsink Size - cm 8 2 (c) Figure 35. Power Ratings of the PWP Package at Ambient Temperatures of +25°C, +55°C, and +105°C 24 Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 Figure 36 is an example of a thermally-enhanced PWB layout for use with the new PWP package. This board configuration was used in the thermal experiments that generated the power ratings shown in Figure 34 and Figure 35. As discussed earlier, copper has been added on the PWB to conduct heat away from the device. RqJA for this assembly is illustrated in Figure 34 as a function of heat-sink area. A family of curves is included to illustrate the effect of airflow introduced into the system. Heatsink Area 1 oz Copper Board thickness Board size Board material Copper trace/heat sink Exposed pad mounting 62 mils 3.2 in ´ 3.2 in FR4 1 oz 63/67 tin/lead solder Figure 36. PWB Layout (Including Copper Heatsink Area) for Thermally-Enhanced PWP Package From Figure 34, RqJA for a PWB assembly can be determined and used to calculate the maximum power-dissipation limit for the component/PWB assembly, with the equation: TJmax - TA PD(max) = RqJA(system) where: • TJmax is the maximum specified junction temperature (+150°C absolute maximum limit, +125°C recommended operating limit) and TA is the ambient temperature. (1) PD(max) should then be applied to the internal power dissipated by the TPS704xx regulator. The equation for calculating total internal power dissipation of the TPS704xx is: PD(total) = VIN1 - VOUT1 ´ IOUT1 + VIN1 ´ IQ + VIN2 - VOUT2 ´ IOUT2 + VIN2 ´ IQ 2 2 (2) ( ( ( ( Since the quiescent current of the TPS704xx is very low, the second term is negligible, further simplifying the equation to: ( ( ( ( PD(total) = VIN1 - VOUT1 ´ IOUT1 + VIN2 - VOUT2 ´ IOUT2 (3) 2 For the case where TA = +55°C, airflow = 200 ft/min, copper heat-sink area = 4 cm , the maximum power-dissipation limit can be calculated. First, from Figure 34, we find the system RqJA is +50°C/W; therefore, the maximum power-dissipation limit is: TJmax - TA +125°C - 55°C PD(max) = = 1.4 W = RqJA(system) +50°C/W (4) If the system implements a TPS704xx regulator, where VIN1 = 5.0V, VIN2 = 2.8 V, IOUT1 = 500 mA, and IOUT2 = 800 mA, the internal power dissipation is: ( ( ( ( PD(total) = VIN1 - VOUT1 ´ IOUT1 + VIN2 - VOUT2 ´ IOUT2 = (5.0 - 3.3) ´ 0.5 + (2.8 - 1.8) ´ 0.8 = 1.25 W Copyright © 2000–2010, Texas Instruments Incorporated (5) Submit Documentation Feedback 25 TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com Comparing PD(total) with PD(max) reveals that the power dissipation in this example does not exceed the calculated limit. When it does, one of two corrective actions should be made: raising the power-dissipation limit by increasing the airflow or the heat-sink area, or lowering the internal power dissipation of the regulator by reducing the input voltage or the load current. In either case, the above calculations should be repeated with the new system parameters. This parameter is measured with the recommended copper heat sink pattern on a 4-layer PWB, 2 oz. copper traces on 4-in × 4-in ground layer. Simultaneous and continuous operation of both regulator outputs at full load may exceed the power dissipation rating of the PWP package. Mounting Information The primary requirement is to complete the thermal contact between the thermal pad and the PWB metal. The thermal pad is a solderable surface and is fully intended to be soldered at the time the component is mounted. Although voiding in the thermal-pad solder-connection is not desirable, up to 50% voiding is acceptable. The data included in Figure 34 and Figure 36 are for soldered connections with voiding between 20% and 50%. The thermal analysis shows no significant difference resulting from the variation in voiding percentage. Figure 37 shows the solder-mask land pattern for the PWP package. The minimum recommended heat-sink area is also illustrated. This is simply a copper plane under the body extent of the package, including metal routed under terminals 1, 12, 13, and 24. Minimum Recommended Heatsink Area Location of Exposed Thermal Pad on PWP Package Figure 37. PWP Package Land Pattern 26 Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 APPLICATION INFORMATION TPS704xxPWP (Fixed Output Option) Sequencing Timing Diagrams This section provides a number of timing diagrams showing how this device functions in different configurations. VOUT1 VIN VOUT1 VIN1 0.22 mF VSENSE1 Application condition: VIN1 and VIN2 are tied to the same fixed input voltage greater than VUVLO. PG2 is tied to MR. 22 mF 250 kW PG1 EN1 and EN2 are initially high; therefore, both regulators are off, and PG1 and PG2 (tied to MR) are at logic low. Since MR is at logic low, RESET is also at logic low. When EN1 is taken to logic low, VOUT1 turns on. Later, when EN2 is taken to logic low, VOUT2 turns on. When VOUT1 reaches 95% of its regulated output voltage, PG1 goes to logic high. When VOUT2 reaches 95% of its regulated output voltage, PG2 (tied to MR) goes to logic high. When VIN1 is greater than VUVLO and M R (tied to PG2) is at logic high, RESET is pulled to logic high after a 120-ms delay. When EN1 and EN2 are returned to logic high, both devices power down and both PG1, PG2 (tied to MR2), and RESET return to logic low. MR VIN2 0.22 mF RESET PG2 EN1 MR 250 kW RESET PG2 EN1 >2 V <0.7 V VSENSE2 EN2 EN2 >2 V VOUT2 VOUT2 <0.7 V 47 mF EN2 EN1 95% VOUT2 VOUT1 95% PG2 PG1 MR (PG2 tied to MR) RESET t1 120 ms NOTES: A. t1: Time at which VIN is greater than VUVLO and MR is logic high. B. The timing diagram is not drawn to scale. Figure 38. Timing When VOUT1 Is Enabled Before VOUT2 Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 27 TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com Application condition: VIN1 and VIN2 are tied to the same fixed input voltage greater than VUVLO. MR is initially logic high but is eventually toggled. TPS704xxPWP (Fixed Output Option) VIN EN1 and EN2 are initially high; therefore, both regulators are off, and PG1 and PG2 are at logic low. Since VIN1 is greater than VUVLO and MR is at logic high, RESET is also at logic high. When EN2 is taken to logic low, VOUT2 turns on. Later, when EN1 is taken to logic low, VOUT1 turns on. When VOUT2 reaches 95% of its regulated output voltage, PG2 goes to logic high. When VOUT1 reaches 95% of its regulated output voltage, PG1 goes to logic high. When MR is taken to logic low, RESET is taken low. When MR returns to logic high, RESET returns to logic high after a 120-ms delay. VIN1 0.22 mF VOUT1 VOUT1 VSENSE1 250 kW 22 mF 250 kW VIN2 250 kW 0.22 mF RESET RESET PG2 EN1 PG2 EN1 >2 V MR MR 2V VSENSE2 <0.7 V EN2 >2 V EN2 VOUT2 <0.7 V 0.7 V VOUT2 47 mF EN2 EN1 VOUT2 VOUT1 95% 95% PG2 PG1 MR RESET t1 120 ms NOTES: A. t1: Time at which VIN is greater than VUVLO and MR is logic high. B. The timing diagram is not drawn to scale. Figure 39. Timing When MR is Toggled 28 Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 Application condition: VIN1 and VIN2 are tied to same fixed input voltage greater than VUVLO. PG1 is tied to MR. EN1 and EN2 are initially high; therefore, both regulators are off, and PG1 (tied to MR) and PG2 are at logic low. Since MR is at logic low, RESET is also at logic low. When EN2 is taken to logic low, VOUT2 turns on. Later, when EN1 is taken to logic low, VOUT1 turns on. When VOUT2 reaches 95% of its regulated output voltage, PG2 goes to logic high. When VOUT1 reaches 95% of its regulated output voltage, PG1 goes to logic high. When VIN1 is greater than VUVLO and MR (tied to PG2) is at logic high, RESET is pulled to logic high after a 120-ms delay. When a fault on VOUT1 causes it to fall below 95% of its regulated output voltage, PG1 (tied to MR) goes to logic low. Since MR is logic low, RESET goes to logic low. VOUT2 is unaffected. TPS704xxPWP (Fixed Output Option) VIN VOUT1 VOUT1 VIN1 0.22 mF 22 mF VSENSE1 250 kW PG1 MR 250 kW VIN2 0.22 mF RESET RESET PG2 PG2 EN1 EN1 >2 V VSENSE2 <0.7 V EN2 EN2 >2 V VOUT2 VOUT2 <0.7 V 47 mF EN2 EN1 VOUT2 95% 95% VOUT1 FAULT ON VOUT1 PG2 PG1 MR (PG1 tied to MR) RESET t1 120 ms NOTES: A. t1: Time at which VIN is greater than VUVLO and MR is logic high. B. The timing diagram is not drawn to scale. Figure 40. Timing When There is a Fault on VOUT1 Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 29 TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com APPLICATION INFORMATION Input Capacitor For a typical application, a ceramic input bypass capacitor (0.22 mF to 1 mF) is recommended. This capacitor should be as close to the input pins as possible. Due to the impedance of the input supply, large transient currents cause the input voltage to droop. If this droop causes the input voltage to drop below the UVLO threshold, the device turns off. Therefore, it is recommended to place a larger capacitor in parallel with the ceramic bypass capacitor at the regulator input. The size of this capacitor depends on the output current, the response time of the main power supply, and the main power supply distance to the regulator. At a minimum, the capacitor should be sized to ensure that the input voltage does not drop below the minimum UVLO threshold voltage during normal operating conditions. Output Capacitor As with most LDO regulators, the TPS704xx requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance value for VOUT1 is 22 mF and the ESR (equivalent series resistance) must be between 50 mΩ and 800 mΩ. The minimum recommended capacitance value for VOUT2 is 47 mF and the ESR must be between 50 mΩ and 2 Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements described above. Larger capacitors provide a wider range of stability and better load transient response. Table 1 gives a partial listing of surface-mount capacitors suitable for use with the TPS704xx for fast transient response applications. This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for user applications. When necessary to achieve low height requirements along with high output current and/or high load capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above. Table 1. Partial Listing of TPS704xx-Compatible Surface-Mount Capacitors 30 VALUE MANUFACTURER MFR PART NO. 680 mF Kemet T510X6871004AS 470 mF Sanyo 4TPB470M 150 mF Sanyo 4TPC150M 220 mF Sanyo 2R5TPC220M 100 mF Sanyo 2R5TPC220M 68 mF Sanyo 10TPC68M 68 mF Kemet T495D6861006AS 47 mF Kemet T495D4761010AS 33 mF Kemet T495C3361016AS 22 mF Kemet T495C2261010AS Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 www.ti.com SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 Programming the TPS70402 Adjustable LDO Regulator The output voltage of the TPS70402 adjustable regulators is programmed using external resistor dividers as shown in Figure 41. Resistors R1 and R2 should be chosen for approximately a 50-mA divider current. Lower value resistors can be used, but offer no inherent advantage and waste more power. Higher values should be avoided as leakage currents at the sense terminal increase the output voltage error. The recommended design procedure is to choose R2 = 30.1 kΩ to set the divider current at approximately 50 mA, and then calculate R1 using Equation 6: VOUT - 1 ´ R2 R1 = VREF (6) ( ( where: • VREF = 1.224 V typ (the internal reference voltage) OUTPUT VOLTAGE PROGRAMMING GUIDE TPS70402 VI IN 0.1 mF >2.0 V OUT EN VO <0.7 V R1 + OUTPUT VOLTAGE R1 R2 UNIT 2.5 V 31.6 30.1 kW 3.3 V 51.1 30.1 kW 3.6 V 59.0 30.1 kW FB GND R2 Figure 41. TPS70402 Adjustable LDO Regulator Programming Regulator Protection Both TPS704xx PMOS-pass transistors have built-in back diodes that conduct reverse currents when the input voltage drops below the output voltage (for example, during power-down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate. The TPS704xx also features internal current limiting and thermal protection. During normal operation, the TPS704xx regulator 1 limits output current to approximately 1.75 A (typ) and regulator 2 limits output current to approximately 3.8 A (typ). When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds +150°C (typ), thermal-protection circuitry shuts it down. Once the device has cooled below +130°C (typ), regulator operation resumes. Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 31 TPS70445, TPS70448 TPS70451, TPS70458 TPS70402 SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (February 2010) to Revision F • Page Changed Tube transport media, quatity values from 70 to 60 in Ordering Information table .............................................. 3 Changes from Revision D (December, 2007) to Revision E Page • Corrected pin description for pin 21 in pinout drawing ......................................................................................................... 1 • Updated Dissipation Ratings table values ............................................................................................................................ 4 • Deleted falling edge delay specification ................................................................................................................................ 6 • Updated Fixed Voltage Version block diagram .................................................................................................................... 7 • Updated Adjustable Voltage Version block diagram ............................................................................................................ 8 32 Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 16-Apr-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS70402PWP ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70402PWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70402PWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70402PWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70445PWP ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70445PWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70445PWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70445PWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70448PWP ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70448PWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70448PWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70448PWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70451PWP ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70451PWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70451PWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70451PWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70458PWP ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70458PWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70458PWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70458PWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 16-Apr-2010 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TPS70402PWPR HTSSOP PWP 24 2000 330.0 16.4 TPS70445PWPR HTSSOP PWP 24 2000 330.0 TPS70448PWPR HTSSOP PWP 24 2000 330.0 TPS70451PWPR HTSSOP PWP 24 2000 TPS70458PWPR HTSSOP PWP 24 2000 6.95 8.3 1.6 8.0 16.0 Q1 16.4 6.95 8.3 1.6 8.0 16.0 Q1 16.4 6.95 8.3 1.6 8.0 16.0 Q1 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS70402PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 TPS70445PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 TPS70448PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 TPS70451PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 TPS70458PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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