TPS786xx www.ti.com SLVS389L – SEPTEMBER 2002 – REVISED OCTOBER 2010 ULTRALOW-NOISE, HIGH-PSRR, FAST, RF, 1.5-A LOW-DROPOUT LINEAR REGULATORS Check for Samples: TPS786xx FEATURES DESCRIPTION • 1.5-A Low-Dropout Regulator With Enable • Available in Fixed and Adjustable (1.2-V to 5.5-V) Output Versions • High PSRR (49 dB at 10 kHz) • Ultralow Noise (48 mVRMS, TPS78630) • Fast Start-Up Time (50 ms) • Stable With a 1-mF Ceramic Capacitor • Excellent Load/Line Transient Response • Very Low Dropout Voltage (390 mV at Full Load, TPS78630) • 3 × 3 SON PowerPAD™, 6-Pin SOT223 and 5-Pin DDPAK Package The TPS786xx family of low-dropout (LDO) low-power linear voltage regulators features high power-supply rejection ratio (PSRR), ultralow noise, fast start-up, and excellent line and load transient responses in small outline, SOT223-6 and DDPAK-5 packages. Each device in the family is stable, with a small 1-mF ceramic capacitor on the output. The family uses an advanced, proprietary BiCMOS fabrication process to yield extremely low dropout voltages (for example, 390 mV at 1.5 A). Each device achieves fast start-up times (approximately 50 ms with a 0.001-mF bypass capacitor) while consuming very low quiescent current (265 mA, typical). Moreover, when the device is placed in standby mode, the supply current is reduced to less than 1 mA. The TPS78630 exhibits approximately 48 mVRMS of output voltage at 3.0-V output noise with a 0.1-mF bypass capacitor. Applications with analog components that are noise sensitive, such as portable RF electronics, benefit from the high PSRR, low noise features, and the fast response time. 1 234 APPLICATIONS RF: VCOs, Receivers, ADCs Audio Bluetooth® , Wireless LAN Cellular and Cordless Telephones Handheld Organizers, PDAs DRB PACKAGE 3mm x 3mm SON (TOP VIEW) EN IN GND OUT NR/FB IN 1 IN 2 OUT 3 OUT 4 1 2 3 4 5 8 EN 7 NC 80 70 5 NR/FB 6 GND KTT (DDPAK) PACKAGE (TOP VIEW) EN IN GND OUT NR/FB TPS78630 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 6 GND 1 2 3 4 5 IOUT = 1 mA Ripple Rejection − dB DCQ PACKAGE SOT223-6 (TOP VIEW) TPS78630 RIPPLE REJECTION vs FREQUENCY 60 Output Spectral Noise Density - mV/ÖHz • • • • • VIN = 4 V COUT = 10 mF CNR = 0.01 mF 50 IOUT = 1.5 A 40 30 20 10 0 1 10 100 1k 10k 100k Frequency (Hz) 1M 10M 0.8 VIN = 5.5 V COUT = 2.2 mF CNR = 0.1 mF 0.7 0.6 0.5 0.4 0.3 IOUT = 1 mA 0.2 0.1 0.0 100 IOUT = 1.5 A 1k 10k 100k Frequency (Hz) 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments Inc. Bluetooth is a registered trademark of Bluetooth SIG, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2010, Texas Instruments Incorporated TPS786xx SLVS389L – SEPTEMBER 2002 – REVISED OCTOBER 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT TPS786xx yyy z (1) (2) VOUT (2) XX is nominal output voltage (for example, 28 = 2.8 V, 285 = 2.85 V, 01 = Adjustable). YYY is package designator. Z is package quantity. For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Output voltages from 1.3 V to 5.0 V in 100-mV increments are available; minimum order quantities may apply. Contact factory for details and availability. ABSOLUTE MAXIMUM RATINGS Over operating temperature (unless otherwise noted) (1) VALUE VIN range –0.3 V to 6 V VEN range –0.3 V to VIN + 0.3 V VOUT range 6V Peak output current Internally limited ESD rating, HBM 2 kV ESD rating, CDM 500 V Continuous total power dissipation See Thermal Information table Junction temperature range, TJ –40°C to +150°C Storage temperature range, Tstg –65°C to +150°C (1) 2 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): TPS786xx TPS786xx www.ti.com SLVS389L – SEPTEMBER 2002 – REVISED OCTOBER 2010 THERMAL INFORMATION TPS786xx (3) THERMAL METRIC (1) (2) Junction-to-ambient thermal resistance (4) qJA (5) DRB DCQ KTT 8 PINS 6 PINS 5 PINS 47.8 70.4 25 qJCtop Junction-to-case (top) thermal resistance 83 70 35 qJB Junction-to-board thermal resistance (6) N/A N/A N/A yJT Junction-to-top characterization parameter (7) 2.1 6.8 1.5 yJB Junction-to-board characterization parameter (8) 17.8 30.1 8.52 qJCbot Junction-to-case (bottom) thermal resistance (9) 12.1 6.3 0.4 (1) (2) (3) (4) (5) (6) (7) (8) (9) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A. For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator. Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations: (a) i. DRB: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array. . ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array. . iii. KTT: The exposed pad is connected to the PCB ground layer through a 5x4 thermal via array. (b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage. . ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage. . iii. KTT: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage. (c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature sections of this data sheet. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): TPS786xx 3 TPS786xx SLVS389L – SEPTEMBER 2002 – REVISED OCTOBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS Over recommended operating temperature range (TJ = –40°C to +125°C), VEN = VIN, VIN = VOUT(nom) + 1 V (1), IOUT = 1 mA, COUT = 10 mF, and CNR = 0.01 mF, unless otherwise noted. Typical values are at +25°C. PARAMETER Input voltage, VIN TEST CONDITIONS MIN (1) Internal reference, VFB (TPS78601) Output voltage range TPS78601 (2) 0 mA ≤ IOUT ≤ 1.5 A, VOUT + 1 V ≤ VIN ≤ 5.5 V (1) Accuracy V V 0 1.5 A 1.225 5.5 – VDO V (1.02)VOUT V (0.98)VOUT 1.225 VOUT Fixed VOUT <5V 0 mA ≤ IOUT ≤ 1.5 A, VOUT + 1 V ≤ VIN ≤ 5.5 V (1) –2.0 +2.0 % Fixed VOUT =5V 0 mA ≤ IOUT ≤ 1.5 A, VOUT + 1 V ≤ VIN ≤ 5.5 V (1) –3.0 +3.0 % Output voltage line regulation (ΔVOUT%/VIN) (1) Load regulation (ΔVOUT%/VOUT) Dropout voltage (3) VIN = VOUT(nom) – 0.1 V UNIT 1.250 1.200 TPS78601 MAX 5.5 Continuous output current IOUT Output voltage TYP 2.7 VOUT + 1 V ≤ VIN ≤ 5.5 V 5 0 mA ≤ IOUT ≤ 1.5 A 7 12 mV TPS78628 IOUT = 1.5 A 410 580 TPS78630 IOUT = 1.5 A 390 550 TPS78633 IOUT = 1.5 A 340 510 TPS78650 IOUT = 1.5 A 310 470 mV Output current limit VOUT = 0 V 4.2 A Ground pin current 0 mA ≤ IOUT ≤ 1.5 A 260 385 mA Shutdown current (4) VEN = 0 V, 2.7 V ≤ VIN ≤ 5.5 V 0.07 1 mA FB pin current VFB = 1.225 V 1 mA Power-supply ripple rejection TPS78630 2.4 %/V f = 100 Hz, IOUT = 10 mA 59 f = 100 Hz, IOUT = 1.5 A 52 f = 10 kHz, IOUT = 1.5 A 49 f = 100 kHz, IOUT = 1.5 A Output noise voltage (TPS78630) Time, start-up (TPS78630) BW = 100 Hz to 100 kHz, IOUT = 1.5 A RL = 2 Ω, COUT = 1 mF dB 32 CNR = 0.001 mF 66 CNR = 0.0047 mF 51 CNR = 0.01 mF 49 CNR = 0.1 mF 48 CNR = 0.001 mF 50 CNR = 0.0047 mF mVRMS 75 CNR = 0.01 mF ms 110 High-level enable input voltage 2.7 V ≤ VIN ≤ 5.5 V 1.7 VIN Low-level enable input voltage 2.7 V ≤ VIN ≤ 5.5 V 0 0.7 V EN pin current VEN = 0 –1 1 mA UVLO threshold VCC rising 2.25 UVLO hysteresis (1) (2) (3) (4) 4 2.65 100 V V mV Minimum VIN = VOUT + VDO or 2.7 V, whichever is greater. The TPS78650 is tested at VIN = 5.5 V. Tolerance of external resistors not included in this specification. Dropout is not measured for TPS78618 or TPS78625 since minimum VIN = 2.7 V. For adjustable version, this applies only after VIN is applied; then VEN transitions high to low. Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): TPS786xx TPS786xx www.ti.com SLVS389L – SEPTEMBER 2002 – REVISED OCTOBER 2010 FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION IN OUT 300Ω Current Sense UVLO Overshoot Detect GND ILIM SHUTDOWN R1 EN FB UVLO Thermal Shutdown R2 Quickstart Bandgap Reference 1.225 V VIN External to the Device VREF 250 kΩ FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION IN OUT 300Ω Current Sense UVLO Overshoot Detect GND ILIM SHUTDOWN R1 EN UVLO Thermal Shutdown R2 R2 = 40 kΩ Quickstart VIN Bandgap Reference 1.225 V VREF NR 250 kΩ PIN CONFIGURATIONS TERMINAL NAME DCQ (SOT223) KTT (DDPAK) DRB (SON) NR 5 5 5 Noise-reduction pin for fixed versions only. An external bypass capacitor, connected to this terminal, in conjunction with an internal resistor, creates a low-pass filter to further reduce regulator noise. EN 1 1 8 The EN terminal is an input that enables or shuts down the device. When EN is a logic high, the device is enabled. When the device is a logic low, the device is in shutdown mode. DESCRIPTION FB 5 5 5 Feedback input voltage for the adjustable device. GND 3, 6 3, TAB 6 Regulator ground IN 2 2 1, 2 Input supply OUT 4 4 3, 4 Regulator output Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): TPS786xx 5 TPS786xx SLVS389L – SEPTEMBER 2002 – REVISED OCTOBER 2010 www.ti.com TYPICAL CHARACTERISTICS TPS78630 OUTPUT VOLTAGE vs OUTPUT CURRENT TPS78628 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE 2.798 5 3.05 VIN = 4 V COUT = 10 µF TJ = 25°C 3.04 3.03 350 VIN = 3.8 V COUT = 10 µF 340 2.794 4 VIN = 3.8 V COUT = 10 µF IOUT = 1 mA 3.02 3.00 2.99 IGND (µA) 330 3.01 VOUT (V) VOUT (V) TPS78628 GROUND CURRENT vs JUNCTION TEMPERATURE 3 2.790 2 2.786 IOUT = 1.5 A 2.98 310 IOUT = 1 mA 2.782 1 2.97 IOUT = 1.5 A 320 300 2.96 2.778 0 −40 −25 −10 5 2.95 0.0 0.3 0.6 0.9 1.2 1.5 TJ (°C) TJ (°C) Figure 1. Figure 2. Figure 3. TPS78630 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY TPS78630 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY TPS78630 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 0.60 0.50 0.40 IOUT = 1 mA 0.20 IOUT = 1.5 A 0.00 100 6 1k 10k 100k 0.5 IOUT = 1.5 A Output Spectral Noise Density − (µV//Hz) 0.70 Output Spectral Noise Density (µV//Hz) Output Spectral Noise Density (µV//Hz) 0.6 VIN = 5.5 V COUT = 2.2 µF CNR = 0.1 µF 0.10 20 35 50 65 80 95 110 125 IOUT (A) 0.80 0.30 290 −40 −25 −10 5 20 35 50 65 80 95 110 125 VIN = 5.5 V COUT = 10 µF CNR = 0.1 µF 0.4 0.3 0.2 IOUT = 1 mA 0.1 0.0 100 1k 10k 100k 3.0 VIN = 5.5 V COUT = 10 µF IOUT = 1.5 A 2.5 CNR = 0.1 µF 2.0 CNR = 0.0047 µF 1.5 CNR = 0.01 µF 1.0 CNR = 0.001 µF 0.5 0.0 100 1k 10k Frequency (Hz) Frequency (Hz) Frequency (Hz) Figure 4. Figure 5. Figure 6. Submit Documentation Feedback 100k Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): TPS786xx TPS786xx www.ti.com SLVS389L – SEPTEMBER 2002 – REVISED OCTOBER 2010 TYPICAL CHARACTERISTICS (continued) TPS78630 ROOT MEAN SQUARED OUTPUT NOISE vs BYPASS CAPACITANCE TPS78628 DROPOUT VOLTAGE vs JUNCTION TEMPERATURE 80 80 600 VIN = 2.7 V COUT = 10 µF IOUT = 1.5 A 60 40 30 300 200 20 IOUT = 1.5 A COUT = 10 µF BW = 100 Hz to 100 kHz 10 0 0.001 µF 0.0047 µF 100 0.01 µF 1 10k 100k 1M TPS78630 RIPPLE REJECTION vs FREQUENCY VIN = 4 V COUT = 10 µF CNR = 0.1 µF 80 VIN = 4 V COUT = 2.2 µF CNR = 0.01 µF 70 20 10 60 IOUT = 1 mA 50 IOUT = 1.5 A 40 30 20 1k 10k 100k 1M 10M 50 IOUT = 1.5 A 40 30 20 0 0 100 60 10 10 0 VIN = 4 V COUT = 2.2 µF CNR = 0.1 µF 70 Ripple Rejection (dB) Ripple Rejection (dB) IOUT = 1 mA 30 10M f (Hz) TPS78630 RIPPLE REJECTION vs FREQUENCY 40 1 10 100 1k 10k 100k 1M 1 10M 10 1k 100 10k 100k 1M 10M f (Hz) f (Hz) f (Hz) Figure 10. Figure 11. Figure 12. TPS78618 LINE TRANSIENT RESPONSE TPS78630 LINE TRANSIENT RESPONSE TPS78628 LOAD TRANSIENT RESPONSE 2 4 5 1 3 dv 1V + ms dt IOUT = 1.5 A COUT = 10 µF CNR = 0.01 µF IOUT (A) 6 VIN (V) 5 4 IOUT = 1.5 A COUT = 10 µF CNR = 0.01 µF 3 80 0 −30 −60 dv 1V + ms dt 150 40 0 −40 VIN = 3.8 V COUT = 10 µF CNR = 0.01 µF di 1.5 A + ms dt 75 0 −75 −150 −80 20 40 60 80 100 120 140 160 180 200 0 −1 ∆VOUT (mV) ∆VOUT (mV) 30 0 1k TPS78630 RIPPLE REJECTION vs FREQUENCY IOUT = 1.5 A 60 100 Figure 9. 60 2 10 Figure 8. IOUT = 1 mA Ripple Rejection (dB) 20 Figure 7. 70 VIN (V) 30 0 80 10 IOUT = 1.5 A 40 TJ (°C) 80 1 50 20 35 50 65 80 95 110 125 CNR (µF) 50 IOUT = 1 mA 60 10 0 −40 −25 −10 5 0.1 µF VIN = 4 V COUT = 10 µF CNR = 0.01 µF 70 400 50 VDO (mV) RMS Output Noise (µVRMS) 500 Ripple Rejection − (dB) 70 ∆VOUT (mV) TPS78630 RIPPLE REJECTION vs FREQUENCY 0 20 40 60 80 100 120 140 160 180 200 t (µs) t (µs) Figure 13. Figure 14. 0 100 200 300 400 500 600 700 800 900 1000 t (µs) Figure 15. Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): TPS786xx 7 TPS786xx SLVS389L – SEPTEMBER 2002 – REVISED OCTOBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) TPS78630 DROPOUT VOLTAGE vs OUTPUT CURRENT TPS78625 POWER-UP/ POWER-DOWN 600 4.0 VOUT = 2.5 V RL = 1.6 Ω CNR = 0.01 µF 3.0 450 500 400 TJ = 125°C 400 VDO (mV) 2.5 2.0 1.5 TJ = 25°C 300 200 VIN TJ = −40°C 200 IOUT = 1.5 A COUT = 10 µF CNR = 0.01 µF 50 0 0 0 400 800 1200 1600 0 0 2000 200 400 600 800 1000 1200 1400 2.5 3.5 4.0 4.5 5.0 VIN (V) Figure 16. Figure 17. Figure 18. MINIMUM REQUIRED INPUT VOLTAGE vs OUTPUT VOLTAGE TPS78630 TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR) vs OUTPUT CURRENT TPS78630 TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR) vs OUTPUT CURRENT ESR − Equivalent Series Resistance (Ω) 5.0 IOUT = 1.5 A 4.5 4.0 TJ = +125°C 3.5 TJ = +25°C 3.0 2.5 2.0 100 100 COUT = 1 µF Region of Instability 10 1 Region of Stability 0.1 0.01 1.5 3.0 IOUT (mA) Time (µs) Minimum VIN (V) TJ = 25°C 250 100 100 VOUT 300 150 TJ = −40°C 1.0 0.5 TJ = 125°C 350 ESR − Equivalent Series Resistance (Ω) VOUT (V) 500 VDO (mV) 3.5 2.0 2.5 3.0 3.5 VOUT (V) Figure 19. 8 TPS78601 DROPOUT VOLTAGE vs INPUT VOLTAGE 4.0 COUT = 2.2 µF Region of Instability 10 1 Region of Stability 0.1 0.01 1 30 125 500 1000 1500 1 30 125 500 IOUT (mA) IOUT (mA) Figure 20. Figure 21. Submit Documentation Feedback 1000 1500 Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): TPS786xx TPS786xx www.ti.com SLVS389L – SEPTEMBER 2002 – REVISED OCTOBER 2010 TYPICAL CHARACTERISTICS (continued) TPS78630 TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR) vs OUTPUT CURRENT START-UP 3 COUT = 10 µF VIN = 4 V, COUT = 10 µF, IIN = 1.5 A 2.75 2.50 Region of Instability 10 CNR = 0.0047 µF 2.25 1 Region of Stability Enable CNR = 0.001 µF 2 VOUT (V) ESR − Equivalent Series Resistance (Ω) 100 1.75 1.50 CNR = 0.01 µF 1.25 1 0.1 0.75 0.50 0.25 0.01 0 1 30 125 500 1000 1500 0 100 200 300 400 IOUT (mA) t (µs) Figure 22. Figure 23. 500 600 Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): TPS786xx 9 TPS786xx SLVS389L – SEPTEMBER 2002 – REVISED OCTOBER 2010 www.ti.com APPLICATION INFORMATION The TPS786xx family of low-dropout (LDO) regulators has been optimized for use in noise-sensitive equipment. The device features extremely low dropout voltages, high PSRR, ultralow output noise, low quiescent current (265 mA, typically), and enable input to reduce supply currents to less than 1 mA when the regulator is turned off. A typical application circuit is shown in Figure 24. VIN IN VOUT OUT TPS786xx 2.2 mF EN GND 2.2 mF NR 0.01 mF Figure 24. Typical Application Circuit EXTERNAL CAPACITOR REQUIREMENTS A 2.2-mF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the TPS786xx, is required for stability and improves transient response, noise rejection, and ripple rejection. A higher-value input capacitor may be necessary if large, fast-rise-time load transients are anticipated and the device is located several inches from the power source. Like most low-dropout regulators, the TPS786xx requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitor is 1 mF. Any 1 mF or larger ceramic capacitor is suitable. The internal voltage reference is a key source of noise in an LDO regulator. The TPS786xx has an NR pin which is connected to the voltage reference through a 250-kΩ internal resistor. The 250-kΩ internal resistor, in conjunction with an external bypass capacitor connected to the NR pin, creates a low pass filter to reduce the voltage reference noise and, therefore, the noise at the regulator output. In 10 order for the regulator to operate properly, the current flow out of the NR pin must be at a minimum, because any leakage current creates an IR drop across the internal resistor, thus creating an output error. Therefore, the bypass capacitor must have minimal leakage current. The bypass capacitor should be no more than 0.1-mF to ensure that it is fully charged during the quickstart time provided by the internal switch shown in the functional block diagram. For example, the TPS78630 exhibits only 48 mVRMS of output voltage noise using a 0.1-mF ceramic bypass capacitor and a 10-mF ceramic output capacitor. Note that the output starts up slower as the bypass capacitance increases due to the RC time constant at the bypass pin that is created by the internal 250-kΩ resistor and external capacitor. BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE To improve ac measurements like PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the ground pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the ground pin of the device. REGULATOR MOUNTING The tab of the SOT223-6 package is electrically connected to ground. For best thermal performance, the tab of the surface-mount version should be soldered directly to a circuit-board copper area. Increasing the copper area improves heat dissipation. Solder pad footprint recommendations for the devices are presented in Application Report SBFA015, Solder Pad Recommendations for Surface-Mount Devices, available from the TI web site at www.ti.com. Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): TPS786xx TPS786xx www.ti.com SLVS389L – SEPTEMBER 2002 – REVISED OCTOBER 2010 PROGRAMMING THE TPS78601 ADJUSTABLE LDO REGULATOR The approximate value of this capacitor can be calculated using Equation 3: (3 x 10−7) x (R 1 ) R 2) C1 + (R1 x R 2) (3) The output voltage of the TPS78601 adjustable regulator is programmed using an external resistor divider as shown in Figure 25. The output voltage is calculated using Equation 1: V OUT + VREF ǒ 1) R1 R2 Ǔ The suggested value of this capacitor for several resistor ratios is shown in the table below. If this capacitor is not used (such as in a unity-gain configuration), then the minimum recommended output capacitor is 2.2 mF instead of 1 mF. (1) where: • VREF = 1.2246 V typ (the internal reference voltage) REGULATOR PROTECTION The TPS786xx PMOS-pass transistor has a built-in back diode that conducts reverse current when the input voltage drops below the output voltage (for example, during power down). Current is conducted from the output to the input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting might be appropriate. Resistors R1 and R2 should be chosen for approximately 40-mA divider current. Lower value resistors can be used for improved noise performance, but the device wastes more power. Higher values should be avoided, as leakage current at FB increases the output voltage error. The TPS786xx features internal current limiting and thermal protection. During normal operation, the TPS786xx limits output current to approximately 2.8 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds approximately +165°C, thermal-protection circuitry shuts it down. Once the device has cooled down to below approximately +140°C, regulator operation resumes. The recommended design procedure is to choose R2 = 30.1 kΩ to set the divider current at 40 mA, C1 = 15 pF for stability, and then calculate R1 using Equation 2: R1 + ǒ VOUT *1 VREF Ǔ R2 (2) In order to improve the stability of the adjustable version, it is suggested that a small compensation capacitor be placed between OUT and FB. OUTPUT VOLTAGE PROGRAMMING GUIDE VIN IN 2.2 mF OUT TPS78601 EN GND VOUT R1 C1 2.2 mF OUTPUT VOLTAGE R1 R2 C1 1.8 V 14.0 kW 30.1 kW 33 pF 3.6 V 57.9 kW 30.1 kW 15 pF FB R2 Figure 25. TPS78601 Adjustable LDO Regulator Programming Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): TPS786xx 11 TPS786xx SLVS389L – SEPTEMBER 2002 – REVISED OCTOBER 2010 www.ti.com THERMAL INFORMATION Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad is critical to avoiding thermal shutdown and ensuring reliable operation. Power dissipation of the device depends on input voltage and load conditions and can be calculated using Equation 4: P D + ǒVIN * VOUTǓ I OUT (4) Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation. Knowing the maximum RqJA, the minimum amount of PCB copper area needed for appropriate heatsinking can be estimated using Figure 26. 160 DCQ DRB KTT 140 120 qJA (°C/W) POWER DISSIPATION 100 80 60 40 20 0 On the SON (DRB) package, the primary conduction path for heat is through the exposed pad to the printed circuit board (PCB). The pad can be connected to ground or be left floating; however, it should be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. On both SOT-223 (DCQ) and DDPAK (KTT) packages, the primary conduction path for heat is through the tab to the PCB. That tab should be connected to ground. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device and can be calculated using Equation 5: ()125OC * T A) R qJA + PD (5) 12 0 Note: 1 2 4 5 7 3 6 Board Copper Area (in2) 8 9 10 qJA value at board size of 9in2 (that is, 3in × 3in) is a JEDEC standard. Figure 26. qJA vs Board Size Figure 26 shows the variation of qJA as a function of ground plane copper area in the board. It is intended only as a guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate actual thermal performance in real application environments. NOTE: When the device is mounted on an application PCB, it is strongly recommended to use ΨJT and ΨJB, as explained in the Estimating Junction Temperature section. Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): TPS786xx TPS786xx www.ti.com SLVS389L – SEPTEMBER 2002 – REVISED OCTOBER 2010 ESTIMATING JUNCTION TEMPERATURE 35 YJB: TJ = TB + YJB · PD 30 YJT and YJB (°C/W) Using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature can be estimated with corresponding formulas (given in Equation 6). For backwards compatibility, an older qJC,Top parameter is listed as well. YJT: TJ = TT + YJT · PD (6) For more information about measuring TT and TB, see the application note SBVA025, Using New Thermal Metrics, available for download at www.ti.com. By looking at Figure 27, the new thermal metrics (ΨJT and ΨJB) have very little dependency on board size. That is, using ΨJT or ΨJB with Equation 6 is a good way to estimate TJ by simply measuring TT or TB, regardless of the application board size. 20 15 10 DCQ YJT 5 Where PD is the power dissipation shown by Equation 5, TT is the temperature at the center-top of the IC package, and TB is the PCB temperature measured 1mm away from the IC package on the PCB surface (as Figure 28 shows). NOTE: Both TT and TB can be measured on actual application boards using a thermo-gun (an infrared thermometer). DCQ DRB YJB KTT 25 DRB YJT 0 0 1 2 3 4 5 7 6 8 9 10 Board Copper Area (in2) Figure 27. ΨJT and ΨJB vs Board Size For a more detailed discussion of why TI does not recommend using qJC(top) to determine thermal characteristics, refer to application report SBVA025, Using New Thermal Metrics, available for download at www.ti.com. For further information, refer to application report SPRA953, IC Package Thermal Metrics, also available on the TI website. (1) TB 1mm KTT YJT TT on top of IC X TT on top of IC TB on PCB surface TB on PCB TT surface (2) 1mm X 1mm (a) Example DRB (SON) Package Measurement (b) Example DCQ (SOT-223) Package Measurement (1) TT is measured at the center of both the X- and Y-dimensional axes. (2) TB is measured below the package lead on the PCB surface. (c) Example KTT (DDPAK) Package Measurement Figure 28. Measuring Points for TT and TB Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): TPS786xx 13 TPS786xx SLVS389L – SEPTEMBER 2002 – REVISED OCTOBER 2010 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision K (August, 2010) to Revision L • Page Corrected typo in Figure 28 ................................................................................................................................................ 13 Changes from Revision J (May, 2009) to Revision K Page • Replaced the Dissipation Ratings table with the Thermal Information Table ....................................................................... 3 • Revised Thermal Information section ................................................................................................................................. 12 14 Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): TPS786xx PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty TPS78601DCQ ACTIVE SOT-223 DCQ 6 TPS78601DCQG4 ACTIVE SOT-223 DCQ 6 TPS78601DCQR ACTIVE SOT-223 DCQ 6 TPS78601DCQRG4 ACTIVE SOT-223 DCQ TPS78601DRBR ACTIVE SON TPS78601DRBT ACTIVE TPS78601KTT 78 Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TBD Call TI Call TI -40 to 125 2500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 PS78601 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS78601 DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OCI SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OCI OBSOLETE DDPAK/ TO-263 KTT 5 TBD Call TI Call TI -40 to 125 TPS78601KTTR ACTIVE DDPAK/ TO-263 KTT 5 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS 78601 TPS78601KTTRG3 ACTIVE DDPAK/ TO-263 KTT 5 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS 78601 TPS78601KTTT ACTIVE DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 78601 TPS78601KTTTG3 ACTIVE DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 78601 TPS78618DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS78618 TPS78618DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS78618 TPS78618DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS78618 TPS78618DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS78618 TPS78618KTT OBSOLETE DDPAK/ TO-263 KTT 5 TBD Call TI Call TI -40 to 125 TPS78618KTTR ACTIVE DDPAK/ TO-263 KTT 5 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR 500 Addendum-Page 1 PS78601 TPS 78618 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 18-Jul-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) TPS78618KTTRE3 ACTIVE DDPAK/ TO-263 KTT 5 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS 78618 TPS78618KTTRG3 ACTIVE DDPAK/ TO-263 KTT 5 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS 78618 TPS78618KTTT ACTIVE DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 78618 TPS78618KTTTG3 ACTIVE DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 78618 TPS78625DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS78625 TPS78625DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS78625 TPS78625DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS78625 TPS78625DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS78625 TPS78625KTT OBSOLETE DDPAK/ TO-263 KTT 5 TBD Call TI Call TI -40 to 125 TPS78625KTTR ACTIVE DDPAK/ TO-263 KTT 5 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS 78625 TPS78625KTTRG3 ACTIVE DDPAK/ TO-263 KTT 5 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS 78625 TPS78625KTTT ACTIVE DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 78625 TPS78625KTTTG3 ACTIVE DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 78625 TPS78628DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS78628 TPS78628DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS78628 TPS78628KTT OBSOLETE DDPAK/ TO-263 KTT 5 TBD Call TI Call TI -40 to 125 TPS78628KTTT ACTIVE DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 78628 TPS78628KTTTG3 ACTIVE DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 78628 Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 18-Jul-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) TPS78630DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS78630 TPS78630DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS78630 TPS78630DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS78630 TPS78630DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS78630 TPS78630KTT OBSOLETE DDPAK/ TO-263 KTT 5 TBD Call TI Call TI -40 to 125 TPS78630KTTT ACTIVE DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 78630 TPS78630KTTTG3 ACTIVE DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR -40 to 125 TPS 78630 TPS78633DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS78633 TPS78633DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS78633 TPS78633DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS78633 TPS78633DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PS78633 TPS78633KTT OBSOLETE DDPAK/ TO-263 KTT 5 TBD Call TI Call TI -40 to 125 TPS78633KTTR ACTIVE DDPAK/ TO-263 KTT 5 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS 78633 TPS78633KTTRE3 ACTIVE DDPAK/ TO-263 KTT 5 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS 78633 TPS78633KTTRG3 ACTIVE DDPAK/ TO-263 KTT 5 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS 78633 TPS78633KTTT ACTIVE DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR (1) -40 to 125 The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. Addendum-Page 3 TPS 78633 Samples PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2013 PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 4 PACKAGE MATERIALS INFORMATION www.ti.com 9-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TPS78601DCQRG4 SOT-223 DCQ 6 2500 330.0 12.4 TPS78601DRBR SON DRB 8 3000 330.0 TPS78601DRBT SON DRB 8 250 180.0 TPS78601KTTR DDPAK/ TO-263 KTT 5 500 TPS78601KTTT DDPAK/ TO-263 KTT 5 TPS78618DCQR SOT-223 DCQ TPS78618KTTR DDPAK/ TO-263 TPS78618KTTRE3 7.05 7.45 1.88 8.0 12.0 Q3 12.4 3.3 3.3 1.1 8.0 12.0 Q2 12.4 3.3 3.3 1.1 8.0 12.0 Q2 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3 KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS78618KTTT DDPAK/ TO-263 KTT 5 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS78625DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3 TPS78625KTTR DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS78625KTTT DDPAK/ TO-263 KTT 5 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS78628DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 9-Sep-2013 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 10.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.6 4.9 16.0 24.0 Q2 TPS78628KTTT DDPAK/ TO-263 KTT 5 50 330.0 24.4 TPS78630DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3 TPS78630KTTT DDPAK/ TO-263 KTT 5 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS78633DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3 TPS78633KTTR DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS78633KTTRE3 DDPAK/ TO-263 KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 TPS78633KTTT DDPAK/ TO-263 KTT 5 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS78601DCQRG4 SOT-223 DCQ 6 2500 358.0 335.0 35.0 TPS78601DRBR SON DRB 8 3000 367.0 367.0 35.0 TPS78601DRBT SON DRB 8 250 210.0 185.0 35.0 TPS78601KTTR DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 TPS78601KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0 TPS78618DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 9-Sep-2013 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS78618KTTR DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 TPS78618KTTRE3 DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 TPS78618KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0 TPS78625DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0 TPS78625KTTR DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 TPS78625KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0 TPS78628DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0 TPS78628KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0 TPS78630DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0 TPS78630KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0 TPS78633DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0 TPS78633KTTR DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 TPS78633KTTRE3 DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 TPS78633KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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