TI LM118H/883

LM118QML
LM118QML Operational Amplifier
Literature Number: SNOSAJ3
LM118QML
Operational Amplifier
General Description
The LM118 is a precision high speed operational amplifier
designed for applications requiring wide bandwidth and high
slew rate. It features a factor of ten increase in speed over
general purpose devices without sacrificing DC performance.
The LM118 has internal unity gain frequency compensation.
This considerably simplifies its application since no external
components are necessary for operation. However, unlike
most internally compensated amplifiers, external frequency
compensation may be added for optimum performance. For
inverting applications, feed forward compensation will boost
the slew rate to over 150V/µs and almost double the bandwidth. Overcompensation can be used with the amplifier for
greater stability when maximum bandwidth is not needed.
Further, a single capacitor can be added to reduce the 0.1%
settling time to under 1 µs.
The high speed and fast settling time of this op amp makes
it useful in A/D converters, oscillators, active filters, sample
and hold circuits, or general purpose amplifiers. This device
is easy to apply and offers an order of magnitude better AC
performance than industry standards such as the LM709.
Features
n
n
n
n
n
n
n
15 MHz small signal bandwidth
Guaranteed 50V/µs slew rate
Maximum bias current of 250 nA
Operates from supplies of ± 5V to ± 20V
Internal frequency compensation
Input and output overload protected
Pin compatible with general purpose op amps
Ordering Information
NS Part Number
NS Package Number
Package Description
LM118H/883
JAN Part Number
H08C
8LD TO-99 Metal Can
LM118J-8/883
J08A
8LD CERDIP
LM118J/883
J14A
LM118WG/883
14LD CERDIP
WG10A
10LD Ceramic SOIC
Fast Voltage Follower
(Note 1)
20128313
Note 1: Do not hard-wire as voltage follower (R1 ≥ 5 kΩ)
© 2005 National Semiconductor Corporation
DS201283
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LM118QML Operational Amplifier
July 2005
LM118QML
Connection Diagram
Metal Can Package
(Note 2)
Dual-In-Line Package
20128302
20128324
Top View
See NS Package Number J14A
Top View
See NS Package Number H08C
Dual-In-Line Package
Ceramic SOIC Package
20128363
Top View
See NS Package Number WG10A
20128303
Top View
See NS Package Number J08A
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Note 2: Pin connections shown on schematic diagram and typical applications are for TO-5 package.
2
LM118QML
Schematic Diagram
20128301
3
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LM118QML
Absolute Maximum Ratings (Note 3)
± 20V
Supply Voltage
Power Dissipation (Note 4)
8 LD Metal Can
750mW
8LD CERDIP
1000mW
14LD CERDIP
1250mW
10LD Ceramic SOIC
600mW
± 10 mA
± 15V
Differential Input Current (Note 5)
Input Voltage (Note 6)
Output Short-Circuit Duration
Continuous
Operating Temperature Range
−55˚C ≤ TA ≤ +125˚C
Thermal Resistance
θJA
8 LD Metal Can (Still Air @ 0.5W)
160˚C/W
8 LD Metal Can (500LF / Min Air flow @ 0.5W)
86˚C/W
8LD CERDIP (Still Air @ 0.5W)
120˚C/W
8LD CERDIP (500LF / Min Air flow @ 0.5W)
66˚C/W
14LD CERDIP (Still Air @ 0.5W)
87˚C/W
14LD CERDIP (500LF / Min Air flow @ 0.5W)
51˚C/W
10LD Ceramic SOIC (Still Air @ 0.5W)
198˚C/W
10LD Ceramic SOIC (500LF / Min Air flow @ 0.5W)
124˚C/W
θJC
8 LD Metal Can
48˚C/W
8LD CERDIP
17˚C/W
14LD CERDIP
17˚C/W
10LD Ceramic SOIC
22˚C/W
Storage Temperature Range
−65˚C ≤ TA ≤ +150˚C
Lead Temperature (Soldering, 10 seconds)
300˚C
ESD Tolerance (Note 7)
2000V
Quality Conformance Inspection
Mil-Std-883, Method 5005; Group A
Subgroup
Description
1
Static tests at
25
2
Static tests at
125
3
Static tests at
-55
4
Dynamic tests at
25
5
Dynamic tests at
125
6
Dynamic tests at
-55
7
Functional tests at
25
8A
Functional tests at
125
8B
Functional tests at
-55
9
Switching tests at
25
10
Switching tests at
125
11
Switching tests at
-55
12
Settling time at
25
13
Settling time at
125
14
Settling time at
-55
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4
Temp˚C
LM118QML
LM118
883 Electrical Characteristics
DC Parameters
The following conditions apply, unless otherwise specified.
DC
Symbol
VIO
VCC = ± 15V, VCM = 0V
Parameter
Input Offset Voltage
Conditions
Notes
Max
Unit
-4.0
+4.0
mV
1
-6.0
+6.0
mV
2, 3
-4.0
+4.0
mV
1
-6.0
+6.0
mV
2, 3
VCC = ± 20V, VCM = ± 15V,
RS = 50Ω
-4.0
+4.0
mV
1
-6.0
+6.0
mV
2, 3
VCC = ± 5V, RS = 50Ω
-4.0
+4.0
mV
1
-6.0
+6.0
mV
2, 3
-50
+50
nA
1
-100
+100
nA
2, 3
-50
+50
nA
1
-100
+100
nA
2, 3
-50
+50
nA
1
-100
+100
nA
2, 3
1.0
250
nA
1
1.0
500
nA
2, 3
1.0
250
nA
1
1.0
500
nA
2, 3
1.0
250
nA
1
1.0
500
nA
2, 3
VCM = ± 11.5V, RS = 50Ω
VCC = ± 20V, RS = 50Ω
IIO
Input Offset Current
VCM = ± 11.5V, RS = 10KΩ
VCC = ± 20V, RS = 10KΩ
VCC = ± 5V, RS = 10KΩ
IIB
Input Bias Current
VCM = ± 11.5V, RS= 10KΩ
VCC = ± 20V, RS = 10KΩ
VCC = ± 5V, RS = 10KΩ
PSRR
Power Supply Rejection Ratio
CMRR
+IOS
Short Circuit Current
t < 25mS
-65
Short Circuit Current
t < 25mS
-IOS
ICC
+VCC = 20V to 5V, RS = 50Ω
70
dB
1, 2, 3
-VCC = -20V to -5V, RS = 50Ω
70
dB
1, 2, 3
Common Mode Rejection Ratio VCC = ± 15V, VCM = ± 11.5V,
RS = 50Ω
80
dB
1, 2, 3
-5.0
mA
1, 2, 3
5.0
65
mA
1, 2
5.0
80
mA
3
8.0
mA
1
7.0
mA
2
11
mA
3
-4.0
mV
1
MΩ
1
V
1, 2, 3
Power Supply Current
VIO adj.
Input Offset Voltage Adjust
RI
Input Resistance
VCC = ± 20V
VCC = ± 20V
4.0
(Note 9)
= ± 15V
VI
Input Voltage Range
VCC
AVS
Large Signal Voltage Gain
RL = 2KΩ, VO = 0 to -10V
(Note 8)
RL = 2KΩ, VO = 0 to +10V
Output Voltage Swing
RL= 2KΩ
1.0
-11.5 +11.5
(Note 10)
50
V/mV
4
(Note 10)
25
V/mV
5, 6
(Note 10)
50
V/mV
4
(Note 10)
VO
Subgroups
Min
25
+12
5
-12
V/mV
5, 6
V
4, 5, 6
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LM118QML
LM118
883 Electrical Characteristics
(Continued)
AC Parameters
The following conditions apply parameters, unless otherwise specified.
AC
VCC = ± 15V, VCM = 0V,
Symbol
SR
RS = 0Ω, RL = 2KΩ,, CL = 33pF
Parameter
Slew Rate
Conditions
Notes
Min
Max
Unit
Subgroups
VCC = ± 20V, VI = -5V to +5V,
AV=1
50
V/µS
7
VCC = ± 20V, VI = +5V to -5V,
AV=1
50
V/µS
7
Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package junction
to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/θJA or the
number given in the Absolute Maximum Ratings, whichever is lower.
Note 5: The inputs are shunted with back-to-back diodes for over voltage protection. Therefore, excessive current will flow if a differential input voltage in excess
of 1V is applied between the inputs unless some limiting resistance is used.
Note 6: For supply voltages less than ± 15V, the absolute maximum input voltage is equal to the supply voltage.
Note 7: Human body model, 1.5 kΩ in series with 100 pF.
Note 8: Guaranteed by CMRR
Note 9: Guaranteed parameter not tested
Note 10: Datalog in K = V/mV
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6
LM118QML
Typical Performance Characteristics
Input Current
Voltage Gain
20128326
20128325
Power Supply Rejection
Input Noise Voltage
20128327
20128328
Common Mode Rejection
Supply Current
20128329
20128330
7
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LM118QML
Typical Performance Characteristics
(Continued)
Closed Loop Output
Impedance
Current Limiting
20128332
20128331
Input Current
Unity Gain Bandwidth
20128334
20128333
Voltage Follower Slew Rate
Inverter Settling Time
20128336
20128335
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8
LM118QML
Typical Performance Characteristics
(Continued)
Large Signal Frequency
Response
Open Loop Frequency
Response
20128337
20128338
Voltage Follower Pulse
Response
Large Signal Frequency
Response
20128340
20128339
Open Loop Frequency
Response
Inverter Pulse Response
20128342
20128341
9
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LM118QML
Auxiliary Circuits
Offset Balancing
Feedforward Compensation
for Greater Inverting Slew Rate
(Note 11)
20128310
Isolating Large Capacitive Loads
20128308
*Balance circuit necessary for increased slew.
Note 11: Slew rate typically 150V/µs.
Compensation for Minimum Settling Time
(Note 12)
20128311
Overcompensation
20128312
20128309
Note 12: Slew and settling time to 0.1% for a 10V step change is 800 ns.
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10
LM118QML
Typical Applications
Fast Voltage Follower
(Note 13)
20128313
Integrator or Slow Inverter
20128314
CF = Large
(CF ≥ 50 pF)
*Do not hard-wire as integrator or slow inverter; insert a 10k-5 pF network in series with the input, to prevent oscillation.
Note 13: Do not hard-wire as voltage follower (R1 ≥ 5 kΩ)
Differential Amplifier
Fast Summing Amplifier
20128316
20128315
11
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LM118QML
Typical Applications
(Continued)
Fast Sample and Hold
20128318
D/A Converter Using Ladder Network
20128319
*Optional — Reduces settling time.
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12
LM118QML
Typical Applications
(Continued)
Four Quadrant Multiplier
20128317
∆Output zero.
*“Y” zero
+“X” zero
‡ Full scale adjust.
D/A Converter Using Binary Weighted Network
20128320
*Optional — Reduces settling time.
13
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LM118QML
Typical Applications
(Continued)
Fast Summing Amplifier with Low Input Current
20128321
Instrumentation Amplifier
Wein Bridge Sine Wave Oscillator
20128322
20128323
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14
LM118QML
Revision History Section
Date
Released
07/12/05
Revision
A
Section
Originator
New Release, Corporate format
L. Lytle
15
Changes
1 MDS data sheet, MNLM118–X Rev 0A0
was converted into the Corp. datasheet
format. MDS datasheet will be archived.
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LM118QML
Physical Dimensions
inches (millimeters) unless otherwise noted
Metal Can Package (H)
NS Package Number H08C
Ceramic Dual-In-Line Package (J)
NS Package Number J08A
Ceramic Dual-In-Line Package (J)
NS Package Number J14A
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16
LM118QML Operational Amplifier
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Ceramic SOIC (WG)
NS Package Number WG10A
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