TI LF412JAN

LF412JAN
LF412JAN Low Offset, Low Drift Dual JFET Input Operational Amplifier
Literature Number: SNOSAQ7
LF412JAN
Low Offset, Low Drift Dual JFET Input Operational
Amplifier
General Description
Features
This device is a low cost, high speed, JFET input operational
amplifier with very low input offset voltage and guaranteed
input offset voltage drift. It requires low supply current yet
maintains a large gain bandwidth product and fast slew rate.
In addition, well matched high voltage JFET input devices
provide very low input bias and offset currents. The LF412
dual is pin compatible with the LM1558, allowing designers to
immediately upgrade the overall performance of existing designs.
This amplifier may be used in applications such as high speed
integrators, fast D/A converters, sample and hold circuits and
many other circuits requiring low input offset voltage and drift,
low input bias current, high input impedance, high slew rate
and wide bandwidth.
■
■
■
■
■
■
■
■
■
Input offset voltage drift: 30 μV/°C (max)
Low input bias current: 50 pA (Typ)
Wide gain bandwidth: 3 MHz (Typ)
High slew rate: 7V/μs (min)
High input impedance: 1012Ω
Low total harmonic distortion <0.02%
Low 1/f noise corner: 50 Hz
Fast settling time to 0.01%: 2 μs
(Typ)
Low input noise current:
Ordering Information
NS Part Number
JAN Part Number
NS Package Number
Package Description
JL412BPA
JM38510/11905BPA
J08A
8LD CERDIP
Connection Diagram
Dual-In-Line Package
20153644
See NS Package Number J08A
BI-FET II™ is a trademark of National Semiconductor Corporation.
© 2010 National Semiconductor Corporation
201536
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LF412JAN Low Offset, Low Drift Dual JFET Input Operational Amplifier
December 8, 2010
LF412JAN
Simplified Schematic
1/2 Dual
20153643
Detailed Schematic
20153632
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2
LF412JAN
Absolute Maximum Ratings (Note 1)
Supply Voltage
Differential Input Voltage
Input voltage Range(Note 3)
Output Short Circuit Duration (Note 4)
Power Dissipation(Note 2)
CERDIP Package
TJmax
Thermal Resistance
±18V
±30V
±15V
Continuous
800mW
175°C
θJA
CERDIP Package (Still Air)
CERDIP Package (500 LF/Min Air Flow)
122°C/W
66°C/W
θJC
CERDIP Package
Supply voltage Range
Operating Temperature Range
15°C/W
±5V to ±15V
−55°C ≤ TA ≤ 125°C
−65°C ≤ TA ≤ 150°C
260°C
1,700V
Storage Temperature Range
Lead Temperature Soldering (10 Sec)
ESD Tolerance(Note 5)
Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A
Subgroup
Description
Temp (°C)
1
Static tests at
+25
2
Static tests at
+125
3
Static tests at
-55
4
Dynamic tests at
+25
5
Dynamic tests at
+125
6
Dynamic tests at
-55
7
Functional tests at
+25
8A
Functional tests at
+125
8B
Functional tests at
-55
9
Switching tests at
+25
10
Switching tests at
+125
11
Switching tests at
-55
12
Settling time at
+25
13
Settling time at
+125
14
Settling time at
-55
3
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LF412JAN
Electrical Characteristics
DC Parameters
The following conditions apply, unless otherwise specified.
Symbol
VIO
Parameter
Input Offset Voltage
±VCC = ±15V, VCM = 0V
Conditions
Notes
Max
Unit
+VCC = 26V, -VCC = -4V,
VCM = -11V
-5.0
5.0
mV
1
-7.0
7.0
mV
2, 3
+VCC = 4V, -VCC = -26V,
VCM = 11V
-5.0
5.0
mV
1
-7.0
7.0
mV
2, 3
-5.0
5.0
mV
1
-7.0
7.0
mV
2, 3
-5.0
5.0
mV
1
-7.0
7.0
mV
2, 3
-0.4
0.2
nA
1
±VCC = ±5V
+VCC = 26V, -VCC = -4V,
VCM = -11V
±IIB
Input Bias Current
+VCC = 4V, -VCC = -26V,
VCM = 11V
IIO
Subgroup
Min
Input Offset Current
-10
50
nA
2
-0.2
0.2
nA
1
-10
50
nA
2
-0.2
1.2
nA
1
-10
70
nA
2
-0.1
0.1
nA
1
-20
20
nA
2
+PSRR
Power Supply Rejection Ratio
+VCC = 20V to 10V,
-VCC = -15V
-PSRR
Power Supply Rejection Ratio
+VCC = 15V,
-VCC = -20V to -10V
80
dB
1, 2, 3
CMRR
Input Voltage Common Mode
Rejection
VCM = -11V to +11V
80
dB
1, 2, 3
+IOS
Output Short Circuit Current
t ≤ 25mS
-80
mA
1, 2, 3
-IOS
Output Short Circuit Current
t ≤ 25mS
80
mA
1, 2, 3
ICC
Supply Current
7.0
mA
1, 2
8.0
mA
3
-30
30
µV/°C
2
-30
30
µV/°C
3
V
4, 5, 6
ΔVIO / ΔT
Input Offset Voltage
+VOP
Output Voltage Swing
25°C ≤ TA ≤ +125°C
-55°C ≤ TA ≤ 25°C
(Note 6)
dB
1, 2, 3
RL = 10KΩ
12
RL = 2KΩ
10
V
4, 5, 6
RL = 10KΩ
-12
V
4, 5, 6
RL = 2KΩ
-10
V
4, 5, 6
-VOP
Output Voltage Swing
-AVS
Open Loop Voltage Gain
RL = 2KΩ, VO = -10V
(Note 8)
+AVS
Open Loop Voltage Gain
RL = 2KΩ, VO = 10V
(Note 8)
AVS
Open Loop Voltage Gain
RL = 10KΩ, VO = ±2V,
±VCC = ±5V
(Note 8)
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80
4
50
V/mV
4
25
V/mV
5, 6
50
V/mV
4
25
V/mV
5, 6
20
V/mV
4, 5, 6
The following conditions apply, unless otherwise specified.
Symbol
Parameter
±VCC = ±15V, VCM = 0V
Conditions
AV = 1, VI = 50mV,
Max
Unit
Subgroup
(Note 7)
200
nS
7, 8A, 8B
(Note 7)
40
%
7, 8A, 8B
Notes
TRTR
Transient Response Rise Time
TROS
Transient Response Overshoot
SR+
Slew Rate
VI = -5V to +5V
SR-
Slew Rate
VI = +5V to -5V
NIBB
Noise Broadband
BW = 10Hz to 15KHz,
RS = 0Ω
(Note 9)
NIPC
Noise Popcorn
BW = 10Hz to 15KHz,
RS = 100KΩ
(Note 9)
CS
Channel Separation
RL = 2KΩ, VI = ±10V
(Note 9)
±tS
Settling Time
AV = 1
(Note 7)
CL = 100pF, RL = 2KΩ
AV = 1, VI = 50mV,
CL = 100pF, RL = 2KΩ
Min
7.0
V/µS
7
5.0
V/µS
8A, 8B
7.0
V/µS
7
5.0
V/µS
8A, 8B
15
µVRMS
7
80
µVPK
7
dB
7
1500
nS
12
Min
Max
Unit
Subgroup
80
DC Drift Parameters
The following conditions apply, unless otherwise specified.
Delta calculations are performed at group B5, only.
Symbol
Parameter
±VCC = ±15V, VCM = 0V
Conditions
Notes
VIO
Input Offset Voltage
-1.0
1.0
mV
1
±IIB
Input Bias Current
-0.1
0.1
nA
1
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package
junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/
θJA or the number given in the Absolute Maximum Ratings, whichever is lower.
Note 3: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
Note 4: Any of the amplifier outputs can be shorted to ground indefinitely, however, more than one should not be simultaneously shorted as the maximum junction
temperature will be exceeded.
Note 5: Human body model, 1.5 kΩ in series with 100 pF.
Note 6: Calculated parameter.
Note 7: Bench test.
Note 8: Datalog reading in K = V/mV.
Note 9: Test on either A360, AC or bench test.
5
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LF412JAN
AC Parameters
LF412JAN
Typical Connection
20153641
Typical Performance Characteristics
Input Bias Current
Input Bias Current
20153610
20153611
Supply Current
Positive Common-Mode
Input Voltage Limit
20153612
20153613
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6
LF412JAN
Negative Common-Mode
Input Voltage Limit
Positive Current Limit
20153615
20153614
Negative Current Limit
Output Voltage Swing
20153616
20153617
Output Voltage Swing
Gain Bandwidth
20153619
20153618
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LF412JAN
Bode Plot
Slew Rate
20153621
20153620
Distortion vs Frequency
Undistorted Output Voltage
Swing
20153622
20153623
Open Loop Frequency
Response
Common-Mode Rejection
Ratio
20153625
20153624
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8
LF412JAN
Power Supply Rejection
Ratio
Equivalent Input Noise
Voltage
20153626
20153627
Output Impedance
Open Loop Voltage Gain
20153628
20153629
Inverter Settling Time
20153630
9
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LF412JAN
Pulse Response
RL=2 kΩ, CL=10 pF
Small Signal Inverting
Small Signal Non-Inverting
20153636
20153637
Large Signal Inverting
Large Signal Non-Inverting
20153639
20153638
Current Limit (RL=100Ω)
20153640
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10
The LF412 JFET input dual op amp is internally trimmed (BIFET II™) providing very low input offset voltages and guaranteed input offset voltage drift. These JFETs have large
reverse breakdown voltages from gate to source and drain
eliminating the need for clamps across the inputs. Therefore,
large differential input voltages can easily be accommodated
without a large increase in input current. The maximum differential input voltage is independent of the supply voltages.
However, neither of the input voltages should be allowed to
exceed the negative supply as this will cause large currents
to flow which can result in a destroyed unit.
Exceeding the negative common-mode limit on either input
will cause a reversal of the phase to the output and force the
amplifier output to the corresponding high or low state.
Exceeding the negative common-mode limit on both inputs
will force the amplifier output to a high state. In neither case
does a latch occur since raising the input back within the
common-mode range again puts the input stage and thus the
amplifier in a normal operating mode.
Exceeding the positive common-mode limit on a single input
will not change the phase of the output, however, if both inputs
exceed the limit, the output of the amplifier may be forced to
a high state.
The amplifiers will operate with a common-mode input voltage
equal to the positive supply; however, the gain bandwidth and
slew rate may be decreased in this condition. When the negative common-mode voltage swings to within 3V of the negative supply, an increase in input offset voltage may occur.
Each amplifier is individually biased by a zener reference
which allows normal circuit operation on ±6.0V power supplies. Supply voltages less than these may result in lower gain
bandwidth and slew rate.
Typical Application
Single Supply Sample and Hold
20153631
11
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LF412JAN
The amplifiers will drive a 2 kΩ load resistance to ±10V over
the full temperature range. If the amplifier is forced to drive
heavier load currents, however, an increase in input offset
voltage may occur on the negative voltage swing and finally
reach an active current limit on both positive and negative
swings.
Precautions should be taken to ensure that the power supply
for the integrated circuit never becomes reversed in polarity
or that the unit is not inadvertently installed backwards in a
socket as an unlimited current surge through the resulting
forward diode within the IC could cause fusing of the internal
conductors and result in a destroyed unit.
As with most amplifiers, care should be taken with lead dress,
component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an
input should be placed with the body close to the input to
minimize “pick-up” and maximize the frequency of the feedback pole by minimizing the capacitance from the input to
ground.
A feedback pole is created when the feedback around any
amplifier is resistive. The parallel resistance and capacitance
from the input of the device (usually the inverting input) to AC
ground set the frequency of the pole. In many instances the
frequency of this pole is much greater than the expected
3 dB frequency of the closed loop gain and consequently
there is negligible effect on stability margin. However, if the
feedback pole is less than approximately 6 times the expected
3 dB frequency a lead capacitor should be placed from the
output to the input of the op amp. The value of the added
capacitor should be such that the RC time constant of this
capacitor and the resistance it parallels is greater than or
equal to the original feedback pole time constant.
Application Hints
LF412JAN
Revision History
Date Released
Revision
Section
12/08/2010
A
New Release to Corporate format
www.national.com
Changes
12
1 MDS datasheet converted into Corporate
datasheet format. MJLF412-X Rev 0C1 will be
archived.
LF412JAN
Physical Dimensions inches (millimeters) unless otherwise noted
Dual-In-Line Package (J)
NS Package Number J08A
13
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LF412JAN Low Offset, Low Drift Dual JFET Input Operational Amplifier
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