DATA SHEET MOS INTEGRATED CIRCUIT µPD16315 1/4- to 1/12-DUTY FIPTM(VFD) CONTROLLER/DRIVER DESCRIPTION The µPD16315 is a FIP (Fluorescent Indicator Panel, or Vacuum Fluorescent Display) controller/driver that is driven on a 1/4- to 1/12- duty factor. It consists of 16 segment output lines, 4 grid output lines, 8 segment/grid output drive lines, a display memory, a control circuit, and a key scan circuit. Serial data is input to the µPD16315 through a three-line serial interface. This FIP controller/driver is ideal as a peripheral device for a single-chip microcomputer. FEATURES • Multiple display modes: 16-segment & 12-digit to 24-segment & 4-digit • Key scanning: 16 x 2 matrix • Dimming circuit: 8 steps • High-withstanding-voltage output: VDD − 35 V MAX. • LED ports: 4 chs., 20 mA MAX. • No external resistors necessary for driver outputs: P-ch open-drain + pull-down resistor output • Serial interface: CLK, STB, DIN, DOUT ORDERING INFORMATION Part Number Package µPD16315GB-3BS 44-pin Plastic QFP (10 x 10) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S14074EJ1V0DS00 (1st edition) Date Published February 2003 NS CP(K) Printed in Japan 1999 µPD16315 1. BLOCK DIAGRAM interface 24 bits x 12 words STB OSC Timing generator Key1, Key2 2 12-bit shift register R Key data memory (2 x 16 bits) Seg17/Grid12 Grid1 8 key scan OSC Segment driver Display memory Multiplexed driver CLK Serial Grid driver DOUT Seg1/KS1 16 24 Data selector DIN Dimming circuit 24-bit output latch Command decoder 8 12 VDD (+5 V) 2 LED4 Data Sheet S14074EJ1V0DS Seg24/Grid5 8 4 4-bit latch LED1 Seg16/KS16 VSS (0 V) VEE (−30 V) Grid4 µPD16315 2. PIN CONFIGURATION (Top View) VSS VDD Grid1 Grid2 Grid3 Grid4 Seg24/Grid5 Seg23/Grid6 Seg22/Grid7 Seg21/Grid8 Seg20/Grid9 44 43 42 41 40 39 38 37 36 35 34 44-pin Plastic QFP (10 x 10) 28 Seg15/KS15 DIN 7 27 Seg14/KS14 CLK 8 26 Seg13/KS13 STB 9 25 Seg12/KS12 KEY1 10 24 Seg11/KS11 KEY2 11 23 Seg10/KS10 22 6 Seg9/KS9 DOUT 21 Seg16/KS16 Seg8/KS8 29 20 5 Seg7/KS7 OSC 19 VEE Seg6/KS6 30 18 4 Seg5/KS5 LED4 17 Seg17/Grid12 Seg4/KS4 31 16 3 Seg3/KS3 LED3 15 Seg18/Grid11 Seg2/KS2 32 14 2 Seg1/KS1 LED2 13 Seg19/Grid10 VDD 33 12 1 VSS LED1 Caution Use all of the power supply pins. Data Sheet S14074EJ1V0DS 3 µPD16315 3. PIN FUNCTION Symbol DIN Pin Name Data input Pin No. 7 I/O Description Input Input serial data at rising edge of shift clock, starting from the low order bit. DOUT Data output 6 Output Output serial data at the falling edge of the shift clock, starting from low order bit. This is N-ch open-drain output pin. STB Strobe − 9 Initializes serial interface at the rising or falling edge of the µPD16315. It then waits for reception of a command. Data input after STB has fallen is processed as a command. While command data is processed, current processing is stopped, and the serial interface is initialized. While STB is high, CLK is ignored. CLK Clock input 8 Input Reads serial data at the rising edge, and outputs data at the falling edge. OSC Oscillator pin − 5 Connect resistor to this pin to determine the oscillation frequency to this pin. Connect resistor between this pin and GND (VSS). Seg1/KS1 to High-withstanding-voltage 14 to 29 Seg16/KS16 output (Segment) Output Segment output pins (Dual function as key source) Grid1 to Grid4 High-withstanding-voltage 39 to 42 Output Grid output pins Output These pins are selectable for segment or grid driving. 1 to 4 Output CMOS output, +20 mA MAX. output (grid) Seg17/Grid12 to High-withstanding-voltage 31 to 38 Seg24/Grid5 output (segment/grid) LED1 to LED4 LED output KEY1, KEY2 Key data input 10, 11 Input VDD Logic power 13, 43 − 5 V ± 10% VSS Logic ground 12, 44 − Connect this pin to system GND. VEE Pull-down level 30 − VDD − 35 V MAX. 4 Data input to these pins is latched at the end of the display cycle. Data Sheet S14074EJ1V0DS µPD16315 4. DISPLAY RAM ADDRESS AND DISPLAY MODE The display RAM stores the data transmitted to the µPD16315 through the serial communication. The addresses are allocated in 8-bit units. Seg1 Seg4 Seg8 Seg12 Seg16 Seg20 Seg24 00HL 00HU 01HL 01HU 02HL 02HU DIG1 03HL 03HU 04HL 04HU 05HL 05HU DIG2 06HL 06HU 07HL 07HU 08HL 08HU DIG3 09HL 09HU 0AHL 0AHU 0BHL 0BHU DIG4 0CHL 0CHU 0DHL 0DHU 0EHL 0EHU DIG5 0FHL 0FHU 10HL 10HU 11HL 11HU DIG6 12HL 12HU 13HL 13HU 14HL 14HU DIG7 15HL 15HU 16HL 16HU 17HL 17HU DIG8 18HL 18HU 19HL 19HU 1AHL 1AHU DIG9 1BHL 1BHU 1CHL 1CHU 1DHL 1DHU DIG10 1EHL 1EHU 1FHL 1FHU 20HL 20HU DIG11 21HL 21HU 22HL 22HU 23HL 23HU DIG12 b0 b3 b4 b7 XXHL XXHU Lower 4 bits Higher 4 bits Data Sheet S14074EJ1V0DS 5 µPD16315 5. KEY MATRIX AND KEY-INPUT DATA STORAGE RAM The key matrix is made up of a 16 x 2 matrix, as shown below. KEY1 Seg16/KS16 Seg15/KS15 Seg14/KS14 Seg13/KS13 Seg12/KS12 Seg11/KS11 Seg10/KS10 Seg9/KS9 Seg8/KS8 Seg7/KS7 Seg6/KS6 Seg5/KS5 Seg4/KS4 Seg3/KS3 Seg2/KS2 Seg1/KS1 KEY2 The data of each key is stored as follows, and is read with the read command starting from the least significant bit. KEY1 KEY2 KEY1 KEY2 KEY1 KEY2 KEY1 KEY2 Seg1/KS1 Seg2/KS2 Seg3/KS3 Seg4/KS4 Seg5/KS5 Seg6/KS6 Seg7/KS7 Seg8/KS8 Seg9/KS9 Seg10/KS10 Seg11/KS11 Seg12/KS12 Seg13/KS13 Seg14/KS14 Seg15/KS15 Seg16/KS16 b4 b6 Reading Sequence b0 b1 b2 b3 b5 b7 5.1 LED Port Data is written to the LED port with the write command, starting from the least significant bit. “L” output when the bit of this port is 0, and “H” output when the bit is 1. The data of bits after the 5th bit are ignored. LSB MSB − − − − b3 b2 b1 b0 Don't care Remark Power ON application, all the LED ports are “L” output. 6 Data Sheet S14074EJ1V0DS LED1 LED2 LED3 LED4 µPD16315 6. COMMANDS Commands set the display mode and status of the FIP TM (VFD) driver. The first 1 byte input to the µPD16315 through the DIN pin after the STB pin has fallen is regarded as a command. If STB is set high while commands/data are transmitted, serial communication is initialized, and the commands/data being transmitted are invalid (however, the commands/data previously transmitted remain valid). (1) Display mode setting commands These commands initialize the µPD16315 and select the number of segments and the number of grids (1/4- to 1/12duty, 16 segments to 24 segments). When these commands are executed, the display is forcibly turned OFF, and key scanning is also stopped. To resume display, the display command “ON” must be executed. If the same mode is selected, however, nothing happens. LSB MSB 0 0 − − Don't care Remark − b2 b1 b0 Display mode settings 0000 : 4 digits 24 segments 0001 : 5 digits 23 segments 0010 : 6 digits 22 segments 0011 : 7 digits 21 segments 0100 : 8 digits 20segments 0101 : 9 digits 19 segments 0110 : 10 digits 18 segments 0111 : 11 digits 17 segments 1xxx : 12 digits 16segments Power ON application, the 12-digit, 16-segment mode is selected. Data Sheet S14074EJ1V0DS 7 µPD16315 (2) Data setting commands These commands set data write and data read modes. LSB MSB 0 1 − − b3 b2 b1 b0 Data write and read mode settings 00 : Write data to display memory 01 : Write data to LED port 10 : Read key data 11 : Don't care Don't care Address increment mode settings (Display memory) 0 : Increments address after data has been written 1 : Fixes address Test mode settings 0 : Nomal operation 1 : Test mode Remark Power ON application, the normal operation and address increment modes are set. (3) Address setting commands These commands set an address of the display memory. LSB MSB 1 1 b5 b4 b3 b2 b1 b0 Address (00H to 23H) Remarks 1. If address 24H or higher is set, data is ignored, until a valid address is set. 2. Power ON application, the address is set to 00H. 8 Data Sheet S14074EJ1V0DS µPD16315 (4) Display control commands LSB MSB 1 0 − − b3 b2 b1 b0 Dimming quantity settings 000 : Set pulse width to 1/16. 001 : Set pulse width to 2/16. 010 : Set pulse width to 4/16. 011 : Set pulse width to 10/16. 100 : Set pulse width to 11/16. 101 : Set pulse width to 12/16. 110 : Set pulse width to 13/16. 111 : Set pulse width to 14/16. Don't care Turns ON/OFF display. 0 : Display OFF (Key scan continuesNote) 1 : Display ON Note Power ON application, key scanning is stopped. Remark Power ON application, the 1/16 pulse width is set and the display is turned OFF. Data Sheet S14074EJ1V0DS 9 µPD16315 7. KEY SCANNING AND DISPLAY TIMING TDISP ≅ 500 µs Key scan data SEG output DIG1 DIG2 DIG3 DIGn G1 1/16TDISP G2 G3 Gn 1 frame = TDISP x (n + 1) Remark One cycle of key scanning consists of two frame, and data in a 16 x 2 matrix is stored in RAM. Key Scan Expansion 1st frame 1 2 3 4 5 6 7 8 DIGn 2nd frame 10 DIG1 9 10 11 12 13 14 15 16 Data Sheet S14074EJ1V0DS DIG1 µPD16315 8. SERIAL COMMUNICATION FORMAT Reception (command/data write) If data continues STB DIN b0 1 CLK b1 b2 b6 3 2 b7 8 7 Transmission (data read) STB b0 DIN 1 CLK b1 b2 2 3 b3 b4 b5 b6 4 5 6 7 b7 8 tWAIT Note 1 2 3 4 5 6 DOUT b0 A data read command is set. b1 b2 b3 b4 b5 Data is read. Note When data is read, a wait time tWAIT of 1 µs is necessary since the rising of the eighth clock that has set the command, until the falling of the first clock that has read the data. Remark Because the DOUT pin is an N-ch, open-drain output pin, be sure to connect an external pull-up resistor (1 to 10 kΩ) to this pin. Data Sheet S14074EJ1V0DS 11 µPD16315 9. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°°C, VSS = 0 V) Parameter Symbol Ratings Unit Logic Supply Voltage VDD −0.5 to +6.0 V Driver Supply Voltage VEE VDD + 0.5 to VDD − 40 V Logic Input Voltage VI1 −0.5 to VDD + 0.5 V FIP Driver Output Voltage VO2 VEE − 0.5 to VDD + 0.5 V LED Driver Output Current IO1 ±20 mA FIP Driver Output Current IO2 −40 (grid) mA −15 (segment) Note 800 Power Dissipation PD mW Operating Ambient Temperature TA −40 to +85 °C Storage Temperature Tstg −65 to +150 °C Note Derate at −6.4 mW/°C at TA = 25°C or higher. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (TA = −20 to 70°°C, VSS = 0 V) Parameter Symbol MIN. TYP. MAX. Unit 5 5.5 V Logic Supply Voltage VDD 4.5 High-Level Input Voltage VIH 0.7 VDD VDD V Low-Level Input Voltage VIL 0 0.3 VDD V Driver Supply Votlage VEE 0 VDD − 35 V Remark Maximum power consumption PMAX. = FIP driver dissipation + RL dissipation + LED driver dissipation + dynamic power consumption Where segment current = 3 mA, grid current = 15 mA, and LED current = 20 mA, FIP driver dissipation = number of segments x 6 + number of grids/(number of grids + 1) x 30 (mW) RL dissipation ≅ (VDD − VEE) /50 x (number of segments + 1) (mW) 2 LED driver dissipation = number of LEDs x 20 (mW) Dynamic power consumption = VDD x 5 (mW) 12 Data Sheet S14074EJ1V0DS µPD16315 Electrical Characteristics (TA = −20 to +70°°C, VDD = 4.5 to 5.5 V, VSS = 0 V, VEE = VDD − 35 V) Parameter Symbol Test Conditions High-Level Output Voltage VOH1 LED1 - LED4, IOH1 = −15 mA Low-Level Output Voltage VOL1 LED1 - LED4, IOL1 = +15 mA Low-Level Output Voltage VOL2 DOUT, IOL2 = 4 mA High-Level Output Current IOH21 VO = VDD − 2 V, MIN. TYP. MAX. VDD − 1 Unit V 1 V 0.4 V −3 mA −15 mA Seg1/ KS1 to Seg16/ KS16 High-Level Output Current IOH22 VO = VDD − 2 V, Grid1 to Grid4 Seg17 / Grid12 to Seg24 / Grid5 Driver Leakage Current IOLEAK VO = VDD − 35 V, driver OFF Output Pull-Down Resistor RL Driver output Input Current II VI = VDD or VSS High-Level Input Voltage VIH Low-Level Input Voltage VIL Hysteresis Voltage VH CLK, DIN, STB Dynamic Current Consumption IDDdyn Under no load, display OFF 40 65 −10 µA 120 kΩ ±1 µA 0.7 VDD V 0.3 VDD 0.35 V V 5 mA Switching Characteristics (TA = −20 to +70°°C, VDD = 4.5 to 5.5 V, VEE = −30 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit 350 500 650 kHz Oscillation Frequency fOSC R = 82 kΩ Propagation Delay Time tPLZ CLK → DOUT 300 ns tPZL CL = 15 pF, RL = 10 kΩ 100 ns tTZH1 CL = 300 pF Rise Time tTZH2 Seg1/KS1 to Seg16/KS16 Grid1 to Grid4, 2 µs 0.5 µs 160 µs Seg17/Grid12 to Seg24/Grid5 Fall Time tTHZ CL = 300 pF, Segn, Gridn Maximum Clock Frequency fMAX. Duty = 50% Input Capacitance CI 1 MHz 15 Data Sheet S14074EJ1V0DS pF 13 µPD16315 Timing Conditions (TA = −20 to 70°°C, VDD = 4.5 to 5.5 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Clock Pulse Width PW CLK 400 ns Strobe Pulse Width PW STB 1 µs Data Setup Time tSETUP 100 ns Data Hold Time tHOLD 100 ns Clock-Strobe Time tCLK-STB 1 µs 1 µs Wait Time tWAIT CLK ↑ → STB ↑ Note CLK ↑ → CLK ↓ Note Refer to the SERIAL COMMUNICATION FORMAT. 14 Data Sheet S14074EJ1V0DS µPD16315 Switching Characteristic Waveforms fOSC 50% OSC PWSTB STB tCLK-STB PWCLK PWCLK CLK tSETUP tHOLD DIN tPZL tPLZ DOUT tTHZ tTZH 90% Sn/Gn 10% Data Sheet S14074EJ1V0DS 15 µPD16315 10. APPLICATIONS Updating display memory by incrementing address STB ........... CLK DIN Command 1 Command 2 Command 3 Data 1 ........... Command 1 : sets display mode Command 2 : sets data Command 3 : sets address Data 1 to n : transfers display data (36 bytes MAX.) Command 4 : controls display Updating specific address STB CLK DIN Command 1 Command 2 Data Command 2 Command 1 : sets data Command 2 : sets address Data 16 : display data Data Sheet S14074EJ1V0DS Data Data n Command 4 µPD16315 11. CIRCUIT EXAMPLE FOR APPLICATION VDD VDD R3 In the case of low-level output is display ON signal. LED LED4 LED3 DOUT DIN CLK STB To Microcontroller LED2 LED1 R1 OSC R2 VSS −30 V VEE 4 R4 KEY1 Seg1/KS1 0V KEY2 Seg16/KS16 C Grid1 to Grid4 VDD +5 V Seg17/Grid12 to Seg24/Grid5 µ PD16315 8 Key Matrix Note (16 x 2) Fluorescent Indicator Panel (FIPTM) (VFD) F+ F– TM Driving voltage for FIP Note Remark (VFD) = R1, R4 = 1 k to 10 kΩ R2 = 82 kΩ R3 = 330 to 1 kΩ C = 0.1 µ to 1.0 µ F Data Sheet S14074EJ1V0DS 17 µPD16315 12. PACKAGE DRAWING 44-PIN PLASTIC QFP (10x10) A B 23 22 33 34 detail of lead end S C D R Q 12 11 44 1 F J G H I P M K M N S L S NOTE ITEM Each lead centerline is located within 0.16 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 13.2±0.2 B 10.0±0.2 C 10.0±0.2 D 13.2±0.2 F 1.0 G 1.0 H 0.37 +0.08 −0.07 I J 0.16 0.8 (T.P.) K 1.6±0.2 L 0.8±0.2 M 0.17 +0.06 −0.05 N 0.10 P 2.7±0.1 Q 0.125±0.075 R 3° +7° −3° S 3.0 MAX. S44GB-80-3BS-2 18 Data Sheet S14074EJ1V0DS µPD16315 13. RECOMMENDED SOLDERING CONDITIONS The following conditions must be met for soldering conditions of the µ PD16315. For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case other soldering process is used, or in case the soldering is done under different conditions. Type of Surface Mount Device µ PD16315GB-3BS : 44-pin plastic QFP (10 x 10) Soldering process Infrared ray reflow Soldering conditions Peak package’s surface temperature: 235°C or below, Symbol IR35-00-3 Reflow time: 30 seconds or below (210°C or higher), Number of reflow process: MAX.3 VPS Peak package’s temperature: 215°C or below, VP15-00-3 Reflow time: 25 to 40 seconds (200°C or higher), Number of reflow process: MAX.3 Wave Soldering Solder temperature: 260°C or below, WS60-00-1 Flow time: 10 seconds or below Temperature of pre-heat: 120°C pr below (Plastic surface temperature) Number of flow process: 1 Partial heating method Terminal temperature: 300°C or below, − Time 3 seconds or below (per side of pin position) Caution Do not apply more than a single process at once, except for partial heating method. Data Sheet S14074EJ1V0DS 19 µPD16315 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 20 Data Sheet S14074EJ1V0DS