PT6311 VFD Driver/Controller IC DESCRIPTION FEATURES PT6311 is a Vacuum Fluorescent Display (VFD) Controller driven on a 1/8 to 1/16 duty factor housed in 52-pin plastic QFP Package. Twelve segment output lines, 8 grid output lines, 8 segment/grid output drive lines, one display memory, control circuit, key scan circuit are all incorporated into a single chip to build a highly reliable peripheral device for a single chip micro computer. Serial data is fed to PT6311 via a three-line serial interface. • • • • CMOS Technology Low Power Consumption Key Scanning (12 x 4 matrix) Multiple Display Modes: (12 segments, 16 digits to 20 segments, 8 digits) • 8-Step Dimming Circuitry • LED Ports Provide (5 channels, 20mA max.) • 4- Bits General Purpose Input Ports Provided • Serial Interface for Clock, Data Input, Data Output, Strobe Pins • No External Resistors Needed for Driver Outputs • Available in 52pins QFP and LQFP APPLICATIONS • Microcomputer Peripheral Devices BLOCK DIAGRAM Con tro l DIN DOUT CLK Ser ial Data Inter face STB Displa y Memo ry VDD OS C Ti ming Ge ner ato r SW1 SW2 SW3 SW4 Ge ner al Inp ut Reg iste r Ke y Matrix Memory LE D1 LE D2 LE D3 LE D4 LE D5 LED Drive r OS C S egmen t Driver / G rid Driver / Ke y Scan O utput Gr id Drive r Dimming Cir cu it K1 K2 K3 K4 VDD GND SG 1/KS 1 SG 2/KS 2 SG 3/KS 3 SG 4/KS 4 SG 5/KS 5 SG 6/KS 6 SG 7/KS 7 SG 8/KS 8 SG 9/KS 9 SG 10/KS 10 SG 11 /K S11 SG 12/KS 12 SG 13/G R1 6 SG 14/G R1 5 SG 15/G R1 4 SG 16/G R1 3 SG 17/G R1 2 SG 18/G R11 SG 19/G R1 0 SG 20/G R9 GR1 GR2 GR3 GR4 GR5 GR6 GR7 GR8 VE E Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan PT6311 12-GRID X 16-SEGMENT VFD APPLICATION CIRCUIT 220 220 220 220 220 0.1uF VDD 56K VDD 40 42 41 43 44 45 46 47 38 3 37 4 36 5 35 PT6311 7 8 34 VEE 33 VDD G3 G2 G1 G4 G5 G7 G6 G9 G8 G10 G12 S2 S1 S3 S5 S4 S6 S7 S8 S9 S11 S10 12-GRID x 16-SEGMENT VFD S12 26 25 S13 24 27 23 13 22 S14 21 28 20 S15 12 19 29 18 S16 11 17 30 16 31 10 15 9 G11 32 14 10K x 4 39 2 6 MCU 48 49 50 1 51 52 10K VDD 1N4148 x 12 10K x 4 V3.2 2 November 2009 PT6311 ORDER INFORMATION Valid Part Number PT6311 PT6311-LQ Package Type 52 Pins, QFP 52 Pins, LQFP Top Code PT6311 PT6311-LQ PIN CONFIGURATION V3.2 3 November 2009 PT6311 PIN DESCRIPTION Pin Name SW1 to SW4 I/O I DOUT O DIN I NC - CLK I STB I K1 to K4 I VDD - SG1/KS1 to SG12/KS12 O Description General Purpose Input Pins Data Output Pin (N-Channel, Open-Drain) This pin outputs serial data at the falling edge of the shift clock (starting from the lower bit). Data Input Pin This pin inputs serial data at the rising edge of the shift clock (starting from the lower bit). No Connection Clock Input Pin This pin reads serial data at the rising edge and outputs data at the falling edge. Serial Interface Strobe Pin The data input after the STB has fallen is processed as a command. When this in is “HIGH”, CLK is ignored. Key Data Input Pins The data inputted to these pins is latched at the end of the display cycle. Logic Power Supply High-Voltage Segment Output Pins Also acts as the Key Source. SG20/GR9 to SG19/GR10 SG18/GR11 to SG13/GR16 VEE GR1 to GR8 LED1 to LED5 GND O High-Voltage Segment/Grid Output Pins O O - OSC I Pull-Down Level High-Voltage Grid Output Pins LED Output Pin Ground Pin Oscillator Input Pin A resistor is connected to this pin to determine the oscillation frequency. V3.2 4 Pin No. 1 to 4 5 6 7 8 9 10 to 13 14, 33, 45 15 to 26 36 to 35 32 to 27 34 44 to 37 50 to 46 51 52 November 2009 PT6311 INPUT/OUTPUT CONFIGURATIONS The schematic diagrams of the input and output circuits of the logic section are shown below: OUTPUT PINS: SGn/GRn INPUT PINS: DIN, CLK, STB INPUT PINS: SW1 TO SW4, K1 TO K4 V3.2 5 November 2009 PT6311 OUTPUT PIN: DOUT OUTPUT PINS: LED1 TO LED5 V3.2 6 November 2009 PT6311 FUNCTION DESCRIPTION COMMANDS Commands determine the display mode and status of PT6311. A command is the first byte (b0 to b7) inputted to PT6311 via the DIN Pin after STB Pin has changed from “HIGH” to “LOW” State. If for some reason the STB Pin is set to “HIGH” while data or commands are being transmitted, the serial communication is initialized, and the data/commands being transmitted are considered invalid. COMMAND 1: DISPLAY MODE SETTING COMMANDS PT6311 provides 9 display mode settings as shown in the diagram below: As stated earlier a command is the first one byte (b0 to b7) transmitted to PT6311 via the DIN Pin when STB is “LOW”. However, for these commands, the bits 5 to 6 (b4 to b5) are ignored, bits 7 & 8 (b6 to b7) are given a value of “0”. The Display Mode Setting Commands determine the number of segments and grids to be used (1/8 to 1/16 duty, 20 to 12 segments). When these commands are executed, the display is forcibly turned off, the key scanning stops. A display command “ON” must be executed in order to resume display. If the same mode setting is selected, no command execution is take place, therefore, nothing happens. When Power is turned “ON”, the 16-digit, 12-segment modes is selected. MSB 0 0 - - Not Relevant V3.2 b3 b2 b1 LSB b0 Display Mode Settings: 0XXX: 8 digits, 20 segments 1000: 9 digits, 19 segments 1001: 10 digits, 18 segments 1010: 11 digits, 17 segments 1011: 12 digits, 16 segments 1100: 13 digits, 15 segments 1101: 14 digits, 14 segments 1110: 15 digits, 13 segments 1111: 16 digits, 12 segments 7 November 2009 PT6311 DISPLAY MODE AND RAM ADDRESS Data transmitted from an external device to PT6311 via the serial interface are stored in the Display RAM and are assigned addresses. The RAM Addresses of PT6311 are given below in 8 bits unit. SG1 SG4 SG5 SG8 SG9 SG13 SG16 SG17 SG20 00HL 00HU 01HL 01HU 02HL DIG1 03HL 03HU 04HL 04HU 05HL DIG2 06HL 06HU 07HL 07HU 08HL DIG3 09HL 09HU 0AHL 0AHU 0BHL DIG4 0CHL 0CHU 0DHL 0DHU 0EHL DIG5 0FHL 0FHU 10HL 10HU 11HL DIG6 12HL 12HU 13HL 13HU 14HL DIG7 15HL 15HU 16HL 16HU 17HL DIG8 18HL 18HU 19HL 19HU 1AHL DIG9 1BHL 1BHU 1CHL 1CHU 1DHL DIG10 1EHL 1EHU 1FHL 1FHU 20HL DIG11 21HL 21HU 22HL 22HU 23HL DIG12 24HL 24HU 25HL 25HU 26HL DIG13 27HL 27HU 28HL 28HU 29HL DIG14 2AHL 2AHU 2BHL 2BHU 2CHL DIG15 2DHL 2DHU 2EHL 2EHU 2FHL DIG16 b0 V3.2 SG12 b3 b4 b7 xxHL xxHU Lower 4 bits Higher 4 bits 8 November 2009 PT6311 COMMAND 2: DATA SETTING COMMANDS The Data Setting Commands executes the Data Write or Data Read Modes for PT6311. The data Setting Command, the bits 5 and 6 (b4, b5) are ignored, bit 7 (b6) is given the value of “1” while bit 8 (b7) is given the value of “0”. Please refer to the diagram below. When power is turned ON, bit 4 to bit 1 (b3 to b0) are given the value of “0”. MSB 0 1 - - Not Relevant b3 b2 b1 LSB b0 Data Write & Read Mode Settings: 00: Write Data to Display Mode 01: Write Data to LED Port 10: Read Key Data 11: Read SW Data Address Increment Mode Settings (Display Mode): 0: Increment Address after Data has been Written 1: Fixed Address Mode Settings: 0: Normal Operation Mode 1: Test Mode V3.2 9 November 2009 PT6311 PT6311 KEY MATRIX & KEY INPUT DATA STORAGE RAM PT6311 Key Matrix consists of 12 x 4 arrays as shown below: K1 K2 K3 SG12/KS12 SG11/KS11 SG10/KS10 SG9/KS9 SG8/KS8 SG7/KS7 SG6/KS6 SG5/KS5 SG4/KS4 SG3/KS3 SG2/KS2 SG1/KS1 K4 Each data inputted by each key are stored as follows. They are read by a READ Command, starting from the last significant bit. When the most significant bit of the data (SG12, b7) has been read, the least significant bit of the next data (SG1, b0) is read. K1…………………K4 SG1/KS1 SG3/KS3 SG5/KS5 SG7/KS7 SG9/KS9 SG11/KS11 b0………………….b3 V3.2 K1…………………K4 SG2/KS2 SG4/KS4 SG6/KS6 SG8/KS8 SG10/KS10 SG12/KS12 b4………………….b7 10 Reading Sequence November 2009 PT6311 LED DISPLAY PT6311 provides 5 LED Display Terminals, namely LED1 to LED5. Data is written to the LED Port starting from the least significant bit (b0) of the port using a WRITE Command. Each bit starting from the least significant (b0) activates a specific LED Display Terminal -- b0 corresponds LED1 Display, b1 activates LED2 and so forth. Since there are only 5 LED display terminals, bits 6 to 8 (b5 ~ b7) are not used and therefore ignored. This means that b5 to b7 does NOT in anyway activate any LED Display, they are totally ignored. When a bit (b0 ~ b4) in the LED Port is “0”, the corresponding LED is ON. Conversely, when the bit is “1”, the LED Display is turned OFF. For example, Bit 1 (as designated by b0) has the value of “0”, then this means that LED1 is ON. It must be noted that when power is turned ON, bit 5 to bit 1 (b4 to b0) are given the value of “1”. Please refer to the diagrams below: MSB - - - - b3 b2 b1 LSB b0 Not Used LED1 LED2 LED3 LED4 LED5 SWITCH DATA PT6311 provides 4 Switch Inputs, namely: SW1 to SW4. SW Data is read starting from the least significant bit (b0) using a READ Command. Each bit starting from the least significant (b0) corresponds to a specific Switch Input -- b0 corresponds SW1, b1 to SW2 and so forth. Since there are only 4 Switch Inputs, Bits 5 to 8 (b4 to 7) are given the value of “0”. Please refer to the diagram below. MSB 0 0 0 0 b3 b2 b1 LSB b0 SW1 SW2 SW3 SW4 V3.2 11 November 2009 PT6311 COMMAND 3: ADDRESS SETTING COMMANDS Address Setting Commands are used to set the address of the display memory. The address is considered valid if it has a value of “00H” to “2FH”. If the address is set to 30H or higher, the data is ignored until a valid address is set. When power is turned ON, the address is set at “00H”. Please refer to the diagram below. MSB 1 1 b5 b4 b3 b2 b1 LSB b0 Address: 00H to 2FH COMMAND 4: DISPLAY CONTROL COMMANDS The Display Control Commands are used to turn ON or OFF a display. It also used to set the pulse width. Please refer to the diagram below. When the power is turned ON, a 1/16 pulse width is selected and the displayed is turned OFF (the key scanning is stopped). MSB 1 0 - - Not Relevant b3 b2 b1 LSB b0 Dimming Quantity Settings: 000: Pulse width = 1/16 001: Pulse width = 2/16 010: Pulse width = 4/16 011: Pulse width = 10/16 100: Pulse width – 11/16 101: Pulse width = 12/16 110: Pulse width = 13/16 111: Pulse width = 14/16 Display Settings: 0: Display Off (Key Scan Continues) 1: Display On V3.2 12 November 2009 PT6311 SCANNING AND DISPLAY TIMING The Key Scanning and display timing diagram is given below. One cycle of key scanning consists of 2 frames. The data of the 12 x 4 matrix is stored in the RAM. V3.2 13 November 2009 PT6311 SERIAL COMMUNICATION FORMAT The following diagram shows the PT6311 serial communication format. The DOUT Pin is an N-channel, open-drain output pin; therefore, it is highly recommended that an external pull-up resistor (1 KΩ to 10 KΩ) must be connected to DOUT. Reception (Data/Command Write) If data continues STB DIN b0 CLK b1 1 b2 3 2 b7 b6 7 8 Transmission (Data Read) STB DIN CLK b0 1 b1 b2 3 2 b3 4 b4 b5 b6 b7 5 6 7 8 t wait 1 2 b0 DOUT Data Read Command is set b1 3 4 b2 5 b3 6 b4 b5 Data Reading Starts where: twait (waiting time) > 1µs It must be noted that when the data is read, the waiting time (twait) between the rising of the eighth clock that has set the command and the falling of the first clock that has read the data is greater or equal to 1µs. V3.2 14 November 2009 PT6311 SWITCHING CHARACTERISTIC WAVEFORM PT6311 Switching Characteristics Waveform is given below. fosc OSC 50% PW STB STB PW CLK PW CLK t setup t hold t CLK-STB CLK DIN t PZL t PLZ DOUT t THZ Sn/Gn t TZH 90% 10% where: fosc = Oscillation Frequency PWSTB (Strobe Pulse Width)≥1µs tsetup (Data Setup Time)≥100ns tTZH1 (Segment Rise Time)≤2µs (VDD=5V) tTZH2 (Grid Rise Time)≤0.5µs (VDD=5V) tTHZ (Segment & Grid Fall Time)≤150µs tPLZ (Propagation Delay Time)≤400ns (VDD=5V) V3.2 PWCLK (Clock Pulse Width)≥400ns tCLK-STB (Clock - Strobe Time)≥1µs thold (Data Hold Time)≥100ns tTZH1 (Segment Rise Time)≤4µs (VDD=3.3V) tTZH2 (Grid Rise Time)≤1.2µs (VDD=3.3V) tPZL (Propagation Delay Time)≤100ns tPLZ (Propagation Delay Time)≤600ns (VDD=3.3V) 15 November 2009 PT6311 APPLICATIONS Display memories are updated by incrementing addresses. Please refer to the following diagram. STB CLK DIN Command 2 Command 3 Data n Data 1 Command 1 Command 4 where: Command 1: Display Mode Setting Command Command 2: Data Setting Command Command 3: Address Setting Command Data 1 to n : Transfer Display Data (48 Bytes max.) Command 4: Display Control Command The following diagram shows the waveforms when updating specific addresses. STB CLK DIN Command 2 Command 3 Data Command 3 Data where: Command 2: Data Setting Command Command 3: Address Setting Command Data: Display Data V3.2 16 November 2009 PT6311 RECOMMENDED SOFTWARE FLOWCHART START Delay 200 ms SET COMMAND 2 (Write Data) SET COMMAND 3 Clear Display RAM (See Note 5) INITIAL SETTING SET COMMAND 1 SET COMMAND 4 (88H~8FH: Display ON) MAIN PROGRAM SET COMMAND 2 (Read Key & Write Data Includeed) MAIN LOOP SET COMMAND 3 SET COMMAND 1 SET COMMAND 4 END Notes: 1. Command 1: Display Mode Commands 2. Command 2: Data Setting Commands 3. Command 3: Address Setting Commands 4. Command 4: Display Control Commands 5. When IC power is applied for the first time, the contents of the Display RAM are not defined; thus, it is strongly suggested that the contents of the Display RAM must be cleared during the initial setting. V3.2 17 November 2009 PT6311 ABSOLUTE MAXIMUM RATINGS (Unless otherwise stated, Ta=25℃, GND=0V) Parameter Logic supply voltage Driver supply voltage Logic input voltage VFD driver output voltage LED driver output current Oscillation frequency Symbol VDD VEE VI VO IOLED fosc Ratings -0.3 to +7 VDD +0.3 to VDD -40 -0.3 to VDD +0.3 VEE -0.3 to VDD +0.3 +25 3M(Max.) Unit V V V V mA Hz Operating temperature Topr -40 to +85 ℃ Storage temperature Tstg -65 to +150 ℃ VFD driver output current IOVFD -40 (Grid) -15 (Segment) mA RECOMMENDED OPERATING RANGE (Unless otherwise stated, Ta=25℃, GND=0V) Parameter Logic supply voltage High-Level input voltage Low-Level input voltage Driver supply voltage Symbol VDD VIH VIL VEE Min. 3 0.7VDD 0 VDD -35 Typ. 5 - Max. 5.5 VDD 0.3VDD 0 Unit V V V V POWER SUPPLY SEQUENCE Note: The power on/off sequence suggestion: Applications must observe the following sequence when turning the power on or off. • At power on: First turn on the logic system power (VDD), and then turn on the driver power (VEE). • At power off: First turn off the driver power (VEE), and then turn off the logic system power (VDD). V3.2 18 November 2009 PT6311 ELECTRICAL CHARACTERISTICS (Unless otherwise stated, VDD=5V, GND=0V, VEE=VDD-35 V, Ta=25℃) Parameter Symbol Test Condition IOHLED=-1mA High-Level output voltage VOHLED LED1 to LED5 IOLLED=+20mA Low-Level output voltage VOLLED LED1 to LED5 Low-Level output voltage VOLDOUT DOUT, IOLDOUT=4mA VO=VDD -2V High-Level output current IOHSG SG1 to SG12 VO=VDD -2V, High-Level output current IOHGR GR1 to GR8, SG13/GR16 to SG20/GR9 High-Level input voltage VIH Low-Level input voltage VIL Oscillation frequency fosc R=56KΩ Min. Typ. Max. Unit 0.9VDD - - V - - 1 V - - 0.4 V -3 - - mA -15 - - mA 0.7VDD 350 500 0.3VDD 650 V V KHz μA mA Input current II VI=VDD or GND - - Dynamic current consumption IDDdyn Under no load Display OFF - - ±1 5 Min. Typ. Max. Unit 0.9VDD - - V - - 1 V - - 0.4 V -1.5 - - mA -6 - - mA 0.7VDD 350 500 0.2VDD 650 V V KHz ±1 3 μA mA (Unless otherwise stated, VDD=3.3V, GND=0V, VEE=VDD-35 V, Ta=25℃) Parameter Symbol Test Condition IOHLED = -1mA High-Level output voltage VOHLED LED1 to LED5 IOLLED = +20mA Low-Level output voltage VOLLED LED1 to LED5 Low-Level output voltage VOLDOUT DOUT, IOLDOUT = 4mA VO = VDD -2V High-Level output current IOHSG SG1 to SG12 VO = VDD -2V High-Level output current IOHGR GR1 to GR8, SG13/GR16 to SG20/GR9 High-Level input voltage VIH Low-Level input voltage VIL Oscillation frequency fosc R = 56 KΩ Input current II VI = VDD or GND - - Dynamic current consumption IDDdyn Under no load Display OFF - - V3.2 19 November 2009 PT6311 PACKAGE INFORMATION 52 PINS, QFP (BODY SIZE: 14MM X 14MM, PITCH=1.00MM) Symbol A A1 A2 b c D D1 E E1 e θ L L1 Dimensions (MM) Min. 0.00 1.90 0.29 0.11 Nom. 0.35 17.20 BSC 14.00 BSC 17.20 BSC 14.00 BSC 1.00 BSC Max. 3.15 0.25 2.90 0.41 0.23 0° - 8° 0.65 1.60 REF 1.05 Note: Refer to JEDEC MS-022 BD V3.2 20 November 2009 PT6311 52 PINS, LQFP Symbol A A1 A2 b c D D1 E E1 e θ L L1 Dimensions (MM) Min. 0.05 1.35 0.35 0.09 Nom. 1.40 16.00 BSC 14.00 BSC 16.00 BSC 14.00 BSC 1.00 BSC Max. 1.60 0.15 1.45 0.50 0.20 0° 3.5° 7° 0.70 0.85 1.30 REF 1.00 Note: Refer to JEDEC MS-026 V3.2 21 November 2009 PT6311 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw V3.2 22 November 2009