PT6958 LED Driver IC DESCRIPTION PT6958 is an LED Controller driven on a 1/6 duty factor. Ten segment output lines, five grid output lines, one display memory, control circuit, key scan circuit are all incorporated into a single chip to build a highly reliable peripheral device for a single chip microcomputer. Serial data is fed to PT6958 via a three-line serial interface. Housed in a 28-pin SOP, PT6958’s pin assignments and application circuit are optimized for easy PCB Layout and cost saving advantages. FEATURES • • • • • • • CMOS Technology Low Power Consumption Up to 10 Segment Output Drivers Up to 5 Grid Output Drivers Key Scanning (6 x 4 Matrix) 8-Step Dimming Circuitry Serial Interface for Clock, Data Input, Data Output, Strobe Pins • Available in 28-pin, SOP APPLICATION • Micro-computer Peripheral Device BLOCK DIAGRAM Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan PT6958 APPLICATION CIRCUIT Notes: 1. The external capacitor (0.1 µF) that is connected between the GND and the VDD pins must be located as close to the PT6958 chip as possible. 2. The PT6958 power supply is separate from the application system power supply. 3. 10 KΩ ≧ R ≧ 1 KΩ COMMON CATHODE TYPE LED PANEL V2.3 2 PT6958 ORDER INFORMATION Valid Part Number PT6958 Package Type 28-pin, SOP, 300mil Top Code PT6958 PIN CONFIGURATION PIN DESCRIPTION Pin Name I/O OSC I DOUT O DIN I CLK I STB I K1 ~ K4 I VDD - SG1/KS1 ~ SG6/KS6 O SG7 ~ SG10 GND GR5 ~ GR1 O O V2.3 Description Oscillator Input Pin A resistor is connected to this pin to determine the oscillation frequency Data Output Pin (N-Channel, Open-Drain) This pin outputs serial data at the falling edge of the shift clock. Data Input Pin This pin inputs serial data at the rising edge of the shift clock (starting from the lower bit) Clock Input Pin This pin reads serial data at the rising edge and outputs data at the falling edge Serial Interface Strobe Pin The data input after the STB has fallen is processed as a command. When this pin is “High”, CLK is ignored. Key Data Input Pins The data sent to these pins are latched at the end of the display cycle. (Internal Pull-Low Resistor) Power Supply Segment Output Pins (P-Channel, open drain) Also acts as the Key Source Segment Output Pins (P-Channel, open drain) Ground Pin Grid Output Pins (N-Channel, open drain) Pin No. 1 2 3 4 5 6~9 10, 21 11 ~ 16 17 ~ 20 22, 28 23 ~ 27 3 PT6958 INPUT/OUTPUT CONFIGURATIONS The schematic diagrams of the input and output circuits of the logic section are shown below. INPUT PINS: CLK, STB, DIN INPUT PINS: K1 TO K4 OUTPUT PINS: DOUT, GR1 TO GR5 OUTPUT PINS: SG1 TO SG10 V2.3 4 PT6958 FUNCTION DESCRIPTION COMMANDS A command is the first byte (b0 to b7) inputted to PT6958 via the DIN Pin after STB Pin has changed from “HIGH” to “LOW” State. If for some reason the STB Pin is set to “HIGH” while data or commands are being transmitted, the serial communication is initialized, and the data/commands being transmitted are considered invalid. COMMAND 1: DATA SETTING COMMANDS The Data Setting Commands executes the Data Write or Data Read Modes for PT6958. The data Setting Command, the bits 5 and 6 (b4, b5) are ignored, bit 7 (b6) is given the value of “1” while bit 8 (b7) is given the value of “0”. Please refer to the diagram below. When power is turned ON, bit 4 to bit 1 (b3 to b0) are given the value of “0”. MSB LSB 0 1 b3 b2 b1 b0 Not Relevant Data Write & Read Mode Settings: 00: Write Data to Display Mode 10: Read Key Data Address Increment Mode Settings (Display Mode): 0: Increment Address after Data has been Written 1: Fixed Address Mode Settings: 0: Normal Operation Mode 1: Test Mode PT6958 KEY MATRIX & KEY INPUT DATA STORAGE RAM PT6958 Key Matrix consists of 6 x 4 array as shown below: Each data entered by each key is stored as follows and read by a READ Command, starting from the last significant bit. When the most significant bit of the data (SG6, b7) has been read, the least significant bit of the next data (SG1, b0) is read. K1…………………K4 K1…………………K4 SG1/KS1 SG2/KS2 Reading SG3/KS3 SG4/KS4 Sequence SG5/KS5 SG6/KS6 b0………………….b3 b4………………….b7 V2.3 5 PT6958 COMMAND 2: ADDRESS SETTING COMMANDS Address Setting Commands are used to set the address of the display memory. The address is considered valid if it has a value of “00H” to 09H”. If the address is set to 0AH or higher, the data is ignored until a valid address is set. When power is turned ON, the address is set at “00H”. Please refer to the diagram below. MSB 1 1 b3 b2 LSB b0 b1 Not Relevant Address: 00H to 09H DISPLAY MODE AND RAM ADDRESS Data transmitted from an external device to PT6958 via the serial interface are stored in the Display RAM and are assigned addresses. The RAM Addresses of PT6958 are given below in 8 bits unit. SG1 SG4 SG5 00HL 02HL 04HL 06HL 08HL SG8 SG9 00HU 02HU 04HU 06HU 08HU b0 b3 xxHL Lower 4 bits SG10 01HL 03HL 05HL 07HL 09HL b4 DIG1 DIG2 DIG3 DIG4 DIG5 b7 xxHU Higher 4 bits COMMAND 3: DISPLAY CONTROL COMMANDS The Display Control Commands are used to turn ON or OFF a display. It also used to set the pulse width. Please refer to the diagram below. When the power is turned ON, a 1/16 pulse width is selected and the displayed is turned OFF (the key scanning is stopped). MSB LSB 1 0 b3 b2 b1 b0 Not Relevant Dimming Quantity Settings: 000: Pulse width = 1/16 001: Pulse width = 2/16 010: Pulse width = 4/16 011: Pulse width = 10/16 100: Pulse width = 11/16 101: Pulse width = 12/16 110: Pulse width = 13/16 111: Pulse width = 14/16 Display Settings: 0: Display Off (Key Scan Continues) 1: Display On V2.3 6 PT6958 SCANNING AND DISPLAY TIMING The Key Scanning and Display Timing diagram is given below. One cycle of key scanning consists of 1 frame. The data of the are 6 x 4 matrix is stored in the RAM. V2.3 7 PT6958 SERIAL COMMUNICATION FORMAT The following diagram shows the PT6958 serial communication format. The DOUT Pin is an N-channel, open-drain output pin, therefore, it is highly recommended that an external pull-up resistor (1 KΩ to 10 KΩ) must be connected to DOUT. where: twait (waiting time) ≥ 1 µs It must be noted that when the data is read, the waiting time (twait) between the rising of the eighth clock that has set the command and the falling of the first clock that has read the data is greater or equal to 1 µs. V2.3 8 PT6958 SWITCHING CHARACTERISTIC WAVEFORM PT6958 Switching Characteristics Waveform is given below. where: fosc = Oscillation Frequency PWSTB (Strobe Pulse Width) ≥ 1 µs tsetup (Data Setup Time) ≥ 100 ns tTZH (Segment Rise Time) ≤ 1 µs tTZL (Grid Fall Time) ≤ 2µs(VDD=3.3V) tTZL (Grid Fall Time) ≤ 1 µs(VDD=5V) tPZL (Propagation Delay Time) ≤ 200 ns(3.3V) tPZL (Propagation Delay Time) ≤ 100 ns(5V) PWCLK (Clock Pulse Width) ≥ 400 ns tCLK-STB (Clock - Strobe Time) ≥ 1 µs thold (Data Hold Time) ≥ 100 ns tTHZ (Segment Fall Time) ≤ 10 µs tTLZ (Grid Rise Time) ≤ 20 µs(VDD=3.3V) tTLZ (Grid Rise Time) ≤ 10 µs(VDD=5V) tPLZ (Propagation Delay Time) ≤ 600 ns(3.3V) tPLZ (Propagation Delay Time) ≤ 300 ns(5V) Note: Test Condition Under tTHZ, tTZH: Pull low resistor=10KΩ, Loading capacitor=300pF tTLZ, tTZL: Pull high resistor=10KΩ, Loading capacitor=300pF V2.3 9 PT6958 APPLICATIONS Display memory is updated by incrementing addresses. Please refer to the following diagram. where: Command 1: Data Setting Command Command 2: Address Setting Command Data 1 to n: Transfer Display Data (10 Byte max.) Command 3: Display Control Command The following diagram shows the waveforms when updating specific addresses. where: Command 1: Data Setting Command Command 2: Address Setting Command Data: Display Data V2.3 10 PT6958 RECOMMENDED SOFTWARE FLOWCHART Notes: 1. Command 1: Data Setting Commands. 2. Command 2: Address Setting Commands. 3. Command 3: Display Control Commands. 4. When IC power is applied for the first time, the contents of the Display RAM are not defined; thus, it is strongly suggested that the contents of the Display RAM must be cleared during the initial setting. V2.3 11 PT6958 SOP 28 (300MIL) THERMAL PERFORMANCE IN STILL AIR TJ= 100℃ Power Dissipation Pd (mW) 1200 1101 1000 800 IC Mounted on Glass Epoxy PCB 751 600 400 IC Single 200 0 -25 0 25 50 75 100 Ambient Temperature, Ta (℃) V2.3 12 PT6958 ABSOLUTE MAXIMUM RATINGS (Unless otherwise stated, Ta = 25℃, GND = 0 V) Parameter Symbol Supply Voltage VDD Logic Input Voltage VI IOLGR Driver Output Current IOHSG Operating Temperature Topr Storage Temperature Tstg Ratings -0.3 to +7 -0.3 to VDD+0.3 +250 -50 -40 ~ +85 -65 ~ +150 Unit V V mA mA ℃ ℃ RECOMMENDED OPERATING RANGE (Unless otherwise stated, Ta = -20 ~ +70℃, GND = 0 V) Parameter Symbol Condition Logic Supply Voltage VDD VDD Dynamic Current (See note) IDDdyn VDD VDD=5V High-Level Input Voltage VIH VDD=3.3V VDD=5V Low-Level Input Voltage VIL VDD=3.3V Note: Test Condition: Set Display Control Commands = 80H (Display Turn OFF State) V2.3 Min. 3.3 0.75VDD 0.75VDD 0 0 Typ. 5 - Max. 5.5 5 VDD VDD 0.3VDD 0.2VDD Unit V mA V V 13 PT6958 ELECTRICAL CHARACTERISTICS (Unless otherwise stated, VDD = 3.3V, GND = 0 V, Ta = 25℃) Parameter Symbol Test Conditions VO = VDD-1 V IOHSG(1) SG1 to SG10 High-Level Output Current VO = VDD-2 V IOHSG(2) SG1 to SG10 VO = 0.3 V Low-Level Output Current IOLGR GR1 to GR5 Low-Level Output Current IOLDOUT VO=0.4V VO = VDD-1 V Segment High-Level ITOLSG Output Current Tolerance SG1 to SG10 High-Level Input Voltage VIH Low-Level Input Voltage VIL Oscillation Frequency fosc R =33KΩ K1 to K4 K1 to K4 Pull Down Resistor RKN VDD = 3.3 V (Unless otherwise stated, VDD =5V, GND=0V, Ta=25℃) Parameter Symbol Test Condition VO= VDD -1V IOHSG(1) SG1 to SG10 High-Level Output Current VO= VDD -2V IOHSG(2) SG1 to SG10 VO=0.3V Low-Level Output Current IOLGR GR1 to GR5 Low-Level Output Current IOLDOUT VO=0.4V VO= VDD -1V Segment High-Level ITOLSG SG1 to SG10 Output Current Tolerance High-Level Input Voltage VIH Low-Level Input Voltage VIL Oscillation Frequency fosc R=51KΩ K1 to K4 K1 to K3 Pull Down Resistor RKN VDD =5V V2.3 Min. Typ. Max. Unit -8 -10 - mA -16 -20 - mA 65 85 - mA 3 - - mA - - ±5 % 0.75VDD 0 350 500 VDD 0.2VDD 650 V V KHz 90 - 180 KΩ Min. Typ. Max. Unit -10 -14 - mA -20 -25 - mA 100 140 - mA 4 - - mA - - ±5 % 0.75VDD 0 350 500 VDD 0.3VDD 650 V V KHz 40 - 100 KΩ 14 PT6958 PACKAGE INFORMATION 28-PIN, SOP, 300MIL Symbol A A1 b c D E E1 e L θ Min. 0.31 0.20 0.38 0° Nom. 17.90 BSC 10.30 BSC 7.50 BSC 1.27 BSC - Max. 2.65 0.30 0.51 0.33 1.27 8° Note: All controlling dimensions are in millimeters. V2.3 15 PT6958 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw V2.3 16