NEC UPD16342

DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16342
96-BIT AC-PDP DRIVER
DESCRIPTION
The µ PD16342 is a high withstand voltage CMOS driver designed for use with a flat display panel such as a PDP,
VFD, or EL panel. It consists of a 96-bit bi-directional shift register, 96-bit latch and high withstand voltage CMOS
driver. The logic block operates with a 5-V power supply interface (CMOS level input) so that it can be directly
connected to a gate array and CPU. The driver block provides a high withstand voltage output: 80 V, +15/–30 mA
MAX. The logic and driver blocks are made of CMOS circuits, consuming lower power.
FEATURES
• Circuit configuration switched by the IBS pin between three 32-bit bi-directional shift registers and six 16-bit
bi-directional shift registers.
• Data control with transfer clock (external) and latch
• High-speed data transfer (fMAX. = 40 MHz MIN. at data latch)
(fMAX. = 25 MHz MIN. at cascade connection)
• High withstand output voltage (80 V, +15/–30 mA MAX.)
• High withstand voltage CMOS structure
ORDERING INFORMATION
Part Number
Package
µ PD16342
Module/TCP
Remark
Consult an our sales representative regarding the module. Since the module characteristics is
based on the module specifications, there may be differences between the contents written in this
document and real characteristics.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S15090EJ2V0DS00 (2nd edition)
Date Published September 2001 NS CP (K)
Printed in Japan
The mark ★ shows major revised points.
©
2000
µ PD16342
★ 1. BLOCK DIAGRAM (1) (IBS = H, 3-BIT INPUT, 32-BIT LENGTH SHIFT REGISTER)
HZ
/LBLK
/HBLK
VDD2
/LE
SR1Note
A1
A1
S1
S4
CLK
CLK
R,/L
R,/L
B1
LE
S1
S2
S3
/L1
O1
VSS2
B1 CLR S94
/CLR
SR2Note
A2
A2
S2
CLK
S5
R,/L
B2
B2 CLR S95
SR3Note
A3
A3
S3
VDD2
S6
CLK
R,/L
B3
B3 CLR S96
S94
S95
S96
/L96
O96
VSS2
Note SRn: 32-bit shift register
Remark /xxx indicates active low signal.
2
Data Sheet S15090EJ2V0DS
µ PD16342
1. BLOCK DIAGRAM (2) (IBS = L, 6-BIT INPUT, 16-BIT LENGTH SHIFT REGISTER)
HZ
/LBLK
/HBLK
VDD2
/LE
A1
CLK
R,/L
B1
/CLR
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
SR1Note
A1
S1
S7
CLK
R,/L
S91
B1 CLR
SR2Note
A2
S2
S8
CLK
R,/L
B2 CLR S92
S1 LE
S2
/L1
S3
S4
S5
S6
O1
VSS2
SR3Note
A3
S3
S9
CLK
R,/L
B3 CLR S93
SR4Note
A4
S4
S10
CLK
R,/L
B4 CLR S94
SR5Note
A5
S5
S11
CLK
R,/L
B5 CLR S95
SR6Note
A6
S6
S12
CLK
R,/L
B6 CLR S96
VDD2
S93
S94
S95
S96
/L96
O96
VSS2
Note SRn: 16-bit shift register
Data Sheet S15090EJ2V0DS
3
µ PD16342
2. PIN FUNCTIONS
Symbol
Pin Name
I/O
Description
/LBLK
Low blanking
Input
/LBLK = L: All output = L
/HBLK
High blanking
Input
/HBLK = L: All output = H
/LE
Latch enable
Input
Latch on a falling edge
HZ
Output high impedance
Input
H: All output set to the high-impedance state
/CLR
Register clear
Input
L: All shift register data cleared to the L level
A1 to A3(6)
RIGHT data
Note
I/O
R,/L = H, A1 to A3(6): Input, B1 to B3(6): Output
The parenthesized pins are used in 6-bit input mode.
B1 to B3(6)
LEFT data
Note
I/O
R,/L = L, A1 to A3(6): Output, B1 to B3(6): Input
The parenthesized pins are used in 6-bit input mode.
CLK
Clock
Input
Shift on a rising edge
R,/L
Shift control
Input
H: Right shift mode
SR1: A1 → S1.......S94 → B1 (SR2 and SR6 also shift in the same direction.)
Left shift mode
SR1: B1 → S94.......S1 → A1 (SR2 and SR6 also shift in the same direction.)
IBS
Input mode switch
Input
H: 32-bit shift registers, 3-bit input mode
L: 16-bit shift registers, 6-bit input mode
O1 to O96
High withstand voltage
VDD1
Logic power supply
Output
−
5 V ± 5%
80 V, +15/–30 mA MAX.
VDD2
Driver power supply
−
15 to 70 V
VSS1
Logic ground
−
Connect to system ground
VSS2
Driver ground
−
Connect to system ground
Note In 3-bit input mode, unused I/O pins must be held at the L level.
To use for module, the back side of IC chip must be held at the VSS (GND) level.
4
Data Sheet S15090EJ2V0DS
µ PD16342
3. TRUTH TABLE
Shift Register Block
Input
Output
R,/L
CLK
H
↑
H
H or L
L
↑
L
H or L
Shift Register
A
B
Input
Output
Output
Note1
Right shift operation performed
Output
Hold
Note2
Output
Left shift operation performed
Input
Hold
Notes 1. On the rising edge of the clock, the data of S91 to S93 (S85 to S90) is shifted to S94 to S96 (S91 to S96), and is
output from B1 to B3 (B1 to B6) (The parenthesized pins are used in 6-bit input mode.).
2. On the rising edge of the clock, the data of S4 to S6 (S7 to S12) is shifted to S1 to S3 (S1 to S6), and is output
from A1 to A3 (A1 to A6) (The parenthesized pins are used in 6-bit input mode.).
Latch Block
/LE
Output State of Latch Section (/Ln)
↓
Latch Sn data
H or L
Hold latch (output) data
Driver Block
A (B)
/HBLK
/LBLK
HZ
x
L
H
L
All driver output: H
x
x
L
L
All driver output: L
x
x
x
H
All driver output: High Impedance
L
H
H
L
L
H
H
H
L
H
Remark
Output State of Driver Block
x: H or L, H: High level, L: Low level
Data Sheet S15090EJ2V0DS
5
µ PD16342
Timing Chart (1) (IBS = H, 3-bit input, right shift)
/CLR
CLK
A1 (B3)
A2 (B2)
A3 (B1)
S1 (S96)
S2 (S95)
S3 (S94)
S4 (S93)
S5 (S92)
S6 (S91)
/LE
(Latch on falling edge)
/HBLK
/LBLK
HZ
High-impedance
O1 (O96)
O2 (O95)
O3 (O94)
O4 (O93)
O5 (O92)
O6 (O91)
Remark Values in parentheses are when R,/L = L.
6
Data Sheet S15090EJ2V0DS
µ PD16342
Timing Chart (2) (IBS = L, 6-bit input, right shift)
/CLR
CLK
A1 (B6)
A2 (B5)
A3 (B4)
A4 (B3)
A5 (B2)
A6 (B1)
S1 (S96)
S2 (S95)
S3 (S94)
S4 (S93)
S5 (S92)
S6 (S91)
S7 (S90)
/LE
(Latch on falling edge)
/HBLK
/LBLK
HZ
High-impedance
O1 (O96)
O2 (O95)
O3 (O94)
O4 (O93)
O5 (O92)
O6 (O91)
O7 (O90)
Remark Values in parentheses are when R,/L = L.
Data Sheet S15090EJ2V0DS
7
µ PD16342
4. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°°C, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Ratings
Unit
Logic Supply Voltage
VDD1
–0.5 to +6.0
V
Driver Supply Voltage
VDD2
–0.5 to +80
V
Logic Input Voltage
VI
–0.5 to VDD1 + 0.5
V
Driver Output Current
IO2
+15/–30
mA
Operating Junction Temperature
TJ
+125
°C
Storage Temperature
Tstg
–65 to +150
°C
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Range (TA = −40 to +85°°C, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
5.0
5.25
V
Logic Supply Voltage
VDD1
4.75
Driver Supply Voltage
VDD2
15
70
V
High-Level Input Voltage
VIH
2.7
VDD1
V
Low-Level Input Voltage
VIL
0
0.6
V
Driver Output Current
IOH2
–24
mA
IOL2
+13
mA
8
Data Sheet S15090EJ2V0DS
µ PD16342
Electrical Characteristics (TA = 25°°C, VDD1 = 5.0 V, VDD2 = 70 V, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
0.9 VDD1
VDD1
V
0.1 VDD1
V
High-Level Output Voltage
VOH1
Logic, IOH1 = –1.0 mA
Low-Level Output Voltage
VOL1
Logic, IOL1 = 1.0 mA
0
High-Level Output Voltage
VOH21
O1 to O96, IOH2 = –0.52 mA
69
V
VOH22
O1 to O96, IOH2 = –5.2 mA
65
V
VOL21
O1 to O96, IOL2 = 1.6 mA
1.0
V
VOL22
O1 to O96, IOL2 = 13 mA
10
V
Input Leakage Current
IIL
V1 = VDD1 or VSS1
±1.0
µA
High-Level Intput Voltage
VIH
VDD1 = 4.75 to 5.25 V
2.7
VDD1
V
Low-Level Input Voltage
VIL
VDD1 = 4.75 to 5.25 V
0
0.6
V
Static Current Dissipation
IDD11
Logic, TA = –40 to +85°C
500
µA
Logic, TA = 25°C
300
µA
Low-Level Output Voltage
IDD12
Logic, TA = –40 to +85°C
Logic, TA = 25°C
IDD2
10
Note
10
Note
mA
mA
Driver, TA = –40 to +85°C
1000
µA
Driver, TA = 25°C
100
µA
Note When input all input high-level (VIH = 2.7 V to VDD1, but both R,/L and IBS pin are fixed by VI = VSS1 or VDD1)
Data Sheet S15090EJ2V0DS
9
µ PD16342
Switching Characteristics (TA = 25°°C, VDD1 = 5.0 V, VDD2 = 70 V, VSS1 = VSS2 = 0 V, Logic CL = 15 pF,
Driver CL = 50 pF, tr = tf = 6.0 ns)
Parameter
Propagation Delay Time
Symbol
tPHL1
Conditions
MIN.
CLK ↑ → A/B
tPLH1
tPHL2
/LE ↓ → O1 to O96
tPLH2
tPHL3
/HBLK → O1 to O96
tPLH3
tPHL4
/LBLK → O1 to O96
tPLH4
Rise Time
Fall Time
Maximum Clock Frequency
Input Capacitance
10
TYP.
MAX.
Unit
34
ns
34
ns
220
ns
220
ns
205
ns
205
ns
200
ns
200
ns
tPHZ
HZ → O1 to O96,
340
ns
tPZH
RL = 10 kΩ
220
ns
tPLZ
340
ns
tPZL
220
ns
O1 to O96
220
ns
tTLZ
O1 to O96,
3
µs
tTZH
RL = 10 kΩ
220
ns
tTHL
O1 to O96
350
ns
tTHZ
O1 to O96,
3
µs
tTZL
RL = 10 kΩ
350
ns
fMAX.
Data latch, duty = 50%
40
MHz
Cascade connection, duty = 50%
25
MHz
tTLH
CI
15
Data Sheet S15090EJ2V0DS
pF
µ PD16342
Timing Requirement (TA = –40 to +85°°C, VDD1 = 4.75 to 5.25 V, VSS1 = VSS2 = 0 V, tr = tf = 6.0 ns)
Parameter
Clock Pulse Width
Symbol
Conditions
PW CLK(H)
MIN.
TYP.
MAX.
Unit
12
ns
12
ns
PW CLK(L)
Latch Enable Pulse Width
PW /LE(H)
PW /LE(L)
Blank Pulse Width
PW /BLK
/HBLK, /LBLK
600
ns
HZ Pulse Width
PW HZ
RL = 10 kΩ
3.3
µs
/CLR Pulse Width
PW /CLR
12
ns
Data Setup Time
tSETUP
4
ns
Data Hold Time
tHOLD
6
ns
Latch Enable Time
t/LE1
12
ns
t/LE2
12
ns
t/CLR
6
ns
/CLR Timing
Data Sheet S15090EJ2V0DS
11
µ PD16342
★
Switching Characteristics Waveform (1/3)
1/fMAX.
PWCLK (H)
PWCLK (L)
3.3 V
50%
50%
50%
CLK
VSS1
tSETUP
An/Bn
(Input)
tHOLD
3.3 V
50%
50%
VSS1
tPHL1
tPLH1
VOH1
Bn/An
(Output)
50%
50%
VOL1
3.3 V
/LE
50%
50%
VSS1
PW/LE (H)
PW/LE (L)
t/LE1
t/LE2
3.3 V
50%
50%
CLK
VSS1
tTHL
tPHL2
VOH2
90%
On
10%
tTLH
tPLH2
90%
10%
On
12
Data Sheet S15090EJ2V0DS
VOL2
VOH2
VOL2
µ PD16342
★ Switching Characteristics Waveform (2/3)
PW/BLK
3.3 V
/LBLK
50%
50%
VSS1
tPHL4
tPLH4
VOH2
90%
On
10%
VOL2
PW/BLK
3.3 V
/HBLK
50%
50%
VSS1
tPHL3
tPLH3
VOH2
90%
On
10%
VOL2
PW/CLR
3.3 V
50%
50%
/CLR
VSS1
t/CLR
3.3 V
50%
CLK
VSS1
Clock rising edge for valid data
Data Sheet S15090EJ2V0DS
13
µ PD16342
★
Switching Characteristics Waveform (3/3)
PWHZ
3.3 V
HZ
50%
50%
VSS1
tPLZ
tPZL
tTLZ
tTZL
VO (H)
90%
90%
On
10%
10%
VOL2
VOH2
90%
90%
On
10%
tPHZ
14
tTHZ
Data Sheet S15090EJ2V0DS
10%
tPZH
tTZH
VO (L)
µ PD16342
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S15090EJ2V0DS
15