DATA SHEET MOS INTEGRATED CIRCUIT µPD16335 96-Bit AC-PDP DRIVER The µPD16335 is a high-voltage CMOS driver designed for flat display panels such as PDPs, VFDs and ELs. It consists of a 96-bit bi-directional shift register, 96-bit latch and high-voltage CMOS driver. The logic block is designed to operate using a 5-V power supply enabling direct connection to a gate array or a microcontroller. In addition, the µPD16335 achieves low power dissipation by employing CMOS structure while having a high withstand voltage output (80 V, +50/–75 mA). FEATURES • Selectable by IBS pin; three 32-bit bi-directional shift register circuits configuration or six 16-bit bi-directional shift register circuits configuration • Data control with transfer clock (external) and latch • High-speed data transfer (fmax. = 25 MHz min. at data fetch) (fmax. = 16 MHz min. at cascade connection) • High withstand output voltage (80 V, +50/–75 mAMAX.) • 5 V CMOS input interface • High withstand voltage CMOS structure • Capable of reversing all driver outputs by PC pin ORDERING INFORMATION Part Number µPD16335 Package COBNote Note Please consult with an NEC sales representative about COB. Document No. S12192EJ2V0DS00 (2nd edition) Date Published May 1998 N CP(K) Printed in Japan © 1998 µPD16335 BLOCK DIAGRAM (IBS = H, 3-BIT INPUT, 32-BIT LENGTH SHIFT REGISTER) OE PC BLK VDD2 LE SR1 A1 A1 CLK CLK R/L R/L B1 B1 S1 S.4 .. .. .. .. .. .. .. . S94 S1 S2 S3 SR2 A2 A2 CLK R/L B2 B2 A3 A3 S2 S.5 .. .. .. .. .. .. .. . S95 SR3 CLK R/L B3 B3 S3 S.6 .. .. .. .. .. .. .. . S96 S94 S95 S96 L1 .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . L96 .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. VSS2 VDD2 O96 SRn: 32-bit shift register VSS2 2 O.1 .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . µPD16335 BLOCK DIAGRAM (IBS = L, 6-BIT INPUT, 16-BIT LENGTH SHIFT REGISTER) OE PC BLK VDD2 LE A1 CLK R/L B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 SR1 A1 S1 CLK S.7 .. R/L S91 B1 SR2 A2 S2 CLK S.8 .. R/L S92 B2 SR3 A3 S3 CLK S.9 .. R/L S93 B3 SR4 A4 S4 CLK S10 .. . R/L S94 B4 SR5 A5 S5 CLK S11 .. . R/L S95 B5 SR6 A6 S6 CLK S12 .. . R/L S96 B6 S1 LE S2 S3 S4 S5 S.6 .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . S93 S94 S95 S96 L1 .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . L96 .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . VSS2 VDD2 O.1 .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. . O96 SRn: 16-bit shift register VSS2 3 µPD16335 PIN DESCRIPTION Symbol Pin Name Description PC Polarity change input PC = L: All driver output invert BLK Blank input BLK = H: All output = H or L LE Latch enable input Data latch by rising edge of this signal. OE Output enable Make output high impedance by input H input/outputNote A1 to A3 (6) RIGHT data B1 to B3 (6) LEFT data input/outputNote When R/L = L (values in parentheses are for 6-bit input) A1 to A3 (6): Output B1 to B3 (6): Input CLK Clock input Shift executed on fall R/L Shift control input Right shift mode when R/L = H SR1: A1 → S1 ··· S94 → B1 (Same direction for SR2 to SR6) Left shift mode when R/L = L SR1: B1 → S94 ··· S1 → A1 (Same direction for SR2 to SR6) IBS Input mode switch H: 32-bit length shift register, 3-bit input L: 16-bit length shift register, 6-bit input O1 to O96 High withstand voltage output 80 V, +50/–75 mA VDD1 Power supply for logic block 5 V ±10% VDD2 Power supply for driver block 10 to 70 V VSS1 Logic GND Connect to system GND VSS2 Driver GND Connect to system GND When R/L = H (values in parentheses are for 6-bit input) A1 to A3 (6): Input B1 to B3 (6): Output MAX . Note When input mode is 3-bit, set unused input and output pins “L” level. TRUTH TABLE 1 (Shift Register Block) Input Output R/L CLK H ↓ H H or L L ↓ L H or L Shift Register A Input OutputNote 2 B OutputNote 1 Right shift execution Output Hold Input Left shift execution Output Hold Notes 1. The data of S91 to S93 (S85 to S90) shifts to S94 to S96 (S91 to S96) and is output from B1 to B3 (B1 to B6) at the falling edge of the clock, respectively. (Values in parentheses are for 6-bit input) 2. The data of S4 to S6 (S7 to S12) shifts to S1 to S 3 (S1 to S6) and is output from A1 to A 3 (A1 to A6) at the falling edge of the clock, respectively (Values in parentheses are for 6-bit input) TRUTH TABLE 2 (Latch Block) LE Output State of Latch Block (Ln) ↑ Latch Sn data H or L Hold latch data TRUTH TABLE 3 (Driver Block) 4 Ln BLK PC OE X H H L H (All driver outputs: H) X H L L L (All driver outputs: L) X L H L Output latch data (Ln) X L L L Output inverted latch data (Ln) X X X H Set output impedance high X: H or L, H: High level, L: Low level Output State of Driver Block µPD16335 TIMING CHART (WHEN IBS = “H”: 3-BIT INPUT, RIGHT SHIFT) Values in parentheses in the following chart are when R/L = L. CLK A1 (B3) A2 (B2) A3 (B1) S1 (S96) S2 (S95) S3 (S94) S4 (S93) S5 (S92) S6 (S91) LE Latch by rising edge BLK PC OE High impedance O1 (O96) O2 (O95) O3 (O94) O4 (O93) O5 (O92) O6 (O91) 5 µPD16335 TIMING CHART (WHEN IBS = “L”: 6-BIT INPUT, RIGHT SHIFT) Values in parentheses in the following chart are when R/L = L. CLK A1 (B6) A2 (B5) A3 (B4) A4 (B3) A5 (B2) A6 (B1) S1 (S96) S2 (S95) S3 (S94) S4 (S93) S5 (S92) S6 (S91) S7 (S90) LE Latch by rising edge BLK PC OE High impedance O1 (O96) O2 (O95) O3 (O94) O4 (O93) O5 (O92) O6 (O91) O7 (O90) 6 µPD16335 ABSOLUTE MAXIMUM RATINGS (TA = 25°C, VSS1 = VSS2 = 0 V) Parameter Symbol Ratings Unit Logic Block Supply Voltage VDD1 –0.5 to +7.0 V Driver Block Supply Voltage VDD2 –0.5 to +80 V Logic Block Input Voltage VI –0.5 to VDD1 +0.5 V Driver Block Output Current IO2 +50/–75 mA Junction Temperature Tj ±125 °C Storage Temperature Tstg. –65 to +150 °C RECOMMENDED OPERATING CONDITIONS (TA = –40 to +85°C, VSS1 = VSS2 = 0 V) Parameter Symbol MIN. TYP. MAX. Unit Logic Block Supply Voltage VDD1 4.5 5.0 5.5 V Driver Block Supply Voltage VDD2 10 70 V High-Level Input Voltage VIH 0.7 VDD1 VDD1 V Low-Level Input Voltage VIL 0 0.2 VDD1 V Driver Output Current IOH2 –60 mA IOL2 +40 mA Caution In order to prevent latch-up breakage, be sure to enter the power to VDD1, logic signal and VDD2 in that order, and turn off the power in the reverse order, keep this order also during a transition period. ELECTRICAL SPECIFICATIONS (TA = 25°C, VDD1 = 5.0 V, VDD2 = 70 V, VSS1 = VSS2 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 0.9 VDD1 VDD1 V 0.1 VDD1 V High-Level Output Voltage VOH1 Logic, IOH1 = –1.0 mA Low-Level Output Voltage VOL1 Logic, IOL1 = 1.0 mA 0 High-Level Output Voltage VOH21 O1 to O96, IOH2 = –1.3 mA 69 V VOH22 O1 to O96, IOH2 = –13 mA 65 V VOL21 O1 to O96, IOL2 = 5 mA 1.0 V VOL22 O1 to O96, IOL2 = 40 mA 10 V ±1.0 µA Low-Level Output Voltage Input Leakage Current IIL High-Level Input Voltage VIH Low-Level Input Voltage VIL Static Current Dissipation IDD1 VI = VDD1 or VSS1 0.7 VDD1 V 0.2 VDD1 V Logic, TA = –40 to +85° 100 µA IDD1 Logic, TA = 25°C 10 µA IDD2 Driver, TA = –40 to +85° 1000 µA IDD2 Driver, TA = 25°C 100 µA 7 µPD16335 SWITCHING CHARACTERISTICS (TA = 25°C, VDD1 = 5.0 V, VDD2 = 130 V, VSS1 = VSS2 = 0 V, logic CL = 15 pF, driver CL = 50 pF, tr = tf = 6.0 ns) Parameter Transmission Delay Time Symbol tPHL1 Conditions MIN. TYP. CLK ↓ → A/B tPLH1 tPHL2 CLK ↑ (LE = H) → O1 to O96 tPLH2 tPHL3 BLK → O1 to O96 tPLH3 tPHL4 PC → O1 to O96 tPLH4 Rise Time Fall Time Maximum Clock Frequency Input Capacitance MAX. Unit 55 ns 55 ns 180 ns 180 ns 165 ns 165 ns 160 ns 160 ns tPHZ OE → O1 to O96 300 ns tPZH RL = 10 kΩ 180 ns tPLZ 300 ns tPZL 180 ns 120 ns 3 µs tTLH O1 to O96 tTLZ RL = 10 kΩ tTZH O1 to O96 120 ns tTHL O1 to O96 150 ns tTHZ RL = 10 kΩ 3 µs tTZL O1 to O96 150 ns fmax. When data is read, duty 50% 25 MHz cascade connection, Duty 50% 16 MHz CI 15 pF TIMING REQUIREMENT (TA = –40 to +85°C, VDD1 = 4.5 to 5.5 V, VSS1, 2 = 0 V, tr = tf = 6.0 ns) Parameter 8 Symbol Condition MIN. TYP. MAX. Unit Clock Pulse Width PWCLK 20 ns Latch Enable Pulse Width PWLE 20 ns Blank Pulse Width PWBLK 200 ns PC Pulse Width PWPC 200 ns OE Pulse Width PWOE 3.3 µs Data Setup Time tsetup 7 ns Data Hold Time thold 10 ns Latch Enable Time 1 tLE1 20 ns Latch Enable Time 2 tLE2 20 ns RL = 10 kΩ µPD16335 SWITCHING CHARACTERISTICS WAVEFORM 1/fmax. PWCLK (H) PWCLK (L) 3.3 V CLK 50% 50% 50% VSS1 tsetup thold 3.3 V An/Bn (Input) 50% 50% VSS1 tPHL1 tPLH1 VOH1 Bn/An (Output) 50% 50% VOL1 3.3 V LE 50% 50% VSS1 PWLE tLE1 tLE2 3.3 V CLK 50% 50% VSS1 tPHL2 90% On VOH2 VOL2 tPLH2 VOH2 On 10% VOL2 9 µPD16335 PWBLK 3.3 V BLK 50% 50% VSS1 tPHL3 tPLH3 VOH2 90% On 10% VOL2 PWPC 3.3 V PC 50% 50% VSS1 tPHL4 tPLH4 VOH2 90% On 10% VOL2 PWOE 3.3 V OE 50% 50% VSS1 tPLZ tTLZ tPZL tTZL VO (H) 90% 90% On 10% 10% VOL2 VOH2 90% 90% On 10% 10% VO (L) tPHZ 10 tTHZ tPZH tTZH µPD16335 [MEMO] 11 µPD16335 No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. 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Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5