NJRC NJU6854

NJU6854
132COMMON x 132RGB LCD DRIVER
FOR 65,536-COLOR STN DISPLAY
! GENERAL DESCRIPTION
The NJU6854 is a 132COMMON x 132RGB LCD driver for
65,536-color STN display. It contains common drivers, RGB drivers, a
serial and a parallel MPU interface circuit, an internal LCD power supply,
grayscale palettes and 278,784-bit display data RAM. The segment
drivers for RGB (Red, Green, Blue) independently produce optimum 64
or 32 grayscales from a built-in grayscale palette, and the LSI achieves
65,536 colors (64x32x32).
In addition, the NJU6854 operates with a low voltage of 1.7V and a
low operating current, therefore it is ideally suited for battery-powered
handheld applications.
PACKAGE
BUMP CHIP
! FEATURES
#
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65,536-color STN LCD driver
Built-in LCD Drivers
: 132-common x 132RGB (396-segment drivers)
Built-in Display Data RAM (DDRAM) : 278,784 bits for Graphic Display
Programmable Display Mode
- 64 grayscales(Green)
- 32 grayscales(Red, Blue)
3 Areas Partial Display
8-/16-bit Parallel Interface Selectable
8-/16-bit Bus Length for Display Data Selectable
3-/4-line Serial Interface Selectable
Programmable Duty Ratio and Bias Ratio
Programmable Internal Voltage Booster : Maximum 6 times
Programmable Contrast Control
: 128-step Electronic Volume Register (EVR)
Various Useful Instructions
Low Operating Current
Low Logic Voltage
: 1.7V to 3.3V
Wide LCD Voltage Range
: 5.0V to 18.0V
C-MOS Technology
Slim Chip for COG
Package
: Bump Chip
Ver.2004-06-29
-1-
NJU6854
TABLE OF CONTENTS
! GENERAL DESCRIPTION
PACKAGE........................................................................................... 1
! FEATURES ................................................................................................................................................... 1
! PAD LOCATION............................................................................................................................................ 4
! PAD COORDINATES.................................................................................................................................... 6
! BLOCK DIAGRAM ..................................................................................................................................... 12
! LCD POWER SUPPLY BLOCK DIAGRAM ............................................................................................... 13
! TERMINAL DESCRIPTION ........................................................................................................................ 14
! FUNCTIONAL DESCRIPTION ................................................................................................................... 17
(1) MPU INTERFACE.................................................................................................................................... 17
(1-1) Selection of Parallel/Serial Interface Mode....................................................................................................................17
(1-2) Selection of MPU Mode.................................................................................................................................................17
(1-3) Data Recognition ...........................................................................................................................................................17
(1-4) Selection of 3-/4-line Serial Interface Mode...................................................................................................................17
(1-5) 4-line Serial Interface Mode...........................................................................................................................................17
(1-6) 3-line Serial Interface Mode...........................................................................................................................................18
(1-7) Data Write......................................................................................................................................................................19
(1-8) Data Read .....................................................................................................................................................................21
(1-9) Selection of 8-/16-bit Bus Length (Parallel Interface Mode) ..........................................................................................22
(2) INITIAL DISPLAY LINE............................................................................................................................ 22
(3) DDRAM.................................................................................................................................................... 23
(3-1) DDRAM Address Range................................................................................................................................................23
(3-2) Window Area for DDRAM Access..................................................................................................................................23
(3-3) DDRAM Access Direction..............................................................................................................................................24
(3-4) Segment Shift Direction.................................................................................................................................................26
(3-5) Block Diagram of DDRAM and Peripheral Circuit..........................................................................................................26
(3-6) DDRAM Mapping...........................................................................................................................................................27
(3-6-1)
(REW, SWAP) = (0,0), SHIFT1 = “0”, SHIFT0 = “0”, VPC = "84H“ (1/132 Duty), FVC = "00H", HCT = “00H”,
SSC1 and SSC2 = “0”, EN3PTL = “0”................................................................................................................................27
(3-6-2)
(REW, SWAP) = (0,0), SHIFT1 = “0”, SHIFT0 = “0”, VPC = "70H“ (1/112 Duty), FVC = "00H", HCT = “0AH”,
SSC1 and SSC2 = “0”, EN3PTL = “0”................................................................................................................................28
(3-7) The Relationship among Bit Assignment, X address and Segment Driver ....................................................................29
(4) PWM CONTROL...................................................................................................................................... 36
(5) FRAME RATE CONTROL(FRC) ............................................................................................................. 36
(6) DISPLAY TIMING GENERATOR............................................................................................................. 36
(7) DATA LATCH CIRCUIT............................................................................................................................ 36
(8) COMMON DRIVERS AND SEGMENT DRIVERS .................................................................................. 37
(9) OSCILLATOR........................................................................................................................................... 38
(10) LCD POWER SUPPLY ............................................................................................................................ 38
(10-1) Voltage Booster ...........................................................................................................................................................39
(10-2) Electrical Volume Register (EVR) ................................................................................................................................39
(10-3) Voltage Converter........................................................................................................................................................40
(10-3-1) Voltage Regulator .............................................................................................................................................40
(10-3-2) Reference Voltage Generator ...........................................................................................................................41
(10-3-3) LCD Bias Voltage Generator.............................................................................................................................41
(10-4) External Components for LCD Power Supply..............................................................................................................42
(10-5) Power ON/OFF............................................................................................................................................................45
(10-6) Discharge Circuit .........................................................................................................................................................45
(10-7) Reset Function ............................................................................................................................................................46
(11) INSTRUCTION TABLES.......................................................................................................................... 47
(12) INSTRUCTION DESCRIPTIONS ............................................................................................................ 51
(12-1) 8-bit Access Mode .......................................................................................................................................................51
(12-1-1) Instruction Register...........................................................................................................................................51
-2-
Ver.2004-06-29
NJU6854
(12-1-2) Auto-increment of Instruction Register Address................................................................................................52
(12-2) 16-bit Access Mode .....................................................................................................................................................53
(12-2-1) Instruction Register...........................................................................................................................................53
(12-2-2) Auto Increment of Instruction Register Address................................................................................................53
(12-3) Oscillation Control .......................................................................................................................................................54
(12-4) Display Data Assignment/ Window Area ONOFF/Increment Control...........................................................................54
(12-5) Display Line Number ...................................................................................................................................................55
(12-6) Blank Line Number ......................................................................................................................................................55
(12-7) X Address ....................................................................................................................................................................56
(12-8) Y Address ....................................................................................................................................................................56
(12-9) Window End X Address ...............................................................................................................................................56
(12-10) Window End Y Address .............................................................................................................................................56
(12-11) Display Mode/Grayscale Mode ..................................................................................................................................56
(12-12) Oscillating Frequency Adjustment/Frequency Dividing..............................................................................................60
(12-13) Header COM .............................................................................................................................................................61
(12-14) Initial Display Line......................................................................................................................................................61
(12-15) Scan Start COM 1......................................................................................................................................................62
(12-16) Scan Start COM 2......................................................................................................................................................62
(12-17) Line Number of Partial Display 1 ...............................................................................................................................62
(12-18) Line Number of Partial Display 2 ...............................................................................................................................62
(12-19) N-Line Inversion ........................................................................................................................................................62
(12-20) Power Control 1.........................................................................................................................................................63
(12-21) Electronic Volume Control .........................................................................................................................................64
(12-22) Display Timing Signal Monitor/PBX Palette ...............................................................................................................64
(12-23) Power Control 2.........................................................................................................................................................65
(12-24) Booster Level/Amplifier Gain .....................................................................................................................................66
(12-25) Voltage Booster Clock ...............................................................................................................................................67
(12-26) Display Control ..........................................................................................................................................................68
(12-27) PWM Control .............................................................................................................................................................69
(12-28) Three Partial Display Areas/ LED Driver Control/REV Bit..........................................................................................70
(12-29) Discharge ON/OFF....................................................................................................................................................72
(12-30) LED Driver Data ........................................................................................................................................................72
(12-31) Instruction Table/Address ..........................................................................................................................................72
(12-32) Scan Start COM 3......................................................................................................................................................73
(12-33) Line Number of Partial Display 3 ...............................................................................................................................73
(12-34) Grayscale Palette (PA0~PA31, PB0~PB31, PC0~PC31) ..........................................................................................74
(13) PARTIAL DISPLAY FUNCTION............................................................................................................... 89
(14) RELATIONSHIP BETWEEN LOGICAL COM NUMBER AND PHYSICAL COMMON DRIVER............. 90
(15) TYPICAL INSTRUCTION SEQUENCES ................................................................................................ 95
! ABSOLUTE MAXIMUM RATINGS............................................................................................................. 98
! RECOMMENDED OPERATING CONDITIONS ......................................................................................... 98
! DC CHARACTERISTICS............................................................................................................................ 99
! AC CHARACTERISTICS.......................................................................................................................... 101
(1) Write operation (80-type MPU) .............................................................................................................. 101
(2) Read operation (80-type MPU).............................................................................................................. 102
(3) Write operation (68-type MPU) .............................................................................................................. 103
(4) Read operation (68-type MPU).............................................................................................................. 104
(5) Serial interface ....................................................................................................................................... 105
(6) Display control timing............................................................................................................................. 106
(7) Reset input timing .................................................................................................................................. 107
! INPUT/OUTPUT BLOCK DIAGRAM ....................................................................................................... 108
! MPU CONNECTIONS............................................................................................................................... 110
Ver.2004-06-29
-3-
NJU6854
SEGC67
SEGB67
SEGA67
SEGC66
SEGB66
SEGA66
COMB1
COMB0
DUMMY
DUMMY
SEGC131
SEGB131
SEGA131
SEGC130
SEGB130
SEGA130
DUMMY
COMB25
COMB24
COMB23
! PAD LOCATION
DUMMY
COMB26
COMB27
COMB28
COMB29
COMB30
COMB31
COMB32
VREF
VSSH
VBA
VREF
VEE
VBA
VDD
VEE
VSSL
VDD
DUMMY
VSSH
VSSH
LDAT
LSCK
LREQ
LRESB
TEST
SEL68
PS
VDDA
RESB
CSB
RS
WRB
RDB
VDDA
VSSA
D0
D1
D2
D3
D4
D5
D6
D7
VDDA
VSSA
D8
D9
D10
D11
D12
D13
D14
D15
LP
M
FLM
OSCO
OSCI
VSSL
COMB59
COMB60
COMB61
COMB62
COMB63
COMB64
COMB65
DUMMY
SEGA0~SEGC131, COMA0~COMA25, COMB0~COMB25, DUMMY
23
140
COMA26~COMA65, COMB26~COMB65, DUMMY
140
23
15
15
CPU interface pads and other pads
50
50
50
15
115
15
115
180
245
15, 40, 65, 115, 120
Bump Material : Au (gold)
-4-
Ver.2004-06-29
CO M A23
CO M A24
CO M A25
DU M MY
SEG C1
SEG B1
SEG A1
SEG C0
SEG B0
SEG A0
DU M MY
DU M MY
CO M A0
CO M A1
SEG C65
SEG B65
SEG A65
SEG C64
SEG B64
SEG A64
NJU6854
DUMMY
COMA26
COMA27
COMA28
COMA29
COMA30
COMA31
COMA32
VSSH
D UM M Y
V4
VSSH
V3
V4
V2
V3
V1
V2
V0
V1
C 5N
V0
C 5P
C 5N
C 4N
C 5P
C 4P
C 4N
C 3N
C 4P
C 3P
C 3N
C 2N
C 3P
C 2P
C 2N
C 1N
C 2P
C 1P
C 1N
VO U T
C 1P
VR EG
VO U T
VSSH
VR EG
COMA59
COMA60
COMA61
COMA62
COMA63
COMA64
COMA65
DUMMY
Note 1) The pads with the same name are connected within the chip.
Note 2) Dummy pads are kept open..
UNIT: um
ITEMS
SIZE
REMARK / PAD NO.
Chip size
PAD pitch / space
(bump)
X
17,643
With scribe lane (100 um)
Driver pads pitch
Interface pads
Driver sides
Interface sides
Driver sides
Interface sides
All pads
PAD open side
PAD size (bump)
BUMP height
Y
2,180
38
70~170
9
9
23
50
126
96
140
115
17.5
ALIGN MARK DESIGN
pattern
forbidden
area
bump
50
50
25
metal only
25
metal only
25
50
25
50
25
25
left bottom align mark
25
50
50
25
bump
right bottom align mark
Coordinates LEFT BOTTOM : X= -8157.92 Y= -515.62
RIGHT BOTTOM : X= 8157.92 Y= -515.62
Ver.2004-06-29
-5-
NJU6854
! PAD COORDINATES
chip size 17,643×2,180 µm ( chip center = 0:0 )
2
PAD
No.
Pad name
X(µm)
Y(µm)
PAD
No.
Pad name
X (µm)
Y (µm)
PAD
No.
Pad name
X (µm)
Y (µm)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DUMMY
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
LDAT
LSCK
LREQ
LRESb
TEST
SEL68
PS
VDDA
RESb
CSb
RS
WRb
RDb
VDDA
VSSA
D0
D1
D2
D3
D4
D5
D6
D7
VDDA
VSSA
D8
D9
D10
D11
D12
D13
D14
-8620.0
-8530.0
-8465.0
-8400.0
-8335.0
-8270.0
-8205.0
-8140.0
-8075.0
-8010.0
-7945.0
-7880.0
-7815.0
-7750.0
-7685.0
-7620.0
-7555.0
-7490.0
-7375.0
-7260.0
-7145.0
-7030.0
-6915.0
-6800.0
-6685.0
-6570.0
-6455.0
-6340.0
-6225.0
-6110.0
-5995.0
-5880.0
-5765.0
-5650.0
-5535.0
-5420.0
-5305.0
-5190.0
-5075.0
-4960.0
-4845.0
-4730.0
-4615.0
-4500.0
-4385.0
-4270.0
-4155.0
-4040.0
-3925.0
-3810.0
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
D15
LP
M
FLM
OSCO
OSCI
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VBA
VBA
VBA
VBA
VBA
VREF
VREF
VREF
VREF
VREF
VSSHA
VSSHA
VSSHA
VSSHA
VSSHA
VSSHA
-3695.0
-3580.0
-3465.0
-3350.0
-3235.0
-3120.0
-3005.0
-2940.0
-2875.0
-2810.0
-2745.0
-2680.0
-2615.0
-2525.0
-2460.0
-2395.0
-2330.0
-2265.0
-2200.0
-2110.0
-2045.0
-1980.0
-1915.0
-1850.0
-1785.0
-1720.0
-1655.0
-1590.0
-1525.0
-1460.0
-1395.0
-1330.0
-1265.0
-1200.0
-1110.0
-1045.0
-980.0
-915.0
-850.0
-760.0
-695.0
-630.0
-565.0
-500.0
-410.0
-345.0
-280.0
-215.0
-150.0
-85.0
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
VSSHA
VSSHA
VSSHA
VSSHA
VREG
VREG
VREG
VREG
VREG
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
C1+
C1+
C1+
C1+
C1+
C1+
C1C1C1C1C1C1C2+
C2+
C2+
C2+
C2+
C2+
C2C2C2C2C2C2C3+
C3+
C3+
C3+
C3+
C3+
C3C3C3C3C3-
-20.0
45.0
110.0
175.0
340.0
405.0
470.0
535.0
600.0
690.0
755.0
820.0
885.0
950.0
1015.0
1105.0
1170.0
1235.0
1300.0
1365.0
1430.0
1520.0
1585.0
1650.0
1715.0
1780.0
1845.0
1935.0
2000.0
2065.0
2130.0
2195.0
2260.0
2350.0
2415.0
2480.0
2545.0
2610.0
2675.0
2765.0
2830.0
2895.0
2960.0
3025.0
3090.0
3180.0
3245.0
3310.0
3375.0
3440.0
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-6-
Ver.2004-06-29
NJU6854
chip size 17,643×2,180 µm2 (chip center = 0:0 )
PAD
No.
Pad name
X(µm)
Y(µm)
C3C4+
C4+
C4+
C4+
C4+
C4+
C4C4C4C4C4C4C5+
C5+
C5+
C5+
C5+
C5+
C5C5C5C5C5C5V0
V0
V0
V0
V0
V0
V1
V1
V1
V1
V1
V1
V2
V2
V2
V2
V2
V2
V3
V3
V3
V3
V3
V3
V4
3505
3595
3660
3725
3790
3855
3920
4010
4075
4140
4205
4270
4335
4425
4490
4555
4620
4685
4750
4840
4905
4970
5035
5100
5165
5335
5400
5465
5530
5595
5660
5750
5815
5880
5945
6010
6075
6165
6230
6295
6360
6425
6490
6660
6725
6790
6855
6920
6985
7075
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Ver.2004-06-29
PAD
No.
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
Pad name
X (µm)
Y (µm)
V4
V4
V4
V4
V4
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
DUMMY
DUMMY
COMA65
COMA64
COMA63
COMA62
COMA61
COMA60
COMA59
COMA58
COMA57
COMA56
COMA55
COMA54
COMA53
COMA52
COMA51
COMA50
COMA49
COMA48
COMA47
COMA46
COMA45
COMA44
COMA43
COMA42
COMA41
COMA40
7140
7205
7270
7335
7400
7490
7555
7620
7685
7750
7815
7880
7945
8010
8075
8140
8205
8270
8335
8400
8465
8530
8620
8652
8652
8652
8652
8652
8652
8652
8652
8652
8652
8652
8652
8652
8652
8652
8652
8652
8652
8652
8652
8652
8652
8652
8652
8652
8652
8652
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-935.5
-794
-756
-718
-680
-642
-604
-566
-528
-490
-452
-414
-376
-338
-300
-262
-224
-186
-148
-110
-72
-34
4
42
80
118
156
194
PAD
No.
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
Pad name
X (µm)
Y (µm)
COMA39
COMA38
COMA37
COMA36
COMA35
COMA34
COMA33
COMA32
COMA31
COMA30
COMA29
COMA28
COMA27
COMA26
DUMMY
DUMMY
COMA25
COMA24
COMA23
COMA22
COMA21
COMA20
COMA19
COMA18
COMA17
COMA16
COMA15
COMA14
COMA13
COMA12
COMA11
COMA10
COMA9
COMA8
COMA7
COMA6
COMA5
COMA4
COMA3
COMA2
COMA1
COMA0
DUMMY
DUMMY
SEGA0
SEGB0
SEGC0
SEGA1
SEGB1
SEGC1
8652
8652
8652
8652
8652
8652
8652
8652
8652
8652
8652
8652
8652
8652
8652
8607
8569
8531
8493
8455
8417
8379
8341
8303
8265
8227
8189
8151
8113
8075
8037
7999
7961
7923
7885
7847
7809
7771
7733
7695
7657
7619
7581
7543
7505
7467
7429
7391
7353
7315
232
270
308
346
384
422
460
498
536
574
612
650
688
726
764
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
-7-
NJU6854
chip size 17,643×2,180 µm2 (chip center = 0:0 )
PAD
No.
Pad name
X(µm)
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
SEGA2
SEGB2
SEGC2
SEGA3
SEGB3
SEGC3
SEGA4
SEGB4
SEGC4
SEGA5
SEGB5
SEGC5
SEGA6
SEGB6
SEGC6
SEGA7
SEGB7
SEGC7
SEGA8
SEGB8
SEGC8
SEGA9
SEGB9
SEGC9
SEGA10
SEGB10
SEGC10
SEGA11
SEGB11
SEGC11
SEGA12
SEGB12
SEGC12
SEGA13
SEGB13
SEGC13
SEGA14
SEGB14
SEGC14
SEGA15
SEGB15
SEGC15
SEGA16
SEGB16
SEGC16
SEGA17
SEGB17
SEGC17
SEGA18
SEGB18
7277
7239
7201
7163
7125
7087
7049
7011
6973
6935
6897
6859
6821
6783
6745
6707
6669
6631
6593
6555
6517
6479
6441
6403
6365
6327
6289
6251
6213
6175
6137
6099
6061
6023
5985
5947
5909
5871
5833
5795
5757
5719
5681
5643
5605
5567
5529
5491
5453
5415
-8-
Y(µm)
PAD
No.
Pad name
X (µm)
Y (µm)
PAD
No.
Pad name
X (µm)
Y (µm)
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
SEGC18
SEGA19
SEGB19
SEGC19
SEGA20
SEGB20
SEGC20
SEGA21
SEGB21
SEGC21
SEGA22
SEGB22
SEGC22
SEGA23
SEGB23
SEGC23
SEGA24
SEGB24
SEGC24
SEGA25
SEGB25
SEGC25
SEGA26
SEGB26
SEGC26
SEGA27
SEGB27
SEGC27
SEGA28
SEGB28
SEGC28
SEGA29
SEGB29
SEGC29
SEGA30
SEGB30
SEGC30
SEGA31
SEGB31
SEGC31
SEGA32
SEGB32
SEGC32
SEGA33
SEGB33
SEGC33
SEGA34
SEGB34
SEGC34
SEGA35
5377
5339
5301
5263
5225
5187
5149
5111
5073
5035
4997
4959
4921
4883
4845
4807
4769
4731
4693
4655
4617
4579
4541
4503
4465
4427
4389
4351
4313
4275
4237
4199
4161
4123
4085
4047
4009
3971
3933
3895
3857
3819
3781
3743
3705
3667
3629
3591
3553
3515
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
SEGB35
SEGC35
SEGA36
SEGB36
SEGC36
SEGA37
SEGB37
SEGC37
SEGA38
SEGB38
SEGC38
SEGA39
SEGB39
SEGC39
SEGA40
SEGB40
SEGC40
SEGA41
SEGB41
SEGC41
SEGA42
SEGB42
SEGC42
SEGA43
SEGB43
SEGC43
SEGA44
SEGB44
SEGC44
SEGA45
SEGB45
SEGC45
SEGA46
SEGB46
SEGC46
SEGA47
SEGB47
SEGC47
SEGA48
SEGB48
SEGC48
SEGA49
SEGB49
SEGC49
SEGA50
SEGB50
SEGC50
SEGA51
SEGB51
SEGC51
3477
3439
3401
3363
3325
3287
3249
3211
3173
3135
3097
3059
3021
2983
2945
2907
2869
2831
2793
2755
2717
2679
2641
2603
2565
2527
2489
2451
2413
2375
2337
2299
2261
2223
2185
2147
2109
2071
2033
1995
1957
1919
1881
1843
1805
1767
1729
1691
1653
1615
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
Ver.2004-06-29
NJU6854
chip size 17,643×2,180 µm2 (chip center = 0:0 )
PAD
No.
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
Pad name
X(µm)
Y(µm)
SEGA52
SEGB52
SEGC52
SEGA53
SEGB53
SEGC53
SEGA54
SEGB54
SEGC54
SEGA55
SEGB55
SEGC55
SEGA56
SEGB56
SEGC56
SEGA57
SEGB57
SEGC57
SEGA58
SEGB58
SEGC58
SEGA59
SEGB59
SEGC59
SEGA60
SEGB60
SEGC60
SEGA61
SEGB61
SEGC61
SEGA62
SEGB62
SEGC62
SEGA63
SEGB63
SEGC63
SEGA64
SEGB64
SEGC64
SEGA65
SEGB65
SEGC65
SEGA66
SEGB66
SEGC66
SEGA67
SEGB67
SEGC67
SEGA68
SEGB68
1577
1539
1501
1463
1425
1387
1349
1311
1273
1235
1197
1159
1121
1083
1045
1007
969
931
893
855
817
779
741
703
665
627
589
551
513
475
437
399
361
323
285
247
209
171
133
95
57
19
-19
-57
-95
-133
-171
-209
-247
-285
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
Ver.2004-06-29
PAD
No.
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
Pad name
X (µm)
Y (µm)
SEGC68
SEGA69
SEGB69
SEGC69
SEGA70
SEGB70
SEGC70
SEGA71
SEGB71
SEGC71
SEGA72
SEGB72
SEGC72
SEGA73
SEGB73
SEGC73
SEGA74
SEGB74
SEGC74
SEGA75
SEGB75
SEGC75
SEGA76
SEGB76
SEGC76
SEGA77
SEGB77
SEGC77
SEGA78
SEGB78
SEGC78
SEGA79
SEGB79
SEGC79
SEGA80
SEGB80
SEGC80
SEGA81
SEGB81
SEGC81
SEGA82
SEGB82
SEGC82
SEGA83
SEGB83
SEGC83
SEGA84
SEGB84
SEGC84
SEGA85
-323
-361
-399
-437
-475
-513
-551
-589
-627
-665
-703
-741
-779
-817
-855
-893
-931
-969
-1007
-1045
-1083
-1121
-1159
-1197
-1235
-1273
-1311
-1349
-1387
-1425
-1463
-1501
-1539
-1577
-1615
-1653
-1691
-1729
-1767
-1805
-1843
-1881
-1919
-1957
-1995
-2033
-2071
-2109
-2147
-2185
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
PAD
No.
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
Pad name
X (µm)
Y (µm)
SEGB85
SEGC85
SEGA86
SEGB86
SEGC86
SEGA87
SEGB87
SEGC87
SEGA88
SEGB88
SEGC88
SEGA89
SEGB89
SEGC89
SEGA90
SEGB90
SEGC90
SEGA91
SEGB91
SEGC91
SEGA92
SEGB92
SEGC92
SEGA93
SEGB93
SEGC93
SEGA94
SEGB94
SEGC94
SEGA95
SEGB95
SEGC95
SEGA96
SEGB96
SEGC96
SEGA97
SEGB97
SEGC97
SEGA98
SEGB98
SEGC98
SEGA99
SEGB99
SEGC99
SEGA100
SEGB100
SEGC100
SEGA101
SEGB101
SEGC101
-2223
-2261
-2299
-2337
-2375
-2413
-2451
-2489
-2527
-2565
-2603
-2641
-2679
-2717
-2755
-2793
-2831
-2869
-2907
-2945
-2983
-3021
-3059
-3097
-3135
-3173
-3211
-3249
-3287
-3325
-3363
-3401
-3439
-3477
-3515
-3553
-3591
-3629
-3667
-3705
-3743
-3781
-3819
-3857
-3895
-3933
-3971
-4009
-4047
-4085
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
-9-
NJU6854
chip size 17,643×2,180 µm2 (chip center = 0:0 )
PAD
No.
Pad name
X(µm)
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
SEGA102
SEGB102
SEGC102
SEGA103
SEGB103
SEGC103
SEGA104
SEGB104
SEGC104
SEGA105
SEGB105
SEGC105
SEGA106
SEGB106
SEGC106
SEGA107
SEGB107
SEGC107
SEGA108
SEGB108
SEGC108
SEGA109
SEGB109
SEGC109
SEGA110
SEGB110
SEGC110
SEGA111
SEGB111
SEGC111
SEGA112
SEGB112
SEGC112
SEGA113
SEGB113
SEGC113
SEGA114
SEGB114
SEGC114
SEGA115
SEGB115
SEGC115
SEGA116
SEGB116
SEGC116
SEGA117
SEGB117
SEGC117
SEGA118
SEGB118
-4123
-4161
-4199
-4237
-4275
-4313
-4351
-4389
-4427
-4465
-4503
-4541
-4579
-4617
-4655
-4693
-4731
-4769
-4807
-4845
-4883
-4921
-4959
-4997
-5035
-5073
-5111
-5149
-5187
-5225
-5263
-5301
-5339
-5377
-5415
-5453
-5491
-5529
-5567
-5605
-5643
-5681
-5719
-5757
-5795
-5833
-5871
-5909
-5947
-5985
- 10 -
Y(µm)
PAD
No.
Pad name
X (µm)
Y (µm)
PAD
No.
Pad name
X (µm)
Y (µm)
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
SEGC118
SEGA119
SEGB119
SEGC119
SEGA120
SEGB120
SEGC120
SEGA121
SEGB121
SEGC121
SEGA122
SEGB122
SEGC122
SEGA123
SEGB123
SEGC123
SEGA124
SEGB124
SEGC124
SEGA125
SEGB125
SEGC125
SEGA126
SEGB126
SEGC126
SEGA127
SEGB127
SEGC127
SEGA128
SEGB128
SEGC128
SEGA129
SEGB129
SEGC129
SEGA130
SEGB130
SEGC130
SEGA131
SEGB131
SEGC131
DUMMY
DUMMY
COMB0
COMB1
COMB2
COMB3
COMB4
COMB5
COMB6
COMB7
-6023
-6061
-6099
-6137
-6175
-6213
-6251
-6289
-6327
-6365
-6403
-6441
-6479
-6517
-6555
-6593
-6631
-6669
-6707
-6745
-6783
-6821
-6859
-6897
-6935
-6973
-7011
-7049
-7087
-7125
-7163
-7201
-7239
-7277
-7315
-7353
-7391
-7429
-7467
-7505
-7543
-7581
-7619
-7657
-7695
-7733
-7771
-7809
-7847
-7885
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
COMB8
COMB9
COMB10
COMB11
COMB12
COMB13
COMB14
COMB15
COMB16
COMB17
COMB18
COMB19
COMB20
COMB21
COMB22
COMB23
COMB24
COMB25
DUMMY
DUMMY
COMB26
COMB27
COMB28
COMB29
COMB30
COMB31
COMB32
COMB33
COMB34
COMB35
COMB36
COMB37
COMB38
COMB39
COMB40
COMB41
COMB42
COMB43
COMB44
COMB45
COMB46
COMB47
COMB48
COMB49
COMB50
COMB51
COMB52
COMB53
COMB54
COMB55
-7923
-7961
-7999
-8037
-8075
-8113
-8151
-8189
-8227
-8265
-8303
-8341
-8379
-8417
-8455
-8493
-8531
-8569
-8607
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
920.5
764
726
688
650
612
574
536
498
460
422
384
346
308
270
232
194
156
118
80
42
4
-34
-72
-110
-148
-186
-224
-262
-300
-338
-376
Ver.2004-06-29
NJU6854
chip size 17,643×2,180 µm2 (chip center = 0:0 )
PAD
No.
Pad name
X(µm)
Y(µm)
751
752
753
754
755
756
757
758
759
760
761
COMB56
COMB57
COMB58
COMB59
COMB60
COMB61
COMB62
COMB63
COMB64
COMB65
DUMMY
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-8652
-414
-452
-490
-528
-566
-604
-642
-680
-718
-756
-794
Ver.2004-06-29
PAD
No.
Pad name
X (µm)
Y (µm)
PAD
No.
Pad name
X (µm)
Y (µm)
- 11 -
NJU6854
COMA0
COMA65
COMB0
COMB65
Driver Control
X address decoder
VREG
VREF
VBA
Voltage
Regulator
Generator
RAM
Interface
LP
FLM
M
Display
Timing
Generator
Data manager
OSCI
OSCO
Oscillator
Circuit
Display
Control
X address counter
Duty
Manager
X address register
Instruction
Decoder
MPU Interface
Register
Control
Register
Bus Holder
Bus I/O Buffer
SEL68
CSb
RS
WRb
PS
RESb
RDb
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4/SPOL
D3/SMODE
D2
D1/SDA
D0/SCL
LDAT
LSCK
LREQ
LRESb
TEST
VDD
VDDA
VSSA
VSS
Display Data RAM
132RGB x 132
278.784bit
132
Decoder
Line Address Register
Data Latch Circuit
Common Driver
Line Counter
Grayscale Control Circuit
Grayscale
Palettes
Y Address Decoder
Voltage
Booster
Segment Driver
396
Y Address Counter
VOUT
C1+
C1C2+
C2C3+
C3C4+
C4C5+
C5-
LCD
Bias
Voltage
Generator
Y Address Register
V0
V1
V2
V3
V4
Driver Power
Line Address Decoder
VEE
VSS
VSSHA
SEGA131
SEGB131
SEGC131
SEGA0
SEGB0
SEGC0
! BLOCK DIAGRAM
- 12 -
Ver.2004-06-29
NJU6854
! LCD POWER SUPPLY BLOCK DIAGRAM
Temp Coefficient
Setting Register
VEE
+
VBA
BG
temperature
bias circuit
-
+
VREG
VREF
LCD Bias
setting
register
+
-
+
-
+
This point is
1/2 VREG
+
-
+
VOUT
VREG
gain
setting
register
C1+
C1C2+
C2C3+
C3C4+
C4C5+
C5-
V0
Electric
volume
Register
DC/DC
booster
Voltage
converter
step setting
register
+
-
V1
V2
V3
V4
VEE
Note) When external VREF is used, keep Reference Voltage Circuit open (VGOFF=”0”, VBON=”0”).
Ver.2004-06-29
- 13 -
NJU6854
! TERMINAL DESCRIPTION
Power Supply
No.
64-69
Terminal
VDD
I/O
Power
26,32,42
VDDA
Power
33,43
VSSA
Power
57-63
VSS
Power
GND for logic circuits
95-104
206-222
VSSHA
VSSH
Power
Power
176-205
V0
V1
V2
V3
V4
Power/O
GND for voltage converter circuits
GND for voltage booster
LCD Bias Voltages
• When the internal LCD power supply is used, internal LCD bias voltages (V0-V4)
are activated by the “Power Control” instruction. Stabilizing capacitors are required
between each bias voltage and VSS.
• When the external LCD power supply is used, LCD bias voltages are externally
supplied on V0, V1, V2, V3 and V4 individually, with the following relation
maintained: VSSH<V4<V3<V2<V1<V0
116-127
128-139
140-151
152-163
164-175
C1+
C1C2+
C2C3+
C3C4+
C4C5+
C5-
Power
Capacitor Connection for Voltage Booster
Power
Capacitor Connection for Voltage Booster
Power
Capacitor Connection for Voltage Booster
Power
Capacitor Connection for Voltage Booster
Power
Capacitor Connection for Voltage Booster
85-89
VBA
Power
70-84
VEE
Power
90-94
VREF
Power
105-109
VREG
Power
110-115
VOUT
Power
- 14 -
Description
Power Supply for Logic Circuits
VDDA is internally connected to VDD to fix SEL68 or P/S to “H” if necessary, and
cannot be used as main power supply.
• VDDA should be open if not used
VSSA is internally connected to VSS to fix SEL68 or P/S to “L” if necessary, and
cannot be used as main GND.
• VSSA should be open if not used.
Reference-Voltage Generator Output
(typically 1.9V at 25℃, with temperature compensation function)
Voltage Booster Input
• VEE is normally connected to VDD.
Voltage Regulator Input
Voltage Regulator Output
• Connect this pin to VSS with a stabilizing capacitor
Voltage Booster Output
• Connect this pin to VSS with a stabilizing capacitor
Ver.2004-06-29
NJU6854
MPU Interface
No.
Terminal
27
34-41
RESb
D0/SCL
D1/SDA
D2
D3/SMODE
D4/SPOL
D5~D7
44-51
28
29
I/O
I
Parallel Interface
D7 to D0: 8-bit Bi-directional Bus(P/S=“H”)
I/O
D8~D15
I/O
CSb
I
RS
Description
Reset
• Active “L”
I
31
RDb(E)
I
30
WRb
(R/W)
I
Serial Interface
SDA: Serial Data
SCL: Shift Clock
SMODE: 3-/4-line Serial Mode Select
SPOL: RS Polarity Select (3-line Serial Interface Mode)
8-bit Bi-directional Bus
• In the 16-bit bus length mode, D15-D8 are assigned to upper 8-bit data bus.
• In the serial interface mode or the 8-bit parallel interface mode, D15-D8 should be
fixed to “H” or “L”.
Chip Select
• Active “L”
Register Select
• This signal interprets transferred data as display data or instruction.
RS
Data
H
Instruction
L
Display Data
80-series MPU Interface (P/S=“H”, SEL68=“L”)
Data Read (RDb) Signal
• Active “L”
68-series MPU Interface (P/S=“H”, SEL68=“H”)
Enable Signal
• Active “H”
80-series MPU Interface (P/S=“H”, SEL68=“L”)
Data Write (WRb) Signal
• Active “L”
68-series MPU Interface (P/S=“H”, SEL68=“H”)
Data Read or Write (R/W) Signal
R/W
Status
H
Read
L
Write
MPU Mode Select
24
SEL68
I
SEL86
MPU
H
68-series
L
80-series
Parallel/Serial Interface Mode Select
Display /
Read
Data
Serial Clock
Instruction
/Write
H
CSb
RS
D0 ~ D7
RDb, WRb
L
CSb
RS
SDA (D1)
Write Only
SCL (D0)
In the serial interface mode (P/S=“L”), RDb, WRb, D2 and D5-D15 should be fixed to
“H” or “L”,.
P/S
25
PS
I
23
TEST
I
Ver.2004-06-29
Chip Select
Maker test terminal
This terminal must be fixed to “H” in the user’s application.
- 15 -
NJU6854
LCD Output
No.
Terminal
I/O
Description
Segment Drivers Output
REV Mode
Turn-off
0
1
Normal
Reverse
295-690
SEGA0~
SEGA131,
SEGB0~
SEGB131,
SEGC0~
SEGC131
O
M signal
Display RAM Data
Nomal mode
Reverse mode
54
FLM
53
52
M
LP
225-292
COMA0~
COMA65
COMB0~
COMB65
Turn-on
1
0
O
O
O
V2
V0
V0
V2
V3
VSS
VSS
V3
Normally open.
Normally open.
Normally open.
Common Divers Output
Data
H
L
H
L
FR
H
H
L
L
Output level
VSSH
V1
V0
V4
Oscillator
56
OSCI
I
55
OSCO
O
When using the internal resistor, connect OSCI to “L” and keep OSCO open
When using an external resistor, connect OSCI and OSCO with the external
resistor, and if using external clock, input 50% duty signal into the OSCI.
White LED Driver Ports
19
20
21
22
- 16 -
LDAT
LSCK
LREQ
LRESb
I/O
O
O
O
White LED control port: data input/output
White LED control port: shift clock output
White LED control port: data request output
White LED control port: reset output
Ver.2004-06-29
NJU6854
! FUNCTIONAL DESCRIPTION
(1) MPU INTERFACE
(1-1) Selection of Parallel/Serial Interface Mode
The P/S selects a parallel or a serial interface mode, as shown in Table 1. In the serial interface mode, neither
display data in the DDRAM nor instruction data in the registers can be read out.
Table 1 Selection of Parallel/Serial Interface Mode
P/S
I/F Mode
CSb
RS
RDb WRb
H
Parallel I/F
CSb
RS
RDb WRb
L
Serial I/F
CSb
RS
NOTE) “ -” : Fix to “H” or “L”.
SEL68
SEL68
-
SDA
SCL
SDA
SCL
Data
D7-D0 (D15-D0)
-
(1-2) Selection of MPU Mode
In the parallel interface mode, the SEL68 selects 68 or 80-series MPU mode, as shown in Table 2.
Table 2 Selection of MPU Mode
SEL68
MPU Mode
H
68-series MPU
L
80-series MPU
CSb
CSb
CSb
RS
RS
RS
RDb
E
RDb
WRb
R/W
WRb
Data
D7-D0 (D15-D0)
D7-D0 (D15-D0)
(1-3) Data Recognition
In the parallel interface mode, the data from MPU is interpreted as display data or instruction according to the
combination of the RS, RDb and WRb (R/W) signals, as shown in Table 3.
Table 3
RS
H
H
L
L
Data Recognition (Parallel Interface Mode)
68-series
80-series
R/W
RDb
WRb
H
L
H
L
H
L
H
L
H
L
H
L
Function
Read Instruction
Write Instruction
Read Display Data
Write Display Data
(1-4) Selection of 3-/4-line Serial Interface Mode
In the serial interface mode, the SMODE selects 3- or 4-line serial interface mode, as shown in Table 4.
Table 4 Selection of 3-/4-line Serial Interface Mode
SMODE
Serial Interface Mode
H
3-line
L
4-line
(1-5) 4-line Serial Interface Mode
While the chip select is active (CSb=“L”), the SDA and SCL are enabled. While the chip select is inactive
(CSb=“H”), the SDA and SCL are disabled, and the internal shift register and the internal counter are being initialized.
8-bit serial data on the SDA is latched at the rising edge of the SCL signal in order of D7, D6,…, and D0, and converted
into 8-bit parallel data at the timing of the internal signal produced from the 8th SCL signal. The data on the SDA is
interpreted as display data or instruction according to the RS.
Table 5 Data Recognition (4-line Serial Interface)
RS
Data Recognition
H
Instruction
L
Display Data
Ver.2004-06-29
- 17 -
NJU6854
Note that the SCL should be set to “L” right after data transmission or during non-access because the serial interface
is susceptible to external noises which may cause malfunctions. For added safety, inactivate the chip-select (CSb=“H”)
temporary whenever 8-bit data transmission is completed. Fig 1 illustrates the interface timing of the 4-line serial
interface mode.
CSb
RS
VALID
SDA
D7
D6
D5
D4
D3
D2
D1
D0
SCL
1
2
3
Fig 1
4
5
6
7
8
4-line Serial Interface Timing
(1-6) 3-line Serial Interface Mode
While the chip select is active (CSb=“L”), the SDA and SCL are enabled. While the chip select is not active
(CSb=“H”), the SDA and SCL are disabled, and the internal shift register and the internal counter are being initialized.
9-bit serial data on the SDA is latched at the rising edge of the SCL signal in order of RS, D7, D6,…, and D0, and then
converted into 9-bit parallel data at the timing of the internal signal produced from the 9th SCL signal. The data on the
SDA is interpreted as display data or instruction according to the combination of the RS bit and the SPOL status, as
follows.
Table 6
RS
0
1
Data Recognition (3-line Serial Interface)
SPOL=L
SPOL=H
Data Recognition
RS
Data Recognition
Display Data
0
Instruction
Instruction
1
Display Data
Note that the SCL should be set to “L” right after data transmission or during non-access because the serial interface
is susceptible to external noises which may cause malfunctions. For added safety, inactivate the chip-select (CSb=“H”)
temporary whenever 9-bit data transmission is completed. Fig 2 illustrates the interface timing of the 3-line serial
interface mode.
CSb
SDA
RS
D7
D6
D5
D4
D3
D2
D1
D0
SCL
1
2
3
Fig 2
- 18 -
4
5
6
7
8
9
3-line Serial Interface Timing
Ver.2004-06-29
NJU6854
(1-7) Data Write
While the chip select is active (CSb=“L”), the data from MPU can be written into the DDRAM or the instruction
register. When the RS is “L”, the data is interpreted as display data which is stored in the DDRAM. The display data is
latched at the rising edge of the WRb signal in the 80-series MPU mode, or at the falling edge of the E signal in the
68-series MPU mode.
Table 7
RS
L
H
Data Recognition
Data Recognition
Display Data
Instruction
8-bit access to DDRAM
DATA0
D0~D7
DATA1
DATA2
DATA3
WRb
RS
Accessing to Instruction Register
Accessing to DDRAM
8-bit access to Instruction Register
D0~D7
MSB=0/Table Address
MSB=1/Table Address
/Register Address
/Counter Number
Data
Datat0
1st Access
Data
Datat0
Datatn-1
1st Access
WRb
RS
Fig 3
Ver.2004-06-29
Data Write Operations in 8-bit
- 19 -
NJU6854
16-bit access to DDRAM
DATA0
D8~D15
DATA1
DATA0
D0~D7
DATA1
DATA2
DATA3
DATA2
DATA3
WRb
RS
Accessing to Instruction Register
Accessing to DDRAM
16-bit access to Instruction Register
MSB=0/Table
MSB=0/Table
Address/Register Address/Register
Address
Address
D8~D15
op code
op code
MSB=1/Table
Address/Counter
Number(n)
op code
DATA0
DATAn-2
invalid
D0~D7
DATA0
DATA0
DATA1
DATAn-2
WRb
RS
Fig 4
- 20 -
Data Write Operations in 16-bit
Ver.2004-06-29
NJU6854
(1-8) Data Read
Just after address setting or data write operation, make sure to conduct dummy read operation once. The reason lies
below, data from CPU is temporarily held in the built-in bus holder, and then released to the internal data bus, therefore a
dummy data will be read out by the 1st “Display Data Read” instruction, the wanted data will be read out by the 2nd
instruction.
Display Data Read in 8-bit
WRb
D 0~ D 7
dummy read
op code
address set(AX,AY)
address= n
address= n
address= n+1
RDB
RDb
RS
Display Data Read in 16-bit
WRb
dummy read
D 8~ D 15
op code
n
n+1
n+2
n+1
n+2
dummy read
D 0~ D 7
n
data read
address = n
address set(AX,AY)
address=n
data read
data read
address = n+1 address = n+2
RDb
RS
Instruction Data Read in 8-bit
WRb
1D H
D0~D7
Set “ RA ”
instruction
address
Table address
/register address
data
Data read
RDb
RS
Instruction Data Read in 16-bit
WRb
Data read
D 8 ~ D 15
data
1D H
Set “ RA ”
D 0~ D 7
/
instruction
address
Table address
register address
1 DH
invalid
data
invalid
address
RDb
RS
Fig 5 Data Read Operations
Ver.2004-06-29
- 21 -
NJU6854
(1-9) Selection of 8-/16-bit Bus Length (Parallel Interface Mode)
Either 8- or 16-bit bus length can be selected by the D0 (SWIF) bit of the CFG register.
SWIF = “0” : 8-bit bus
D0
D1
D2
D3
D4
D5
D6
D7
D4
D5
D6
D7
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
SWIF = “1” : 16-bit bus
D0
D1
D2
D3
D8
D9
D10
D11
D12
D13
D14
D15
Bit assignment is determined by the D1 (UDS) bit of the CFG register.
16-bit access
UDS = “0”
Internal BUS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9 D10 D11 D12 D13 D14 D15
IO PAD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9 D10 D11 D12 D13 D14 D15
Internal BUS
D8
D9 D10 D11 D12 D13 D14 D15 D0
D1
IO PAD
D0
D1
D2
D3
D9 D10 D11 D12 D13 D14 D15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D0
D1
D2
D3
D4
D0
D5
D1
D6
D2
D7
D3
D0
D4
D1
D5
D2
D6
D3
D7
D4
D0
D1
D2
D3
D4
D5
D6
D7
UDS = “1”
D4
D5
D6
D7
D8
D2
D3
D4
D5
D6
D7
8-bit access
UDS = “0”
Internal
BUS
IO PAD
nd
IO PAD
2
access
D13
D14
D15
D5
st
1
access
D6
D7
UDS = “1”
Internal BUS
D0
D0
IO PAD
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
D8
D0
1
access
D0
D1
D2
D3
D4
D9 D10 D11 D12 D13 D14 D15
D1 D2 D3 D4 D5 D6 D7
D7
D5 D6
D0
D1
D2
D3
D4
D5
st
nd
IO PAD
D6
D7
2
access
During 8-bit access, D15~D8 pins become high impedance, make sure fix them to H” or ”L”.
(2) INITIAL DISPLAY LINE
The Initial Display Line register(HST) specifies a DDRAM Y address, and display data corresponding to this
address will be displayed by the Scan Start COM 1.
The Y address specified by the Initial Display Line register is preset into the line counter whenever the FLM
becomes “H”. At the rising edge of the LP signal, the line counter is counted-up, then display data is latched into the data
latch circuit. At the falling edge of the LP signal, the latch data is released to the grayscale control circuit to decide a
grayscale level, then the segment drivers Ai, Bi and Ci (i=0 to 131) generate LCD waveforms.
- 22 -
Ver.2004-06-29
NJU6854
(3) DDRAM
(3-1) DDRAM Address Range
The DDRAM is capable of 132 bits for Y address and 2,112 bits (16-bit x 132-segment) for X address. The x and
Y address are from 00H to 83 H. Address setting outside these ranges is not allowed, otherwise it may cause malfunctions.
When auto-increment(auto-decrement) function is used during DDRAM access, Y address and/or X address will be
automatically increased(decreased). This operation is independent from line counter count-up (count-down).
X-address
83H
0H
16bit
16bit
0H
Y-address
16bit
83H
16bit
(3-2) Window Area for DDRAM Access
Besides the normal DDRAM access discussed previously, it is possible to access only a specified window area by
using CFG, ADRH, ADRL, EADRH and EADRL registers to define a start point and an end point.
When auto-increment(auto-decrement) function enabled, Y address and/or X address will be automatically
increased(decreased) whenever DDRAM is accessed. And, the start point is specified by the X address Register (ADRH)
and Y address Register(ADRL), the end point by the Window End X address Register(EADRH) and Window End Y
address Register(EADRL). For the details, refer to the Instruction Table. The typical sequence of the window area setting
is listed below.
1. Set D7 (AIM1), D6 (AIM0), D5 (VWR), D4 (IDSY), D3 (IDSX), and D2 (WIN) bit of CFG register.
2. Set start point by ADRH and ADRL register.
3. Set end point by EADRH and EADRL register.
4. Window area is set up, and DDRAM can be accessed.
X Address
Y Address
Start Point
(X, Y)
End Point
(X, Y)
DDRAM Area
Window Area
NOTE1)
The following relationship should be maintained to avoid malfunctions.
- AX (Window Start X address) < EX (Window End X address) < Maximum X address
- AY (Window Start Y address) < EY (Window End Y address) < Maximum Y address
NOTE2)
Auto-increment in the window area
Start
Address
End
Address
Start
Address
Column Address
NOTE3)
End
Address
Row Address
When AIM[1:0]=(0,1), read-modify-write operation is valid.
Ver.2004-06-29
- 23 -
NJU6854
(3-3) DDRAM Access Direction
00 X 00 X
0
(H) (H) (H) (H)
83 X 00 X
0
(H) (H) (H) (H)
00 X 83 X
0
(H) (H) (H) (H)
83 X 83 X
0
(H) (H) (H) (H)
00
00
00
00
0
1
0
1
0
0
1
1
DDDRAM Access Direction
VWR
IDSY
IDSX
AIM
WIN
EADRL
ADRL
EADRH
ADRH
Registers setting
Remark
00,00 01,00
83,00
00,83
83,83
00,00
82,00 83,00
00,83
83,83
00,00
83,00
00,83 01,83
83,83
00,00
83,00
00,83
82,83 83,83
0
0
0
0
Window Area
06 7D 10 6A 1
(H) (H) (H) (H)
00
0
0
06,10 07,10
7D,10
06,6A
7D,6A
06,10
7C,10 7D,10
06,6A
7D,6A
06,10
7D,10
06,6A 07,6A
7D,6A
06,10
7D,10
06,6A
7C,6A 7D,6A
0
Window Area
7D 06 10 6A 1
(H) (H) (H) (H)
00
1
0
0
Window Area
06 7D 6A 10
1
(H) (H) (H) (H)
00
0
1
0
Window Area
7D 06 6A 10
1
(H) (H) (H) (H)
- 24 -
00
1
1
0
Ver.2004-06-29
NJU6854
00 X 00 X
0
(H) (H) (H) (H)
83 X 00 X
0
(H) (H) (H) (H)
00 X 83 X
0
(H) (H) (H) (H)
83 X 83 X
0
(H) (H) (H) (H)
00
00
00
00
0
1
0
1
0
0
1
1
DDDRAM Access Direction
VWR
IDSY
IDSX
AIM
WIN
EADRL
ADRL
EADRH
ADRH
Registers setting
Remark
00,00
00,01
83,00
00,83
83,83
00,00
83,00
83,01
00,83
83,83
00,00
83,00
00,82
00,83
83,83
00,00
83,00
00,83
83,82
83,83
1
1
1
1
Window Area
06 7D 10 6A 1
(H) (H) (H) (H)
00
0
0
1
06,10
06,11
7D,10
06,6A
7D,6A
06,10
7D,10
7D,11
06,6A
7D,6A
06,10
7D,10
06.69
06,6A
7D,6A
06,10
7D,10
06,6A
7D,69
7D,6A
Window Area
7D 06 10 6A 1
(H) (H) (H) (H)
00
1
0
1
Window Area
06 7D 6A 10
1
(H) (H) (H) (H)
00
0
1
1
Window Area
7D 06 6A 10
1
(H) (H) (H) (H)
Ver.2004-06-29
00
1
1
1
- 25 -
NJU6854
(3-4) Segment Shift Direction
The DDRAM access direction can be selected through setting the D7(REF) bit of the Display Control register
(DISPLAY), This function enables to reverse segment shift direction to reduce the restriction on the IC location on an
LCD module.
(3-5) Block Diagram of DDRAM and Peripheral Circuit
SEGMENT OUTPUT I/F
Grayscale Control Circuit
Read
data
REF,SWAP
Segment data
Line Counter
Y Address (00H~83H)
Y address
Y Counter
Y Register
Data
write
Data Latch
Display Data RAM
HST Register
Internal Data Bus
X-Address (00H-83H)
X Address Counter
REF
X Register
MPU I/F
- 26 -
Ver.2004-06-29
NJU6854
(3-6) DDRAM Mapping
(3-6-1) (REW, SWAP) = (0,0), SHIFT1 = “0”, SHIFT0 = “0”, VPC = "84H“ (1/132 Duty), FVC = "00H", HCT =
“00H”, SSC1 and SSC2 = “0”, EN3PTL = “0”
HST=00H
HST=05H
RAM Address
Y address
COMB63
COMB64
COMB65
X=83H
---------------------------------------
---------------------------------------
--------------------------------------3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
---------------------------------------
----------
81H
82H
83H
Segment Output
Ver.2004-06-29
----------
---------------------------------------
---------------------------------------
COMA63
COMA64
COMA65
COMB0
COMB1
COMB2
COMB3
X address
----------
00H
01H
02H
03H
04H
05H
06H
07H
---------------------------------------
---------------------------------------
COMA0
COMA1
COMA2
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
X=00H
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
COM output
SEGA0
SEGB0
SEGC0
----------
SEGA131
SEGB131
SEGC131
- 27 -
NJU6854
(3-6-2) (REW, SWAP) = (0,0), SHIFT1 = “0”, SHIFT0 = “0”, VPC = "70H“ (1/112 Duty), FVC = "00H", HCT =
“0AH”, SSC1 and SSC2 = “0”, EN3PTL = “0”
HST=00H
HST=05H
RAM Address
--------------------------------------COMB63
COMB64
COMB65
X=83H
-------------------------
-------------------------
-------------------------
----------
---------------------------------------
----------
6DH
6EH
6FH
70H
71H
72H
73H
74H
75H
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
80H
81H
82H
83H
Segment Output
- 28 -
X address
----------
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
---------------------------------------
Unused COM driver
COMA63
COMA64
COMA65
COMB0
COMB1
COMB2
COMB3
COMB4
COMB5
COMB6
COMB7
COMB8
COMB9
COMB10
COMB11
COMB12
00H
01H
02H
03H
04H
05H
06H
07H
---------------------------------------
COMA0
COMA1
COMA2
COMA3
COMA4
COMA5
COMA6
COMA7
COMA8
COMA9
COMA10
COMA11
COMA12
---------------------------------------
Unused COM driver
Y address
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
X=00H
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
COM output
SEGA0
SEGB0
SEGC0
----------
SEGA131
SEGB131
SEGC131
Ver.2004-06-29
NJU6854
(3-7) The Relationship among Bit Assignment, X address and Segment Driver
Three sub pixels(R, G, B) individually driven by 3 segment drivers (SEGAi, SEGBi, SEGCi) consist one pixel of
the color STN panel. In the 65k display mode, 5-bit display data for SEGAi and SEGCi can output 32-level grayscale
respectively, and 6-bit display data for SEGBi can output 64-level grayscale, so the total quantity of possible colors is
65,536(32x32x64). In 4k-color mode, 4-bit display data for every SEGAi, SEGBi and SEGCi, so the total quantity of
possible colors is 4,096(16x16x16).
Weighting value of display data is dependent on the status of the SWAP bit and the REF bit of DISPLAY register.
16-bit Bus Access (65k-color Mode)
(REF,SWAP)=(0,0) or (1,1)
MODED = 0 (65,536 color display)
SEGCi
SEGBi
SEGAi
Palette Cj
Palette Bj
Palette Aj
PWM control
PWM control
+ 2 FRC
i = 0 to 131
Grayscale Palette
j = 0 to 31
Grayscale control
PWMM[1:0]=00 for 64 level
PWMM[1:0]=01 for 32 level
PWMM[1:0]=11 for 128 level
PWM control
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MSB
Display data
LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X Address : nH
Note Internal Access X Address : nH (REF = 0)
:83H - nH (REF = 1)
MPU Write Data
MODE[1:0] = 00
(REF,SWAP)=(0,1) or (1,0)
MODED = 0 (65,536 color display)
SEGCi
SEGBi
SEGAi
Palette Aj
Palette Bj
Palette Cj
PWM control
PWM control
+ 2 FRC
PWM control
D4 D3 D2 D1 D0 D10 D9 D8 D7 D6 D5 D15 D14 D13 D12 D11
i = 0 to 131
Grayscale Palette
j = 0 to 31
Grayscale control
PWMM[1:0]=00 for 64 level
PWMM[1:0]=01 for 32 level
PWMM[1:0]=11 for 128 level
Display data
MSB
LSB
MPU Write Data
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X Address : nH
Note Internal Access X Address : nH (REF= 0)
:83H - nH (REF= 1)
Ver.2004-06-29
MODE[1:0] = 00
- 29 -
NJU6854
16-bit Bus Access (4k-color Mode 1)
(REF,SWAP)=(0,0) or (1,1)
MODED = 1 (4,096 color display)
SEGCi
Palette Cj
SEGBi
Palette Bj
SEGAi
i = 0 to 131
Grayscale Palette
j = 1, 3, 5 ... 29, 31
Palette Aj
PWM
control
PWM
control
PWM
control
D15 D14 D13 D12
D10 D9 D8 D7
D4 D3 D2 D1
MSB
D15 D14 D13 D12
D10 D9 D8 D7
D4 D3 D2 D1
Grayscale control
PWMM[1:0]=00 for 64 level
PWMM[1:0]=01 for 32 level
PWMM[1:0]=10 for 16 level
PWMM[1:0]=11 for 128 level
Display data
LSB
MPU Write Data
X Address : nH
Note Internal Access X Address : nH (REF = 0)
:83H - nH (REF = 1)
MODE[1:0] = 01
(REF,SWAP)=(0,1) or (1,0)
MODED = 1 (4,096 color display)
SEGCi
SEGBi
SEGAi
Palette Aj
Palette Bj
Palette Cj
PWM
control
PWM
control
PWM
control
D4 D3 D2 D1
D10 D9 D8 D7
D15 D14 D13 D12
MSB
D15 D14 D13 D12
D10 D9 D8 D7
D4 D3 D2 D1
Grayscale Palette
j = 1, 3, 5 ... 29, 31
Grayscale control
PWMM[1:0]=00 for 64 level
PWMM[1:0]=01 for 32 level
PWMM[1:0]=10 for 16 level
PWMM[1:0]=11 for 128 level
Display data
LSB
X Address : nH
Note Internal Access X Address : nH (REF = 0)
:83H - nH (REF = 1)
- 30 -
i = 0 to 131
MPU Write Data
MODE[1:0] = 01
Ver.2004-06-29
NJU6854
16-bit Bus Access (4k-color Mode 2)
(REF,SWAP)=(0,0) or (1,1)
MODED = 1 (4,096 color display)
SEGCi
SEGBi
SEGAi
Palette Cj
Palette Bj
Palette Aj
PWM
control
PWM
control
PWM
control
D11 D10 D9 D8
D7 D6 D5 D4
D3 D2 D1 D0
MSB
i = 0 to 131
Grayscale Palette
j = 1, 3, 5 ... 29, 31
Grayscale control
PWMM[1:0]=00 for 64 level
PWMM[1:0]=01 for 32 level
PWMM[1:0]=10 for 16 level
PWMM[1:0]=11 for 128 level
Display data
LSB
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X Address : nH
Note Internal Access X Address : nH (REF = 0)
:83H - nH (REF = 1)
MPU Write Data
MODE[1:0] = 10
(upper 4 bit invalid)
(REF,SWAP)=(0,1) or (1,0)
MODED = 1 (4,096 color display)
SEGCi
SEGBi
SEGAi
Palette Aj
Palette Bj
Palette Cj
PWM
control
PWM
control
PWM
control
D3 D2 D1 D0
D7 D6 D5 D4
D11 D10 D9 D8
MSB
Grayscale Palette
j = 1, 3, 5 ... 29, 31
Grayscale control
PWMM[1:0]=00 for 64 level
PWMM[1:0]=01 for 32 level
PWMM[1:0]=10 for 16 level
PWMM[1:0]=11 for 128 level
Display data
LSB
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X Address : nH
Note Internal Access X Address : nH (REF = 0)
:83H - nH (REF = 1)
Ver.2004-06-29
i = 0 to 131
MPU Write Data
MODE[1:0] = 10
upper 4 bit invalid
- 31 -
NJU6854
Relationship among Display Data, X address and Segment Drivers(16-bit Access Mode)
65k-color mode, MODE[1:0]=0H
IDSX
Palette A
Palette B
Palette C
SEGA0
SEGB0
SEGC0
IDSX
SEGC131
Palette C
Palette B
Palette A
SEGA0
SEGB0
SEGC0
Palette C
Palette B
Palette A
SEGA131
SEGB131
SEGC131
IDSX
Palette A
Palette B
Palette C
SEGA0
SEGB0
SEGC0
IDSX
- 32 -
D7 D15
D6 D14
D5 D13
D4 D12
D2 D10
D1 D9
D0 D8
D15 D7
D12 D4
D11 D3
D10 D2
D9 D1
:
:
:
SEGA131
SEGB131
SEGC131
Palette C
Palette B
Palette A
SEGA0
SEGB0
SEGC0
D12 D4
D11 D3
D10 D2
D9 D1
D2 D10
D1 D9
D0 D8
D15 D7
D7 D15
D6 D14
D5 D13
D4 D12
:
:
X = 00H
:
X = 83H
:
D7 D15
D6 D14
D5 D13
1
D4 D12
UDS
0
Palette C
:
X = 83H
Palette B
Palette C
Palette B
Palette A
:
83H←00H 83H→00H
D12 D4
0
D11 D3
1
D10 D2
X = 00H
D9 D1
00H→83H 00H←83H
D2 D10
1
Palette A
X Address / Display Data / Grayscale Palette / Segment Driver
1
D1 D9
0
0
D0 D8
SWAP
D15 D7
REF
:
D11 D3
D12 D4
1
D10 D2
D9 D1
0
X = 00H
:
X = 83H
X = 83H
:
83H←00H 83H→00H
D7 D15
1
D6 D14
1
D5 D13
X = 00H
D4 D12
00H→83H 00H←83H
D2 D10
0
D1 D9
0
UDS
X Address / Display Data / Grayscale Palette / Segment Driver
1
D0 D8
SWAP
D15 D7
REF
SEGA131
SEGB131
SEGC131
Ver.2004-06-29
D12 D4
D11 D3
D10 D2
D9 D1
D8 D0
D2 D10
D1 D9
D0 D8
D15 D7
D14 D6
D7 D15
D13 D5
D6 D14
D5 D13
D4 D12
:
X = 00H
D3 D11
:
X = 83H
4k-color mode 1, MODE[1:0]=1H
0
D7 D15
D6 D14
D5 D13
D4 D12
D3 D11
D2 D10
D1 D9
D0 D8
D15 D7
D14 D6
D13 D5
D11 D3
D12 D4
D9 D1
D10 D2
:
:
:
SEGB131
:
D0 D8
D15 D7
D14 D6
D13 D5
D7 D15
D6 D14
D5 D13
1
D4 D12
D3 D11
0
UDS
SEGA131
:
X = 83H
Palette C
:
83H←00H 83H→00H
Palette B
:
0
D12 D4
1
D11 D3
X = 00H
D10 D2
00H→83H 00H←83H
D9 D1
1
Palette A
X Address / Display Data / Grayscale Palette / Segment Driver
1
D8 D0
0
0
D2 D10
SWAP
D1 D9
REF
:
D15 D7
D14 D6
D13 D5
D11 D3
D12 D4
D9 D1
1
D10 D2
D8 D0
UDS
0
X = 00H
D8 D0
X = 83H
D7 D15
83H←00H 83H→00H
:
1
X = 83H
:
1
D6 D14
X = 00H
D5 D13
00H→83H 00H←83H
D4 D12
0
D3 D11
X Address / Display Data / Grayscale Palette / Segment Driver
1
D2 D10
0
0
D1 D9
SWAP
D0 D8
REF
NJU6854
4k-color mode, MODE[1:0]=2H
IDSX
Palette A
Palette B
Palette C
SEGA0
SEGB0
SEGC0
IDSX
Ver.2004-06-29
D3 D11
D2 D10
D1 D9
D0 D8
D15 D7
D14 D6
D13 D5
D11 D3
D12 D4
D9 D1
D10 D2
:
:
:
:
Palette C
SEGA131
SEGB131
SEGC131
Palette C
Palette B
Palette A
SEGA0
SEGB0
SEGC0
D11 D3
D10 D2
D9 D1
D8 D0
D15 D7
D14 D6
D13 D5
D3 D11
D12 D4
D2 D10
D1 D9
:
D0 D8
:
:
X = 00H
:
X = 83H
:
D3 D11
D2 D10
D1 D9
1
D0 D8
0
Palette B
Palette C
Palette B
Palette A
:
X = 83H
D11 D3
83H←00H 83H→00H
D10 D2
0
D9 D1
1
D8 D0
X = 00H
D15 D7
00H→83H 00H←83H
D14 D6
1
Palette A
X Address / Display Data / Grayscale Palette / Segment Driver
1
D13 D5
0
0
D12 D4
SWAP
UDS
REF
X = 00H
D8 D0
D11 D3
D9 D1
1
D10 D2
D8 D0
0
D3 D11
X = 83H
:
83H←00H 83H→00H
X = 83H
:
1
D2 D10
1
D1 D9
X = 00H
D0 D8
00H→83H 00H←83H
D15 D7
0
UDS
X Address / Display Data / Grayscale Palette / Segment Driver
1
D14 D6
0
0
D13 D5
SWAP
D12 D4
REF
SEGA131
SEGB131
SEGC131
- 33 -
NJU6854
Relationship among Display Data, X address and Segment Drivers(8-bit Access Mode)
st
1 write in data
nd
2 write in data
D01
D02
D11
D12
D21
D22
D31
D32
D41
D42
D51
D52
D61
D62
D71
D72
65k-color mode, MODE[1:0]=0H
IDSX
Palette A
Palette B
Palette C
SEGA0
SEGB0
SEGC0
IDSX
SEGC131
Palette C
Palette B
Palette A
SEGA0
SEGB0
SEGC0
Palette C
Palette B
Palette A
SEGA131
SEGB131
SEGC131
IDSX
Palette A
Palette B
Palette C
SEGA0
SEGB0
SEGC0
IDSX
- 34 -
D71 D72
D61 D62
D51 D52
D41 D42
D21 D22
D11 D12
D01 D02
D72 D71
D42 D41
D32 D31
D22 D21
D12 D11
:
:
:
SEGA131
SEGB131
SEGC131
Palette C
Palette B
Palette A
SEGA0
SEGB0
SEGC0
D42 D41
D32 D31
D22 D21
D12 D11
D21 D22
D11 D12
D01 D02
D72 D71
D71 D72
D61 D62
D51 D52
D41 D42
:
:
X = 00H
:
X = 83H
:
D71 D72
D61 D62
D51 D52
1
D41 D42
UDS
0
Palette C
:
X = 83H
Palette B
Palette C
Palette B
Palette A
:
83H←00H 83H→00H
D42 D41
0
D32 D31
1
D22 D21
X = 00H
D12 D11
00H→83H 00H←83H
D21 D22
1
Palette A
X Address / Display Data / Grayscale Palette / Segment Driver
1
D11 D12
0
0
D01 D02
SWAP
D72 D71
REF
:
D42 D41
D32 D31
1
D22 D21
D12 D11
0
X = 00H
:
X = 83H
X = 83H
:
83H←00H 83H→00H
D71 D72
1
D61 D62
1
D51 D52
X = 00H
D41 D42
00H→83H 00H←83H
D21 D22
0
D11 D12
0
UDS
X Address / Display Data / Grayscale Palette / Segment Driver
1
D01 D02
SWAP
D72 D71
REF
SEGA131
SEGB131
SEGC131
Ver.2004-06-29
D42 D41
D32 D31
D22 D21
D12 D11
D02 D01
D21 D22
D11 D12
D01 D02
D72 D71
D62 D61
D52 D51
D71 D72
D61 D62
D51 D52
D41 D42
:
X = 00H
D31 D32
:
X = 83H
4k-color mode, MODE[1:0]=1H
0
D71 D72
D61 D62
D51 D52
D41 D42
D31 D32
D11 D12
D21 D22
D01 D02
D72 D71
D62 D61
D52 D51
D42 D41
D32 D31
D22 D21
D12 D11
:
:
SEGB131
:
D01 D02
D72 D71
D62 D61
D52 D51
D71 D72
D61 D62
D51 D52
1
D41 D42
D31 D32
0
UDS
SEGA131
:
X = 83H
Palette C
:
83H←00H 83H→00H
Palette B
:
0
D42 D41
1
D32 D31
X = 00H
D22 D21
00H→83H 00H←83H
D12 D11
1
Palette A
X Address / Display Data / Grayscale Palette / Segment Driver
1
D02 D01
0
0
D21 D22
SWAP
D11 D12
REF
:
D01 D02
D72 D71
D62 D61
D52 D51
D42 D41
D32 D31
D22 D21
1
D12 D11
D02 D01
UDS
0
X = 00H
:
X = 83H
D02 D01
83H←00H 83H→00H
D71 D72
1
:
1
X = 83H
:
X = 00H
D61 D62
00H→83H 00H←83H
D51 D52
0
D41 D42
X Address / Display Data / Grayscale Palette / Segment Driver
1
D31 D32
0
0
D11 D12
SWAP
D21 D22
REF
NJU6854
4k-color mode, MODE[1:0]=2H
IDSX
Palette A
Palette B
Palette C
SEGA0
SEGB0
SEGC0
IDSX
Ver.2004-06-29
D31 D32
D11 D12
D21 D22
D01 D02
D72 D71
D62 D61
D52 D51
D42 D41
D32 D31
D22 D21
D12 D11
:
:
:
:
SEGA131
SEGB131
SEGC131
Palette C
Palette B
Palette A
SEGA0
SEGB0
SEGC0
D32 D31
D22 D21
D12 D11
D02 D01
D72 D71
D62 D61
D52 D51
D42 D41
D31 D32
D11 D12
D21 D22
D01 D02
:
:
X = 00H
:
X = 83H
:
D32 D31
D31 D32
D21 D22
D11 D12
1
D01 D02
0
Palette C
:
X = 83H
Palette B
Palette C
Palette B
Palette A
:
83H←00H 83H→00H
D22 D21
0
D12 D11
1
D02 D01
X = 00H
D72 D71
00H→83H 00H←83H
D62 D61
1
Palette A
X Address / Display Data / Grayscale Palette / Segment Driver
1
D52 D51
0
0
D42 D41
SWAP
UDS
REF
X = 00H
D02 D01
D32 D31
D22 D21
1
D12 D11
D02 D01
0
D31 D32
X = 83H
:
83H←00H 83H→00H
X = 83H
:
1
D11 D12
1
D21 D22
X = 00H
D01 D02
00H→83H 00H←83H
D72 D71
0
UDS
X Address / Display Data / Grayscale Palette / Segment Driver
1
D62 D61
0
0
D52 D51
SWAP
D42 D41
REF
SEGA131
SEGB131
SEGC131
- 35 -
NJU6854
(4) PWM CONTROL
There are three variable grayscale modes and one fixed grayscale mode for NJU6854.
In the 65k variable grayscale mode ((PWMM1,PWMM0)=(1,1)), every Aj, Bj and Cj(j=0-31) grayscale palette can
select one of 32 PWM values from 128 levels(0/127~127/127).
In the 4k mode, every Aj, Bj and Cj(j=0-31) grayscale palette can select one of 16 PWM values from 128 levels
(0/127~127/127).
Table 8 PWM and Grayscale mode
PWMM1 PWMM0
Grayscale Mode
0
0
Variable
0
1
Variable
1
0
Fixed
1
1
Variable
Grayscale Display Mode
32 options from 64 levels （65k-color mode）, or 16 options（4k-color mode）
32 options from 32 levels （65k-color mode）, or 16 options（4k-color mode）
16 options from 16 levels （4k-color mode）
32 options from 128 levels （65k-color mode）, or 16 options（4k-color mode）
(5) FRAME RATE CONTROL(FRC)
FRC (Frame Rate control) is the method which averages PWM value (grayscale level) by changing this value by the
frame. The FRC is used for the SEGBi (palette Bj) in combination with PWM control in the 65K mode, so that the
SEGBi can generate 64 grayscales (32 grayscales x 2) by total 6 bits data (5-bit PWM data and 1-bit FRC data).
(6) DISPLAY TIMING GENERATOR
The display timing generator generates timing clocks such as the LP (Latch Pulse), M (Frame Rate) and FLM (First
Line Maker) by dividing an oscillation frequency.
The LP is used for the line counter and the data latch circuit. At the rising edge of the LP signal, the line counter is
counted up, then display data is latched into the data latch circuit. At the falling edge of the LP signal, the latch data is
released to the grayscale control circuit, then segment drivers Ai, Bi and Ci (i=0~131) produce LCD driving waveforms.
The internal data-transmission timing between the DDRAM and segment drivers is completely independent of external
data-transmission timing, so that MPU makes access to the LSI without concern for the LSI’s internal operation.
The M toggles once every frame in the default status, and can be programmed to toggle once every N lines. And the
FLM is used to specify an initial display line, which is preset whenever the FLM becomes “H”.
(7) DATA LATCH CIRCUIT
The data latch circuit is used to temporarily store display data which is released to the grayscale control circuit. The
display data in this circuit is updated in synchronization with the LP. The “Display ON/OFF” and “Reverse Display
ON/OFF” instructions control the data in this circuit, but does not change the data in the DDRAM.
- 36 -
Ver.2004-06-29
NJU6854
(8) COMMON DRIVERS AND SEGMENT DRIVERS
SEGA
SEGB
SEGC
The LSI includes 132-common drivers and 396-segment drivers. The common drivers generate LCD driving
waveforms formed on the V0, V1, V4 and VSSH levels. The segment drivers generate waveforms formed on the V0, V2, V3
and VSSH levels.
LP
COMA0
FLM
COMA1
M
SEGA
SEGB
SEGC
COMA2
COMA0
COMA0
COMA1
COMA1
COMA2
COMA2
SEGA
SEGB
SEGC
SEGA
SEGB
COMA0
COMA1
SEGC
COMA2
Fig 6
Ver.2004-06-29
LCD Driving Waveforms (1/132Duty)
- 37 -
NJU6854
(9) OSCILLATOR
The oscillator consists of a resistor and a capacitor, and generates internal clocks for the display timing generator
and the voltage booster. Through Oscillation Control register(CR), oscillating signal can be generated by using the
internal resistor or an external resistor. Besides, external clock can be used too.
If using the internal resistor, ground OSCI pin and keep OSCO pin open. Frequency can be adjusted or divided by
using Frequency Control register(MDIV). If using the external resistor, connect OSCI and OSCO with an resistor. If
using external clock, input 50% duty signal to the OSCI pin.
(10) LCD POWER SUPPLY
The internal LCD power supply is organized into the voltage converter and the voltage booster. The voltage
converter consists of the reference voltage generator with temperature compensation circuit, the voltage regulator with
EVR control and the LCD bias voltage generator. Furthermore the configuration of the LCD power supply can be
arranged by setting Power Control 1 register(TCBI) and Power Control 2 register (POW2). It is possible to use part of
the internal LCD power supply with an external supply, as shown in Table 17.
DCON
AMPON
VGOFF
VBON
Table 9 Configuration of LCD Power Supply
Voltage
Booster
0
0
X
X
DISABLE
0
1
1
1
Voltage Converter
Voltage Regulator
(VREG output)
Reference Voltage
Generator
(VBA output)
LCD Bias
Generator
DISABLE
DISABLE
DISABLE
ENABLE
DISABLE
DISABLE
DISABLE
External Power Supply
Note
VOUT, V0, V1, V2, V3 and V4 are
supplied
1
VOUT, VREF are supplied
2
VOUT, VREG are supplied
3
0
0
1
X
0
1
ENABLE
ENABLE
VOUT is supplied
4
0
0
ENABLE
DISABLE
VREF is supplied
5
1
X
DISABLE
DISABLE
VREG is supplied
6
0
1
ENABLE
ENABLE
DISABLE
ENALBLE
ENABLE
ENABLE
NOTE1) The LCD bias voltages are externally supplied, and C1±, C2±, C3±, C4±, C5±, VREF, VREG and VEE are open.
NOTE2) The VOUT and VREF are externally supplied, and the C1±, C2±, C3±, C4±, C5± and VEE are open.
NOTE3) The VOUT and VREG are externally supplied, and the C1±, C2±, C3±, C4±, C5± and VEE are open.
NOTE4) The VOUT is externally supplied, and the C1±, C2±, C3±, C4± and C5± are open.
NOTE5) The VREF is externally supplied.
NOTE6) The VREG is externally supplied
- 38 -
Ver.2004-06-29
NJU6854
(10-1) Voltage Booster
The internal voltage booster generates up to 6xVEE voltage. The boost level is selected from 2x~6x by setting the
Boost Level register(GVU). The boost voltage VOUT must not exceed 18.0V, otherwise the voltage stress may cause a
permanent damage to the LSI.
VOUT=18.0V
VOUT=9V
VEE=3V
VEE=3V
VSSH=0V
VSSH=0V
6-time boost
3-time boost
Fig 7
Boost Voltage
5-time Boost
6-time Boost
C1+
C1C2+
C2C3+
C3C4+
C4C5+
C5VOUT
VSSH
4-time Boost
C1+
C1C2+
C2C3+
C3C4+
C4C5+
C5VOUT
VSSH
Fig 8
C1+
C1C2+
C2C3+
C3C4+
C4C5+
C5VOUT
VSSH
+
+
+
+
+
+
3-time Boost
+
+
+
+
C1+
C1C2+
C2C3+
C3C4+
C4C5+
C5VOUT
VSSH
+
+
+
+
+
2-time Boost
+
+
+
C1+
C1C2+
C2C3+
C3C4+
C4C5+
C5VOUT
VSSH
+
+
External Capacitor Connection of Voltage Booster
(10-2) Electrical Volume Register (EVR)
The EVR is used to fine-tune the V0 voltage to optimize display contrast. The EVR value is controlled in 128 steps
by setting the Electrical Volume register(EVOL).
Ver.2004-06-29
- 39 -
NJU6854
(10-3) Voltage Converter
(10-3-1) Voltage Regulator
The voltage regulator consists of an operational amplifier with gain control and EVR. The VREF voltage is
multiplied to obtain the VREG voltage, and gain control is set by the GSEL bit of the Boost Level register (GVU). When
GSEL=0, boost level is determined by VU2~VU0 bits value. When GSEL=1, booster level is determined by RG2~RG0 bit
value.
The relationship of VREG and LCD driving voltage(V0) is shown as below:
available V0 voltage range by control VREG gain
18
Volt
EVR =7FH
16
14
EVR =7FH
VREF=2.7V external reference
VREF=1.9V internal reference
12
10
EVR =00H
8
EVR =00H
6
4
2
VREG
gain
2x
3x
4x
5x
6x
6.45 x
7x
7.3 x
8.0 x
Fig 9 Relationship of V0 and VREG
Table 10 VREG gain
GSEL = ‘0’
VU2
VU1
VU0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
1
1
RG2
0
0
0
0
1
1
1
1
GSEL = ‘1’
RG1
RG0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
VREG Gain
Remark
2
3
4
5
6
6.45
7
7.3
8.0
-
default VU[2:0]
default RG[2:0]
VREG can be calculated by the following equation:
VREG = VREF x N
(N: Boost Level)
Note) To stabilize the VREG, connect a capacitor to the VREG pin.
- 40 -
Ver.2004-06-29
NJU6854
(10-3-2) Reference Voltage Generator
The reference voltage generator outputs about 1.9V reference voltage. When using the internal LCD power supply,
connect the VBA and the VREF. When using an external LCD power supply, input external power into VREF pin and keep
VBA open.
The temperature compensating circuit is built in, compensation coefficient can be selected from the following
shown 4 levels by setting TCV1~TVC0 bits of Power Control 1 register(TCBI).
reference voltage
-0.24% /°C
-0.20% / °C
-0.13% / °C
1.9
-0.0% / C
30
0
-30
Fig 10
60
temperature
Temperature Compensation
Table 11 Temperature Coefficient Selection
TCV[1]
0
0
1
1
TCV[0]
0
1
0
1
VBA Output
0.0 % /°C
- 0.13 % /°C
- 0.20 % /°C
- 0.24 % /°C
Remark
Default setting
(10-3-3) LCD Bias Voltage Generator
The LCD bias voltage generator consists of buffer amplifiers and bleeder resistors, and the bias ratio can be selected
from1/5~1/12 through setting B2~B0 bits of Power Control 1 register(TCBI).
Ver.2004-06-29
- 41 -
NJU6854
(10-4) External Components for LCD Power Supply
Using External Power Supply
Only Using Internal Power Supply
VDD
VEE
VDD
VEE
VBA
VREF
CA1
NJU6854
CA1
CA1
CA1
CA1
VOUT
External
power
circuit
V0
V0
V1
V1
V2
V2
V3
V3
V4
V4
Fig 11
VSS
CA2
CA2
CA2
CA2
CA2
VSS
C1 +
C1 C2 +
C2 C3 +
C3 C4 +
C4 C5 +
C5 -
NJU6854
CA1
C1 C2 +
C2 C3 +
C4 C5 +
C5 -
VREG
VSS
C1 +
C4 +
VREF
CA3
VSS
VREG
C3 -
VBA
CA3
VOUT
V0
V1
V2
V3
V4
Fig 12
Reference guide values of capacitor
CA1
0.47 ~ 4.7 uF
CA2
0.47 ~ 2.2 uF
CA3
0~0.1uF
NOTE1) B grade capacitor is recommended for CA1-CA3. Make sure what is the best capacitor value in the particular
application.
NOTE2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VSSH, VOUT, V0, V1, V2, V3 and V4) reduces step-up
efficiency of the voltage booster, and may have an impact on the LSI’s operation and display quality. To minimize this
impact, be sure to lay out the shortest wires and place capacitors as close to the LSI as possible.
- 42 -
Ver.2004-06-29
NJU6854
Using Internal Power Supply
without Reference Voltage
Generator(1)
Using Internal Power Supply
without Reference Voltage
Generator(2)
VDD
VEE
VDD
VEE
VBA
CA3
VREG
CA1
CA1
CA1
CA1
CA1
VSS
CA2
CA2
CA2
CA2
CA2
VSS
CA1
C1 +
C1 C2 +
C2 C3 +
C3 C4 +
C4 C5 +
C5 -
VREF
VREG
VSS
VSS
CA1
CA3
CA1
CA1
CA1
CA1
CA1
VOUT
VSS
CA2
V0
CA2
V1
CA2
V2
CA2
V3
CA2
V4
Fig 11
VSS
C1 +
C1 C2 +
C2 C3 +
C3 C4 +
C4 C5 +
C5 -
NJU6854
CA3
CA3
VREF
NJU6854
thermistor
VBA
VOUT
V0
V1
V2
V3
V4
Fig 12
Reference guide values of capacitor
CA1
0.47 ~ 4.7 uF
CA2
0.47 ~ 2.2 uF
CA3
0~0.1uF
NOTE1) B grade capacitor is recommended for CA1-CA3. Make sure what is the best capacitor value in the particular
application.
NOTE2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VSSH, VOUT, V0, V1, V2, V3 and V4) reduces step-up
efficiency of the voltage booster, and may have an impact on the LSI’s operation and display quality. To minimize this
impact, be sure to lay out the shortest wires and place capacitors as close to the LSI as possible.
.
Ver.2004-06-29
- 43 -
NJU6854
Using Internal Power Supply
Without Voltage Booster
VDD
VEE
VBA
CA3
VREF
VREG
VSS
C1 +
C3 C4 +
C4 C5 +
C5 -
External
power
circuit
NJU6854
C1 C2 +
C2 C3 +
VOUT
CA2
CA2
CA2
CA2
CA2
VSS
V0
V1
V2
V3
V4
Fig 15
Reference guide values of capacitor
CA1
0.47 ~ 4.7 uF
CA2
0.47 ~ 2.2 uF
CA3
0~0.1uF
NOTE1) B grade capacitor is recommended for CA1-CA3. Make sure what is the best capacitor value in the particular
application.
NOTE2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VSSH, VOUT, V0, V1, V2, V3 and V4) reduces step-up
efficiency of the voltage booster, and may have an impact on the LSI’s operation and display quality. To minimize this
impact, be sure to lay out the shortest wires and place capacitors as close to the LSI as possible.
- 44 -
Ver.2004-06-29
NJU6854
(10-5) Power ON/OFF
To protect the LSI from over current, the following sequences must be maintained to turn on and off the power
supply.
Using Internal LCD Power Supply
Power ON
First “VDD and VEE ON”, next “Reset by RESb”, then “Internal LCD power supply ON”. Be sure to execute the
“Display ON” instruction later than the completion of this power ON sequence. Otherwise, unexpected pixels may be
turned on instantly.
Power OFF
First “Reset by RESb or “HALT” instruction”, next “VDD and VEE OFF”. If using different power sources for the
VDD and the VEE, the VEE must be turned off after the reset or the “HALT”. After that, the VDD can be turned off, waiting
until the LCD bias voltages (V0~V4) drop below the threshold level of LCD pixels.
Using External LCD Power Supply
Power ON
First “VDD and VEE ON”, next “Reset by RESb”, then “External LCD power supply ON”. When using only external
VOUT, first “VDD ON”, next “Reset by RESb”, then “External VOUT ON”, as well.
Power OFF
First “Reset by RESb or “HALT” instruction” to isolate external LCD bias voltages, next “VDD OFF”. For more
safety, placing a resistor in series on the V0 line (or the VOUT line in using only the external VOUT) is recommended. That
resistance is usually between 50Ω and 100Ω.
VDD, VEE
Fig 16 Rising Time of the Power Supply
Item
Recommended Rising Time
Applicable Power
tr
VDD, VEE
30 ㎲ ~ 100 ㎳
Note : The rising time is the time from 10% VDD to 90%VEE
(10-6) Discharge Circuit
The LSI incorporates two independently discharge circuits for the capacitors connected to VOUT and V1-V4. When
setting DSI1 bit of Discharge ON/OFF register (DISC) to “1”, or executing reset instruction, the capacitors on V1-V4 are
discharged, by the same way, setting DSI2 to “1” or resetting, the capacitor on VOUT is discharged.
Be sure to turn off the internal or external LCD power supply during discharging, otherwise discharge circuit will
function as a current load and increase operating current.
Ver.2004-06-29
- 45 -
NJU6854
(10-7) Reset Function
The reset function initializes the LSI to the following default status by setting the RESb to “L”. Usually connect the
RESb to MPU’s reset pin, so that the LSI and MPU are initialized simultaneously.
Table 12 Default Status
ITEM
DDRAM
Y address
X address
DDRAM access increment mode
Bus length
Initial display line
Display ON/OFF
Reverse display ON/OFF
Display clock monitor
Duty cycle ratio
Vertical Blanking Area
n-line Inversion ON/OFF
Common scan direction
REF
Swap
Electronic Volume Register(EVR)
Internal LCD Power Supply
Display mode
Bias ratio
Colors Select
Grayscale palette Aj[6:0]
Grayscale palette Bj[6:0]
Grayscale palette Cj[6:0]
Extra palette PCX[6:0]
PWM output mode
Discharge ON/OFF
- 46 -
Initial value
Undefined
00H
00H
X/Y address increment ON
8bit
st
0H (1 line)
OFF
OFF(Normal)
OFF
1/132
0
OFF
COMA0 → COMA65 → COMB0 → COMB65
REF=0(Normal)
OFF(Normal)
(0, 0, 0, 0, 0, 0)
OFF
Variable grayscale mode(64 grayscales)
1/9 bias
65,536 colors
Default value
Default value
Default value
Default value
Forward PWM
OFF(0)
Ver.2004-06-29
NJU6854
(11) INSTRUCTION TABLES
Table 0 [2:0] = 000B
RA[3:0]
0
0000
Name
D7
D6
D5
D4
D3
D2
D1
D0
REMARK
CR
*
*
*
*
*
CRF
CRS1
CRS0
OSC control
1
0001
CFG
AIM1
AIM0
VWR
IDSY
IDSX
WIN
UDS
SWIF
Display data Configuration
/Window Area ON/OFF
/Increment Control
2
0010
VPC
VPC7
VPC6
VPC5
VPC4
VPC3
VPC2
VPC1
VPC0
Display Line Number
3
0011
FVC
*
*
*
*
FVC3
FVC2
FVC1
FVC0
Blank Line Number
4
0100
ADRH
XA7
XA6
XA5
XA4
XA3
XA2
XA1
XA0
DDRAM X address
5
0101
ADRL
YA7
YA6
YA5
YA4
YA3
YA2
YA1
YA0
DDRAM Y address
6
0110
EADRH
XEA7
XEA6
XEA5
XEA4
XEA3
XEA2
XEA1
XEA0
Window End X address
7
0111
EADRL
YEA7
YEA6
YEA5
YEA4
YEA3
YEA2
YEA1
YEA0
Window End Y address
8
1000
COLOR
PWMM1
PWMM0
*
MODE1
MODE0
*
*
MODED
Display Mode/Grayscale Mode
9
1001
MDIV
*
MDIV2
MDIV1
MDIV0
*
CRB2
CRB1
CRB0
OSC Frequency control
10
1010
HCT
*
HCT6
HCT5
HCT4
HCT3
HCT2
HCT1
HCT0
Header COM
11
1011
HST
HST7
HST6
HST5
HST4
HST3
HST2
HST1
HST0
Initial Display Line
12
1100
SSC1
SSC17
SSC16
SSC15
SSC14
SSC13
SSC12
SSC11
SSC10
Scan Start COM 1
13
1101
SSC2
SSC27
SSC26
SSC25
SSC24
SSC23
SSC22
SSC21
SSC20
Scan Start COM 2
14
1110
PCC1
PCC17
PCC16
PCC15
PCC14
PCC13
PCC12
PCC11
PCC10
Partial Display Line Number1
15
1111
PCC2
PCC27
PCC26
PCC25
PCC24
PCC23
PCC22
PCC21
PCC20
Partial Display Line Number 2
Table1 [2:0] = 001B
RA[3:0]
Name
D7
D6
D5
D4
D3
D2
D1
D0
REMARK
0
0000
MC
MC7
MC6
MC5
MC4
MC3
MC2
MC1
MC0
N-line Inversion
1
0001
TCBI
VGOFF
VBON
TCV1
TCV0
*
B2
B1
B0
Power Control 1
2
0010
EVOL
*
EVOL6
EVOL5
EVOL4
EVOL3
EVOL2
EVOL1
EVOL0
Electronic Volume
3
0011
PBX
MON
*
*
GS
PBX3
PBX2
PBX1
PBX0
Display Timing Signal
Monitor/Grayscale palette BX
4
0100
*
*
*
*
*
*
*
*
*
N/A
5
0101
POW2
*
*
*
CKCONT
AMPON
HALT
DCON
RES
Power control 2
6
0110
GVU
GSEL
RG2
RG1
RG0
*
VU2
VU1
VU0
Amplifier gain/ Booster Level
7
0111
BCK
BCKS
BCKG
*
*
BCK3
BCK2
BCK1
BCK0
Booster clock
8
1000
DISPLAY
REF
SWAP
*
SHIFT1
SHIFT0
TBC
TEN
ON/OFF
Display control
9
1001
PWM
*
*
PWMC1
PWMC0
PWMB1
PWMB0
PWMA1
PWMA0
PWM Mode control
10
1010
ECONT
TST0
EN3PTL
ENLED
REV
LED13
LED12
LED11
LED10
3 Partial Display
/ LED control / Rev
11
1011
DISC
*
*
*
*
*
*
DIS2
DIS1
Discharge control
12
1100
EDATA
LED27
LED26
LED25
LED24
LED23
LED22
LED21
LED20
LED control signal
13
1101
RA
RSS
RA6
RA5
RA4
RA3
RA2
RA1
RA0
Setting Instruction Table
14
1110
SSC3
SSC37
SSC36
SSC35
SSC34
SSC33
SSC32
SSC31
SSC30
Scan Start COM 3
15
1111
PCC3
PCC37
PCC36
PCC35
PCC34
PCC33
PCC32
PCC31
PCC30
Partial Display Line Number3
Ver.2004-06-29
- 47 -
NJU6854
Table2 [2:0] = 010B
RA[3:0]
Name
D7
D6
D5
D4
D3
D2
D1
D0
REMARK
0
0000
PA0
*
PA06
PA05
PA04
PA03
PA02
PA01
PA00
Grayscale palette A0 (0/31)
1
0001
PA1
*
PA16
PA15
PA14
PA13
PA12
PA11
PA10
Grayscale palette A1 (1/31)
2
0010
PA2
*
PA26
PA25
PA24
PA23
PA22
PA21
PA20
Grayscale palette A2 (2/31)
3
0011
PA3
*
PA36
PA35
PA34
PA33
PA32
PA31
PA30
Grayscale palette A3 (3/31)
4
0100
PA4
*
PA46
PA45
PA44
PA43
PA42
PA41
PA40
Grayscale palette A4 (4/31)
5
0101
PA5
*
PA56
PA55
PA54
PA53
PA52
PA51
PA50
Grayscale palette A5 (5/31)
6
0110
PA6
*
PA66
PA65
PA64
PA63
PA62
PA61
PA60
Grayscale palette A6 (6/31)
7
0111
PA7
*
PA76
PA75
PA74
PA73
PA72
PA71
PA70
Grayscale palette A7 (7/31)
8
1000
PA8
*
PA86
PA85
PA84
PA83
PA82
PA81
PA80
Grayscale palette A8 (8/31)
9
1001
PA9
*
PA96
PA95
PA94
PA93
PA92
PA91
PA90
Grayscale palette A9 (9/31)
10
1010
PA10
*
PA106
PA105
PA104
PA103
PA102
PA101
PA100
Grayscale palette A10 (10/31)
11
1011
PA11
*
PA116
PA115
PA114
PA113
PA112
PA111
PA110
Grayscale palette A11 (11/31)
12
1100
PA12
*
PA126
PA125
PA124
PA123
PA122
PA121
PA120
Grayscale palette A12 (12/31)
13
1101
PA13
*
PA136
PA135
PA134
PA133
PA132
PA131
PA130
Grayscale palette A13 (13/31)
14
1110
PA14
*
PA146
PA145
PA144
PA143
PA142
PA141
PA140
Grayscale palette A14 (14/31)
15
1111
PA15
*
PA156
PA155
PA154
PA153
PA152
PA151
PA150
Grayscale palette A15 (15/31)
Name
D7
D6
D5
D4
D3
D2
D1
D0
REMARK
Table3 [2:0] = 011B
RA[3:0]
0
0000
PA16
*
PA166
PA165
PA164
PA163
PA162
PA161
PA160
Grayscale palette A16 (16/31)
1
0001
PA17
*
PA176
PA175
PA174
PA173
PA172
PA171
PA170
Grayscale palette A17 (17/31)
2
0010
PA18
*
PA186
PA185
PA184
PA183
PA182
PA181
PA180
Grayscale palette A18 (18/31)
3
0011
PA19
*
PA196
PA195
PA194
PA193
PA192
PA191
PA190
Grayscale palette A19 (19/31)
4
0100
PA20
*
PA206
PA205
PA204
PA203
PA202
PA201
PA200
Grayscale palette A20 (20/31)
5
0101
PA21
*
PA216
PA215
PA214
PA213
PA212
PA211
PA210
Grayscale palette A21 (21/31)
6
0110
PA22
*
PA226
PA225
PA224
PA223
PA222
PA221
PA220
Grayscale palette A22 (22/31)
7
0111
PA23
*
PA236
PA235
PA234
PA233
PA232
PA231
PA230
Grayscale palette A23 (23/31)
8
1000
PA24
*
PA246
PA245
PA244
PA243
PA242
PA241
PA240
Grayscale palette A24 (24/31)
9
1001
PA25
*
PA256
PA255
PA254
PA253
PA252
PA251
PA250
Grayscale palette A25 (25/31)
10
1010
PA26
*
PA266
PA265
PA264
PA263
PA262
PA261
PA260
Grayscale palette A26 (26/31)
11
1011
PA27
*
PA276
PA275
PA274
PA273
PA272
PA271
PA270
Grayscale palette A27 (27/31)
12
1100
PA28
*
PA286
PA285
PA284
PA283
PA282
PA281
PA280
Grayscale palette A28 (28/31)
13
1101
PA29
*
PA296
PA295
PA294
PA293
PA292
PA291
PA290
Grayscale palette A29 (29/31)
14
1110
PA30
*
PA306
PA305
PA304
PA303
PA302
PA301
PA300
Grayscale palette A30 (30/31)
15
1111
PA31
*
PA316
PA315
PA314
PA313
PA312
PA311
PA310
Grayscale palette A31 (31/31)
- 48 -
Ver.2004-06-29
NJU6854
Table4 [2:0] = 100B
RA[3:0]
Name
D7
D6
D5
D4
D3
D2
D1
D0
REMARK
0
0000
PB0
*
PB06
PB05
PB04
PB03
PB02
PB01
PB00
Grayscale palette B0 (0/31)
1
0001
PB1
*
PB16
PB15
PB14
PB13
PB12
PB11
PB10
Grayscale palette B1 (1/31)
2
0010
PB2
*
PB26
PB25
PB24
PB23
PB22
PB21
PB20
Grayscale palette B2 (2/31)
3
0011
PB3
*
PB36
PB35
PB34
PB33
PB32
PB31
PB30
Grayscale palette B3 (3/31)
4
0100
PB4
*
PB46
PB45
PB44
PB43
PB42
PB41
PB40
Grayscale palette B4 (4/31)
5
0101
PB5
*
PB56
PB55
PB54
PB53
PB52
PB51
PB50
Grayscale palette B5 (5/31)
6
0110
PB6
*
PB66
PB65
PB64
PB63
PB62
PB61
PB60
Grayscale palette B6 (6/31)
7
0111
PB7
*
PB76
PB75
PB74
PB73
PB72
PB71
PB70
Grayscale palette B7 (7/31)
8
1000
PB8
*
PB86
PB85
PB84
PB83
PB82
PB81
PB80
Grayscale palette B8 (8/31)
9
1001
PB9
*
PB96
PB95
PB94
PB93
PB92
PB91
PB90
Grayscale palette B9 (9/31)
10
1010
PB10
*
PB106
PB105
PB104
PB103
PB102
PB101
PB100
Grayscale palette B10 (10/31)
11
1011
PB11
*
PB116
PB115
PB114
PB113
PB112
PB111
PB110
Grayscale palette B11 (11/31)
12
1100
PB12
*
PB126
PB125
PB124
PB123
PB122
PB121
PB120
Grayscale palette B12 (12/31)
13
1101
PB13
*
PB136
PB135
PB134
PB133
PB132
PB131
PB130
Grayscale palette B13 (13/31)
14
1110
PB14
*
PB146
PB145
PB144
PB143
PB142
PB141
PB140
Grayscale palette B14 (14/31)
15
1111
PB15
*
PB156
PB155
PB154
PB153
PB152
PB151
PB150
Grayscale palette B15 (15/31)
Table5 [2:0] = 101B
RA[3:0]
Name
D7
D6
D5
D4
D3
D2
D1
D0
REMARK
0
0000
PB16
*
PB166
PB165
PB164
PB163
PB162
PB161
PB160
Grayscale palette B16 (16/31)
1
0001
PB17
*
PB176
PB175
PB174
PB173
PB172
PB171
PB170
Grayscale palette B17 (17/31)
2
0010
PB18
*
PB186
PB185
PB184
PB183
PB182
PB181
PB180
Grayscale palette B18 (18/31)
3
0011
PB19
*
PB196
PB195
PB194
PB193
PB192
PB191
PB190
Grayscale palette B19 (19/31)
4
0100
PB20
*
PB206
PB205
PB204
PB203
PB202
PB201
PB200
Grayscale palette B20 (20/31)
5
0101
PB21
*
PB216
PB215
PB214
PB213
PB212
PB211
PB210
Grayscale palette B21 (21/31)
6
0110
PB22
*
PB226
PB225
PB224
PB223
PB222
PB221
PB220
Grayscale palette B22 (22/31)
7
0111
PB23
*
PB236
PB235
PB234
PB233
PB232
PB231
PB230
Grayscale palette B23 (23/31)
8
1000
PB24
*
PB246
PB245
PB244
PB243
PB242
PB241
PB240
Grayscale palette B24 (24/31)
9
1001
PB25
*
PB256
PB255
PB254
PB253
PB252
PB251
PB250
Grayscale palette B25 (25/31)
10
1010
PB26
*
PB266
PB265
PB264
PB263
PB262
PB261
PB260
Grayscale palette B26 (26/31)
11
1011
PB27
*
PB276
PB275
PB274
PB273
PB272
PB271
PB270
Grayscale palette B27 (27/31)
12
1100
PB28
*
PB286
PB285
PB284
PB283
PB282
PB281
PB280
Grayscale palette B28 (28/31)
13
1101
PB29
*
PB296
PB295
PB294
PB293
PB292
PB291
PB290
Grayscale palette B29 (29/31)
14
1110
PB30
*
PB306
PB305
PB304
PB303
PB302
PB301
PB300
Grayscale palette B30 (30/31)
15
1111
PB31
*
PB316
PB315
PB314
PB313
PB312
PB311
PB310
Grayscale palette B31 (31/31)
Ver.2004-06-29
- 49 -
NJU6854
Table6 [2:0] = 110B
RA[3:0]
Name
D7
D6
D5
D4
D3
D2
D1
D0
REMARK
0
0000
PC0
*
PC06
PC05
PC04
PC03
PC02
PC01
PC00
Grayscale palette C0 (0/31)
1
0001
PC1
*
PC16
PC15
PC14
PC13
PC12
PC11
PC10
Grayscale palette C1 (1/31)
2
0010
PC2
*
PC26
PC25
PC24
PC23
PC22
PC21
PC20
Grayscale palette C2 (2/31)
3
0011
PC3
*
PC36
PC35
PC34
PC33
PC32
PC31
PC30
Grayscale palette C3 (3/31)
4
0100
PC4
*
PC46
PC45
PC44
PC43
PC42
PC41
PC40
Grayscale palette C4 (4/31)
5
0101
PC5
*
PC56
PC55
PC54
PC53
PC52
PC51
PC50
Grayscale palette C5 (5/31)
6
0110
PC6
*
PC66
PC65
PC64
PC63
PC62
PC61
PC60
Grayscale palette C6 (6/31)
7
0111
PC7
*
PC76
PC75
PC74
PC73
PC72
PC71
PC70
Grayscale palette C7 (7/31)
8
1000
PC8
*
PC86
PC85
PC84
PC83
PC82
PC81
PC80
Grayscale palette C8 (8/31)
9
1001
PC9
*
PC96
PC95
PC94
PC93
PC92
PC91
PC90
Grayscale palette C9 (9/31)
10
1010
PC10
*
PC106
PC105
PC104
PC103
PC102
PC101
PC100
Grayscale palette C10 (10/31)
11
1011
PC11
*
PC116
PC115
PC114
PC113
PC112
PC111
PC110
Grayscale palette C11 (11/31)
12
1100
PC12
*
PC126
PC125
PC124
PC123
PC122
PC121
PC120
Grayscale palette C12 (12/31)
13
1101
PC13
*
PC136
PC135
PC134
PC133
PC132
PC131
PC130
Grayscale palette C13 (13/31)
14
1110
PC14
*
PC146
PC145
PC144
PC143
PC142
PC141
PC140
Grayscale palette C14 (14/31)
15
1111
PC15
*
PC156
PC155
PC154
PC153
PC152
PC151
PC150
Grayscale palette C15 (15/31)
Table7 [2:0] = 111B
RA[3:0]
Name
D7
D6
D5
D4
D3
D2
D1
D0
REMARK
0
0000
PC16
*
PC166
PC165
PC164
PC163
PC162
PC161
PC160
Grayscale palette C16 (16/31)
1
0001
PC17
*
PC176
PC175
PC174
PC173
PC172
PC171
PC170
Grayscale palette C17 (17/31)
2
0010
PC18
*
PC186
PC185
PC184
PC183
PC182
PC181
PC180
Grayscale palette C18 (18/31)
3
0011
PC19
*
PC196
PC195
PC194
PC193
PC192
PC191
PC190
Grayscale palette C19 (19/31)
4
0100
PC20
*
PC206
PC205
PC204
PC203
PC202
PC201
PC200
Grayscale palette C20 (20/31)
5
0101
PC21
*
PC216
PC215
PC214
PC213
PC212
PC211
PC210
Grayscale palette C21 (21/31)
6
0110
PC22
*
PC226
PC225
PC224
PC223
PC222
PC221
PC220
Grayscale palette C22 (22/31)
7
0111
PC23
*
PC236
PC235
PC234
PC233
PC232
PC231
PC230
Grayscale palette C23 (23/31)
8
1000
PC24
*
PC246
PC245
PC244
PC243
PC242
PC241
PC240
Grayscale palette C24 (24/31)
9
1001
PC25
*
PC256
PC255
PC254
PC253
PC252
PC251
PC250
Grayscale palette C25 (25/31)
10
1010
PC26
*
PC266
PC265
PC264
PC263
PC262
PC261
PC260
Grayscale palette C26 (26/31)
11
1011
PC27
*
PC276
PC275
PC274
PC273
PC272
PC271
PC270
Grayscale palette C27 (27/31)
12
1100
PC28
*
PC286
PC285
PC284
PC283
PC282
PC281
PC280
Grayscale palette C28 (28/31)
13
1101
PC29
*
PC296
PC295
PC294
PC293
PC292
PC291
PC290
Grayscale palette C29 (29/31)
14
1110
PC30
*
PC306
PC305
PC304
PC303
PC302
PC301
PC300
Grayscale palette C30 (30/31)
15
1111
PC31
*
PC316
PC315
PC314
PC313
PC312
PC311
PC310
Grayscale palette C31 (31/31)
- 50 -
Ver.2004-06-29
NJU6854
(12) INSTRUCTION DESCRIPTIONS
(12-1) 8-bit Access Mode
(12-1-1) Instruction Register
Set MSB bit of the 1st byte to “0”. Data to instruction register is transferred in 2 bytes, For the 1st byte, D6~D4 is
used to set the instruction table address, and D3~D0 to set instruction register address. The 2nd byte is instruction data.
MSB
0
Instruction Table Address
LSB
Instruction Register Address
st
1 access
nd
data
2 access
(Example) X, Y address of DDRAM
st
Step 1: 1 byte(X address)
Step 2: 2
nd
D7
0
D6
0
D5
0
D4
0
0
Table address
D3
0
D2
1
D1
0
D0
0
CSb
0
Register address
RS
1
RDb
1
WRb
0
Pins setting
byte(X address)
D7
XA7
D6
XA6
D5
XA5
D4
XA4
D3
XA3
D2
XA2
D1
XA1
D0
XA0
CSb
0
RS
1
RDb
1
WRb
0
D5
0
D4
0
D3
0
D2
1
D1
0
D0
1
CSb
0
RS
1
RDb
1
WRb
0
st
Step 3: 1 byte(Y address)
Step 4: 2
nd
D7
0
D6
0
0
Table address
Pins setting
byte(Y address).
D7
YA7
Ver.2004-06-29
Register address
D6
YA6
D5
YA5
D4
YA4
D3
YA3
D2
YA2
D1
YA1
D0
YA0
CSb
0
RS
1
RDb
1
WRb
0
- 51 -
NJU6854
(12-1-2) Auto-increment of Instruction Register Address
By setting MSB bit of the 1st byte to “1”, instruction data can be written to the registers successively. For the 1st
byte, D6~D4 is used to set the instruction table address(Table[2:0]) and D3~D0 to set the count number for the registers,
from the 2nd byte, data will be automatically written to the successive registers.
MSB
1
LSB
Table address
Count number(n)
data of address 0
count 1
data of address 1
.
.
.
.
.
data of address n-1
count 2
count n
If the counter number is set as 0, data is written to the registers from the address 0 to 15.
(Example) Oscillator and others.
Step 1: 8bit auto increment / table address set / count number
D7
1
D6
0
D5
0
D4
0
1
Table address
D3
0
D2
1
D1
0
D0
1
CSb
0
RS
1
RDb
1
WRb
0
Pins setting
count number = 5
Step 2: 8bit auto increment / count = 1
D7
*
D6
*
D5
*
D4
*
D3
*
D2
D1
D0
CSb
RS
RDb
WRb
CRF
CRS1
CRS0
0
1
1
0
Step 3: 8 bit auto increment / count = 2
D7
D6
D5
D4
D3
D2
D1
D0
CSb
RS
RDb
WRb
AIM1
AIM0
VWR
IDSY
IDSX
WIN
UDS
SWIF
0
1
1
0
Step 4: 8 bit auto increment / count = 3
D7
D6
D5
D4
D3
D2
D1
D0
CSb
RS
RDb
WRb
VPC7
VPC6
VPC5
VPC4
VPC3
VPC2
VPC1
VPC0
0
1
1
0
Step 5: 8 bit auto increment / count = 4
D7
D6
D5
D4
D3
D2
D1
D0
CSb
RS
RDb
WRb
*
*
*
*
FVC3
FVC2
FVC1
FVC0
0
1
1
0
Step 6: 8 bit auto increment / count = 5
- 52 -
D7
D6
D5
D4
D3
D2
D1
D0
CSb
RS
RDb
WRb
XA7
XA6
XA5
XA4
XA3
XA2
XA1
XA0
0
1
1
0
Ver.2004-06-29
NJU6854
(12-2) 16-bit Access Mode
(12-2-1) Instruction Register
Set MSB bit to”0”. Instruction table number, instruction register address and instruction data will be transferred in
one 16-bit data. Instruction table number is determined by D14~D12, instruction register is determined by D11~D8, and
D7~D0 is instruction data.
MSB
0
LSB
Table address
Register address
Instruction data
(Example) X, Y address of DDRAM
Step 1: X address setting.
D15
0
0
D14
0
D13
0
D12
0
D11
0
D10
1
D9
0
D8
0
D7
XA7
D6
XA6
D5
XA5
D4
XA4
Register address
Table address
D3
XA3
D2
XA2
D1
XA1
D0
XA0
D2
YA2
D1
YA1
D0
YA0
data
Step 1: Y address setting
D15
0
0
D14
0
D13
0
D12
0
D11
0
D10
1
D9
0
D8
1
D7
YA7
D6
YA6
D5
YA5
D4
YA4
Register address
Table address
D3
YA3
data
(12-2-2) Auto Increment of Instruction Register Address
By setting MSB bit of the 1st byte to “1”, instruction data can be written to the registers successively. For the 1st
byte, only upper 8-bit data is valid, D14~D12 is used to set the instruction table number(Table[2:0]) and D11~D8 to set
the count number of the registers. From the 2nd byte, data will be automatically written to the successive registers.
MSB
1
LSB
Count number(n)
Table address
data of address 0
data of address 1
data of address 2
..
.
.
data of address n-2
data of address 3
..
.
.
data of address n-1
If count number is 0, data is written to the registers from the address 0 to 15.
(Example) Oscillator and Configuration control
Step 1:
D15
1
1
D14
0
D13
0
D12
0
Table address
D11
0
D10
1
D9
0
D8
1
D7
*
D6
*
count number = 5
D5
*
D4
*
D3
*
D2
*
D1
*
D0
*
data (don’t care )
Step 2:
D15
*
D14
*
D13
*
D12
*
D11
*
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CRF
CRS1
CRS0
AIM1
AIM0
VWR
IDSY
IDSX
WIN
UDS
SWIF
Step 3:
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VPC7
VPC6
VPC5
VPC4
VPC3
VPC2
VPC1
VPC0
*
*
*
*
FVC3
FVC2
FVC1
FVC0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
XA7
XA6
XA5
XA4
XA3
XA2
XA1
XA0
*
*
*
*
*
*
*
*
Step 4:
(*: not applicable)
Ver.2004-06-29
- 53 -
NJU6854
(12-3) Oscillation Control
Register : CR Table0 [0H]
D7
*
D6
*
D5
*
D4
*
D3
*
D2
CRF
D1
CRS1
D0
CRS0
CSb
0
RS
1
RDb
1
WRb
0
(default: {CRF, CRS1, CRS0} = 0H, address: 0H)
Setting Frequency
CRF
0
0
0
0
1
1
1
1
CRS1
0
0
1
1
0
0
1
1
CRS0
0
1
0
1
0
1
0
1
Function
OSCI (730 kHz)
OSC2 (170 kHz)
OSC5 (external R, external source)
Invalid
OSC3 (1,200 kHz)
OSC4 (285 kHz)
Invalid
Invalid
In OSC5 mode, connect the OSCI pin and the OSCO pin with a resistor, and input external clock signal to OSCI.
(12-4) Display Data Assignment/ Window Area ONOFF/Increment Control
Register: CFG / Table 0 [1H]
D7
AIM1
D6
AIM0
D5
VWR
D4
IDSY
D3
IDSX
D2
WIN
D1
UDS
D0
SWIF
CSb
0
RS
1
RDb
1
WRb
0
(default: {AIM1, AIM0, VWR, IDSY, ISDX, WIN, UDS, SWIF} = 0H, address: 1H)
(i) SWIF
SWIF
0
1
Bus length
8bit I/F (Initial Value)
16bit I/F
(ii) UDS
Assignment of MPU data on the DDRAM
16 Bit I/F Access
UDS = “0”: the lower 8-bit MPU data corresponding to the lower 8-bit display data
the upper 8-bit MPU data corresponding to the upper 8-bit display data
UDS = “1”: the lower 8-bit MPU data corresponding to the upper 8-bit display data
the upper 8-bit MPU data corresponding to the lower 8-bit display data
8 Bit I/F Access
UDS = “0”: 1st MPU data corresponding to the lower 8-bit display data
2nd MPU data corresponding to the upper 8-bit display data
UDS = “1”: 1st MPU data corresponding to the upper 8-bit display data
2nd MPU data corresponding to the lower 8-bit display data
(iii) WIN
WIN = “1” : Window area ON
WIN = “0” : Window area OFF(default)
(iv) IDSX
X address auto increment/auto decrement
IDSX = “0” : auto increment
IDSX = “1” : auto decrement
(v) IDSY
Y address auto increment/auto decrement
IDSY = “0” : auto increment
IDSY = “1” : auto decrement
- 54 -
Ver.2004-06-29
NJU6854
(vi) VWR
Setting the direction of data write /read to DDRAM
VWR = “0” : start from X direction
VWR = “1” : start from Y direction
(vii) AIM[1:0]
AIM1
0
0
1
1
AIM0
0
1
0
1
Auto increment/decrement during data writing and reading
Auto increment/decrement during data writing
Auto increment/decrement OFF
Prohibited
(12-5) Display Line Number
Register: VPC TABLE0 [2H]
D7
VPC7
D6
VPC6
D5
VPC5
D4
VPC4
D3
VPC3
D2
VPC2
D1
VPC1
D0
VPC0
CSb
0
RS
1
RDb
1
WRb
0
(default: VPC[7:0] = 84H, address: 2H)
VPC[7:0]: display line number (displayed pixel number in Y direction).
Setting within the range of 2~132（02H~84H）
VPC7
0
0
0
0
0
0
VPC6
0
0
0
0
0
0
VPC5
0
0
0
0
0
0
VPC4
0
0
0
0
0
0
VPC3
0
0
0
0
0
0
VPC2
0
0
0
0
1
1
VPC1
0
0
1
1
0
0
VPC0
0
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
Vertical Pixel Number
Forbidden
Forbidden
2
3
4
5
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
130
131
132
Forbidden
1
1
1
1
1
Forbidden
D4
*
D3
FVC3
D1
FVC1
D0
FVC0
:
:
(12-6) Blank Line Number
Register : FVC TABLE0 [3H]
D7
*
D6
*
D5
*
D2
FVC2
CSb
0
RS
1
RDb
1
WRb
0
(default: FVC[3:0]=0H, address: 3H)
FVC[3:0]: Blank line number(not displayed pixel number in Y direction)
FVC3
0
0
FVC2
0
0
1
1
1
1
FVC1
0
0
FVC0
0
1
Vertical blanking Lines
0
1
1
1
0
1
14
15
:
Ver.2004-06-29
- 55 -
NJU6854
(12-7) X Address
Register : ADRH TABLE0 [4H]
D7
XA7
D6
XA6
D5
XA5
D4
XA4
D3
XA3
D2
XA2
D1
XA1
D0
XA0
CSb
0
RS
1
RDb
1
WRb
0
D2
YA2
D1
YA1
D0
YA0
CSb
0
RS
1
RDb
1
WRb
0
D2
XEA2
D1
XEA1
D0
XEA0
CSb
0
RS
1
RDb
1
WRb
0
RS
1
RDb
1
WRb
0
RS
1
RDb
1
WRb
0
(default: XA[7:0] = 0H, address: 4H)
X address range is from 00H to 83H.
(12-8) Y Address
Register : ADRL TABLE0 [5H]
D7
YA7
D6
YA6
D5
YA5
D4
YA4
D3
YA3
(default: YA[7:0] = 0H, address: 5H)
Y address range is from 00H to 83H.
(12-9) Window End X Address
Register : EADRH TABLE0 [6H]
D7
XEA7
D6
XEA6
D5
XEA5
D4
XEA4
D3
XEA3
(default: XEA[7:0] = 0H, address: 6H)
Setting X address of window area when window area access is valid(WIN=”1”).
(12-10) Window End Y Address
Register : EADRL TABLE0 [7H]
D7
YEA7
D6
YEA6
D5
YEA5
D4
YEA4
D3
YEA3
D2
YEA2
D1
YEA1
D0
YEA0
CSb
0
(default: YEA[7:0] = 0H, address: 7H)
Setting Y address of window area when window area access is valid(WIN=”1”).
(12-11) Display Mode/Grayscale Mode
Register : COLOR TABLE0 [8H]
D7
D6
PWMM1 PWMM0
D5
*
D4
D3
MODE1 MODE0
D2
*
D1
*
D0
MODED
CSb
0
(default: PWMM[1:0], MODE[1:0], MODED = 0H, address: 8H)
(i) MODED
Setting 65k-color or 4k-color display mode
MODED
0
1
Display Color Mode
65,536 Colors Mode (PWM 5bit + 2 FRC)
4,096 Colors(4bit PWM only)
(ii) MODE[1:0]
Bit assignment of display data
MODE[1:0]
Input data
Remark
MODE1
MODE0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
0
1
0
1
C4
C3
C3
C2
C2
C1
C1
C0
C0
B5
B3
C2
B4
B2
C1
B3
B1
C0
B2
B0
B3
B1
B0
B2
B1
A4
A3
B0
A3
A2
A3
A2
A1
A2
A1
A0
A1
A0 Note
(2)
Note
(3)
A0 Note
Invalid
C3
(1)
Note (1) 65,536 colors 5-6-5 data
(2) 4,096 colors 4-4-4 data
(3) 4,096 colors4-4-4 data, upper 4 bits invalid
- 56 -
Ver.2004-06-29
NJU6854
(iii) PWMM[1:0]
Setting grayscale mode through PWM control.
PWMM1
0
0
1
1
PWMM0
0
1
0
1
Select 32 grayscales
Select 32 grayscales
Select 16 grayscales
Select 32 grayscales
Grayscale Mode
（65k mode） or 16 grayscales （4k mode） from 64 levels.
（65k mode） or 16 grayscales （4k mode） from 32 levels.
（4k mode） from 16 levels.
（65k mode） or 16 grayscales （4k mode） from 128 levels.
Using PWM control (PWMM[1:0]) and Frame rate control(FRC), the following display mode can be selected.
MODED
Display Mode
FRC control
65,536 color
mode
4,096 color
mode
0
1
2 scan
unavailable
PWM control
32 grayscales 16 grayscales
base
base
32grayscales
Forbidden
selectable
16 grayscales 16 grayscales
selectable
selectable
64 grayscales
base
32 grayscales
selectable
16 grayscales
selectable
128 grayscales
base
32 grayscales
selectable
16 grayscales
selectable
The relationship among the oscillating circuit, built-in clock and frame frequency
Original source clock
OSCI,OSC2,OSC3,OSC4,OSC5(external) selection
Internal oscillator resistor selection(0.7~1.3xR)
CRF,CRS[1:0]
register
CRB[2:0] register
GCK(Source clock for grayscale signal) signal generator
Frequency dividing ratio selection (1/1~1/8) MDIV[2:0] register
GCK
LP(Latch Pulse) signal generator
Decided by dividing rate(1/127,63,31,15)
PWMM[1:0], MODED
BCKG
BCKG LP
Selection
one
Duty set
Decided by VPC or (PPC1+PPC2)
or (PPC1+PPC2+PPC3) : 1/2~1/132
LP
VPC,PPC1,PPC2,PPC3
Vertical blanking line set
Number of inserted LP pulse(0~15)
FVC[3:0]
FLM
Source clock for DCDC booster
Booster clock making BCK[3:0]
Booster clock
FVC[3:0]
BLANK
CKCONT
OSC
CRB[2:0]
MDIV
MDIV[2:0]
1/127,63,31,15
PWMM[1:0]
1/duty
+
FLM
VPC,
PPC1,PPC2,PPC3
LP
CRF
CRS[1:0]
GCK
0
BCK
0
1/8
1
BCKG
BCKG 1
booster
clock
BCK[3:0]
BCKS
BCKS
Fig 17 Block Diagram of Oscillator
Frame Duty = 1 / (duty + blank)
Ver.2004-06-29
- 57 -
NJU6854
PWM duty vs. display mode
Display mode
MODED
65,536 color mode
4,096 color mode
0
1
PWMM=00
variable
1/63
1/63
PWM control
PWMM=01
PWMM=10
variable
fixed
1/31
Forbidden
1/31
1/15
PWMM=11
variable
1/127
1/127
Frame frequency vs. display mode
Usage Oscillator
GCK
Display
mode
Grayscale mode
( PWMM[1:0] )
Duty
Blank
Equation
*1)
0
FLM=1200kHz/(1x127x(132+ 0))=72Hz
1/1
Among
65,536 color Variable
1/132
undivided
128
5
FLM=1200kHz/(1x127x(132+ 5))=69Hz
0
FLM=285kHz/(1x31x(132+ 0))=70Hz
1/1
Among
2
285 kHz
4,096 color Variable
1/132
undivided
32
10
FLM=285kHz/(1x31x(132+10))=65Hz
0
FLM=170kHz/(1x15x(132+ 0))=86Hz
1/1
Among
3
170 kHz
4,096 color
Fixed
1/132
undivided
32
15
FLM=170kHz/(1x15x(132+15))=77Hz
0
FLM=730kHz/(1x63x(132+ 0))=88Hz
1/1
Among
4
730 kHz
65,536 color Variable
1/132
undivided
64
8
FLM=730kHz/(1x63x(132+ 8))=83Hz
NOTE): FLM: frame frequency = fOSC / (MDIV(1,2,3,4,5,6,7,8) x PWMM(15,31,63,127) x (Duty + Blank))
1
- 58 -
1200 kHz
Ver.2004-06-29
NJU6854
65k Colors Display Mode
Display data and grayscale palette.
A4
B5
C4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A3
B4
C3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Display RAM data
A2
A1
B3
B2
C2
C1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
A0
B1
C0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A/C
32 gray
GS=X
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
Grayscale by PWM + FRC
B
64 gray (1)
GS=1
PB0
PB0
( PB0 + PB1 ) / 2
PB1
( PB1 + PB2 ) / 2
PB2
( PB2 + PB3 ) / 2
PB3
( PB3 + PB4 ) / 2
PB4
( PB4 + PB5 ) / 2
PB5
( PB5 + PB6 ) / 2
PB6
( PB6 + PB7 ) / 2
PB7
( PB7 + PB8 ) / 2
PB8
( PB8 + PB9 ) / 2
PB9
( PB9 + PB10 ) / 2
PB10
( PB10 + PB11 ) / 2
PB11
( PB11 + PB12 ) / 2
PB12
( PB12 + PB13 ) / 2
PB13
( PB13 + PB14 ) / 2
PB14
( PB14 + PB15 ) / 2
PB15
( PB15 + PB16 ) / 2
PB16
( PB16 + PB17 ) / 2
PB17
( PB17 + PB18 ) / 2
PB18
( PB18 + PB19 ) / 2
PB19
( PB19 + PB20 ) / 2
PB20
( PB20 + PB21 ) / 2
PB21
( PB21 + PB22 ) / 2
PB22
( PB22 + PB23 ) / 2
PB23
( PB23 + PB24 ) / 2
PB24
( PB24 + PB25 ) / 2
PB25
( PB25 + PB26 ) / 2
PB26
( PB26 + PB27 ) / 2
PB27
( PB27 + PB28 ) / 2
PB28
( PB28 + PB29 ) / 2
PB29
( PB29 + PB30 ) / 2
PB30
( PB30 + PB31 ) / 2
PB31
GS=0
PB0
PBX
( PB0 + PB1 ) / 2
PB1
( PB1 + PB2 ) / 2
PB2
( PB2 + PB3 ) / 2
PB3
( PB3 + PB4 ) / 2
PB4
( PB4 + PB5 ) / 2
PB5
( PB5 + PB6 ) / 2
PB6
( PB6 + PB7 ) / 2
PB7
( PB7 + PB8 ) / 2
PB8
( PB8 + PB9 ) / 2
PB9
( PB9 + PB10 ) / 2
PB10
( PB10 + PB11 ) / 2
PB11
( PB11 + PB12 ) / 2
PB12
( PB12 + PB13 ) / 2
PB13
( PB13 + PB14 ) / 2
PB14
( PB14 + PB15 ) / 2
PB15
( PB15 + PB16 ) / 2
PB16
( PB16 + PB17 ) / 2
PB17
( PB17 + PB18 ) / 2
PB18
( PB18 + PB19 ) / 2
PB19
( PB19 + PB20 ) / 2
PB20
( PB20 + PB21 ) / 2
PB21
( PB21 + PB22 ) / 2
PB22
( PB22 + PB23 ) / 2
PB23
( PB23 + PB24 ) / 2
PB24
( PB24 + PB25 ) / 2
PB25
( PB25 + PB26 ) / 2
PB26
( PB26 + PB27 ) / 2
PB27
( PB27 + PB28 ) / 2
PB28
( PB28 + PB29 ) / 2
PB29
( PB29 + PB30 ) / 2
PB30
( PB30 + PB31 ) / 2
PB31
C/A
32 gray
GS=X
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
Note1) 5 bits for PWM control and 1 bit for Frame rate control(total 6 bits display data), SEGBi can realize 64-grayscale
(32-grayscalex2) display.
Note2) Real 64-grayscael can be realized by setting PBX bit(GS=”0”).
Ver.2004-06-29
- 59 -
NJU6854
4k Colors Display Mode
Display data and grayscale palette.
Display RAM data
A3
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
A/C
16 gray
GS=X
PA1
PA3
PA5
PA7
PA9
PA11
PA13
PA15
PA17
PA19
PA21
PA23
PA25
PA27
PA29
PA31
Grayscale by PWM
B
16 gray
GS=X
PB1
PB3
PB5
PB7
PB9
PB11
PB13
PB15
PB17
PB19
PB21
PB23
PB25
PB27
PB29
PB31
C/A
16 gray
GS=X
PC1
PC3
PC5
PC7
PC9
PC11
PC13
PC15
PC17
PC19
PC21
PC23
PC25
PC27
PC29
PC31
Note) Under 4k colors display mode, GS bit is invalid.
(12-12) Oscillating Frequency Adjustment/Frequency Dividing
Register : MDIV TABLE0 [9H]
D7
*
D6
D5
MDIV2 MDIV1
D4
MDIV0
D3
*
D2
CRB2
D1
CRB1
D0
CRB0
CSb
0
RS
1
RDb
1
WRb
0
(default: MDIV[2:0], CRB[2:0] = 0H, address : 9H)
(i) CRB[2:0]
Frame frequency can be modified by adjusting the resistor of oscillating circuit.
Relationship between RF and Resistance ratio
CRB2
0
0
0
0
1
1
1
1
CRB1
0
0
1
1
0
0
1
1
CRB0
0
1
0
1
0
1
0
1
Status
Initial Resistance Ratio
1.1 times of Initial Resistance Ratio
1.2 times of Initial Resistance Ratio
1.3 times of Initial Resistance Ratio
0.9 times of Initial Resistance Ratio
0.8 times of Initial Resistance Ratio
0.7 times of Initial Resistance Ratio
Forbidden
(ii) MDIV[2:0]
Oscillating Frequency or external clock frequency can be divided.
MDIV2
0
0
0
0
1
1
1
1
- 60 -
MDIV1
0
0
1
1
0
0
1
1
MDIV0
0
1
0
1
0
1
0
1
Divide Ratio
1/1 dividing
1/2 dividing
1/3 dividing
1/4 dividing
1/5 dividing
1/6 dividing
1/7 dividing
1/8 dividing
Ver.2004-06-29
NJU6854
(12-13) Header COM
Register : HCT TABLE0 [AH]
D7
*
D6
HCT6
D5
HCT5
D4
HCT4
D3
HCT3
D2
HCT2
D1
HCT1
D0
HCT0
CSb
0
RS
1
RDb
1
WRb
0
(default: HCT [6:0] = 0H, address: AH)
For small panel size(row number is less than 132), this instruction is used to decide Header COM position to
specify available COM drivers. The setting range is from COMA0/COMB0 ~ COMA65/COMB65. Refer to “(13)
Relationship Between Logic COM Number and Physical COM Driver” for details. Note that this instruction is not used
to specify a scan start position, The scan start position is decided by the “Scan Start COM 1~3”.
0 ≤ HCT ≤ (132-VPC)/2
HCT6
0
0
0
0
0
0
HCT5
0
0
0
0
0
0
HCT4
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
0
1
1
1
HCT3
0
0
0
0
0
0
···
1
1
0
0
0
···
1
HCT2
0
0
0
0
1
1
HCT1
0
0
1
1
0
0
HCT0
0
1
0
1
0
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
0
1
1
1
Header COM
COMA0/COMB0
COMA1/COMB1
COMA2/COMB2
COMA3/COMB3
COMA4/COMB4
COMA5/COMB5
···
COMA62/COMB62
COMA63/COMB63
COMA64/COMB64
COMA65/COMB65
Forbidden
···
Forbidden
(12-14) Initial Display Line
Register : HST TABLE0 [BH]
D7
HST7
D6
HST6
D5
HST5
D4
HST4
D3
HST3
D2
HST2
D1
HST1
D0
HST0
CSb
0
RS
1
RDb
1
WRb
0
(default : HST[7:0] = 0H, address: BH)
This instruction sets the DDRAM Y address, and the addressed RAM data will be displayed by the scan start
COM 1 driver. The available Y address range is from 0~131.
HST7
0
0
0
0
0
0
HST6
0
0
0
0
0
0
HST5
0
0
0
0
0
0
HST4
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
1
1
HST3
0
0
0
0
0
0
HST2
0
0
0
0
1
1
HST1
0
0
1
1
0
0
HST0
0
1
0
1
0
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
1
1
···
···
Ver.2004-06-29
Y address
0
1
2
3
4
5
:
128
129
130
131
Forbidden
···
Forbidden
- 61 -
NJU6854
(12-15) Scan Start COM 1
Register : SSC1 TABLE0 [CH]
D7
D6
D5
D4
D3
SSC17 SSC16 SSC15 SSC14 SSC13
D2
D1
SSC12 SSC11
D0
SSC10
CSb
0
RS
1
RDb
1
WRb
0
(default : SSC1[7:0] = 0H, address: CH)
Totally three partial area can be display on the screen once time. This instruction sets the logical number of the scan
start COM driver for the full screen display or for the first partial display. Refer to (13) Relationship between logical
COM number and physical COM driver for details. The available setting range is: 0 ≤ SSC1 ≤ (VPC – 1)
(12-16) Scan Start COM 2
Register : SSC2 TABLE0 [DH]
D7
D6
D5
D4
D3
SSC27 SSC26 SSC25 SSC24 SSC23
D2
D1
SSC22 SSC21
D0
SSC20
CSb
0
RS
1
RDb
1
WRb
0
(default : SSC2[7:0] = 0H, address: DH)
This instruction sets the logical number of the scan start COM driver for the second partial display. Refer to (13)
Relationship between logical COM number and physical COM driver for details. The available setting range is:
SSC1+PCC1 ≤ SSC2 ≤ (VPC – 1)
(12-17) Line Number of Partial Display 1
Register : PCC1 TABLE0 [EH]
D7
D6
D5
D4
D3
D2
D1
D0
PCC17 PCC16 PCC15 PCC14 PCC13 PCC12 PCC11 PCC10
CSb
0
RS
1
RDb
1
WRb
0
(default : PCC1[7:0] = 0H, address: EH)
This instruction sets line number(DDRAM Y address range) for the first partial display. In the partial display mode,
this instruction has priority over the Display Line Number(VPC) setting. PCC1+PCC2+PCC3 will be the display duty.
The available setting range is: 0 ≤ PCC1 ≤ (VPC - SSC1)
(12-18) Line Number of Partial Display 2
Register : PCC2 TABLE0 [FH]
D7
D6
D5
D4
D3
D2
D1
D0
PCC27 PCC26 PCC25 PCC24 PCC23 PCC22 PCC21 PCC20
CSb
0
RS
1
RDb
1
WRb
0
(default : PCC2[7:0] = 0H, address: FH)
This instruction sets line number(DDRAM Y address range) for the second partial display. In the partial display
mode, this instruction has priority over the Display Line Number(VPC) setting. PCC1+PCC2+PCC3 will be the display
duty. The available setting range is: 0 ≤ PCC2 ≤ (VPC – SSC2).
(12-19) N-Line Inversion
Register : MC TABLE1 [0H]
D7
MC7
D6
MC6
D5
MC5
D4
MC4
D3
MC3
D2
MC2
D1
MC1
D0
MC0
CSb
0
RS
1
RDb
1
WRb
0
(default : MC[7:0] = 0H, address: 0H)
This instruction can let LCD driving signal polarity (M signal) to be alternated every N(2=<N<=132) lines. Under
default setting( MC[7:0]=0H), driving signal polarity alternates every frame.
MC7
0
0
0
0
:
1
:
1
- 62 -
MC6
0
0
0
0
:
0
:
0
MC5
0
0
0
0
:
0
:
1
MC4
0
0
0
0
:
0
:
1
MC3
0
0
0
0
:
0
:
0
MC2
0
0
0
0
:
0
:
0
MC1
0
0
1
1
:
1
:
0
MC0
0
1
0
1
:
1
:
0
Function
Frame inversion (Default State)
2 line inversion
3 line inversion
4 line Inversion
:
132 Line Inversion
prohibited
prohibited.
Ver.2004-06-29
NJU6854
(i) Frame Inversion (1/132 DUTY)
1st line
2nd line 3rd line
131st line132nd line 1st line
LP
FLM
M
(ii) N Line Inversion
nth line cycle
1 st line
2nd line
3rd line
n-1th line
nth line
1 st line
LP
FLM
M
(12-20) Power Control 1
Register : TCBI TABLE1 [1H]
D7
D6
VGOFF VBON
D5
TCV1
D4
TCV0
D3
*
D2
B2
D1
B1
D0
B0
CSb
0
RS
1
RDb
1
WRb
0
(default: VGOFF, VBON, TCV[1:0] = 0H, B[2:0] = 4H, address: 1H)
(i)VGOFF
Voltage Regulator (VREG output) ON/OFF
VG OFF = 0: AMPON=”1”, Voltage Regulator ON
VG OFF = 1:
Voltage Regulator OFF
(ii)VBON
Reference Voltage Generator (VBA output) ON/OFF
VBON = 0: Reference Voltage Circuit OFF
VBON = 1: AMPON=”1” & VGOFF=”0“, Reference Voltage Circuit ON
(iii)TCV[1:0]
Setting temperature compensation coefficient for Reference Voltage Circuit.
TCV[1]
TCV[0]
VBA output
remark
0
0
Default setting
0.0 % /°C
0
1
- 0.13 % /°C
1
0
- 0.20 % /°C
1
1
- 0.24 % /°C
Ver.2004-06-29
- 63 -
NJU6854
(iv) B[2:0] LCD Bias Ratio
B2
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
Function
1/5 Bias
1/6 Bias
1/7 Bias
1/8 Bias
1/9 Bias (Initial state)
1/10 Bias
1/11 Bias
1/12 Bias
(12-21) Electronic Volume Control
Register: EVOL TABLE1 [2H]
D7
*
D6
D5
D4
D3
D2
D1
D0
EVOL6 EVOL5 EVOL4 EVOL3 EVOL2 EVOL1 EVOL0
CSb
0
RS
1
RDb
1
WRb
0
RDb
1
WRb
0
(default: EVOL[6:0] = 0H, address: 2H)
128 steps available
EVOL6
0
0
EVOL5
0
0
EVOL4
0
0
1
1
1
1
1
1
EVOL3
0
0
···
1
1
EVOL2
0
0
EVOL1
0
0
EVOL0
0
1
1
1
1
1
0
1
Output Voltage
Lower
···
Higher
VREG can be calculated from the equation (1)
VREG = VREF x N ..............................................................................................................(1)
(N determined by VU[2:0](boost level), RG[2:0] and GSEL bits of GVU register)
LCD driving voltage V0 can be calculated from the equation (2)
V0 = 0.5 x VREG + M x (VREG – 0.5 VREG) / 127 ………………......…… …………….(2)
(electronic volume M determined by EVOL[6:0] bits of EVOL register)
(12-22) Display Timing Signal Monitor/PBX Palette
Register : PBX TABLE1 [3H]
D7
MON
D6
*
D5
*
D4
GS
D3
PBX3
D2
PBX2
D1
PBX1
D0
PBX0
CSb
0
RS
1
(default: MON, GS = 0H, PBX[3:0] = 3H, address: 3H)
(i) MON
Setting FLM, LP and M signals output ON/OFF
MON
0
1
Function
FLM, LP, M signal output OFF（default）
FLM, LP, M signal output ON
(ii) GS, PBX[3:0]
When GS=”0”, palette PBX setting is available. When GS=”1”, PB0 is selected.
GS=1
PBX[3:0] register invalid
(Note 1)
GS=0
0
0
0
PBX3
PBX2
PBX1
PBX0
Note 1) Under 65k colors mode , palette PBX is selected to set B data. PBX is used to display the grayscale between PB0
and PB1.
- 64 -
Ver.2004-06-29
NJU6854
(12-23) Power Control 2
Register : POW2 TABLE1 [5H]
D7
*
D6
*
D5
*
D4
D3
CKCONT AMPON
D2
HALT
D1
DCON
D0
RES
CSb
0
RS
1
RDb
1
WRb
0
(default: CKCONT, AMPON, HALT, DCON, RES = 0H, address: 5H)
(i) RES
RES = “0”: Default
RES = “1”: Initialization
Note 1) After initialization(RES=”1”), RES bit turn to “0”.
Note 2) After initialization, at least two LP signal cycles is needed to wait to execute the next instruction.
(ii) DCON
Setting voltage booster ON/OFF.
DCON= “0”: voltage booster OFF
DCON= “1”: voltage booster ON
(iii) HALT
Setting power save mode ON/OFF
HALT = “0”: power save mode OFF(default)
HALT = “1”: power save mode ON
LSI Internal status under power save mode:
a. Internal oscillator and LCD power supply is in the halted state.
b. COM/SEG outputs VSSH level voltage.
c. External clock is unacceptable.
d. DDRAM data is remained
e. Instruction Register data is remained
(iv) AMPON
Using together with VGOFF and VBON bits of Power control 1register (TCBI) to set voltage converter ON/OFF.
AMPON = “0” voltage converter OFF
AMPON = “1”: voltage converter ON
(v) CKCONT
Setting GCK signal and LP signal ON/OFF
CKCONT = “0”: GCK and LP OFF
CKCONT = “1”: GCK and LP ON
Note) NJU6854 use internal oscillator or external clock signal to generate GCK and LP signal. Not only used as display
clock, GCK and LP are also used as operating clock for voltage booster. Be sure to set CKCONT=”1” when voltage
booster is used(DCON= “1”).
Ver.2004-06-29
- 65 -
NJU6854
(12-24) Booster Level/Amplifier Gain
Register : GVU TABLE1 [6H]
D7
GSEL
D6
RG2
D5
RG1
D4
RG0
D3
*
D2
VU2
D1
VU1
D0
VU0
CSb
0
RS
1
RDb
1
WRb
0
(default: GSEL, RG[2:0] = 0H, VU[2:0] = 0H, address: 6H)
(i) GSEL
Setting amplifier gain of VREG
GSEL = 0: Amplifier gain is determined by VU[2:0] bits as the same as the boost level.
GSEL = 1: Amplifier gain is determined by RG[2:0] bits
(ii)RG[2:0]
When GSEL=”1”, the relationship between RG[2:0] and amplifier gain is showed as below.
VU2
0
0
0
0
1
1
GSEL = ‘0’
VU1
0
0
1
1
0
0
VU0
0
1
0
1
0
1
1
1
1
1
0
1
RG2
GSEL = ‘1’
RG1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
RG0
Amplifier gain (N)
Remark
2
3
4
5
6
6.45
7
7.3
8.0
-
default VU[2:0]
0
1
0
1
0
1
0
1
default RG[2:0]
(iii) VU[2:0]
Setting boost level. And when GSEL=”0”, also setting amplifier gain of VREG.
VU2
0
0
0
0
1
1
1
1
- 66 -
VU1
0
0
1
1
0
0
1
1
VU0
0
1
0
1
0
1
0
1
Function
No Boost Up
2 Times Boost Up
3 Times Boost Up
4 Times Boost Up
5 Times Boost Up
6 Times Boost Up
Forbidden
Forbidden
Ver.2004-06-29
NJU6854
(12-25) Voltage Booster Clock
Register : BCK TABLE1 [7H]
D7
BCKS
D6
BCKG
D5
*
D4
*
D3
BCK3
D2
BCK2
D1
BCK1
D0
BCK0
CSb
0
RS
1
RDb
1
WRb
0
(default: BCKS, BCKG, BCK[3:0] = 0H, address: 7H)
Note) NJU6854 use internal oscillator or external clock to generate GCK and LP signal. Not only used as display clock,
GCK and LP are also used as operating clock for voltage booster. Be sure to set CKCONT=”1” when voltage booster is
used(DCON= “1”).
(i) BCK[3:0]
Setting dividing ratio for the oscillating signal or external clock to generate GCK and LP.
BCK3
0
0
0
0
0
···
1
1
1
1
1
BCK2
0
0
0
0
1
BCK1
0
0
1
1
0
BCK0
0
1
0
1
0
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
Function
1/1 Dividing (There is a restriction)
1/2 Dividing
1/3 Dividing
1/4 Dividing
1/5 Dividing
···
1/12 Dividing
1/13 Dividing
1/14 Dividing
1/15 Dividing
1/16 Dividing
Note) When BCK[3:0]=[0000, MDIV[2:0]=[000] and BCKS=”1” settings are prohibited.
(ii) BCKG
When BCKG=”1”, MDIV output signal is equally divided into 8 time slots.
(iii) BCKS
Selecting divided clock signal.
BCKS = “0” : LP signal
BCKS = “1” : BCKG signal
Note) There is a trade-off relationship between voltage booster driving capability and current consumption, so the optimal
booster clock shall be decided by your LCD module.
Ver.2004-06-29
- 67 -
NJU6854
(12-26) Display Control
Register : Display TABLE1 [8H]
D7
REF
D6
SWAP
D5
*
D4
D3
SHIFT1 SHIFT0
D2
TBC
D1
TEN
D0
ON/OFF
CSb
0
RS
1
RDb
1
WRb
0
(default: REF, SWAP, SHIFT[1:0], TBC, TEN, ON/OFF = 0H, address: 8H)
(i) ON/OFF
Display Control ON/OFF
ON/OFF = “0”: Display OFF
ON/OFF = “1”: Display ON
(ii) TEN
TEN = “0”: Normal
TEN = “1”: Independent from DDRAM data, pixels are forced to be ON or OFF.
(iii) TBC(TEN = “1”)
TBC = “0” : All pixels ON
TBC = “1” : All pixels OFF
(iv) SHIFT[1:0]
Setting the shift direction of the COM drivers’ output.
(v) SWAP
Switching corresponding relationship between DDRAM data and palette A, B, C. This bit shall be set before
DDRAM data writing.
SWAP = “0”: Normal
SWAP = “1”: SWAP
(vi) REF
Reversing the shift direction of SEG drivers’ output by redirecting X address. This bit shall be set before DDRAM
data writing.
REF = “0”: Normal
REF = “1”: Opposite Direction
- 68 -
Ver.2004-06-29
NJU6854
(12-27) PWM Control
Register : PWM TABLE1 [9H]
D7
*
D6
*
D5
D4
D3
D2
D1
D0
PWMC1 PWMC0 PWMB1 PWMB0 PWMA1 PWMA0
CSb
0
RS
1
RDb
1
WRb
0
(default: PWMC[1:0], PWMB[1:0],PWMA[1:0] = 0H, address: 9H)
(i) PWMC[1:0], PWMB[1:0], PWMA[1:0]
Setting PWM signals for SEGA, SEGB, and SEGC respectively.
SEGAi (i=0~131)
PWMA1
0
0
1
1
PWMA0
0
1
0
1
Output Timing
Forward PWM
Backward PWM
Forward and Backward alternately
Shift Phase
PWMB0
0
1
0
1
Output Timing
Forward PWM
Backward PWM
Forward and Backward alternately
Shift Phase
PWMC0
0
1
0
1
Output Timing
Forward PWM
Backward PWM
Forward and Backward alternately
Shift Phase
SEGBi (i=0~131)
PWMB1
0
0
1
1
SEGCi (i=0~131)
PWMC1
0
0
1
1
LP
forward
backward
forward and
backward
alternatively
shift phase
M
Ver.2004-06-29
- 69 -
NJU6854
(12-28) Three Partial Display Areas/ LED Driver Control/REV Bit
Register : ECONT TABLE1 [AH]
D7
D6
D5
TST0 EN3PTL ENLED
D4
REV
D3
LED13
D2
D1
LED12 LED11
D0
LED10
CSb
0
RS
1
RDb
1
WRb
0
(default: TST0, EN3PTL, ENLED, REV, LED1[3:0] = 0H, address: AH)
(i) TST0
For maker testing, usually set to ”0”.
(ii) EN3PTL
When EN3PTL=”1”, three specified partial areas can be displayed through setting SSC1[7:0]~SSC3[7:0] and
PCC1[7:0]~PCC3[7:0]. If setting EN3PTL=”0”, one or two partial area can be displayed.
(iii) ENLED
When ENLED=”1”, data saved at LED1[3:0] can be used to control white LED through control port(LDAT, LSCK,
LREQ, LRESB)
ENLED = 0 : LDAT, LSCK, LREQ, LRESB ports invalid (high impedance)
ENLED = 1 : LDAT, LSCK, LREQ, LRESB ports valid.
(iv) LED1 [3:0]
When ENLED=”1”, white LED control ports (LDAT, LSCK, LREQ, LRESB) are valid, LED control signal output
from LDAT, LSCK, LREQ and LRESB to LED10, LED11, LED12 and LED13 respectively.
Concerning white LED driver, please refer to NJRC white LED controller series (NJU6051/52/53). Besides, the
above mentioned bits and ports can be used as general-purpose ports too.
Note) For NJRC white LED driver, data pin state will be changed according to request pin. When request pin is “L”, data
pin of white LED driver is in input state, and when request pin is “H”, data pin become output state. when LREQ pin of
NJU6854 is “L”, LDAT pin output signals, and when LREQ is “H”, LDAT is in input state. So, if LDAT, LSCK, LREQ and
LRESB are used as common ports, please pay attention to this point. LSCK, LREQ and LRESB pins can be used as 3-bit
general-purpose ports too.
Example of connection with NJU6053
RSTb
LRESB
REQ
LREQ
SCK
LSCK
DATA
LDAT
NJU6053
NJU6854
Timing Sequence of data sending
LRESb
LREQ
LSCK
LDAT
- 70 -
B7
B6
B5
B1
B0
Ver.2004-06-29
NJU6854
Timing Sequence of data receiving
LRESb
LREQ
LSCK
LDAT
B7
B6
B5
B1
B0
Follow Chart of NJU6053 Operation
Initialization of NJU6053
(LRESB=L->H)
“0”-> LED13
or “1” ->LED13
Data Receiving Request Active
(LREQ=H)
“1” -> LED12
Data Sending Request Active (LREQ=L)
“0”-> LED12
Data Setting(LDAT=DATA(7))
Data(7th bit) -> LED10
Clock Setting(LSCK=L->H)
“0” ->LED11
Or “1” -> LED11
DATA 6 ~ 1 sent
under the same way
Clock Setting (LSCK=L->H)
“0” -> LED11
or “1” -> LED11
Cycle 8
times
Data
sending
Data
Receiving
Clock Setting (LSCK=L->H)
“0” -> LED11
Or “1” -> LED11
Data Setting (LDAT=DATA(0))
data(0 bit) -> LED10
Clock Setting (LSCK=L->H)
“0” -> LED11
Or “1” -> LED11
EDATA Read
In instruction data read,
EDATA is read out
(v) REV
Without changing data in DDRAM, pixel display state can be inverted
REV = “0”: data=”1” pixel ON (Normal)
REV = “1”: data=”0” pixel ON (Reversed)
Ver.2004-06-29
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NJU6854
(12-29) Discharge ON/OFF
Register : DIS TABLE1 [BH]
D7
*
D6
*
D5
*
D4
*
D3
*
D2
*
D1
DIS2
D0
DIS1
CSb
0
RS
1
RDb
1
WRb
0
(default: DIS[2:1] = 0H, address: BH)
(i) DIS1
If DIS1=”1”, the capacitors connected to V0~V4 pins discharge.
DIS1 = “0”: Discharge OFF
DIS1 = “1”: Discharge ON
(ii) DIS2
If DIS2=”1”, the capacitor connected to VOUT pin discharge
DIS2 = “0”: discharge OFF
DIS2 = “1”: discharge ON
Vout
V0
V1
V2
V3
V4
100k(typ)
5M(typ)
DIS1
DIS2
VEE
V SSH
(12-30) LED Driver Data
Register : EDATA TABLE1 [CH]
D7
D6
LED27 LED26
D5
D4
D3
LED25 LED24 LED23
D2
D1
LED22 LED21
D0
LED20
CSb
0
RS
1
RDb
1
WRb
0
RS
1
RDb
1
WRb
0
(default: LED2[7:0] = 0H, address: CH)
(i)LED2[7:0]
Data from NJRC white LED driver(NJU6051/52/53) is saved in this register.
(12-31) Instruction Table/Address
Register : RA TABLE1 [DH]
D7
RSS
D6
RA6
D5
RA5
D4
RA4
D3
RA3
D2
RA2
D1
RA1
D0
RA0
CSb
0
(default: RA[6:0] = 0H, address: DH)
RA[6:4] : Instruction table selection
RA6
0
0
0
0
1
1
1
1
- 72 -
RA5
0
0
1
1
0
0
1
1
RA4
0
1
0
1
0
1
0
1
Table indicator
0
1
2
3
4
5
6
7
Ver.2004-06-29
NJU6854
RA[3:0] :Register address selection during direct access, or increment number selection in auto increment mode.
RA3
RA2
RA1
RA0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
···
Direct access
(address selection)
0H
1H
2H
3H
4H
5H
6H
7H
···
BH
CH
DH
EH
FH
Auto increment
（setting increment number）
1
2
3
4
5
6
7
8
···
12
13
14
15
0
RSS: RSS = “1”: increment number in auto increment mode.
RSS = “0”: register address selection for direct access
(12-32) Scan Start COM 3
Register : SSC3 TABLE1 [EH]
D7
D6
D5
D4
D3
SSC37 SSC36 SSC35 SSC34 SSC33
D2
D1
SSC32 SSC31
D0
SSC30
CSb
0
RS
1
RDb
1
WRb
0
(default: SSC3[7:0] = 0H, address: EH)
This instruction sets the logical number of the scan start COM driver for the third partial display, and the setting
method just as of the Scan Start COM 1 or 2. This instruction can not be used with normal display and single partial
display. When EN3PTL = “1”, the setting is valid.
Range: SSC2 + PCC2 ≤ SSC3 ≤ (VPC – 1)
(12-33) Line Number of Partial Display 3
Register : PCC3 TABLE1 [FH]
D7
D6
D5
D4
D3
D2
D1
D0
PCC37 PCC36 PCC35 PCC34 PCC33 PCC32 PCC31 PCC30
CSb
0
RS
1
RDb
1
WRb
0
(default: PCC3[7:0] = 0H, address: FH)
This instruction set line number(DDRAM Y address range) for the third partial display area. In the partial display
mode, this instruction has priority over the Display Line Number(VPC) setting. PCC1+PCC2+PCC3 will be the display
duty. When EN3PTL = “1”, the setting is valid
Range: 0 ≤ PCC3 ≤ (VPC – SSC3)
Ver.2004-06-29
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NJU6854
(12-34) Grayscale Palette (PA0~PA31, PB0~PB31, PC0~PC31)
Register : PA0 TABLE2 [0H]
D7
*
D6
PA06
D5
PA05
D4
PA04
D3
PA03
D2
PA02
D1
PA01
D0
PA00
CSb
0
RS
1
RDb
1
WRb
0
D0
PA10
CSb
0
RS
1
RDb
1
WRb
0
D0
PA20
CSb
0
RS
1
RDb
1
WRb
0
D0
PA30
CSb
0
RS
1
RDb
1
WRb
0
D0
PA40
CSb
0
RS
1
RDb
1
WRb
0
D0
PA50
CSb
0
RS
1
RDb
1
WRb
0
D0
PA60
CSb
0
RS
1
RDb
1
WRb
0
D0
PA70
CSb
0
RS
1
RDb
1
WRb
0
D0
PA80
CSb
0
RS
1
RDb
1
WRb
0
D0
PA90
CSb
0
RS
1
RDb
1
WRb
0
D0
PA100
CSb
0
RS
1
RDb
1
WRb
0
(Initialization: PA0[6:0] = 0H, Register Address: 0H)
Register : PA1 TABLE2 [1H]
D7
*
D6
PA16
D5
PA15
D4
PA14
D3
PA13
D2
PA12
D1
PA11
(Initialization: PA1[6:0] = 6H, Register Address: 1H)
Register : PA2 TABLE2 [2H]
D7
*
D6
PA26
D5
PA25
D4
PA24
D3
PA23
D2
PA22
D1
PA21
(Initialization: PA2[6:0] = AH, Register Address: 2H)
Register : PA3 TABLE2 [3H]
D7
*
D6
PA36
D5
PA35
D4
PA34
D3
PA33
D2
PA32
D1
PA31
(Initialization: PA3[6:0] = EH, Register Address: 3H)
Register : PA4 TABLE2 [4H]
D7
*
D6
PA46
D5
PA45
D4
PA44
D3
PA43
D2
PA42
D1
PA41
(Initialization: PA4[6:0] = 12H, Register Address: 4H)
Register : PA5 TABLE2 [5H]
D7
*
D6
PA56
D5
PA55
D4
PA54
D3
PA53
D2
PA52
D1
PA51
(Initialization: PA5[6:0] = 16H, Register Address: 5H)
Register : PA6 TABLE2 [6H]
D7
*
D6
PA66
D5
PA65
D4
PA64
D3
PA63
D2
PA62
D1
PA61
(Initialization: PA6[6:0] = 1AH, Register Address: 6H)
Register : PA7 TABLE2 [7H]
D7
*
D6
PA76
D5
PA75
D4
PA74
D3
PA73
D2
PA72
D1
PA71
(Initialization: PA7[6:0] = 1EH, Register Address: 7H)
Register : PA8 TABLE2 [8H]
D7
*
D6
PA86
D5
PA85
D4
PA84
D3
PA83
D2
PA82
D1
PA81
(Initialization: PA8[6:0] = 22H, Register Address: 8H)
Register : PA9 TABLE2 [9H]
D7
*
D6
PA96
D5
PA95
D4
PA94
D3
PA93
D2
PA92
D1
PA91
(Initialization: PA9[6:0] = 26H, Register Address: 9H)
Register : PA10 TABLE2 [AH]
D7
*
D6
PA106
D5
D4
PA105 PA104
D3
PA103
D2
D1
PA102 PA101
(Initialization: PA10[6:0] = 2AH, Register Address: AH)
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Ver.2004-06-29
NJU6854
Register : PA11 TABLE2 [BH]
D7
*
D6
PA116
D5
PA115
D4
PA114
D3
PA113
D2
PA112
D1
PA111
D0
PA110
CSb
0
RS
1
RDb
1
WRb
0
D0
PA120
CSb
0
RS
1
RDb
1
WRb
0
D0
PA130
CSb
0
RS
1
RDb
1
WRb
0
D0
PA140
CSb
0
RS
1
RDb
1
WRb
0
D0
PA150
CSb
0
RS
1
RDb
1
WRb
0
D0
PA160
CSb
0
RS
1
RDb
1
WRb
0
D0
PA170
CSb
0
RS
1
RDb
1
WRb
0
D0
PA180
CSb
0
RS
1
RDb
1
WRb
0
D0
PA190
CSb
0
RS
1
RDb
1
WRb
0
D0
PA200
CSb
0
RS
1
RDb
1
WRb
0
D0
PA210
CSb
0
RS
1
RDb
1
WRb
0
(Initialization: PA11[6:0] = 2EH, Register Address: BH)
Register : PA12 TABLE2 [CH]
D7
*
D6
PA126
D5
D4
PA125 PA124
D3
PA123
D2
D1
PA122 PA121
(Initialization: PA12[6:0] = 32H, Register Address: CH)
Register : PA13 TABLE2 [DH]
D7
*
D6
PA136
D5
D4
PA135 PA134
D3
PA133
D2
D1
PA132 PA131
(Initialization: PA13[6:0] = 36H, Register Address: DH)
Register : PA14 TABLE2 [EH]
D7
*
D6
PA146
D5
D4
PA145 PA144
D3
PA143
D2
D1
PA142 PA141
(Initialization: PA14[6:0] = 3AH, Register Address: EH)
Register : PA15 TABLE2 [FH]
D7
*
D6
PA156
D5
D4
PA155 PA154
D3
PA153
D2
D1
PA152 PA151
(Initialization: PA15[6:0] = 3EH, Register Address: FH)
Register : PA16 TABLE3 [0H]
D7
*
D6
PA166
D5
D4
PA165 PA164
D3
PA163
D2
D1
PA162 PA161
(Initialization: PA16[6:0] = 42H, Register Address: 0H)
Register : PA17 TABLE3 [1H]
D7
*
D6
PA176
D5
D4
PA175 PA174
D3
PA173
D2
D1
PA172 PA171
(Initialization: PA17[6:0] = 46H, Register Address: 1H)
Register : PA18 TABLE3 [2H]
D7
*
D6
PA186
D5
D4
PA185 PA184
D3
PA183
D2
D1
PA182 PA181
(Initialization: PA18[6:0] = 4AH, Register Address: 2H)
Register : PA19 TABLE3 [3H]
D7
*
D6
PA196
D5
D4
PA195 PA194
D3
PA193
D2
D1
PA192 PA191
(Initialization: PA19[6:0] = 4EH, Register Address: 3H)
Register : PA20 TABLE3 [4H]
D7
*
D6
PA206
D5
D4
PA205 PA204
D3
PA203
D2
D1
PA202 PA201
(Initialization: PA20[6:0] = 52H, Register Address: 4H)
Register : PA21 TABLE3 [5H]
D7
*
D6
PA216
D5
D4
PA215 PA214
D3
PA213
D2
D1
PA212 PA211
(Initialization: PA21[6:0] = 56H, Register Address: 5H)
Ver.2004-06-29
- 75 -
NJU6854
Register : PA22 TABLE3 [6H]
D7
*
D6
PA226
D5
D4
PA225 PA224
D3
PA223
D2
D1
PA222 PA221
D0
PA220
CSb
0
RS
1
RDb
1
WRb
0
D0
PA230
CSb
0
RS
1
RDb
1
WRb
0
D0
PA240
CSb
0
RS
1
RDb
1
WRb
0
D0
PA250
CSb
0
RS
1
RDb
1
WRb
0
D0
PA260
CSb
0
RS
1
RDb
1
WRb
0
D0
PA270
CSb
0
RS
1
RDb
1
WRb
0
D0
PA280
CSb
0
RS
1
RDb
1
WRb
0
D0
PA290
CSb
0
RS
1
RDb
1
WRb
0
D0
PA300
CSb
0
RS
1
RDb
1
WRb
0
D0
PA310
CSb
0
RS
1
RDb
1
WRb
0
D0
PB00
CSb
0
RS
1
RDb
1
WRb
0
(Initialization: PA22[6:0] = 5AH, Register Address: 6H)
Register : PA23 TABLE3 [7H]
D7
*
D6
PA236
D5
D4
PA235 PA234
D3
PA233
D2
D1
PA232 PA231
(Initialization: PA23[6:0] = 5EH, Register Address: 7H)
Register : PA24 TABLE3 [8H]
D7
*
D6
PA246
D5
D4
PA245 PA244
D3
PA243
D2
D1
PA242 PA241
(Initialization: PA24[6:0] = 62H, Register Address: 8H)
Register : PA25 TABLE3 [9H]
D7
*
D6
PA256
D5
D4
PA255 PA254
D3
PA253
D2
D1
PA252 PA251
(Initialization: PA25[6:0] = 66H, Register Address: 9H)
Register : PA26 TABLE3 [AH]
D7
*
D6
PA266
D5
D4
PA265 PA264
D3
PA263
D2
D1
PA262 PA261
(Initialization: PA26[6:0] = 6AH, Register Address: AH)
Register : PA27 TABLE3 [BH]
D7
*
D6
PA276
D5
D4
PA275 PA274
D3
PA273
D2
D1
PA272 PA271
(Initialization: PA27[6:0] = 6EH, Register Address: BH)
Register : PA28 TABLE3 [CH]
D7
*
D6
PA286
D5
D4
PA285 PA284
D3
PA283
D2
D1
PA282 PA281
(Initialization: PA28[6:0] = 72H, Register Address: CH)
Register : PA29 TABLE3 [DH]
D7
*
D6
PA296
D5
D4
PA295 PA294
D3
PA293
D2
D1
PA292 PA291
(Initialization: PA29[6:0] = 76H, Register Address: DH)
Register : PA30 TABLE3 [EH]
D7
*
D6
PA306
D5
D4
PA305 PA304
D3
PA303
D2
D1
PA302 PA301
(Initialization: PA30[6:0] = 7AH, Register Address: EH)
Register : PA31 TABLE3 [FH]
D7
*
D6
PA316
D5
D4
PA315 PA314
D3
PA313
D2
D1
PA312 PA311
(Initialization: PA31[6:0] = 7FH, Register Address: FH)
Register : PB0 TABLE4 [0H]
D7
*
D6
PB06
D5
PB05
D4
PB04
D3
PB03
D2
PB02
D1
PB01
(Initialization: PB0[6:0] = 0H, Register Address: 0H)
- 76 -
Ver.2004-06-29
NJU6854
Register : PB1 TABLE4 [1H]
D7
*
D6
PB16
D5
PB15
D4
PB14
D3
PB13
D2
PB12
D1
PB11
D0
PB10
CSb
0
RS
1
RDb
1
WRb
0
D0
PB20
CSb
0
RS
1
RDb
1
WRb
0
D0
PB30
CSb
0
RS
1
RDb
1
WRb
0
D0
PB40
CSb
0
RS
1
RDb
1
WRb
0
D0
PB50
CSb
0
RS
1
RDb
1
WRb
0
D0
PB60
CSb
0
RS
1
RDb
1
WRb
0
D0
PB70
CSb
0
RS
1
RDb
1
WRb
0
D0
PB80
CSb
0
RS
1
RDb
1
WRb
0
D0
PB90
CSb
0
RS
1
RDb
1
WRb
0
D0
PB100
CSb
0
RS
1
RDb
1
WRb
0
D0
PB110
CSb
0
RS
1
RDb
1
WRb
0
D0
PB120
CSb
0
RS
1
RDb
1
WRb
0
(Initialization: PB1[6:0] = 6H, Register Address: 1H)
Register : PB2 TABLE4 [2H]
D7
*
D6
PB26
D5
PB25
D4
PB24
D3
PB23
D2
PB22
D1
PB21
(Initialization: PB2[6:0] = AH, Register Address: 2H)
Register : PB3 TABLE4 [3H]
D7
*
D6
PB36
D5
PB35
D4
PB34
D3
PB33
D2
PB32
D1
PB31
(Initialization: PB3[6:0] = EH, Register Address: 3H)
Register : PB4 TABLE4 [4H]
D7
*
D6
PB46
D5
PB45
D4
PB44
D3
PB43
D2
PB42
D1
PB41
(Initialization: PB4[6:0] = 12H, Register Address: 4H)
Register : PB5 TABLE4 [5H]
D7
*
D6
PB56
D5
PB55
D4
PB54
D3
PB53
D2
PB52
D1
PB51
(Initialization: PB5[6:0] = 16H, Register Address: 5H)
Register : PB6 TABLE4 [6H]
D7
*
D6
PB66
D5
PB65
D4
PB64
D3
PB63
D2
PB62
D1
PB61
(Initialization: PB6[6:0] = 1AH, Register Address: 6H)
Register : PB7 TABLE4 [7H]
D7
*
D6
PB76
D5
PB75
D4
PB74
D3
PB73
D2
PB72
D1
PB71
(Initialization: PB7[6:0] = 1EH, Register Address: 7H)
Register : PB8 TABLE4 [8H]
D7
*
D6
PB86
D5
PB85
D4
PB84
D3
PB83
D2
PB82
D1
PB81
(Initialization: PB8[6:0] = 22H, Register Address: 8H)
Register : PB9 TABLE4 [9H]
D7
*
D6
PB96
D5
PB95
D4
PB94
D3
PB93
D2
PB92
D1
PB91
(Initialization: PB9[6:0] = 26H, Register Address: 9H)
Register : PB10 TABLE4 [AH]
D7
*
D6
PB106
D5
D4
D3
PB105 PB104 PB103
D2
D1
PB102 PB101
(Initialization: PB10[6:0] = 2AH, Register Address: AH)
Register : PB11 TABLE4 [BH]
D7
*
D6
PB116
D5
D4
PB115 PB114
D3
PB113
D2
D1
PB112 PB111
(Initialization: PB11[6:0] = 2EH, Register Address: BH)
Register : PB12 TABLE4 [CH]
D7
*
D6
PB126
D5
D4
D3
PB125 PB124 PB123
D2
D1
PB122 PB121
(Initialization: PB12[6:0] = 32H, Register Address: CH)
Ver.2004-06-29
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NJU6854
Register : PB13 TABLE4 [DH]
D7
*
D6
PB136
D5
D4
D3
PB135 PB134 PB133
D2
D1
PB132 PB131
D0
PB130
CSb
0
RS
1
RDb
1
WRb
0
D0
PB140
CSb
0
RS
1
RDb
1
WRb
0
D0
PB150
CSb
0
RS
1
RDb
1
WRb
0
D0
PB160
CSb
0
RS
1
RDb
1
WRb
0
D0
PB170
CSb
0
RS
1
RDb
1
WRb
0
D0
PB180
CSb
0
RS
1
RDb
1
WRb
0
D0
PB190
CSb
0
RS
1
RDb
1
WRb
0
D0
PB200
CSb
0
RS
1
RDb
1
WRb
0
D0
PB210
CSb
0
RS
1
RDb
1
WRb
0
D0
PB220
CSb
0
RS
1
RDb
1
WRb
0
D0
PB230
CSb
0
RS
1
RDb
1
WRb
0
(Initialization: PB13[6:0] = 36H, Register Address: DH)
Register : PB14 TABLE4 [EH]
D7
*
D6
PB146
D5
D4
D3
PB145 PB144 PB143
D2
D1
PB142 PB141
(Initialization: PB14[6:0] = 3AH, Register Address: EH)
Register : PB15 TABLE4 [FH]
D7
*
D6
PB156
D5
D4
D3
PB155 PB154 PB153
D2
D1
PB152 PB151
(Initialization: PB15[6:0] = 3EH, Register Address: FH)
Register : PB16 TABLE5 [0H]
D7
*
D6
PB166
D5
D4
D3
PB165 PB164 PB163
D2
D1
PB162 PB161
(Initialization: PB16[6:0] = 42H, Register Address: 0H)
Register : PB17 TABLE5 [1H]
D7
*
D6
PB176
D5
D4
D3
PB175 PB174 PB173
D2
D1
PB172 PB171
(Initialization: PB17[6:0] = 46H, Register Address: 1H)
Register : PB18 TABLE5 [2H]
D7
*
D6
PB186
D5
D4
D3
PB185 PB184 PB183
D2
D1
PB182 PB181
(Initialization: PB18[6:0] = 4AH, Register Address: 2H)
Register : PB19 TABLE5 [3H]
D7
*
D6
PB196
D5
D4
D3
PB195 PB194 PB193
D2
D1
PB192 PB191
(Initialization: PB19[6:0] = 4EH, Register Address: 3H)
Register : PB20 TABLE5 [4H]
D7
*
D6
PB206
D5
D4
D3
PB205 PB204 PB203
D2
D1
PB202 PB201
(Initialization: PB20[6:0] = 52H, Register Address: 4H)
Register : PB21 TABLE5 [5H]
D7
*
D6
PB216
D5
D4
D3
PB215 PB214 PB213
D2
D1
PB212 PB211
(Initialization: PB21[6:0] = 56H, Register Address: 5H)
Register : PB22 TABLE5 [6H]
D7
*
D6
PB226
D5
D4
D3
PB225 PB224 PB223
D2
D1
PB222 PB221
(Initialization: PB22[6:0] = 5AH, Register Address: 6H)
Register : PB23 TABLE5 [7H]
D7
*
D6
PB236
D5
D4
D3
PB235 PB234 PB233
D2
D1
PB232 PB231
(Initialization: PB23[6:0] = 5EH, Register Address: 7H)
- 78 -
Ver.2004-06-29
NJU6854
Register : PB24 TABLE5 [8H]
D7
*
D6
PB246
D5
D4
D3
PB245 PB244 PB243
D2
D1
PB242 PB241
D0
PB240
CSb
0
RS
1
RDb
1
WRb
0
D0
PB250
CSb
0
RS
1
RDb
1
WRb
0
D0
PB260
CSb
0
RS
1
RDb
1
WRb
0
D0
PB270
CSb
0
RS
1
RDb
1
WRb
0
D0
PB280
CSb
0
RS
1
RDb
1
WRb
0
D0
PB290
CSb
0
RS
1
RDb
1
WRb
0
D0
PB300
CSb
0
RS
1
RDb
1
WRb
0
D0
PB310
CSb
0
RS
1
RDb
1
WRb
0
D0
PC00
CSb
0
RS
1
RDb
1
WRb
0
D0
PC10
CSb
0
RS
1
RDb
1
WRb
0
D0
PC20
CSb
0
RS
1
RDb
1
WRb
0
(Initialization: PB24[6:0] = 62H, Register Address: 8H)
Register : PB25 TABLE5 [9H]
D7
*
D6
PB256
D5
D4
D3
PB255 PB254 PB253
D2
D1
PB252 PB251
(Initialization: PB25[6:0] = 66H, Register Address: 9H)
Register : PB26 TABLE5 [AH]
D7
*
D6
PB266
D5
D4
D3
PB265 PB264 PB263
D2
D1
PB262 PB261
(Initialization: PB26[6:0] = 6AH, Register Address: AH)
Register : PB27 TABLE5 [BH]
D7
*
D6
PB276
D5
D4
D3
PB275 PB274 PB273
D2
D1
PB272 PB271
(Initialization: PB27[6:0] = 6EH, Register Address: BH)
Register : PB28 TABLE5 [CH]
D7
*
D6
PB286
D5
D4
D3
PB285 PB284 PB283
D2
D1
PB282 PB281
(Initialization: PB28[6:0] = 72H, Register Address: CH)
Register : PB29 TABLE5 [DH]
D7
*
D6
PB296
D5
D4
D3
PB295 PB294 PB293
D2
D1
PB292 PB291
(Initialization: PB29[6:0] = 76H, Register Address: DH)
Register : PB30 TABLE5 [EH]
D7
*
D6
PB306
D5
D4
D3
PB305 PB304 PB303
D2
D1
PB302 PB301
(Initialization: PB30[6:0] = 7AH, Register Address: EH)
Register : PB31 TABLE5 [FH]
D7
*
D6
PB316
D5
D4
D3
PB315 PB314 PB313
D2
D1
PB312 PB311
(Initialization: PB31[6:0] = 7FH, Register Address: FH)
Register : PC0 TABLE6 [0H]
D7
*
D6
PC06
D5
PC05
D4
PC04
D3
PC03
D2
PC02
D1
PC01
(Initialization: PC0[6:0] = 0H, Register Address: 0H)
Register : PC1 TABLE6 [1H]
D7
*
D6
PC16
D5
PC15
D4
PC14
D3
PC13
D2
PC12
D1
PC11
(Initialization: PC1[6:0] = 6H, Register Address: 1H)
Register : PC2 TABLE6 [2H]
D7
*
D6
PC26
D5
PC25
D4
PC24
D3
PC23
D2
PC22
D1
PC21
(Initialization: PC2[6:0] = AH, Register Address: 2H)
Ver.2004-06-29
- 79 -
NJU6854
Register : PC3 TABLE6 [3H]
D7
*
D6
PC36
D5
PC35
D4
PC34
D3
PC33
D2
PC32
D1
PC31
D0
PC30
CSb
0
RS
1
RDb
1
WRb
0
D0
PC40
CSb
0
RS
1
RDb
1
WRb
0
D0
PC50
CSb
0
RS
1
RDb
1
WRb
0
D0
PC60
CSb
0
RS
1
RDb
1
WRb
0
D0
PC70
CSb
0
RS
1
RDb
1
WRb
0
D0
PC80
CSb
0
RS
1
RDb
1
WRb
0
D0
PC90
CSb
0
RS
1
RDb
1
WRb
0
D0
PC100
CSb
0
RS
1
RDb
1
WRb
0
D0
PC110
CSb
0
RS
1
RDb
1
WRb
0
D0
PC120
CSb
0
RS
1
RDb
1
WRb
0
D0
PC130
CSb
0
RS
1
RDb
1
WRb
0
D0
PC140
CSb
0
RS
1
RDb
1
WRb
0
(Initialization: PC3[6:0] = EH, Register Address: 3H)
Register : PC4 TABLE6 [4H]
D7
*
D6
PC46
D5
PC45
D4
PC44
D3
PC43
D2
PC42
D1
PC41
(Initialization: PC4[6:0] = 12H, Register Address: 4H)
Register : PC5 TABLE6 [5H]
D7
*
D6
PC56
D5
PC55
D4
PC54
D3
PC53
D2
PC52
D1
PC51
(Initialization: PC5[6:0] = 16H, Register Address: 5H)
Register : PC6 TABLE6 [6H]
D7
*
D6
PC66
D5
PC65
D4
PC64
D3
PC63
D2
PC62
D1
PC61
(Initialization: PC6[6:0] = 1AH, Register Address: 6H)
Register : PC7 TABLE6 [7H]
D7
*
D6
PC76
D5
PC75
D4
PC74
D3
PC73
D2
PC72
D1
PC71
(Initialization: PC7[6:0] = 1EH, Register Address: 7H)
Register : PC8 TABLE6 [8H]
D7
*
D6
PC86
D5
PC85
D4
PC84
D3
PC83
D2
PC82
D1
PC81
(Initialization: PC8[6:0] = 22H, Register Address: 8H)
Register : PC9 TABLE6 [9H]
D7
*
D6
PC96
D5
PC95
D4
PC94
D3
PC93
D2
PC92
D1
PC91
(Initialization: PC9[6:0] = 26H, Register Address: 9H)
Register : PC10 TABLE6 [AH]
D7
*
D6
PC106
D5
D4
D3
PC105 PC104 PC103
D2
D1
PC102 PC101
(Initialization: PC10[6:0] = 2AH, Register Address: AH)
Register : PC11 TABLE6 [BH]
D7
*
D6
PC116
D5
D4
D3
PC115 PC114 PC113
D2
D1
PC112 PC111
(Initialization: PC11[6:0] = 2EH, Register Address: BH)
Register : PC12 TABLE6 [CH]
D7
*
D6
PC126
D5
D4
D3
PC125 PC124 PC123
D2
D1
PC122 PC121
(Initialization: PC12[6:0] = 32H, Register Address: CH)
Register : PC13 TABLE6 [DH]
D7
*
D6
PC136
D5
D4
D3
PC135 PC134 PC133
D2
D1
PC132 PC131
(Initialization: PC13[6:0] = 36H, Register Address: DH)
Register : PC14 TABLE6 [EH]
D7
*
D6
PC146
D5
D4
D3
PC145 PC144 PC143
D2
D1
PC142 PC141
(Initialization: PC14[6:0] = 3AH, Register Address: EH)
- 80 -
Ver.2004-06-29
NJU6854
Register : PC15 TABLE6 [FH]
D7
*
D6
PC156
D5
D4
D3
PC155 PC154 PC153
D2
D1
PC152 PC151
D0
PC150
CSb
0
RS
1
RDb
1
WRb
0
D0
PC160
CSb
0
RS
1
RDb
1
WRb
0
D0
PC170
CSb
0
RS
1
RDb
1
WRb
0
D0
PC180
CSb
0
RS
1
RDb
1
WRb
0
D0
PC190
CSb
0
RS
1
RDb
1
WRb
0
D0
PC200
CSb
0
RS
1
RDb
1
WRb
0
D0
PC210
CSb
0
RS
1
RDb
1
WRb
0
D0
PC220
CSb
0
RS
1
RDb
1
WRb
0
D0
PC230
CSb
0
RS
1
RDb
1
WRb
0
D0
PC240
CSb
0
RS
1
RDb
1
WRb
0
D0
PC250
CSb
0
RS
1
RDb
1
WRb
0
(Initialization: PC15[6:0] = 3EH, Register Address: FH)
Register : PC16 TABLE7 [0H]
D7
*
D6
PC166
D5
D4
D3
PC165 PC164 PC163
D2
D1
PC162 PC161
(Initialization: PC16[6:0] = 42H, Register Address: 0H)
Register : PC17 TABLE7 [1H]
D7
*
D6
PC176
D5
D4
D3
PC175 PC174 PC173
D2
D1
PC172 PC171
(Initialization: PC17[6:0] = 46H, Register Address: 1H)
Register : PC18 TABLE7 [2H]
D7
*
D6
PC186
D5
D4
D3
PC185 PC184 PC183
D2
D1
PC182 PC181
(Initialization: PC18[6:0] = 4AH, Register Address: 2H)
Register : PC19 TABLE7 [3H]
D7
*
D6
PC196
D5
D4
D3
PC195 PC194 PC193
D2
D1
PC192 PC191
(Initialization: PC19[6:0] = 4EH, Register Address: 3H)
Register : PC20 TABLE7 [4H]
D7
*
D6
PC206
D5
D4
D3
PC205 PC204 PC203
D2
D1
PC202 PC201
(Initialization: PC20[6:0] = 52H, Register Address: 4H)
Register : PC21 TABLE7 [5H]
D7
*
D6
PC216
D5
D4
D3
PC215 PC214 PC213
D2
D1
PC212 PC211
(Initialization: PC21[6:0] = 56H, Register Address: 5H)
Register : PC22 TABLE7 [6H]
D7
*
D6
PC226
D5
D4
D3
PC225 PC224 PC223
D2
D1
PC222 PC221
(Initialization: PC22[6:0] = 5AH, Register Address: 6H)
Register : PC23 TABLE7 [7H]
D7
*
D6
PC236
D5
D4
D3
PC235 PC234 PC233
D2
D1
PC232 PC231
(Initialization: PC23[6:0] = 5EH, Register Address: 7H)
Register : PC24 TABLE7 [8H]
D7
*
D6
PC246
D5
D4
D3
PC245 PC244 PC243
D2
D1
PC242 PC241
(Initialization: PC24[6:0] = 62H, Register Address: 8H)
Register : PC25 TABLE7 [9H]
D7
*
D6
PC256
D5
D4
D3
PC255 PC254 PC253
D2
D1
PC252 PC251
(Initialization: PC25[6:0] = 66H, Register Address: 9H)
Ver.2004-06-29
- 81 -
NJU6854
Register : PC26 TABLE7 [AH]
D7
*
D6
PC266
D5
D4
D3
PC265 PC264 PC263
D2
D1
PC262 PC261
D0
PC260
CSb
0
RS
1
RDb
1
WRb
0
D0
PC270
CSb
0
RS
1
RDb
1
WRb
0
D0
PC280
CSb
0
RS
1
RDb
1
WRb
0
D0
PC290
CSb
0
RS
1
RDb
1
WRb
0
D0
PC300
CSb
0
RS
1
RDb
1
WRb
0
D0
PC310
CSb
0
RS
1
RDb
1
WRb
0
(Initialization: PC26[6:0] = 6AH, Register Address: AH)
Register : PC27 TABLE7 [BH]
D7
*
D6
PC276
D5
D4
D3
PC275 PC274 PC273
D2
D1
PC272 PC271
(Initialization: PC27[6:0] = 6EH, Register Address: BH)
Register : PC28 TABLE7 [CH]
D7
*
D6
PC286
D5
D4
D3
PC285 PC284 PC283
D2
D1
PC282 PC281
(Initialization: PC28[6:0] = 72H, Register Address: CH)
Register : PC29 TABLE7 [DH]
D7
*
D6
PC296
D5
D4
D3
PC295 PC294 PC293
D2
D1
PC292 PC291
(Initialization: PC29[6:0] = 76H, Register Address: DH)
Register : PC30 TABLE7 [EH]
D7
*
D6
PC306
D5
D4
D3
PC305 PC304 PC303
D2
D1
PC302 PC301
(Initialization: PC30[6:0] = 7AH, Register Address: EH)
Register : PC31 TABLE8 [FH]
D7
*
D6
PC316
D5
D4
D3
PC315 PC314 PC313
D2
D1
PC312 PC311
(Initialization: PC31[6:0] = 7FH, Register Address: FH)
- 82 -
Ver.2004-06-29
NJU6854
65k-color Mode(32 Grayscale from 128 Levels, PWM1=1, PWM0=1)
[Three groups of palettes Aj, Bj and Cj (j=0~31) are available]
Palette
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
Grayscale level
0/127
1/127
2/127
3/127
4/127
5/127
6/127
7/127
8/127
9/127
10/127
11/127
12/127
13/127
14/127
15/127
16/127
17/127
18/127
19/127
20/127
21/127
22/127
23/127
24/127
25/127
26/127
27/127
28/127
29/127
30/127
31/127
32/127
33/127
34/127
35/127
36/127
37/127
38/127
39/127
40/127
41/127
42/127
43/127
44/127
45/127
46/127
47/127
48/127
49/127
50/127
51/127
52/127
53/127
54/127
55/127
56/127
57/127
58/127
59/127
60/127
61/127
62/127
63/127
Remarks(2)
Palette 0 initial value[6:0]
Palette X initial value [6:0](1)
Palette 1 initial value[6:0]
Palette 2 initial value[6:0]
Palette 3 initial value[6:0]
Palette 4 initial value[6:0]
Palette 5 initial value[6:0]
Palette 6 initial value[6:0]
Palette 7 initial value[6:0]
Palette 8 initial value[6:0]
Palette 9 initial value[6:0]
Palette 10 initial value[6:0]
Palette 11 initial value[6:0]
Palette 12 initial value[6:0]
Palette 13 initial value[6:0]
Palette 14 initial value[6:0]
Palette 15 initial value[6:0]
(marking points are default positions)
Palette
Grayscale level
1000000
64/127
1000001
65/127
1000010
66/127
1000011
67/127
1000100
68/127
1000101
69/127
1000110
70/127
1000111
71/127
1001000
72/127
1001001
73/127
1001010
74/127
1001011
75/127
1001100
76/127
1001101
77/127
1001110
78/127
1001111
79/127
1010000
80/127
1010001
81/127
1010010
82/127
1010011
83/127
1010100
84/127
1010101
85/127
1010110
86/127
1010111
87/127
1011000
88/127
1011001
89/127
1011010
90/127
1011011
91/127
1011100
92/127
1011101
93/127
1011110
94/127
1011111
95/127
1100000
96/127
1100001
97/127
1100010
98/127
1100011
99/127
1100100
100/127
1100101
101/127
1100110
102/127
1100111
103/127
1101000
104/127
1101001
105/127
1101010
106/127
1101011
107/127
1101100
108/127
1101101
109/127
1101110
110/127
1101111
111/127
1110000
112/127
1110001
113/127
1110010
114/127
1110011
115/127
1110100
116/127
1110101
117/127
1110110
118/127
1110111
119/127
1111000
120/127
1111001
121/127
1111010
122/127
1111011
123/127
1111100
124/127
1111101
125/127
1111110
126/127
1111111
127/127
Remarks(2)
Palette 16 initial value[6:0]
Palette 17 initial value[6:0]
Palette 18 initial value[6:0]
Palette 19 initial value[6:0]
Palette 20 initial value[6:0]
Palette 21 initial value[6:0]
Palette 22 initial value[6:0]
Palette 23 initial value[6:0]
Palette 24 initial value[6:0]
Palette 25 initial value[6:0]
Palette 26 initial value[6:0]
Palette 27 initial value[6:0]
Palette 28 initial value[6:0]
Palette 29 initial value[6:0]
Palette 30 initial value[6:0]
Palette 31 initial value[6:0]
Remark 1) PBX[6:0] grayscale palette is enable under GS = ‘0’(defaults) setting.
Remark 2) Please refer to the description of setting range, effective bit and rule for each grayscale palettes
Ver.2004-06-29
- 83 -
NJU6854
65k-color Mode(32 Grayscale from 64 Levels, PWM1=0, PWM0=0)
(marking points are default positions)
[Three groups of palettes Aj, Bj and Cj (j=0~31) are available]
Palette
000000X
000001X
000010X
000011X
000100X
000101X
000110X
000111X
001000X
001001X
001010X
001011X
001100X
001101X
001110X
001111X
010000X
010001X
010010X
010011X
010100X
010101X
010110X
010111X
011000X
011001X
011010X
011011X
011100X
011101X
011110X
011111X
Grayscale level
0/63
1/63
2/63
3/63
4/63
5/63
6/63
7/63
8/63
9/63
10/63
11/63
12/63
13/63
14/63
15/63
16/63
17/63
18/63
19/63
20/63
21/63
22/63
23/63
24/63
25/63
26/63
27/63
28/63
29/63
30/63
31/63
Remarks
Palette 0 initial value[6:1]
Palette X initial value[6:1]
Palette 1 initial value[6:1]
Palette 2 initial value[6:1]
Palette 3 initial value[6:1]
Palette 4 initial value[6:1]
Palette 5 initial value[6:1]
Palette 6 initial value[6:1]
Palette 7 initial value[6:1]
Palette 8 initial value[6:1]
Palette 9 initial value[6:1]
Palette 10 initial value[6:1]
Palette 11 initial value[6:1]
Palette 12 initial value[6:1]
Palette 13 initial value[6:1]
Palette 14 initial value[6:1]
Palette 15 initial value[6:1]
Palette
100000X
100001X
100010X
100011X
100100X
100101X
100110X
100111X
101000X
101001X
101010X
101011X
101100X
101101X
101110X
101111X
110000X
110001X
110010X
110011X
110100X
110101X
110110X
110111X
111000X
111001X
111010X
111011X
111100X
111101X
111110X
111111X
Grayscale level
32/63
33/63
34/63
35/63
36/63
37/63
38/63
39/63
40/63
41/63
42/63
43/63
44/63
45/63
46/63
47/63
48/63
49/63
50/63
51/63
52/63
53/63
54/63
55/63
56/63
57/63
58/63
59/63
60/63
61/63
62/63
63/63
Remarks
Palette 16 initial value[6:1]
Palette 17 initial value[6:1]
Palette 18 initial value[6:1]
Palette 19 initial value[6:1]
Palette 20 initial value[6:1]
Palette 21 initial value[6:1]
Palette 22 initial value[6:1]
Palette 23 initial value[6:1]
Palette 24 initial value[6:1]
Palette 25 initial value[6:1]
Palette 26 initial value[6:1]
Palette 27 initial value[6:1]
Palette 28 initial value][6:1]
Palette 29 initial value[6:1]
Palette 30 initial value[6:1]
Palette 31 initial value[6:1]
65k-color Mode(32 Grayscale from 32 Levels, PWM1=0, PWM0=1)
[Three groups of palettes Aj, Bj and Cj (j=0~31) are available]
(marking points are default positions)
Palette
00000XX
00001XX
00010XX
00011XX
00100XX
00101XX
00110XX
00111XX
01000XX
01001XX
01010XX
01011XX
01100XX
01101XX
01110XX
01111XX
- 84 -
Grayscale level
0/31
1/31
2/31
3/31
4/31
5/31
6/31
7/31
8/31
9/31
10/31
11/31
12/31
13/31
14/31
15/31
Remarks
Palette 0/X initial value[6:2]
Palette 1 initial value[6:2]
Palette 2 initial value[6:2]
Palette 3 initial value[6:2]
Palette 4 initial value[6:2]
Palette 5 initial value[6:2]
Palette 6 initial value[6:2]
Palette 7 initial value[6:2]
Palette 8 initial value[6:2]
Palette 9 initial value[6:2]
Palette 10 initial value[6:2]
Palette 11 initial value[6:2]
Palette 12 initial value[6:2]
Palette 13 initial value[6:2]
Palette 14 initial value[6:2]
Palette 15 initial value[6:2]
Palette
10000XX
10001XX
10010XX
10011XX
10100XX
10101XX
10110XX
10111XX
11000XX
11001XX
11010XX
11011XX
11100XX
11101XX
11110XX
11111XX
Grayscale level
16/31
17/31
18/31
19/31
20/31
21/31
22/31
23/31
24/31
25/31
26/31
27/31
28/31
29/31
30/31
31/31
Remarks
Palette 16 initial value[6:2]
Palette 17 initial value[6:2]
Palette 18 initial value[6:2]
Palette 19 initial value[6:2]
Palette 20 initial value[6:2]
Palette 21 initial value[6:2]
Palette 22 initial value[6:2]
Palette 23 initial value[6:2]
Palette 24 initial value[6:2]
Palette 25 initial value[6:2]
Palette 26 initial value[6:2]
Palette 27 initial value[6:2]
Palette 28 initial value][6:2]
Palette 29 initial value[6:2]
Palette 30 initial value[6:2]
Palette 31 initial value[6:2]
Ver.2004-06-29
NJU6854
4k-color Mode(16 Grayscale from 128 Levels, PWM1=1, PWM0=1)
Only odd number palettes ( ex palette1 palette3 .. palette31)are effective under 4k color mode.
[Three groups of palettes Aj, Bj and Cj (j=1,3,5 …29, 31) are available] (marking points are default positions)
Palette
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
Ver.2004-06-29
Grayscale level
0/127
1/127
2/127
3/127
4/127
5/127
6/127
7/127
8/127
9/127
10/127
11/127
12/127
13/127
14/127
15/127
16/127
17/127
18/127
19/127
20/127
21/127
22/127
23/127
24/127
25/127
26/127
27/127
28/127
29/127
30/127
31/127
32/127
33/127
34/127
35/127
36/127
37/127
38/127
39/127
40/127
41/127
42/127
43/127
44/127
45/127
46/127
47/127
48/127
49/127
50/127
51/127
52/127
53/127
54/127
55/127
56/127
57/127
58/127
59/127
60/127
61/127
62/127
63/127
Remarks
Palette 1 initial value[6:0]
Palette 3 initial value[6:0]
Palette 5 initial value[6:0]
Palette 7 initial value[6:0]
Palette 9 initial value[6:0]
Palette 11 initial value[6:0]
Palette 13 initial value[6:0]
Palette 15 initial value[6:0]
Palette
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
1010000
1010001
1010010
1010011
1010100
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
Grayscale level
64/127
65/127
66/127
67/127
68/127
69/127
70/127
71/127
72/127
73/127
74/127
75/127
76/127
77/127
78/127
79/127
80/127
81/127
82/127
83/127
84/127
85/127
86/127
87/127
88/127
89/127
90/127
91/127
92/127
93/127
94/127
95/127
96/127
97/127
98/127
99/127
100/127
101/127
102/127
103/127
104/127
105/127
106/127
107/127
108/127
109/127
110/127
111/127
112/127
113/127
114/127
115/127
116/127
117/127
118/127
119/127
120/127
121/127
122/127
123/127
124/127
125/127
126/127
127/127
Remarks
Palette 17 initial value[6:0]
Palette 19 initial value[6:0]
Palette 21 initial value[6:0]
Palette 23 initial value[6:0]
Palette 25 initial value[6:0]
Palette 27 initial value[6:0]
Palette 29 initial value[6:0]
Palette 31 initial value[6:0]
- 85 -
NJU6854
4k-color Mode(16 Grayscale from 64 Levels, PWM1=0, PWM0=0)
[Three groups of palettes Aj, Bj and Cj (j=1,3,5 …29, 31) are available]
Palette
000000X
000001X
000010X
000011X
000100X
000101X
000110X
000111X
001000X
001001X
001010X
001011X
001100X
001101X
001110X
001111X
010000X
010001X
010010X
010011X
010100X
010101X
010110X
010111X
011000X
011001X
011010X
011011X
011100X
011101X
011110X
011111X
Grayscale level
0/63
1/63
2/63
3/63
4/63
5/63
6/63
7/63
8/63
9/63
10/63
11/63
12/63
13/63
14/63
15/63
16/63
17/63
18/63
19/63
20/63
21/63
22/63
23/63
24/63
25/63
26/63
27/63
28/63
29/63
30/63
31/63
Remarks
Palette 1 initial value[6:1]
Palette 3 initial value[6:1]
Palette 5 initial value[6:1]
Palette 7 initial value[6:1]
Palette 9 initial value[6:1]
Palette 11 initial value[6:1]
Palette 13 initial value[6:1]
Palette 15 initial value[6:1]
Palette
100000X
100001X
100010X
100011X
100100X
100101X
100110X
100111X
101000X
101001X
101010X
101011X
101100X
101101X
101110X
101111X
110000X
110001X
110010X
110011X
110100X
110101X
110110X
110111X
111000X
111001X
111010X
111011X
111100X
111101X
111110X
111111X
(marking points are default positions)
Grayscale level
Remarks
32/63
33/63
34/63
35/63
Palette 17 initial value[6:1]
36/63
37/63
38/63
39/63
Palette 19 initial value[6:1]
40/63
41/63
42/63
43/63
Palette 21 initial value[6:1]
44/63
45/63
46/63
47/63
Palette 23 initial value[6:1]
48/63
49/63
50/63
51/63
Palette 25 initial value[6:1]
52/63
53/63
54/63
55/63
Palette 27 initial value[6:1]
56/63
57/63
58/63
59/63
Palette 29 initial value[6:1]
60/63
61/63
62/63
63/63
Palette 31 initial value[6:1]
4k-color Mode(16 Grayscale from 32 Levels, PWM1=0, PWM0=1)
[Three groups of palettes Aj, Bj and Cj (j=1,3,5 …29, 31) are available] (marking points are default positions)
Palette
00000XX
00001XX
00010XX
00011XX
00100XX
00101XX
00110XX
00111XX
01000XX
01001XX
01010XX
01011XX
01100XX
01101XX
01110XX
01111XX
Grayscale level
0/31
1/31
2/31
3/31
4/31
5/31
6/31
7/31
8/31
9/31
10/31
11/31
12/31
13/31
14/31
15/31
Remarks
Palette 1 initial value[6:2]
Palette 3 initial value[6:2]
Palette 5 initial value[6:2]
Palette 7 initial value[6:2]
Palette 9 initial value[6:2]
Palette 11 initial value[6:2]
Palette 13 initial value[6:2]
Palette 15 initial value[6:2]
Palette
10000XX
10001XX
10010XX
10011XX
10100XX
10101XX
10110XX
10111XX
11000XX
11001XX
11010XX
11011XX
11100XX
11101XX
11110XX
11111XX
Grayscale level
16/31
17/31
18/31
19/31
20/31
21/31
22/31
23/31
24/31
25/31
26/31
27/31
28/31
29/31
30/31
31/31
Remarks
Palette 17 initial value[6:2]
Palette 19 initial value[6:2]
Palette 21 initial value[6:2]
Palette 23 initial value[6:2]
Palette 25 initial value[6:2]
Palette 27 initial value[6:2]
Palette 29 initial value[6:2]
Palette 31 initial value[6:2]
4k-color Mode(16 Grayscale from 16 Levels, PWM1=1, PWM0=0)
[Three groups of palettes Aj, Bj and Cj (j=1,3,5 …29, 31) are available] (marking points are default positions)
Palette
0000XXX
0001XXX
0010XXX
0011XXX
0100XXX
0101XXX
0110XXX
0111XXX
- 86 -
Grayscale level
0/15
1/15
2/15
3/15
4/15
5/15
6/15
7/15
Remarks
Palette 1 initial value[6:3]
Palette 3 initial value[6:3]
Palette 5 initial value[6:3]
Palette 7 initial value[6:3]
Palette 9 initial value[6:3]
Palette 11 initial value[6:3]
Palette 13 initial value[6:3]
Palette 15 initial value[6:3]
Palette
1000XXX
1001XXX
1010XXX
1011XXX
1100XXX
1101XXX
1110XXX
1111XXX
Grayscale level
8/15
9/15
10/15
11/15
12/15
13/15
14/15
15/15
Remarks
Palette 17 initial value[6:3]
Palette 19 initial value[6:3]
Palette 21 initial value[6:3]
Palette 23 initial value[6:3]
Palette 25 initial value[6:3]
Palette 27 initial value[6:3]
Palette 29 initial value[6:3]
Palette 31 initial value[6:3]
Ver.2004-06-29
NJU6854
The setting range of the palette level which can be set up is limited in each palette (RGB common).
level
Hex Dec
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
A
10
B
11
C
12
D
13
E
14
F
15
10
16
11
17
12
18
13
19
14
20
15
21
16
22
17
23
18
24
19
25
1A
26
1B
27
1C
28
1D
29
1E
30
1F
31
20
32
21
33
22
34
23
35
24
36
25
37
26
38
27
39
28
40
29
41
2A
42
2B
43
2C
44
2D
45
2E
46
2F
47
30
48
31
49
32
50
33
51
34
52
35
53
36
54
37
55
38
56
39
57
3A
58
3B
59
3C
60
3D
61
3E
62
3F
63
40
64
41
65
42
66
43
67
44
68
45
69
46
70
47
71
48
72
49
73
4A
74
4B
75
4C
76
4D
77
4E
78
4F
79
50
80
51
81
52
82
53
83
54
84
55
85
56
86
57
87
58
88
59
89
5A
90
5B
91
5C
92
5D
93
5E
94
5F
95
60
96
61
97
62
98
63
99
64
100
65
101
66
102
67
103
68
104
69
105
6A
106
6B
107
6C
108
6D
109
6E
110
6F
111
70
112
71
113
72
114
73
115
74
116
75
117
76
118
77
119
78
120
79
121
7A
122
7B
123
7C
124
7D
125
7E
126
7F
127
P6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Palette register
P4
P3
P2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
0
1
1
0
1
1
0
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
0
1
1
0
1
1
0
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
0
1
1
0
1
1
0
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
0
1
1
0
1
1
0
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
P1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
P0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
1
2
3
4
5
6
7
8
9
10
11
12
13
Palette selection range
14
15
16
17
Caution: Do not set same level for each grayscale palette ( palettem = paletten , m = 0~31, n = 0~31)
Ver.2004-06-29
18
19
20
21
22
23
24
25
26
27
28
29
30
Forbidden random level palette ( paletten > paletten+1)
- 87 -
31
NJU6854
The setting range of the palette level can be expressed as the following table.
Palette No.
0
X
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Palette register
MSB
6
5
0
0
4
3
2
1
LSB
0
Anything
Anything
Anything
Anything
Anything
Anything
Anything
Anything
Anything
0
0
0
Except(1,1)
Except(1,1)
Except(1,1)
Except(1,1)
Anything
Anything
Anything
Anything
Anything
Anything
Anything
Anything
Except(0,0)
Except(0,0)
Except(0,0)
Except(0,0)
Except(0,0)
Except(0,0)
Except(0,0)
Except(0,0)
1
1
1
1
1
1
1
1
Anything
Anything
Anything
Anything
Anything
Anything
Anything
Anything
Anything
Anything
Anything
Anything
Anything
Anything
Anything
Anything
Caution:
(1) Do not set the same grayscale level in each grayscale palette(forbidden case: palettem = palettem+n , m=0~31 n=0~31)
(2) Do not set the zigzag typed grayscale palette. (forbidden case: paletten > paletten+1, n=0~31 )
- 88 -
Ver.2004-06-29
NJU6854
(13) PARTIAL DISPLAY FUNCTION
Partial display function is used to save power. In the partial display mode, only specified common drivers output
scanning signals, therefore part of the panel area is selected for display. Because the duty ratio and LCD driving
voltage are lowed in partial display mode. Current consumption can be minimized.
NJU6854 can realize 3 partial display areas on the screen once. The setting of Partial display function is conducted
through Scan Start COM 1~3(SSC1~3) registers, Partial Display Line Number 1~3(PCC1~3) registers, Power Control
1~2 (TCBI,POW2) registers, Amplifier Gain/Booster Level(GVU) register, and 3 Partial Display/LED Control/Rev
(ECONT) register. Refer to (15)TYPICAL INSTRUCTION SEQUENCES for the functions setting
The image of partial display.
(i) Full Screen Display
SSC1
(Scan Start COM1)
VPC(Display line number)
(ii) Partial Display (1 area)
VPC(Display line number)
SSC1
(Scan Start COM1)
PCC1(partial display line number 1)
(iii) Partial Display (2 areas)
VPC(Display line number)
SSC1
(Scan Start COM1)
SSC2
(Scan Start COM 2)
PCC1(partial display line number 1)
PCC2(partial display line number 2)
(iv) Partial Display (3 areas)
SSC1
(Scan Start COM1)
VPC(Display line number)
PCC1(partial display line number 1)
SSC2
(Scan Start COM 2)
PCC2(partial display line number 2)
SSC3
(Scan Start COM 3)
PCC3(partial display line number 3)
Note) For the full screen display, set the Scan Start COM 1(SCC1) and the Display Line Number(VPC).
For the partial display, set the Scan Start COM 1~3(SCC1~3) and the Partial Display Line Number 1~3(PCC1~3). In this
case, the Partial Display Line Number 1~3(PCC1~3) have priority over the Display Line Number(VPC), and thus the
display duty is: Duty=PCC1+PCC2+PCC.
Ver.2004-06-29
- 89 -
NJU6854
(14) RELATIONSHIP BETWEEN LOGICAL COM NUMBER AND PHYSICAL COMMON DRIVER
(EN3PTL=’0’)
Physical COM name
VPC (Display line number)
HCT (Header COM)
SHIFT[1] (COM shift A/B set)
SHIFT[0] (COM shift direction)
SSC1 (Scan Start COM 1)
SSC2 (Scan Start COM 2)
PCC1 (Line No. of partial display 1)
PCC2 (Line No. of partial display 2)
SSC3 (Scan Start COM 3)
PCC3 (Line No. of partial display 3)
A
COMA0
COMA1
COMA2
COMA3
COMA4
COMA5
COMA6
COMA7
COMA8
COMA9
COMA10
COMA11
COMA12
COMA13
COMA14
COMA15
COMA16
COMA17
COMA18
COMA19
COMA20
COMA21
COMA22
COMA23
COMA24
COMA25
COMA26
COMA27
COMA28
COMA29
COMA30
COMA31
COMA32
COMA33
COMA34
COMA35
COMA36
COMA37
COMA38
COMA39
COMA40
COMA41
COMA42
COMA43
COMA44
COMA45
COMA46
COMA47
COMA48
COMA49
COMA50
COMA51
COMA52
COMA53
COMA54
COMA55
COMA56
COMA57
COMA58
COMA59
COMA60
COMA61
COMA62
COMA63
COMA64
COMA65
REMARK
- 90 -
B
COMB0
COMB1
COMB2
COMB3
COMB4
COMB5
COMB6
COMB7
COMB8
COMB9
COMB10
COMB11
COMB12
COMB13
COMB14
COMB15
COMB16
COMB17
COMB18
COMB19
COMB20
COMB21
COMB22
COMB23
COMB24
COMB25
COMB26
COMB27
COMB28
COMB29
COMB30
COMB31
COMB32
COMB33
COMB34
COMB35
COMB36
COMB37
COMB38
COMB39
COMB40
COMB41
COMB42
COMB43
COMB44
COMB45
COMB46
COMB47
COMB48
COMB49
COMB50
COMB51
COMB52
COMB53
COMB54
COMB55
COMB56
COMB57
COMB58
COMB59
COMB60
COMB61
COMB62
COMB63
COMB64
COMB65
106
13
‘0’ (A start-> A end -> B start -> B end)
‘0’
logical
COM
number
A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
B
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
(A -> B)
‘1’
0
0
0
0
*
*
10
0
0
0
*
*
36
80
20
15
*
*
A
B
A
B
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
96
97
98
99
100
101
102
103
104
105
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
one area
one area
Normal
A
logical
COM
number
B
17
18
19
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
two area
A
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
B
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
(A <- B)
0
0
0
0
*
*
96
0
0
0
*
*
11
50
15
20
*
*
A
B
A
B
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
one area
one area
Reversed
A
B
17
16
15
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
two area
Ver.2004-06-29
NJU6854
(EN3PTL= ‘1’)
VPC (Display line number)
106
HCT (Header COM)
13
‘1’ (B start-> B end -> A start -> A end)
SHIFT[1] (COM shift A/B set)
‘0’
SHIFT[0] (COM shift direction)
‘1’
SSC1 (Scan Start COM 1)
logical
0
10
36
logical
0
96
11
SSC2 (Scan Start COM 2)
COM
0
0
80
COM
0
0
50
number
0
0
20
0
0
15
PCC2 (Line No. of partial display 2)
0
0
15
0
0
20
SSC3 (Scan Start COM 3)
*
*
*
*
*
*
PCC3 (Line No. of partial display 3)
*
*
*
*
*
*
Physical COM name
PCC1 (Line No. of partial display 1)
number
A
B
A
B
COMA0
COMA1
COMA2
COMA3
COMA4
COMA5
COMA6
COMA7
COMA8
COMA9
COMA10
COMA11
COMA12
COMA13
COMA14
COMA15
COMA16
COMA17
COMA18
COMA19
COMA20
COMA21
COMA22
COMA23
COMA24
COMA25
COMA26
COMA27
COMA28
COMA29
COMA30
COMA31
COMA32
COMA33
COMA34
COMA35
COMA36
COMA37
COMA38
COMA39
COMA40
COMA41
COMA42
COMA43
COMA44
COMA45
COMA46
COMA47
COMA48
COMA49
COMA50
COMA51
COMA52
COMA53
COMA54
COMA55
COMA56
COMA57
COMA58
COMA59
COMA60
COMA61
COMA62
COMA63
COMA64
COMA65
COMB0
COMB1
COMB2
COMB3
COMB4
COMB5
COMB6
COMB7
COMB8
COMB9
COMB10
COMB11
COMB12
COMB13
COMB14
COMB15
COMB16
COMB17
COMB18
COMB19
COMB20
COMB21
COMB22
COMB23
COMB24
COMB25
COMB26
COMB27
COMB28
COMB29
COMB30
COMB31
COMB32
COMB33
COMB34
COMB35
COMB36
COMB37
COMB38
COMB39
COMB40
COMB41
COMB42
COMB43
COMB44
COMB45
COMB46
COMB47
COMB48
COMB49
COMB50
COMB51
COMB52
COMB53
COMB54
COMB55
COMB56
COMB57
COMB58
COMB59
COMB60
COMB61
COMB62
COMB63
COMB64
COMB65
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
REMARK
Ver.2004-06-29
(B -> A)
A
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
B
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
one area
A
B
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
one area
Normal
A
B
A
B
A
B
A
B
A
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
17
16
15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
two area
(B <- A)
one area
one area
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
B
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
two area
Reversed
- 91 -
NJU6854
(EN3PTL= ‘1’)
VPC (Display line number)
106
HCT (Header COM)
13
SHIFT[1] (COM shift A/B set)
‘0’ (A start-> A end -> B start -> B end)
SHIFT[0] (COM shift direction)
‘0’
‘1’
SSC1 (Scan Start COM 1)
logical
0
10
36
logical
0
96
0
SSC2 (Scan Start COM 2)
COM
0
0
80
COM
0
0
11
number
PCC1 (Line No. of partial display 1)
0
20
0
0
15
SSC3 (Scan Start COM 3)
0
0
101
0
0
50
PCC3 (Line No. of partial display 3)
0
0
5
0
0
20
Physical COM name
0
PCC2 (Line No. of partial display 2)
A
B
A
B
COMA0
COMA1
COMA2
COMA3
COMA4
COMA5
COMA6
COMA7
COMA8
COMA9
COMA10
COMA11
COMA12
COMA13
COMA14
COMA15
COMA16
COMA17
COMA18
COMA19
COMA20
COMA21
COMA22
COMA23
COMA24
COMA25
COMA26
COMA27
COMA28
COMA29
COMA30
COMA31
COMA32
COMA33
COMA34
COMA35
COMA36
COMA37
COMA38
COMA39
COMA40
COMA41
COMA42
COMA43
COMA44
COMA45
COMA46
COMA47
COMA48
COMA49
COMA50
COMA51
COMA52
COMA53
COMA54
COMA55
COMA56
COMA57
COMA58
COMA59
COMA60
COMA61
COMA62
COMA63
COMA64
COMA65
COMB0
COMB1
COMB2
COMB3
COMB4
COMB5
COMB6
COMB7
COMB8
COMB9
COMB10
COMB11
COMB12
COMB13
COMB14
COMB15
COMB16
COMB17
COMB18
COMB19
COMB20
COMB21
COMB22
COMB23
COMB24
COMB25
COMB26
COMB27
COMB28
COMB29
COMB30
COMB31
COMB32
COMB33
COMB34
COMB35
COMB36
COMB37
COMB38
COMB39
COMB40
COMB41
COMB42
COMB43
COMB44
COMB45
COMB46
COMB47
COMB48
COMB49
COMB50
COMB51
COMB52
COMB53
COMB54
COMB55
COMB56
COMB57
COMB58
COMB59
COMB60
COMB61
COMB62
COMB63
COMB64
COMB65
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
REMARK
- 92 -
number
(A -> B)
A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
B
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
one area
A
B
96
97
98
99
100
101
102
103
104
105
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
one area
Normal
A
B
17
18
19
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
two area
0
0
5
0
0
15
A
B
A
B
A
B
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
(A <- B)
one area
one area
A
B
22
21
20
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
two area
Reversed
Ver.2004-06-29
NJU6854
(EN3PTL= ‘1’)
VPC (Display line number)
106
HCT (Header COM)
13
SHIFT[1] (COM shift A/B set)
‘1’ (B start-> B end -> A start -> A end)
SHIFT[0] (COM shift direction)
‘0’
‘1’
SSC1 (Scan Start COM 1)
logical
0
10
36
logical
0
96
0
SSC2 (Scan Start COM 2)
COM
0
0
80
COM
0
0
11
number
0
0
20
number
0
0
5
0
0
15
0
0
15
PCC1 (Line No. of partial display 1)
PCC2 (Line No. of partial display 2)
0
0
101
0
0
20
PCC3 (Line No. of partial display 3)
0
0
5
0
0
10
Physical COM name
SSC3 (Scan Start COM 3)
A
B
A
B
COMA0
COMA1
COMA2
COMA3
COMA4
COMA5
COMA6
COMA7
COMA8
COMA9
COMA10
COMA11
COMA12
COMA13
COMA14
COMA15
COMA16
COMA17
COMA18
COMA19
COMA20
COMA21
COMA22
COMA23
COMA24
COMA25
COMA26
COMA27
COMA28
COMA29
COMA30
COMA31
COMA32
COMA33
COMA34
COMA35
COMA36
COMA37
COMA38
COMA39
COMA40
COMA41
COMA42
COMA43
COMA44
COMA45
COMA46
COMA47
COMA48
COMA49
COMA50
COMA51
COMA52
COMA53
COMA54
COMA55
COMA56
COMA57
COMA58
COMA59
COMA60
COMA61
COMA62
COMA63
COMA64
COMA65
COMB0
COMB1
COMB2
COMB3
COMB4
COMB5
COMB6
COMB7
COMB8
COMB9
COMB10
COMB11
COMB12
COMB13
COMB14
COMB15
COMB16
COMB17
COMB18
COMB19
COMB20
COMB21
COMB22
COMB23
COMB24
COMB25
COMB26
COMB27
COMB28
COMB29
COMB30
COMB31
COMB32
COMB33
COMB34
COMB35
COMB36
COMB37
COMB38
COMB39
COMB40
COMB41
COMB42
COMB43
COMB44
COMB45
COMB46
COMB47
COMB48
COMB49
COMB50
COMB51
COMB52
COMB53
COMB54
COMB55
COMB56
COMB57
COMB58
COMB59
COMB60
COMB61
COMB62
COMB63
COMB64
COMB65
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
REMARK
Ver.2004-06-29
(B -> A)
A
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
B
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
one area
A
B
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
one area
Normal
A
B
A
B
A
B
A
B
A
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
22
21
20
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
two area
(B <- A)
one area
one area
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
B
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
two area
Reversed
- 93 -
NJU6854
Example of panel connection 1 (HCT=00H)
Physical COM Layout
RAM Mapping
Scanning Direction
SHIFT[1:0]
=(0,1)
00H
X Address
83H
Y Address
PANEL
00H
83H
Scanning Direction
SHIFT[1:0]
=(0,0)
COMB[65~0]
COMA[0~65]
Example of panel connection 2 (HCT=0AH)
Physical COM Layout
RAM Mapping
Scanning Direction
SHIFT[1:0]
=(0,1)
00H
X Address
83H
Y Address
PANEL
00H
Scanning Direction
COMB[65~10]
- 94 -
6FH
70H
SHIFT[1:0]
=(0,0)
83H
COMA[10~65]
Ver.2004-06-29
NJU6854
(15) TYPICAL INSTRUCTION SEQUENCES
(1) Initialization (internal power supply)
VDD, VEE – VSS RESb=”L”
Power Supply Stabilization
Note 1 ) If VEE is different from VDD, input VDD first
Note 2) Waiting until VDD and VEE stabilization
RESb=”H”
Note 3) Waiting at least 10 us
WAIT
Bus length selection
8 or 16-bit bus length selection
Display Control
Duty ratio
Blank line number
N-line inversion
Display mode
Power Supply
Boost level, amplifier gain for VREG
Electronic volume
Bias ratio
VREG, VBA
Power Control
(CKCONT=”1", DCON=”1")
WAIT
Note 4) Waiting until VOUT stabilization
Note 5) Waiting until V0 and V1~V4 stabilization
Power Supply
Power control
(AMPON=”1")
WAIT
End of Initialization
Ver.2004-06-29
- 95 -
NJU6854
(2) Initialization (external power supply)
VDD ON, RESb=”L”
Power supply stabilization
Note 1) Waiting until VDD stabilization
Note 2) Waiting at least 10 us
RESb=”H”
VOUT, V0~V4 ON
Note 3) Waiting until VOUT, V0~V4 stabilization
WAIT
Display Control
Duty ratio
Blank line number
N-line inversion
Display mode
End of Initialization
(3) Data Write
Initialization
Display Control
Initial Display Line
Display data configuration / window area
X address Y address
Display data write
Display data ON (ON/OFF=”1")
End of display data setting
(4) Power OFF
Optional condition
Function
Execute HALT or reset instruction
(All drivers outputs VSS)
Execute discharge instruction
(V0 and V1~V4 capacitors discharge)
Wait
VEE, VDD~VSS OFF
- 96 -
Ver.2004-06-29
NJU6854
(5) Partial Display
Optional Condition
Display OFF(ON/OFF="0")
Internal power supply OFF
(DCON="0", AMPON="0")
Note 1) Waiting until voltage booster OFF
WAIT
Power Supply
Boost Lever, amplifier gain of VREG
Electronic volume
Bias ratio
VREG, VBA
Power control
Note 2) Waiting until VOUT stabilization
(DCON="1", AMPON="1")
WAIT
Note 3) Waiting until VOUT V0 and V1 ~V4 stabilization
Display Control
Duty ratio
Initial display line
Partial display
Display ON(ON/OFF="1")
Partial display ON
Ver.2004-06-29
- 97 -
NJU6854
! ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
CONDITION
TERMINAL
RATING
Supply Voltage (1)
VDD
VDD
-0.3 to +4.0
Supply Voltage (2)
VEE
VEE
-0.3 to +4.0
Supply Voltage (3)
VOUT
VOUT
-0.3 to +20.0
VSS=0V
Supply Voltage (4)
VREG
VREG
-0.3 to +20.0
Ta = +25°C
Supply Voltage (5)
V0
V0
-0.3 to +20.0
Supply Voltage (6)
V1, V2, V3, V4
V1, V2, V3, V4
-0.3 to V0 + 0.3
Input Voltage
VI
*1
-0.3 to VDD + 0.3
Storage Temperature
Tstg
-45 to +125
Note 1) D0 ~ D15, CSb, RS, RDb, WRb, OSCI, RESb pins
Note 2) To stabilize the LSI operation, place decoupling capacitors between VDD and VSS, VEE and VSSH.
UNIT
V
V
V
V
V
V
V
°C
! RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
Operating Voltage
SYMBOL
VDD1
VDD2
VEE
V0
VOUT
VREG
VREF
TERMINAL
VDD
VEE
V0
VOUT
VREG
VREF
MIN
1.7
2.4
2.4
5
TYP
MAX
UNIT
3.3
V
3.3
V
3.3
V
18.0
V
18.0
V
V
VOUT × 0.9
3.3
V
1.59(TBD)
Operating
Topr
-30
Temperature
Note1) Applies to the condition when the reference voltage generator is not used.
Note2) Applies to the condition when the reference voltage generator is used.
Note3) Applies to the condition when the voltage booster is used.
Note4) The following relationship among the supply voltages must be maintained.
VSSH<V4<V3<V2<V1<V0<VOUT
Note5) The relationship: VREF<VEE must be maintained.
- 98 -
85
NOTE
*1
*2
*3
*4
*5
°C
Ver.2004-06-29
NJU6854
! DC CHARACTERISTICS
SYM
PARAMETER
BOL
High level input voltage
VIH
Low level input voltage
VIL
High level output voltage VOH1
Low level output voltage VOL1
High level output voltage VOH2
Low level output voltage VOL2
Input leakage current
ILI
Output leakage current
ILO
Driver ON-resistance
RON1
Stand-by current
ISTB
fOSCI
fOSC2
fOSC3
fOSC4
Internal oscillation
Frequency
External oscillation
Frequency
Voltage converter
output voltage
fr1
VOUT
Supply current (1)
IDD1
Supply current (2)
IDD2
Supply current (3)
IDD3
Supply current (4)
IDD4
Supply current (5)
IDD5
Supply current (6)
IDD6
VBA Operating voltage
VBA
VREG Operating voltage
VREG
Output Voltage
V2
V3
VD12
VD34
VD24
Ver.2004-06-29
VSS = 0V, VDD = +1.7 to +3.3V, Ta = -30 to +85°C
NOT
CONDITION
MIN
TYP
MAX
UNIT
E
0.8 VDD
VDD
V
*1
0
0.2VDD
V
*1
IOH = -0.4mA
VDD - 0.4
V
*2
IOL = 0.4mA
0.4
V
*2
IOH = -0.1mA
VDD - 0.4
V
*3
IOL = 0.1mA
0.4
V
*3
*4
-10
10
VI = VSS or VDD
µA
*5
-10
10
VI = VSS or VDD
µA
V0 = 10V
1
2
*6
kΩ
|∆VON| = 0.5V
2
4
V0 = 6V
*7
15
CSb=VDD, Ta=25°C VDD = 3V
µA
TBD
730
TBD
VDD = 3V
TBD
170
TBD
kHz
*8
Ta = 25°C
TBD
1200
TBD
TBD
285
TBD
Rf=15kΩ, VDD = 3V,Ta = 25°C
N-time booster (N=2 to 6)
RL = 500kΩ (VOUT - VSS)
VDD = 3V, 6-time booster
Whole ON pattern
VDD = 3V, 6-time booster
Checker pattern
VDD = 3V, 5-time booster
Whole ON pattern
VDD = 3V, 5-time booster
Checker pattern
VDD = 3V, 4-time booster
Whole ON pattern
VDD = 3V, 4-time booster
Checker pattern
VEE = 2.4 to 3.3V@ T=25°C
VEE = 2.4 to 3.3V
VREF = 1.9
N-time booster (N=2 to 6)
730
(N x VEE)
x 0.95
kHz
*9
V
*10
µA
*11
TBD(760) TBD(1140)
TBD(930) TBD(1400)
1.86
TBD(520)
TBD(780)
TBD(650)
TBD(980)
TBD(360)
TBD(540)
TBD(450)
TBD(680)
1.9
1.94
V
*12
(VREF x N)
x 1.03
V
*13
+100
+100
+30
+30
+30
mV
*14
(VREF x N)
(VREF x N)
x 0.97
-100
-100
-30
-30
-30
0
0
0
0
0
- 99 -
NJU6854
● Applicable Pins and Conditions
*1
*2
*3
*4
*5
*6
*7
*8
*9
*10
*11
*12
*13
*14
D0-D15, CSb, RS, RDb, WRb, PS, SEL68, RESb
D0-D15
LP, FLM, M
CSb, RS, SEL68, RDb, WRb, PS, RESb, OSCI
D0-D15 , M, FLM, LP in the high impedance
SEGA0-SEGA131, SEGB0-SEGB131, SEGC0-SEGC131, COMA0-COMA65, COMB0-COMB65
Defines the resistance between the COM/SEG terminals and the power supply terminals (V0, V1, V2, V3
and V4) at the condition of 0.5V deference and 1/9 LCD bias ratio.
VDD
The oscillator is halted, CSb=”1” (disabled), No-load on the COM/SEG drivers
fOSCI
- Defines the internal oscillation frequency at (CRF, CRS1, CRS0) = (0, 0, 0).
fOSC2
- Defines the internal oscillation frequency at (CRF, CRS1, CRS0) = (0, 0, 1).
fOSC3
- Defines the internal oscillation frequency at (CRF, CRS1, CRS0) = (1, 0, 0).
fOSC4
- Defines the internal oscillation frequency at (CRF, CRS1, CRS0) = (1, 0, 1).
fr1
- Defines the internal oscillation frequency at (CRF, CRS1, CRS0) = (0, 1, 0).
VOUT
- N x boosting (N=2~6), applicable under internal oscillator circuit and internal power circuit are ON state.
- VEE=2.4V to 3.3V, EVR= (1,1,1,1,1,1,1), 1/5 to 1/12 LCD bias, duty is 1/132 , No loads on COM/SEG
drivers.
- RL=500KΩ between the VOUT and the VSS, CA1=CA2=1.0uF, CA3=0.1uF, DCON=”1”, AMPON=”1”
VDD
- Applies to the condition using the internal oscillator and internal power circuits, no access between the LSI
and MPU.
EVR value is ‘1,1,1,1,1,1,1’.
Driving patterns are ‘all pixels turned-on’ or ‘checkerboard’ display in grayscale mode.
No load are connected on the COM/SEG drivers.
- VDD=VEE, VREF=0.9VEE, CA1=CA2=1.0uF, CA3=0.1uF, DCON=”1”, AMPON=”1”, NLIN=”0”, 1/132 Duty cycle,
Ta=25°C
VBA
VEE=2.4V to 3.3V , Ta=25°C
VREG
- VEE=2.4V to 3.3V, VREF=1.9(external)V, VOUT=18V, bias ratio is from 1/5 to 1/12, 1/132 duty cycle,
EVR=(1,1,1,1,1,1,1),
Checkerboard display, No-load on the COM/SEG drivers, the voltage booster
N=2 to 6. CA1=CA2=1.0uF, CA3=0.1uF, DCON=”0”, AMPON=”1”, NLIN=”0”
V0, V1, V2, V3, V4
- VEE=3.0V, VREF=0.9VEE, VOUT=15V, 1/5 to 1/12 LCD Bias, EVR= (1,1,1,1,1,1,1), Display OFF, No-load on
the COM/SEG drivers, voltage booster N=5. CA1=CA2=1.0uF, CA3=0.1uF, DCON=”0”, AMPON=”1”
1
V0
V1
VD12 = 1 - 2
V2
VD34 = 3 - 4
2
V3
3
V4
4
- 100 -
VD24 = 2 - 4
(VD24 is applied to the condition
that VD12 and VD34 are out of
specifications.)
VSS
Ver.2004-06-29
NJU6854
! AC CHARACTERISTICS
(1) Write operation (80-type MPU)
tAS8
tAH8
CSb
RS
WRb
tWRLW8
tWRHW8
tDS8
tDH8
D0 to D15
tCYC8
PARAMETER
Address hold time
Address setup time
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
Data setup time
Data hold time
SYMBOL
tAH8
tAS8
CONDITION
MIN.
0
0
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
MAX.
UNIT
TERMINAL
ns
CSb
ns
RS
tCYC8
tWRLW8
tWRHW8
240
110
110
ns
ns
ns
WRb
tDS8
tDH8
60
15
ns
ns
D0 to D15
(VDD=1.7 to 2.5V, Ta=-30 to +85°C)
PARAMETER
Address hold time
Address setup time
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
Data setup time
Data hold time
SYMBOL
tAH8
tAS8
CONDITION
MIN.
0
0
MAX.
UNIT
ns
ns
TERMINAL
CSb
RS
tCYC8
tWRLW8
tWRHW8
300
95
95
ns
ns
ns
WRb
tDS8
tDH8
80
20
ns
ns
D0 to D15
Note) Each timing is specified based on 20% and 80% of VDD.
Ver.2004-06-29
- 101 -
NJU6854
(2) Read operation (80-type MPU)
tAH8
tAS8
CSb
RS
tWRLR8
RDb
tWRHR8
tRDH8
D0 to D15
tRDD8
tCYC8
PARAMETER
Address hold time
Address setup time
SYMBOL
tAH8
tAS8
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC8
tWRLR8
tWRHR8
Read Data delay time
Read Data hold time
TRDD8
TRDH8
PARAMETER
Address hold time
Address setup time
SYMBOL
tAH8
tAS8
CONDITION
MIN.
0
0
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
MAX.
UNIT
TERMINAL
ns
CSb
ns
RS
260
120
120
CL=15pF
90
0
ns
ns
ns
RDb
ns
ns
D0 to D15
(VDD=1.7 to 2.5V, Ta=-30 to +85°C)
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
Read Data delay time
Read Data hold time
CONDITION
tCYC8
tWRLR8
tWRHR8
tRDD8
tRDH8
MIN.
0
0
MAX.
360
170
170
CL=15pF
150
0
UNIT
ns
ns
TERMINAL
CSb
RS
ns
ns
ns
RDb
ns
ns
D0 to D15
Note) Each timing is specified based on 20% and 80% of VDD.
- 102 -
Ver.2004-06-29
NJU6854
(3) Write operation (68-type MPU)
tAS6
tAH6
CSb
RS
R/W
(WRb)
tELW6
tEHW6
E
(RDb)
tDS6
tDH6
D0 to D15
tCYC6
PARAMETER
Address hold time
Address setup time
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
Data setup time
Data hold time
SYMBOL
tAH6
tAS6
CONDITION
MIN.
0
0
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
MAX.
UNIT
TERMINAL
ns
CSb
ns
RS
tCYC6
tELW6
tEHW6
240
110
110
ns
ns
ns
E
tDS6
tDH6
70
15
ns
ns
D0 to D15
(VDD=1.7 to 2.5V, Ta=-30 to +85°C)
PARAMETER
Address hold time
Address setup time
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
Data setup time
Data hold time
SYMBOL
tAH6
tAS6
CONDITION
MIN.
0
0
MAX.
UNIT
ns
ns
TERMINAL
CSb
RS
tCYC6
tELW6
tEHW6
300
95
95
ns
ns
ns
E
tDS6
tDH6
80
20
ns
ns
D0 to D15
Note) Each timing is specified based on 20% and 80% of VDD.
Ver.2004-06-29
- 103 -
NJU6854
(4) Read operation (68-type MPU)
tAS6
tAH6
CSb
RS
R/W
(WRb)
tELR6
tEHR6
E
(RDb)
tRDH6
D0 to D15
tRDD6
tCYC6
PARAMETER
Address hold time
Address setup time
SYMBOL
tAH6
tAS6
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC6
tELR6
tEHR6
Read Data delay time
Read Data hold time
tRDD6
tRDH6
PARAMETER
Address hold time
Address setup time
SYMBOL
tAH6
tAS6
System cycle time
Enable ”L” level pulse width
Enable ”H” level pulse width
tCYC6
tELR6
tEHR6
Read Data delay time
Read Data hold time
tRDD6
tRDH6
CONDITION
MIN.
0
0
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
MAX.
UNIT
TERMINAL
ns
CSb
ns
RS
260
120
120
CL=15pF
CONDITION
100
0
MIN.
0
0
150
0
E
ns
ns
D0 to D15
(VDD=1.7 to 2.5V, Ta=-30 to +85°C)
MAX.
UNIT
TERMINAL
ns
CSb
ns
RS
360
170
170
CL=15pF
ns
ns
ns
ns
ns
ns
E
ns
ns
D0 to D15
Note) Each timing is specified based on 20% and 80% of VDD.
- 104 -
Ver.2004-06-29
NJU6854
(5) Serial interface
CSb
tCSH
tCSS
RS
tASS
SCL
tAHS
tSLW
tSHW
tCYCS
tDSS
tDHS
SDA
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
PARAMETER
Serial clock cycle
SCL ”H” level pulse width
SCL ”L” level pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CSb – SCL time
CSb hold time
SYMBOL
tCYCS
tSHW
tSLW
tASS
tAHS
tDSS
tDHS
tCSS
tCSH
CONDITION
MIN.
TBD(75)
TBD(33)
TBD(33)
TBD(33)
TBD(33)
TBD(33)
TBD(33)
TBD(33)
TBD(33)
MAX.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
TERMINAL
SCL
RS
SDA
CSb
(VDD=1.7 to 2.5V, Ta=-30 to +85°C)
PARAMETER
SYMBOL CONDITION
tCYCS
Serial clock cycle
SCL ”H” level pulse width
tSHW
SCL ”L” level pulse width
tSLW
Address setup time
tASS
Address hold time
tAHS
Data setup time
tDSS
Data hold time
tDHS
CSb – SCL time
tCSS
tCSH
CSb hold time
Note) Each timing is specified based on 20% and 80% of VDD.
Ver.2004-06-29
MIN.
TBD(120)
TBD(55)
TBD(55)
TBD(55)
TBD(55)
TBD(55)
TBD(55)
TBD(55)
TBD(55)
MAX.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
TERMINAL
SCL
RS
SDA
CSb
- 105 -
NJU6854
(6) Display control timing
OSCI
tDLP
LP
tDFLM
tDFLM
FLM
tM
M
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
Output timing
PARAMETER
FLM delay time
FR delay time
CL delay time
SYMBOL
tDFLM
tFR
tDCL
CONDITION
CL=15pF
MIN.
0
0
0
- 106 -
UNIT
ns
ns
ns
TERMINAL
FLM
FR
CL
(VDD=1.7 to 2.5V, Ta=-30 to +85°C)
Output timing
PARAMETER
SYMBOL
CONDITION
FLM delay time
tDFLM
CL=15pF
FR delay time
tFR
CL delay time
tDCL
Note) Each timing is specified based on 20% and 80% of VDD.
MAX.
500
500
200
MIN.
0
0
0
MAX.
1000
1000
200
UNIT
ns
ns
ns
TERMINAL
FLM
FR
CL
Ver.2004-06-29
NJU6854
(7) Reset input timing
tRW
RESb
tR
Internal circuit
status
PARAMETER
Reset time
RESb “L” level pulse width
PARAMETER
Reset time
SYMBOL
CONDITION
MIN.
tR
tRW
SYMBOL
(VDD=2.4 to 3.3V, Ta=-30 to +85°C)
UNIT
MAX.
Terminal
1.0
CONDITION
MIN.
tR
RESb
(VDD=1.7 to 2.4V, Ta=-30 to +85°C)
UNIT
Terminal
MAX.
1.5
10.0
µs
µs
10.0
RESb “L” level pulse width
tRW
Note) Each timing is specified based on 20% and 80% of VDD.
Ver.2004-06-29
End of reset
During reset
µs
µs
RESb
- 107 -
NJU6854
! INPUT/OUTPUT BLOCK DIAGRAM
PARAMETER
Basic delay time of gate
SYMBOL
Ta=+25°C, VSS=0V, VDD=3.0V
MIN
TYP
10
MAX
UNIT
ns
I/O circuit types
(a) Input Circuit
VDD
Input
Input signal
Applicable Pins : CSb, RS RDb, WRb, SEL68,
P/S, RESb, TEST, OSCI
(b) Output Circuit
VDD
output
output
signal
Applicable Pins : FLM, LP, M, OSCO
- 108 -
Ver.2004-06-29
NJU6854
(c) Input/Output Circuit
VDD
input/
output
Input signal
input control signal
VDD
output
control signal
output
signal
Applicable Pins : D0 ~ D15,
(d) LCD Drive Circuit for Graphic Display
VLCD
VLCD
V1/V2
output
control
signal 1
output
control
signal 2
output
control
signal 3
output
control
signal 4
output
V3/V4
Applicable Pins : SEGA0 to SEGA131
SEGB0 to SEGB131
SEGC0 to SEGC131
COMA0 to COMA65
COMB0 to COMB65
Ver.2004-06-29
- 109 -
NJU6854
! MPU Connections
80-type MPU interface
1.7 V ~ 3.3 V
RS
A0
A1 ~A7 7
decoder
VDD
NJU6854
VCC
CSb
IORQ
D0~D7
80 series
GND
8
D0 ~D7
RDb
RDb
WRb
WRb
RESb
RESb
reset input
VSS
68-type MPU interface
1.7 V ~ 3.3 V
RS
A0
A1~A15 15
decoder
VMA
D0 ~D7
68 series
8
E
CSb
~D7
D0 ~
RDb(E)
WRB
WRb
GND
VDD
NJU6854
VCC
WRb(R/W)
RESB
RESb
RESb
reset input
VSS
Serial interface
1.7 V ~ 3.3 V
RS
A0
A1 ~A7 7
decoder
VDD
CSB
CSb
NJU6854
VCC
(CPU)
GND
- 110 -
PORT1
SDA
PORT2
SCL
RESB
RESb
RESb
RESB
reset input
VSS
Ver.2004-06-29
NJU6854
Memo
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
Ver.2004-06-29
- 111 -