DATA SHEET MOS INTERGRATED CIRCUIT µPD16686, 16687 1/128 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM DESCRIPTION The µPD16686 and 16687 are controller/drivers which include display RAM for full-dot LCDs that can provide a four-level gray scale display. These ICs are able to drive full-dot LCDs that contain up to 128 x 128 dots. FEATURES • µPD16686: COM outputs configured on both sides of chip • µPD16687: COM outputs configured on one side of chip • LCD controller/driver with on-chip display RAM • Can operate using single power supply (logic system) in range from +1.7 to +3.6 V. • On-chip booster: Switchable from x2 to x9 modes • Dot display RAM: 128 x 128 x 2 bits • Selection of four levels of gray scales from among 33 possible levels (four-frame rate control + 8 pulse width modulation) • Full dot outputs: 128 segment outputs and 128 common outputs • Static icon outputs: 20 segment outputs and 2 common outputs (same signal is output) • Serial data input and 8-bit parallel data input (i80 series interface and M68 series interface) • On-chip voltage divider resistor • Selectable bias levels: 1/12 to 1/7 bias (normal display), 1/6 or 1/5 bias (partial display) • Duty settings: 1/128 to 1/1 duty • On-chip oscillator ORDERING INFORMATION Part Number Package µ PD16686P Chip µ PD16686W Wafer µ PD16687P Chip µ PD16687W Wafer Remark Purchasing the chip/wafer entails the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representative. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S15548EJ1V0DS00 (1st Edition) Date Published July 2001 NS CP(K) The mark shows major revised points. 1999, 2001 µPD16686, 16687 BLOCK DIAGRAM SEG1 SEG128 COM1 Segment driver Data register TM,S SIGIN1 SIGIN2 TSTIFS TSTRTST TSTVIHL C86 PSX /CS1 CS2 /RD(E) /WR(R,/W) D7(SI) D6(SCL) D5 to D0 RS /RES TESTOUT OSCIN1 OSCIN2 OSCOUT TOSCSYNC CLS COM128 Common driver PCOM1 Pictograph common driver PSEG1 Segment G/S and blink control Pictograph segment driver PSEG20 Display data latch Display data RAM (128 x 128 x 2 bit) Common timing generator Icon data RAM (20 x 2 bit) TFR TFRSYNC TDOF TSISYNC Pictograph common timing generator I/O buffer Address decoder Segment G/S and blink timer Register Command decoder Timing generator Oscillator D/A converter C1,+ C1 - + C9 , C9 DC/DC converter LCD voltage generator Op amp C1A VOUT VRS IRS VR AMPOUTP AMPOUT VLCD VLC1 Remark /xxx indicates active low signals. 2 Data Sheet S15548JJ1V0DS VLC2 VLC3 VLC4 VDD1 VDD2 VSS µPD16686, 16687 PIN CONFIGURATION (PAD LAYOUT) (1) µPD16686 Chip size：3.04 x 13.98 mm2 Chip thickness：485 µm (TYP.) 502 468 M1 1 467 Y X 220 254 M2 221 253 Data Sheet S15548JJ1V0DS 3 µPD16686, 16687 ▪ µPD16686 Pad Layout (1/3) Pad Type X [µ m] Y [µ m] DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY B A A A A A A A A A A A A -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 6575.000 6480.000 6420.000 6360.000 6300.000 6240.000 6180.000 6120.000 6060.000 6000.000 5940.000 5880.000 5820.000 71 72 73 74 75 76 77 78 79 80 81 82 83 14 DUMMY 15 PSEG1 A A -1385.000 -1385.000 16 PSEG1 17 PSEG2 A A 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 4 Pin Name PSEG2 PSEG3 PSEG3 PSEG4 PSEG4 PSEG5 PSEG5 PSEG6 PSEG6 PSEG7 PSEG7 PSEG8 PSEG8 PSEG9 PSEG9 PSEG10 PSEG10 VSS VRS VRS DUMMY AMPOUTP AMPOUTP AMPOUT AMPOUT VR VR VLC4 VLC4 VLC3 VLC3 VLC2 VLC2 VLC1 VLC1 VLCD VLCD VSS VOUT VOUT VSS DUMMY DUMMY DUMMY C9C9C9+ C9+ C8C8C8+ C8+ C7- Pad Type X [µ m] Y [µ m] Pad No. C7C7+ C7+ C6C6C6+ C6+ C5C5C5+ C5+ C4C4- A A A A A A A A A A A A A -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 2340.000 2280.000 2220.000 2160.000 2100.000 2040.000 1980.000 1920.000 1860.000 1800.000 1740.000 1680.000 1620.000 141 142 143 144 145 146 147 148 149 150 151 152 153 5760.000 5700.000 84 C4+ 85 C4+ A A -1385.000 -1385.000 1560.000 1500.000 -1385.000 -1385.000 5640.000 5580.000 86 C387 C3- A A -1385.000 -1385.000 1440.000 1380.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 5520.000 5460.000 5400.000 5340.000 5280.000 5220.000 5160.000 5100.000 5040.000 4980.000 4920.000 4860.000 4800.000 4740.000 4680.000 4620.000 4560.000 4500.000 4440.000 4380.000 4320.000 4260.000 4200.000 4140.000 4080.000 4020.000 3960.000 3900.000 3840.000 3780.000 3720.000 3660.000 3600.000 3540.000 3480.000 3420.000 3360.000 3300.000 3240.000 3180.000 3120.000 3060.000 3000.000 2940.000 2880.000 2820.000 2760.000 2700.000 2640.000 2580.000 2520.000 2460.000 2400.000 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 1320.000 1260.000 1200.000 1140.000 1080.000 1020.000 960.000 900.000 840.000 780.000 720.000 660.000 600.000 540.000 480.000 420.000 360.000 300.000 240.000 180.000 120.000 60.000 0.000 -60.000 -120.000 -180.000 -240.000 -300.000 -360.000 -420.000 -480.000 -540.000 -600.000 -660.000 -720.000 -780.000 -840.000 -900.000 -960.000 -1020.000 -1080.000 -1140.000 -1200.000 -1260.000 -1320.000 -1380.000 -1440.000 -1500.000 -1560.000 -1620.000 -1680.000 -1740.000 -1800.000 Pad No. 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Pin Name C3+ C3+ C2C2C2+ C2+ C1C1C1+ C1+ C1A C1A VDD2 VDD2 VDD2 VDD1 VDD1 VDD1 VSS VSS VSS CLS CLS VDD1 TM,S TM,S VSS C86 C86 PSX PSX VDD1 IRS IRS VSS /CS1 /CS1 CS2 CS2 VDD1 /RES /RES RS RS VSS /WR (R,/W) /WR (R,/W) /RD (E) /RD (E) VDD1 D7 (SI) D7 (SI) D6 (SCL) Data Sheet S15548JJ1V0DS Pad Type X [ µ m] Y [µ m] A A A A A A A A A A A A A -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1860.000 -1920.000 -1980.000 -2040.000 -2100.000 -2160.000 -2220.000 -2280.000 -2340.000 -2400.000 -2460.000 -2520.000 -2580.000 154 TFRSYNC 155 TFRSYNC A A -1385.000 -1385.000 -2640.000 -2700.000 156 TFR 157 TFR A A -1385.000 -1385.000 -2760.000 -2820.000 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -2880.000 -2940.000 -3000.000 -3060.000 -3120.000 -3180.000 -3240.000 -3300.000 -3360.000 -3420.000 -3480.000 -3540.000 -3600.000 -3660.000 -3720.000 -3780.000 -3840.000 -3900.000 -3960.000 -4020.000 -4080.000 -4140.000 -4200.000 -4260.000 -4320.000 -4380.000 -4440.000 -4500.000 -4560.000 -4620.000 -4680.000 -4740.000 -4800.000 -4860.000 -4920.000 -4980.000 -5040.000 -5100.000 -5160.000 -5220.000 -5280.000 -5340.000 -5400.000 -5460.000 -5520.000 -5580.000 -5640.000 -5700.000 -5760.000 -5820.000 -5880.000 -5940.000 -6000.000 Pin Name D6 (SCL) D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 TDOF TDOF OSCIN1 OSCIN1 OSCIN2 OSCIN2 OSCOUT OSCOUT TOSCSYNC TOSCSYNC TSISYNC TSISYNC VSS SIGIN1 SIGIN1 VDD1 SIGIN2 SIGIN2 VSS TESTOUT TESTOUT TSTIFS TSTIFS TSTRTST TSTRTST TSTVIHL TSTVIHL VSS PSEG11 PSEG11 PSEG12 PSEG12 PSEG13 PSEG13 PSEG14 PSEG14 PSEG15 PSEG15 PSEG16 PSEG16 PSEG17 PSEG17 PSEG18 PSEG18 PSEG19 PSEG19 PSEG20 PSEG20 DUMMY DUMMY DUMMY DUMMY DUMMY µPD16686, 16687 ▪ µPD16686 Pad Layout (2/3) Pad Type X [ µ m] Y [ µ m] Pad No. Pin Name DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY PCOM1 A A A A A A A A A B B A A -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1185.000 -1090.000 -1030.000 -6060.000 -6120.000 -6180.000 -6240.000 -6300.000 -6360.000 -6420.000 -6480.000 -6540.000 -6635.000 -6766.600 -6766.600 -6766.600 281 282 283 284 285 286 287 288 289 290 291 292 293 224 PCOM1 225 COM41 A A -970.000 -910.000 226 COM42 227 COM43 A A 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 A A A A A A A A A A A A A A A A A A A A A A A A B B B B B A A A A A A A A A A A A A A A A A A A A A A A A Pad No. 211 212 213 214 215 216 217 218 219 220 221 222 223 Pin Name COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 COM80 COM82 COM84 COM86 COM88 COM90 COM92 COM94 COM96 COM98 COM100 Pad Type X [µ m] Y [ µ m] Pad No. Pin Name COM102 COM104 COM106 COM108 COM110 COM112 COM114 COM116 COM118 COM120 COM122 COM124 COM126 A A A A A A A A A A A A A 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 -4830.000 -4770.000 -4710.000 -4650.000 -4590.000 -4530.000 -4470.000 -4410.000 -4350.000 -4290.000 -4230.000 -4170.000 -4110.000 351 352 353 354 355 356 357 358 359 360 361 362 363 -6766.600 -6766.600 294 COM128 295 DUMMY A A 1296.600 1296.600 -850.000 -790.000 -6766.600 -6766.600 296 DUMMY 297 DUMMY A A -730.000 -670.000 -610.000 -550.000 -490.000 -430.000 -370.000 -310.000 -250.000 -190.000 -130.000 -70.000 -10.000 50.000 110.000 170.000 230.000 290.000 350.000 410.000 470.000 530.000 590.000 650.000 745.000 875.000 1005.000 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6495.000 -6365.000 -6270.000 -6210.000 -6150.000 -6090.000 -6030.000 -5970.000 -5910.000 -5850.000 -5790.000 -5730.000 -5670.000 -5610.000 -5550.000 -5490.000 -5430.000 -5370.000 -5310.000 -5250.000 -5190.000 -5130.000 -5070.000 -5010.000 -4950.000 -4890.000 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A SEG128 SEG127 SEG126 SEG125 SEG124 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 SEG99 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 Pad Type X [µ m] Y [ µ m] SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 A A A A A A A A A A A A A 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 -630.000 -570.000 -510.000 -450.000 -390.000 -330.000 -270.000 -210.000 -150.000 -90.000 -30.000 30.000 90.000 -4050.000 -3990.000 364 SEG62 365 SEG61 A A 1296.600 1296.600 150.000 210.000 1296.600 1296.600 -3930.000 -3870.000 366 SEG60 367 SEG59 A A 1296.600 1296.600 270.000 330.000 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 -3810.000 -3750.000 -3690.000 -3630.000 -3570.000 -3510.000 -3450.000 -3390.000 -3330.000 -3270.000 -3210.000 -3150.000 -3090.000 -3030.000 -2970.000 -2910.000 -2850.000 -2790.000 -2730.000 -2670.000 -2610.000 -2550.000 -2490.000 -2430.000 -2370.000 -2310.000 -2250.000 -2190.000 -2130.000 -2070.000 -2010.000 -1950.000 -1890.000 -1830.000 -1770.000 -1710.000 -1650.000 -1590.000 -1530.000 -1470.000 -1410.000 -1350.000 -1290.000 -1230.000 -1170.000 -1110.000 -1050.000 -990.000 -930.000 -870.000 -810.000 -750.000 -690.000 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 390.000 450.000 510.000 570.000 630.000 690.000 750.000 810.000 870.000 930.000 990.000 1050.000 1110.000 1170.000 1230.000 1290.000 1350.000 1410.000 1470.000 1530.000 1590.000 1650.000 1710.000 1770.000 1830.000 1890.000 1950.000 2010.000 2070.000 2130.000 2190.000 2250.000 2310.000 2370.000 2430.000 2490.000 2550.000 2610.000 2670.000 2730.000 2790.000 2850.000 2910.000 2970.000 3030.000 3090.000 3150.000 3210.000 3270.000 3330.000 3390.000 3450.000 3510.000 Data Sheet S15548JJ1V0DS SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 5 µPD16686, 16687 ▪ µPD16686 Pad Layout (3/3) Pad Type X [µ m] Y [µ m] Pad No. Pin Name SEG5 SEG4 SEG3 SEG2 SEG1 DUMMY DUMMY DUMMY COM127 COM125 COM123 COM121 COM119 A A A A A A A A A A A A A 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 3570.000 3630.000 3690.000 3750.000 3810.000 3870.000 3930.000 3990.000 4050.000 4110.000 4170.000 4230.000 4290.000 491 492 493 494 495 496 497 498 499 500 501 502 COM8 COM7 COM6 COM5 COM4 OCM3 COM2 COM1 PCOM1 PCOM1 DUMMY DUMMY 434 COM117 435 COM115 A A 1296.600 1296.600 4350.000 4410.000 436 COM113 437 COM111 A A 1296.600 1296.600 4470.000 4530.000 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A B B B B B A A A A A A A A A A A A A A A A A A A 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1030.000 900.000 770.000 675.000 615.000 555.000 495.000 435.000 375.000 315.000 255.000 195.000 135.000 75.000 15.000 -45.000 -105.000 -165.000 -225.000 -285.000 -345.000 -405.000 4590.000 4650.000 4710.000 4770.000 4830.000 4890.000 4950.000 5010.000 5070.000 5130.000 5190.000 5250.000 5310.000 5370.000 5430.000 5490.000 5550.000 5610.000 5670.000 5730.000 5790.000 5850.000 5910.000 5970.000 6030.000 6090.000 6150.000 6210.000 6270.000 6365.000 6495.000 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 Pad No. Pin Name 421 422 423 424 425 426 427 428 429 430 431 432 433 6 COM109 COM107 COM105 COM103 COM101 COM99 COM97 COM95 COM93 COM91 COM89 COM87 COM85 COM83 COM81 COM40 COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 COM31 COM30 COM29 COM28 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 Pad Type X [µ m] Y [µ m] A A A A A A A A A A A B -465.000 -525.000 -585.000 -645.000 -705.000 -765.000 -825.000 -885.000 -945.000 -1005.000 -1065.000 -1160.000 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 Pad type A: Pad size(Al) : 48 x 106 µ m2 TYP. Pad size(Through hall) :10 x 60.48 µ m2 TYP. Bump size : 35 x 92.5 µ m2 TYP. Bump height : 17 µ m TYP. Pad type B: Pad size(Al) : 108 x 106 µ m2 TYP. Pad size(Through hall) :78 x 60.48 µ m2 TYP. Bump size : 110 x 92.5 µ m2 TYP. Bump height : 17 µ m TYP. Alingment mark Alingment mark coordinate X [µ m] Y [µ m] M1 M2 -1382.00 1220.00 6830.00 -6760.00 Alingment mark form (µ m) 124 M1 56 168 Mark point 56 M2 56 Mark point 112 56 168 Data Sheet S15548JJ1V0DS µPD16686, 16687 (2) µPD16687 Chip size：3.04 x 13.98 mm2 Chip thickness：485 µm (TYP.) 502 468 M1 1 467 Y X 220 254 M2 221 253 Data Sheet S15548JJ1V0DS 7 µPD16686, 16687 ▪ µPD16687 Pad Layout (1/3) Pad No. Pad Type X [µ m] Y [µ m] Pad No. C7C7+ C7+ C6C6C6+ C6+ C5C5C5+ A A A A A A A A A A -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 2340.000 2280.000 2220.000 2160.000 2100.000 2040.000 1980.000 1920.000 1860.000 1800.000 141 142 143 144 145 146 147 148 149 150 5940.000 5880.000 5820.000 81 C5+ 82 C483 C4- A A A -1385.000 -1385.000 -1385.000 1740.000 1680.000 1620.000 -1385.000 -1385.000 5760.000 5700.000 84 C4+ 85 C4+ A A -1385.000 -1385.000 A A -1385.000 -1385.000 5640.000 5580.000 86 C387 C3- A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 5520.000 5460.000 5400.000 5340.000 5280.000 5220.000 5160.000 5100.000 5040.000 4980.000 4920.000 4860.000 4800.000 4740.000 4680.000 4620.000 4560.000 4500.000 4440.000 4380.000 4320.000 4260.000 4200.000 4140.000 4080.000 4020.000 3960.000 3900.000 3840.000 3780.000 3720.000 3660.000 3600.000 3540.000 3480.000 3420.000 3360.000 3300.000 3240.000 3180.000 3120.000 3060.000 3000.000 2940.000 2880.000 2820.000 2760.000 2700.000 2640.000 2580.000 2520.000 2460.000 2400.000 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Pad Type X [mm] Y [mm] Pad No. DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY B A A A A A A A A A -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 6575.000 6480.000 6420.000 6360.000 6300.000 6240.000 6180.000 6120.000 6060.000 6000.000 71 72 73 74 75 76 77 78 79 80 11 DUMMY 12 DUMMY 13 DUMMY A A A -1385.000 -1385.000 -1385.000 14 DUMMY 15 PSEG1 A A 16 PSEG1 17 PSEG2 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 1 2 3 4 5 6 7 8 9 10 8 Pin Name PSEG2 PSEG3 PSEG3 PSEG4 PSEG4 PSEG5 PSEG5 PSEG6 PSEG6 PSEG7 PSEG7 PSEG8 PSEG8 PSEG9 PSEG9 PSEG10 PSEG10 VSS VRS VRS DUMMY AMPOUTP AMPOUTP AMPOUT AMPOUT VR VR VLC4 VLC4 VLC3 VLC3 VLC2 VLC2 VLC1 VLC1 VLCD VLCD VSS VOUT VOUT VSS DUMMY DUMMY DUMMY C9C9C9+ C9+ C8C8C8+ C8+ C7- 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Pin Name C3+ C3+ C2C2C2+ C2+ C1C1C1+ C1+ C1A C1A VDD2 VDD2 VDD2 VDD1 VDD1 VDD1 VSS VSS VSS CLS CLS VDD1 TM,S TM,S VSS C86 C86 PSX PSX VDD1 IRS IRS VSS /CS1 /CS1 CS2 CS2 VDD1 /RES /RES RS RS VSS /WR (R,/W) /WR (R,/W) /RD (E) /RD (E) VDD1 D7 (SI) D7 (SI) D6 (SCL) Pad Type X [µ m] Y [µ m] A A A A A A A A A A -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1860.000 -1920.000 -1980.000 -2040.000 -2100.000 -2160.000 -2220.000 -2280.000 -2340.000 -2400.000 151 D1 152 D0 153 D0 A A A -1385.000 -1385.000 -1385.000 -2460.000 -2520.000 -2580.000 1560.000 1500.000 154 TFRSYNC 155 TFRSYNC A A -1385.000 -1385.000 -2640.000 -2700.000 -1385.000 -1385.000 1440.000 1380.000 156 TFR 157 TFR A A -1385.000 -1385.000 -2760.000 -2820.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 1320.000 1260.000 1200.000 1140.000 1080.000 1020.000 960.000 900.000 840.000 780.000 720.000 660.000 600.000 540.000 480.000 420.000 360.000 300.000 240.000 180.000 120.000 60.000 0.000 -60.000 -120.000 -180.000 -240.000 -300.000 -360.000 -420.000 -480.000 -540.000 -600.000 -660.000 -720.000 -780.000 -840.000 -900.000 -960.000 -1020.000 -1080.000 -1140.000 -1200.000 -1260.000 -1320.000 -1380.000 -1440.000 -1500.000 -1560.000 -1620.000 -1680.000 -1740.000 -1800.000 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -2880.000 -2940.000 -3000.000 -3060.000 -3120.000 -3180.000 -3240.000 -3300.000 -3360.000 -3420.000 -3480.000 -3540.000 -3600.000 -3660.000 -3720.000 -3780.000 -3840.000 -3900.000 -3960.000 -4020.000 -4080.000 -4140.000 -4200.000 -4260.000 -4320.000 -4380.000 -4440.000 -4500.000 -4560.000 -4620.000 -4680.000 -4740.000 -4800.000 -4860.000 -4920.000 -4980.000 -5040.000 -5100.000 -5160.000 -5220.000 -5280.000 -5340.000 -5400.000 -5460.000 -5520.000 -5580.000 -5640.000 -5700.000 -5760.000 -5820.000 -5880.000 -5940.000 -6000.000 Data Sheet S15548JJ1V0DS Pin Name D6 (SCL) D5 D5 D4 D4 D3 D3 D2 D2 D1 TDOF TDOF OSCIN1 OSCIN1 OSCIN2 OSCIN2 OSCOUT OSCOUT TOSCSYNC TOSCSYNC TSISYNC TSISYNC VSS SIGIN1 SIGIN1 VDD1 SIGIN2 SIGIN2 VSS TESTOUT TESTOUT TSTIFS TSTIFS TSTRTST TSTRTST TSTVIHL TSTVIHL VSS PSEG11 PSEG11 PSEG12 PSEG12 PSEG13 PSEG13 PSEG14 PSEG14 PSEG15 PSEG15 PSEG16 PSEG16 PSEG17 PSEG17 PSEG18 PSEG18 PSEG19 PSEG19 PSEG20 PSEG20 DUMMY DUMMY DUMMY DUMMY DUMMY µPD16686, 16687 ▪ µPD16687 Pad Layout (2/3) Pad Type X [µ m] Y [µ m] Pad No. Pin Name DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY A A A A A A A A A B -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -1385.000 -6060.000 -6120.000 -6180.000 -6240.000 -6300.000 -6360.000 -6420.000 -6480.000 -6540.000 -6635.000 281 282 283 284 285 286 287 288 289 290 221 DUMMY 222 DUMMY 223 PCOM1 B A A -1185.000 -1090.000 -1030.000 224 PCOM1 225 SEG128 A A 226 SEG127 227 SEG126 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 Pad Pin Name No. 211 212 213 214 215 216 217 218 219 220 SEG125 SEG124 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 SEG107 SEG106 SEG105 SEG104 SEG103 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY SEG102 SEG101 SEG100 SEG99 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 Pad Type X [µ m] Y [µ m] SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 A A A A A A A A A A 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 -4770.000 -4710.000 -4650.000 -4590.000 -4530.000 -4470.000 -4410.000 -4350.000 -4290.000 -4230.000 351 352 353 354 355 356 357 358 359 360 -6766.600 -6766.600 -6766.600 291 SEG69 292 SEG68 293 SEG67 A A A 1296.600 1296.600 1296.600 -970.000 -910.000 -6766.600 -6766.600 294 SEG66 295 SEG65 A A A A -850.000 -790.000 -6766.600 -6766.600 296 SEG64 297 SEG63 A A A A A A A A A A A A A A A A A A A A A A A B B B B B A A A A A A A A A A A A A A A A A A A A A A A A A -730.000 -670.000 -610.000 -550.000 -490.000 -430.000 -370.000 -310.000 -250.000 -190.000 -130.000 -70.000 -10.000 50.000 110.000 170.000 230.000 290.000 350.000 410.000 470.000 530.000 590.000 685.000 815.000 945.000 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6766.600 -6495.000 -6365.000 -6270.000 -6210.000 -6150.000 -6090.000 -6030.000 -5970.000 -5910.000 -5850.000 -5790.000 -5730.000 -5670.000 -5670.000 -5550.000 -5490.000 -5430.000 -5370.000 -5310.000 -5250.000 -5190.000 -5130.000 -5070.000 -5010.000 -4950.000 -4890.000 -4830.000 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 Pad Type X [ µ m] Y [µ m] SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 DUMMY A A A A A A A A A A 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 -570.000 -510.000 -450.000 -390.000 -330.000 -270.000 -210.000 -150.000 -90.000 -30.000 -4170.000 -4110.000 -4050.000 361 DUMMY 362 DUMMY 363 COM128 A A A 1296.600 1296.600 1296.600 30.000 90.000 150.000 1296.600 1296.600 -3990.000 -3930.000 364 COM127 365 COM126 A A 1296.600 1296.600 210.000 270.000 A A 1296.600 1296.600 -3870.000 -3810.000 366 COM125 367 COM124 A A 1296.600 1296.600 330.000 390.000 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 -3750.000 -3690.000 -3630.000 -3570.000 -3510.000 -3450.000 -3390.000 -3330.000 -3270.000 -3210.000 -3150.000 -3090.000 -3030.000 -2970.000 -2910.000 -2850.000 -2790.000 -2730.000 -2670.000 -2610.000 -2550.000 -2490.000 -2430.000 -2370.000 -2310.000 -2250.000 -2190.000 -2130.000 -2070.000 -2010.000 -1950.000 -1890.000 -1830.000 -1770.000 -1710.000 -1650.000 -1590.000 -1530.000 -1470.000 -1410.000 -1350.000 -1290.000 -1230.000 -1170.000 -1110.000 -1050.000 -990.000 -930.000 -870.000 -810.000 -750.000 -690.000 -630.000 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 450.000 510.000 570.000 630.000 690.000 750.000 810.000 870.000 930.000 990.000 1050.000 1110.000 1170.000 1230.000 1290.000 1350.000 1410.000 1470.000 1530.000 1590.000 1650.000 1710.000 1770.000 1830.000 1890.000 1950.000 2010.000 2070.000 2130.000 2190.000 2250.000 2310.000 2370.000 2430.000 2490.000 2550.000 2610.000 2670.000 2730.000 2790.000 2850.000 2910.000 2970.000 3030.000 3090.000 3150.000 3210.000 3270.000 3330.000 3390.000 3450.000 3510.000 3570.000 Data Sheet S15548JJ1V0DS Pad Pin Name No. COM123 COM122 COM121 COM120 COM119 COM118 COM117 COM116 COM115 COM114 COM113 COM112 COM111 COM110 COM109 COM108 COM107 COM106 COM105 COM104 COM103 COM102 COM101 COM100 COM99 COM98 COM97 COM96 COM95 COM94 COM93 COM92 COM91 COM90 COM89 COM88 COM87 COM86 COM85 COM84 COM83 COM82 COM81 COM80 COM79 COM78 COM77 COM76 COM75 COM74 COM73 COM72 COM71 9 µPD16686, 16687 ▪ µPD16687 Pad Layout (3/3) Pad Type X [ µ m] Y [µ m] Pad No. COM70 COM69 COM68 COM67 COM66 COM65 COM64 COM63 COM62 COM61 A A A A A A A A A A 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 3630.000 3690.000 3750.000 3810.000 3870.000 3930.000 3990.000 4050.000 4110.000 4170.000 491 492 493 494 495 496 497 498 499 500 431 COM60 432 COM59 433 COM58 A A A 1296.600 1296.600 1296.600 4230.000 4290.000 4350.000 434 COM57 435 COM56 A A 1296.600 1296.600 4410.000 4470.000 436 COM55 437 COM54 A A 1296.600 1296.600 4530.000 4590.000 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 A A A A A A A A A A A A A A A A A A A A A A A A A A A A B B B B B A A A A A A A A A A A A A A A A A A A A 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 1296.600 970.000 840.000 710.000 615.000 555.000 495.000 435.000 375.000 315.000 255.000 195.000 135.000 75.000 15.000 -45.000 -105.000 -165.000 -225.000 -285.000 -345.000 -405.000 -465.000 -525.000 4650.000 4710.000 4770.000 4830.000 4890.000 4950.000 5010.000 5070.000 5130.000 5190.000 5250.000 5310.000 5370.000 5430.000 5490.000 5550.000 5610.000 5670.000 5730.000 5790.000 5850.000 5910.000 5970.000 6030.000 6090.000 6150.000 6210.000 6270.000 6365.000 6495.000 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 Pad Pin Name No. 421 422 423 424 425 426 427 428 429 430 10 COM53 COM52 COM51 COM50 COM49 COM48 COM47 COM46 COM45 COM44 COM43 COM42 COM41 COM40 COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 COM31 COM30 COM29 COM28 COM27 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 Pin Name COM6 COM5 COM4 OCM3 COM2 COM1 PCOM1 PCOM1 DUMMY DUMMY Pad Type X [µ m] Y [µ m] A A A A A A A A A B -585.000 -645.000 -705.000 -765.000 -825.000 -885.000 -945.000 -1005.000 -1065.000 -1160.000 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 6766.600 Pad type A: Pad size(Al) : 48 x 106 µ m2 TYP. Pad size(Through hall) :10 x 60.48 µ m2 TYP. Bump size : 35 x 92.5 µ m2 TYP. Bump height : 17 µ m TYP. Pad type B: Pad size(Al) : 108 x 106 µ m2 TYP. Pad size(Through hall) :78 x 60.48 µ m2 TYP. Bump size : 110 x 92.5 µ m2 TYP. Bump height : 17 µ m TYP. Alingment mark Alingment mark coordinate X [µ m] Y [µ m] M1 M2 -1382.00 1220.00 Alingment mark form (µ m) 124 M1 56 168 Mark point 56 M2 56 Mark point 112 56 168 Data Sheet S15548JJ1V0DS 6830.00 -6760.00 µPD16686, 16687 TABLE OF CONTENTS 1. PIN FUNCTIONS.................................................................................................................................... 14 1.1 Power Supply System Pins ............................................................................................................................14 1.2 Logic System Pins ..........................................................................................................................................15 1.3 Driver-Related Pins .........................................................................................................................................17 1.4 Test Pins ..........................................................................................................................................................18 2. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS.................................. 19 3. DESCRIPTION OF FUNCTIONS ........................................................................................................... 20 3.1 CPU Interface...................................................................................................................................................20 3.1.1 Selection of interface type ...........................................................................................................................20 3.1.2 Parallel interface ..........................................................................................................................................20 3.1.3 Serial interface.............................................................................................................................................22 3.1.4 Chip select ...................................................................................................................................................22 3.1.5 Display data RAM and on-chip register access ...........................................................................................22 3.2 Display Data RAM............................................................................................................................................25 3.2.1 Display data RAM ........................................................................................................................................25 3.2.2 X address circuit ..........................................................................................................................................26 3.2.3 Column address circuit ................................................................................................................................26 3.2.4 Y address circuit ..........................................................................................................................................26 3.2.5 Common scan circuit ...................................................................................................................................26 3.2.6 Display start line set.....................................................................................................................................28 3.2.7 Display data latch circuit ..............................................................................................................................28 3.3 Blink/Reverse Display Circuit.........................................................................................................................29 3.4 Oscillator..........................................................................................................................................................31 3.5 Display Timing Generator...............................................................................................................................35 3.6 Power Supply Circuit ......................................................................................................................................37 3.6.1 Power supply circuit.....................................................................................................................................37 3.6.2 Booster ........................................................................................................................................................37 3.6.3 Voltage regulator .........................................................................................................................................39 3.6.4 Use of op amp for level power supply control ..............................................................................................42 3.6.5 Application examples of power supply circuits.............................................................................................43 3.7 LCD Display Drivers........................................................................................................................................46 3.7.1 Full-dot pulse width modulation ...................................................................................................................46 3.7.2 Full-dot frame rate control............................................................................................................................51 3.7.3 Line shift driver ............................................................................................................................................52 3.7.4 Display size settings ....................................................................................................................................54 3.7.5 Setting of LCD AC driver's inversion cycle and AC driver's inversion position.............................................54 Data Sheet S15548JJ1V0DS 11 µPD16686, 16687 3.8 Display Modes .................................................................................................................................................56 3.8.1 Partial display mode ....................................................................................................................................56 3.8.2 Monochrome (black/white) display...............................................................................................................58 3.8.3 Icon display..................................................................................................................................................60 3.9 Reset ................................................................................................................................................................62 4. COMMANDS .......................................................................................................................................... 63 4.1 Control Register 1 (R0) ...................................................................................................................................64 4.2 Control Register 2 (R1) ...................................................................................................................................65 4.3 Reset Command (R2) ......................................................................................................................................66 4.4 X Address Register (R3) .................................................................................................................................66 4.5 Y Address Register (R4) .................................................................................................................................66 4.6 Duty Setting Register (R5)..............................................................................................................................67 4.7 AC Driver Inversion Cycle Register (R6) .......................................................................................................67 4.8 AC Driver Inversion Position Shift Register (R7)..........................................................................................68 4.9 Partial AC Driver Inversion Cycle Register (R8) ...........................................................................................68 4.10 Partial AC Driver Inversion Position Shift Register (R9)............................................................................69 4.11 Partial Display Mode Setting (R10) ..............................................................................................................69 4.12 Display Memory Access Register (R11) ......................................................................................................70 4.13 Display Start Line Set (R12) .........................................................................................................................70 4.14 Blink X Address Register (R13)....................................................................................................................70 4.15 Blink Start Line Address Register (R14) .....................................................................................................71 4.16 Blink End Line Address Register (R15).......................................................................................................71 4.17 Blink Data Memory (R16) ..............................................................................................................................71 4.18 Inverted X Address Register (R17) ..............................................................................................................72 4.19 Inversion Start Line Address Register (R18) ..............................................................................................72 4.20 Inversion End Line Address Register (R19)................................................................................................72 4.21 Inverted Data Memory (R20) .........................................................................................................................73 4.22 Partial Start Line Address Register (R21) ...................................................................................................73 4.23 Gray Scale Data Registers 1 to 4 (R23, R24, R25, R26)..............................................................................74 4.24 Partial Gray Scale Data Registers 1 to 4 (R27, R28, R29, R30) ..................................................................74 4.25 Power System Control 1 (R32) .....................................................................................................................75 4.26 Power System Control 2 (R33) .....................................................................................................................76 4.27 Power System Control 3 (R34) .....................................................................................................................77 4.28 Electronic Volume Register (R35)................................................................................................................78 4.29 Partial Electronic Volume Register (R36)....................................................................................................78 4.30 Boost Adjustment Register (R37) ................................................................................................................78 4.31 Static Icon Address (R40).............................................................................................................................79 4.32 Static Icon Data Register (R41) ....................................................................................................................79 4.33 Static Icon Contrast (R42) ............................................................................................................................79 4.34 RAM Test Mode Setting (R44) ......................................................................................................................80 4.35 Signature Read (R45) ....................................................................................................................................80 12 Data Sheet S15548JJ1V0DS µPD16686, 16687 5. LIST OF µPD16686, 16687 REGISTERS.............................................................................................. 81 6. POWER SUPPLY SEQUENCE ............................................................................................................. 82 6.1 Power ON Sequence (When Using On-Chip Power Supply, Power Supply ON → Display ON)................82 6.2 Power OFF Sequence (When Using On-Chip Power Supply)......................................................................83 6.3 Power ON Sequence (When Using External Driver Power Supply, Power ON → Display ON).................83 6.4 Power Supply OFF Sequence (When Using External Driver Power Supply)..............................................84 6.5 VOUT, VLCD Voltage Sequence (Power ON → Power OFF).............................................................................85 7. USE OF RAM TEST MODE ................................................................................................................... 86 8. USE OF STANDBY/HALT MODE ......................................................................................................... 87 9. ELECTRICAL SPECIFICATIONS.......................................................................................................... 88 10. CPU INTERFACE (REFERENCE EXAMPLE) .................................................................................... 97 Data Sheet S15548JJ1V0DS 13 µPD16686, 16687 1. PIN FUNCTIONS 1.1 Power Supply System Pins Symbol VDD1 Name Logic power supply pin VDD2 Boost circuit µPD16686 Pad No. µPD16687 Pad No. 103 to 105, 111, 103 to 105, 111, I/O Description − Power supply pin for logic circuit 119, 127, 137, 173 119, 127, 137, 173 100 to 102 100 to 102 − Power supply pin for booster 35, 55, 58, 35, 55, 58, − Ground pin for logic and driver circuits 106 to 108, 114, 106 to 108, 114, 122, 132, 170, 122, 132, 170, 176, 185 176, 185 56, 57 56, 57 − Power supply pin for driver. Output pin for on- power supply pin VSS Logic and driver ground pin VOUT Driver power supply pin chip booster. Connect a 1 µF boost capacitor between this pin and the GND pin. If not using the on-chip booster, a direct driver power supply can be input. 54 to 45 54 to 45 − VLCD, Reference power These are reference power supply pins for the VLC1 to VLC4 supply pins for LCD driver. driver Connect a capacitor between these pins and the GND pin if an internal bias has been selected. C1+, C1− + − C2 , C2 Boost capacitor 97 to 62 97 to 62 − connection pins (1) These are capacitor connection pins for the booster. When using the on-chip booster, C3+, C3− connect a 1 µF capacitor between positive (+) C4+, C4− and negative (-) pins. C5+, C5− C6+, C6− C7+, C7− C8+, C8− C9+, C9− C1A Boost capacitor 98, 99 98, 99 − connection pin (2) This is a capacitor connection pin for boost adjustment. When using the on-chip booster, connect a 1 µF capacitor between this pin and the GND pin. 14 Data Sheet S15548JJ1V0DS µPD16686, 16687 1.2 Logic System Pins (1/2) Symbol PSX Name Select data µPD16686 Pad No. µPD16687 Pad No. 117, 118 117, 118 I/O Description Input This pin is used to select between parallel data transfer input and serial data input. PSX = H: Parallel data input PSX = L: Serial data input /CS1, Chip select CS2 123, 124, 123, 124, 125, 126 125, 126 Input These pins are used for chip select signals. When /CS1 = L (CS2 = H), the chip is active and can perform data input/output operations including command and data I/O. /RD Read (enable) 135, 136 135, 136 Input (E) When i80 series parallel data transfer (/RD) has been selected, the signal at this pin is used to enable read operations. Data is output to the data bus only when this pin is L. When M68 series parallel data transfer (E) has been selected, the signal at this pin is used to enable write operations. Data is written at the falling edge of this signal. /WR Write (read/write) 133, 134 133, 134 Input (R,/W) When i80 series parallel data transfer (/WR) has been selected, the signal at this pin is used to enable write operations. Data is written at the rising edge of this signal. When 68 series parallel data transfer (R,/W) has been selected, this pin is used to determine the direction of data transfer. 0: Write 1: Read C86 Select interface 115, 116 115, 116 Input This pin is used to switch between interface modes (i80 series CPU or M68 series CPU). 0: Selects i80 series CPU mode 1: Selects M68 series CPU mode D0 to D5, Data bus D6 (SCL) (serial clock) bus that connects to an 8-bit or 16-bit standard D7 (SI) (serial input) CPU bus. 153 to 138 153 to 138 I/O These pins comprise an 8-bit bidirectional data When the serial interface has been selected (PSX = L), D6 functions as a serial clock input pin (SCL) and D7 functions as a serial data input pin (SI). In either case, pins D0 to D5 are in high impedance mode. When the chip is not selected, D0 to D7 are in high impedance mode. RS Index 130, 131 130, 131 Input Usually, this pin is connected to the LSB of the register/data, standard CPU address bus and is used to command distinguish between data from index registers selection and data/commands. RS = H: Indicates that data from D0 to D7 is data/command RS = L: Indicates that data from D0 to D7 is index register contents Data Sheet S15548JJ1V0DS 15 µPD16686, 16687 (2/2) Symbol /RES Name Reset µPD16686 Pad No. µPD16687 Pad No. 128, 129 128, 129 I/O Input Description When /RES is low, an internal reset is performed. The reset operation is executed at the /RES signal level. CLS Select clock 109, 110 109, 110 Input division This pin is used to select whether or not to use the divider within the display clock oscillator. CLS = H: Use divider CLS = L: Do not use divider When using an external clock, the CLS = L setting is input via the OSCIN1 and OSCIN2 pins as normal and partial clocks respectively. When CLS = H, clock input is via the OSCIN1 pin only. IRS VLCD regulation 120, 121 120, 121 Input This pin is used to select the resistor that is used for VLCD voltage regulation. IRS = H: Uses internal resistor IRS = L: Does not use internal resistor. The VLCD voltage level is regulated using the external voltage division resistor that is connected to the VR pin. SIGIN1, Signature setting 171, 172, 171, 172, SIGIN2 pins 174, 175 174, 175 Input These pins can be used to set a unique signature for the IC. The signal set via these pins can subsequently be read from the signature read register (R45). OSCIN1 Oscillation signal 160, 161 160, 161 Input pins A resistor can be inserted between OSCIN1 and OSCOUT, and OSCIN2 and OSCOUT. When using an external oscillator, a clock signal is input via OSCIN2 162, 163 162, 163 Input the OSCIN pins according to the CLS pin's status and the OSCOUT pin is left unconnected. OSCOUT 164, 165 164, 165 Output The wiring between OSCIN1-OSCOUT and OSCIN2-OSCOUT must be as short as possible, and use after proper evalluation. 16 Data Sheet S15548JJ1V0DS µPD16686, 16687 1.3 Driver-Related Pins Symbol SEG1 to Name Segment µPD16686 Pad No. µPD16687 Pad No. 425 to 298 SEG128 COM1 to 359 to 258, I/O Description Output Segment output pins Output Common output pins Output Segment output pins for static icon Output Common output pins for static icon Input These are op amp input pins for regulating the 250 to 225 Common COM128 498 to 472, 363 to 464, 465 to 429, 471 to 496 294 to 258, 251 to 225 PSEG1 Static segment to PSEG20 PCOM1 Static common VRS Op amp input 15 to 34, 15 to 34, 186 to 205 186 to 205 223, 224, 223, 224, 499, 500 497, 498 36, 37 36, 37 (Same driver waveform is output from two pins.) driving voltage of the LCD. VRS is a reference voltage input for the LCD voltage regulation amplifier. When using the internal drive circuit (i.e., when OP1 = 1), we recommend inserting a 0.1 to 1 µF capacitor between this pin and GND. VR is an input for the op amp's feedback 43, 44 VR connection. Insert this pin between GND and 43, 44 AMPOUT when using the feedback resistor for this input. This pin is valid only when not using an internal resistor for VLCD voltage regulation (i.e., when IRS = L). This pin cannot be used when using the internal resistor for VLCD voltage regulation (i.e., when IRS = H). AMPOUT Op amp output 41, 42 41, 42 Output These are op amp output pins for regulating the driving voltage of the LCD. When not using an internal resistor for VLCD voltage regulation (i.e., when IRS = L), these outputs are connected to 39, 40 AMPOUTP the LCD drive voltage regulation resistor (see 39, 40 3.6.3 Voltage regulator). NEC recommends inserting a 0.1 to 1 µF capacitor between these pins in order to stabilize the internal op amp's output. DUMMY Dummy pin 1 to 14, 38, 1 to 14, 38, 59 to 61, 59 to 61, 206 to 222, 206 to 222, 252 to 257, 251 to 257, 295 to 297, 360 to 362, 426 to 428, 465 to 470, 466 to 471, 499, 500 − Dummy pin These pins are not connected inside IC. Usually, leave these pins open. 501, 502, Data Sheet S15548JJ1V0DS 17 µPD16686, 16687 1. 4 Test Pins Symbol Name µPD16686 Pad No. µPD16686 Pad No. I/O Description TESTOUT Test output 177, 178 177, 178 Output These pins are used when the IC is in test mode. TFR Test output 156, 157 156, 157 Output Usually, leave them open. TFRSYNC Test output 154, 155 154, 155 Output TDOF Test output 158, 159 158, 159 Output TSISYNC Test output 168, 169 168, 169 Output TM,S Test input 112, 113 112, 113 Input This pin is used when the IC is in test mode. Usually, connect to VDD1. TOSCSYNC Test output 166, 167 166, 167 Output This test output pin is used when the IC is in test mode. Usually, leave it open. TSTIFS 179, 180, 179, 180, TSTRTST 181, 182, 181, 182, IC. TSTVIHL 183, 184 183, 184 Normally, connect these pins to VSS. 18 Test input Input Data Sheet S15548JJ1V0DS These pins are used to set a test mode for the µPD16686, 16687 2. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS The I/O circuit type of each pin and recommended connection of unused pins are described below. Pin Name Input Type I/O Recommended Connection of Unused Pins Notes Note 1 PSX Schmitt trigger Input Mode setting pin /CS1 Filter Input Connect to VSS − CS2 Filter Input Connect to VDD1 − /RD(E) Filter Input Connect to VDD1 (i80 series interface), connect to VDD1 or − VSS (serial interface) /WR(R,/W) Input C86 Schmitt trigger Input D0 to D5 Filter I/O Leave open − D6(SCL) Filter I/O − − D7(SI) Filter I/O − RS Filter Input TESTOUT − /RES Schmitt trigger Output Input Connect to VDD1 or VSS (serial interface) − Filter Mode setting pin Register setting pin Note 1 − Note 2 Leave open − Connect to VDD1 − CLS Schmitt trigger Input Mode setting pin Note 1 IRS Schmitt trigger Input Mode setting pin Note 1 SIGIN1 Schmitt trigger Input Connect to VDD1 or VSS − SIGIN2 Schmitt trigger Input Connect to VDD1 or VSS − OSCIN1 CMOS Input − − OSCIN2 CMOS Input Connect to VDD1 or VSS (CLS = H) − OSCOUT − Output Leave open (when using external clock) − TFR CMOS Output Leave open − TFRSYNC CMOS Output Leave open − TDOF CMOS Output Leave open − TSISYNC CMOS Output Leave open − TM,S Schmitt trigger TOSCSYNC − TSTIFS Schmitt trigger TSTRTST TSTVIHL Connect to VDD1 − Leave open − Input Connect to VSS (during normal use) − Schmitt trigger Input Connect to VSS (during normal use) − Schmitt trigger Input Connect to VSS (during normal use) − Input Output Notes 1. Connect to either VDD1 or VSS, depending on the mode setting. 2. Input either VDD1 or VSS output from CPU, depending on the mode setting. Data Sheet S15548JJ1V0DS 19 µPD16686, 16687 3. DESCRIPTION OF FUNCTIONS 3.1 CPU Interface 3.1.1 Selection of interface type The µPD16686, 16687 chips transfer data using an 8-bit bidirectional data bus (D7 to D0) or a serial data input (SI). Setting the polarity of the PSX pin as either H (high) or L (low) selects between 8-bit parallel or serial data input, as shown in the following table. CS RS /RD /WR C86 D7 D6 D5 to D0 H: Parallel input PSX CS RS /RD /WR C86 D7 D6 D5 to D0 L: Serial input CS RS Note1 Note1 Note1 SI SCL Hi-ZNote2 Notes 1. Fixed as either H or L 2. Hi-Z: High impedance 3.1.2 Parallel interface When the parallel interface has been selected (PSX = H), setting the C86 pin as either H or L enables a direct connection to an i80 series or M68 series CPU (see table below). C86 CS RS /RD /WR D7 to D0 H: M68 series CPU CS RS E R,/W D7 to D0 L: i80 series CPU CS RS /RD /WR D7 to D0 The data bus signal is identified according to the combination of the RS, /RD(E), and /WR(R,/W) signals, as shown in the following table. Common M68 RS R,/W /RD /WR 1 1 0 1 Reads display data and registers 1 0 1 0 Writes display data and registers 20 i80 Function 0 1 0 1 Prohibited 0 0 1 0 Writes to control index register Data Sheet S15548EJ1V0DS µPD16686, 16687 (1) i80 series parallel interface When i80 series parallel data transfer has been selected, data is written to the µ PD16686, 16687 at the rising edge of the /WR signal. The data is output to the data bus when the /RD signal is L. Figure 3-1. i80 Series Interface Data Bus Status /CS1 (CS2=H) /WR /RD Hi-Z Hi-Z Valid data DBn Data write Data Read (2) M68 series parallel interface When M68 series parallel data transfer has been selected, data is written at the falling edge of the E signal when the R,/W signal is L. During the data read operation, the data bus enters the output status when the R,/W signal is H, outputs valid data at the rising edge of the E signal, and enters the high-impedance state at the falling edge of the R,/W signal (R,/W = L) Figure 3-2. M68 Series Interface Data Bus Status /CS1 (CS2=H) R,/W E Hi-Z DBn Hi-Z Invalid data Valid data Data Sheet S15548EJ1V0DS 21 µPD16686, 16687 3.1.3 Serial interface When the serial interface has been selected (PSX = L), if the chip is active (/CS1 = L, CS2 = H), serial data input (SI) and serial clock input (SCL) can be received. Serial data is read from D7 and then from D6 to D0 on the rising edge of the serial clock, via the serial input pin. This data is synchronized on the eighth serial clock's rising edge and is then converted to parallel data for processing. RS input is used to judge serial input data as display data or command data: when RS = H the data is display/command data and when RS = L the data is index data. When the chip enters active mode, RS input is read at the rising edge after every eighth serial clock and is then used to judge the serial input data. The serial interface signal chart is shown below. Figure 3-3. Serial Interface Signal Chart CS2="H" /CS1 SI D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SCL RS Remarks 1. If the chip is not active, the shift register and counter are reset to their initial settings. 2. The data read function is disabled during serial interface mode. 3. When using SCL wiring, take care concerning the possible effects of terminating reflection and noise from external sources. NEC recommends checking operation with the actual device. 3.1.4 Chip select The µPD16686, 16687 have two chip select pins (/CS1 and CS2). The CPU parallel interface or serial interface can be used only when /CS1 = L and CS2 = H. When chip select is inactive, D0 to D7 are set to high impedance (invalid) and input of RS, /RD, or /WR is not active. If serial interface mode has been set, the shift register and counter are both reset. 3.1.5 Display data RAM and on-chip register access Because only the required cycle time (tcyc) is saisfied when accessing the µPD16686, 16687 from the CPU, high-speed data transfer is possible. There is no need to consider any wait time. No dummy data is needed when writing data. Even when data is read, there is no need for dummy data except in the display memory access register (R11). In other words, dummy data is required only when reading data from the display memory access register (R11). Figure 3-4 illustrates this relationship. 22 Data Sheet S15548EJ1V0DS µPD16686, 16687 Figure 3-4. Write and Read (1/2) Write <CPU> /WR DATA N N+1 <Internal timing> N+2 N+3 Latch BUS holder N N+1 N+2 N+3 Write signal Read (display memory access register) <CPU> /WR /RD DATA N n N n+1 <Internal timing> Address preset Read signal Column address Preset N BUS holder N Address set #n N+2 Increment N + 1 n Dummy read Data Sheet S15548EJ1V0DS n+1 Data read #n n+2 Data read #n + 1 23 µPD16686, 16687 Figure 3-4. Write and Read (2/2) Read (other than display memory access register) <CPU> /WR /RD DATA IRn IR address set #n 24 IRn data IRn register data read IRn+1 IR address set #n + 1 Data Sheet S15548EJ1V0DS IRn + 1 Data IRn + 1 register data read µPD16686, 16687 3.2 Display Data RAM 3.2.1 Display data RAM This is the RAM that is used to store the display's dot data. The RAM configuration is 256 bits (32 x 8 bits) x 128 bits. Any specified bit can be accessed by selecting the corresponding X address and Y address. In the data sent from the CPU, D0 to D7 corresponds to SEGx on the LCD display (see Figure 3-5). The CPU writes data to and reads data from the display RAM via the I/O buffer, and these read/write operations are independent of the signal read operations for the LCD driver. Accordingly, there are no adverse effects (such as flicker) in the LCD display when display data RAM is accessed asynchronously. Figure 3-5. Display Data RAM MSB D7 LSB D6 D5 D4 D3 D2 D1 Pixel 3 D0 Pixel 1 Pixel 2 Pixel 4 LCD panel Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 1 Pixel 2 Pixel 3 Pixel 4 X address 00H X address 01H SEG1 SEG2 D7 D6 D5 D4 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 COM0 COM1 COM2 COM3 COM4 Display data LCD display Data Sheet S15548EJ1V0DS 25 µPD16686, 16687 3.2.2 X address circuit As shown in Figure 3-6, the display data RAM's X address is specified via the X address register (R3). When using X address increment mode (INC = 0: control register 2 (R1)), the specified X address is incremented (by 1) each time a display data read or write operation is executed. The CPU is able to continuously access the display data. The X address is incremented to 1FH, after which the Y address is incremented after each read or write operation and the X address is set back to 00H. For monochrome (black-and-white) display, the X address is incremented to 0FH, after which the Y address is incremented after each read or write operation and the X address is set back to 00H. 3.2.3 Column address circuit When displaying the contents of the display data RAM, the column address corresponds to the SEG output, as shown in Figure 3-6. Similarly, the static icon address corresponds to the PSEG output. As is shown in Tables 3-1 and 3-2, the correspondence between the display RAM's column address and segment output can be inverted using the ADC flag in control register 1 (R0) (segment driver direction selection flag). This reduces the constraints on chip layout when assembling the LCD module. Table 3-1. Relationship Between Column Address and SEG Output SEG Output SEG1 SEG128 ADC 0 00H → Column address → 7FH (D1) 1 7FH ← Column address ← 00H Table 3-2. Relationship Between Column Address for Static Icon and PSEG Output PSEG Output PSEG1 PSEG20 ADC 0 00H → Column address → 04H (D1) 1 04H ← Column address ← 00H 3.2.4 Y address circuit As is shown in Figure 3-6, the Y address register (R4) is used to specify the display data RAM's Y address. When using Y address increment mode (INC = 1: control register 2 (R1)), the specified Y address is incremented (by 1) each time a display data read or write operation is executed. The CPU is able to continuously access the display data. The Y address is incremented to 7FH, after which the X address is incremented after each read or write operation and the Y address is set back to 00H. 3.2.5 Common scan circuit The common scan circuit sets the scan lines for common signals. The scan direction is set using the COMR flag in control register 1 (R0), as shown in Table 3-3. For example, when using 1/80 duty, when COMR = L the scan direction is COM1 → COM80 and when COMR = H, the scan direction is COM80 → COM1 using the COM80 to COM1 pins. Table 3-3. Relationship Between Common Scan Circuit and Scan Direction 26 COMR 0 COM1 → COM128 (D0) 1 COM128 ← COM1 Data Sheet S15548EJ1V0DS µPD16686, 16687 D4 D3 D2 D1 0 0 0 0 0 1 0 0 0 1 1 1 D0 0 1 1 00H 01H Data D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 1FH D7 D6 D5 D4 D3 D2 D1 D0 COM output Line address 00H COM1 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 Start Data Sheet S15548EJ1V0DS ADC Column address COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127 COM128 1 0 LCD output D0 D0 SEG128 00 7F SEG127 01 7E SEG126 02 7D SEG125 03 7C 78 07 SEG8 79 06 SEG7 7A 05 SEG6 SEG5 7B 04 7C 03 SEG4 7D 02 SEG3 SEG2 7F 00 7E 01 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH SEG1 X address Figure 3-6. Configuration of X Address Register 27 µPD16686, 16687 3.2.6 Display start line set As is shown in Figure 3-6, display start line set specifies the Y address that corresponds to the COM1 output for displaying the contents of display data RAM. The display start line set (R12) is used to specify the top line in the display. The screen can be scrolled, overwritten, etc. A 7-bit display start address is set to the display start line register. 3.2.7 Display data latch circuit The display data latch circuit is used for temporary storage of data that is output to the LCD driver from the display data RAM. The display scan command that sets normal or reverse display mode and the display ON/OFF command control latched data so that there is no effect on the data in the display data RAM. 28 Data Sheet S15548EJ1V0DS µPD16686, 16687 3.3 Blink/Reverse Display Circuit The µPD16686, 16687 enable blinking display and reverse display in designated parts of the full dot display. A blinking display is achieved by cycling ON/OFF (level 0 when four-level gray scale mode has been selected) at approximately 1 Hz and reverse display is achieved by inverting the display level value. The area designated for blinking is specified via the blink start/end line address registers (R14 and R15), the blink X address register (R13), and the blink data memory (R16). First, the blinking display's start and end line addresses are selected via the blink start/end line address registers. Next, the blink X address register (R13) and the blink data memory (R16) are used to select the column for the blinking display. The inversion start/end line address registers (R18 and R19), the inverted X address register (R17), and inverted data memory (R20) are used to select the reverse display area. First, the inversion start/end line address registers (R18 and R19) are set to select the line addresses where the reverse display will start and end. Next, the inverted X address register (R17) and the inverted data memory (R20) are used to select the column for the reverse display. The specified blink/inverted X address is incremented (by 1) with each input of blink/reverse display data. The blink RAM and inversion RAM, which have a 128 bit (16 x 8 bit) configuration, are used to store data for blinking display and reverse display respectively. To access the desired bit, simply specify the corresponding X address. The blink/reverse data (data bits D0 to D7 sent from the CPU) correspond to SEGx on the LCD display, as shown in Figure 3-7. After the area and data settings are complete, the BLD bit and IVD bit in the control register 1 (R0) are set to H, at which point the blinking and/or reverse display of data begins. Figure 3-8 illustrates the relationship between the start line address, end line address, blink/reverse data, and LCD display. Table 3-4. Inversion Manipulation and Display Original Level After Inversion Four-level gray scale display mode 0, 0 1, 1 0, 1 1, 0 1, 0 0, 1 1, 1 0, 0 B/W display mode 1 0 0 1 D3 0 0 D2 0 0 1 D1 D0 0 0 1 0 00H 1 01H 1 0FH 1 Data Sheet S15548EJ1V0DS Column address ADC 1 0 LCD output D0 D0 SEG128 00 7F SEG127 01 7E SEG126 02 7D SEG125 03 7C SEG124 04 7B SEG123 05 7A SEG122 08 79 77 08 D7 D6 D5 D4 D3 D2 D1 D0 SEG121 07 78 78 07 SEG9 SEG16 70 0F 79 06 SEG8 SEG15 71 0E 7A 05 SEG7 SEG14 72 0D 7B 04 SEG6 SEG13 73 0C 7C 03 SEG5 SEG12 74 0B 7D 02 SEG4 SEG11 75 0A 7E 01 SEG3 SEG10 76 09 7F 00 SEG2 Data D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SEG1 X address Figure 3-7. Correspomdence Between Blink/Reverse Data and Segments 29 µPD16686, 16687 Figure 3-8. Setting Image of Blink/Reverse Display Area Blink/revese data n n+1 n+2 n+3 n+4 n+5 Start line End line Blinking or reverse display pixels. Example of sequence for setting blink/reverse display Blink/inversion start line address register Blink/inversion end line address register Blink/inverted X address register Blink/inverted data memory Data Write completed ? Yes Control register 1 (BLD, IVD = H) 30 n+6 n+7 001 100 10 00 10 01 10 00 01 01 00 00 10 01 10 0 001 01 00 0 011 00 10 0 011 0010 0 001 0100 Data Sheet S15548EJ1V0DS No µPD16686, 16687 3.4 Oscillator The µPD16686, 16687 include a CR-type oscillator (R external) for normal and partial display, which generates the display clocks. The clocks from this oscillator are controlled via the CLS pin and the DTY flag in the control register 2 (R1). The clock configuration for the display can be set to suit the target system. The functions of this circuit are described below. •The oscillator for normal and partial display is enabled only when resistors RN and RP have been connected. The DTY flag in the control register 2 (R1) and the CLS pin status are used to switch between the oscillation clocks for normal display and partial display modes. •The divider divides the external clock that has been input for the normal oscillator and the normal display into a clock for partial display. The external clock that is input for the partial oscillator and partial display is also divided for the partial display. •The division level is automatically set for the divider based on the relationship between the ON/OFF status of the divider setting pin (CLS pin) and the duty of the specified partial display, as shown in Table 3-5. Figure 3-9. Oscillator Block Selected via DTY/CLS OSCIN1 OSCIN2 Normal display/ partial display oscillator Signal to select division level for partial display OSCOUT MUX TOSCSYNC To graphic driver Partial display divider Normal/partial signal CLS Signal to select division level for static icon display Static icon display divider To static icon driver The relationship between the frame frequency (fFRAME), oscillation frequency (fOSCIN1), and setting duty (in normal display mode) is described below. fFRAME = fOSCIN1 ÷ 8 ÷ N (in four-level gray scale display mode) fFRAME = fOSCIN1 ÷ 4 ÷ N (in B/W display mode) N = 1/N duty (setting duty) Data Sheet S15548EJ1V0DS 31 µPD16686, 16687 Table 3-5. Setting of Division Level for Partial Display and Static Icon Display (1/2) In four-level gray scale display mode (GRAY = L, control register 2 (R1)) Display Normal Display Partial Display Mode Duty Ratio Duty Ratio Division Divider Normal/Partial Source ON/OFF OSCIN1 Select DTY CLS /OSCIN2 1/38 1/25 1/12 Partial Static Icon Division Division Ratio Ratio - 1/12 Comments L(OFF) OSCIN1 L (Normal) Static icon frame frequency: fOSCIN1 /12(division ratio) /32 1/38 H(ON) 1/25 1/1 to 1/80 1/12 1/38 1/25 1/1 OSCIN2 L(OFF) 1/12 1/1 H (Partial) 1/38 1/25 1/4 1/2 1/2 OSCIN1 H(ON) 1/2 1/12 1/12 1/4 Partial frame frequency: fOSCIN2 /8 /38 Partial frame frequency: fOSCIN2 /8 /25 Partial frame frequency: fOSCIN2 /2(division ratio) /8 /12 Partial frame frequency: fOSCIN1 /2(division ratio) /8 /38 Partial frame frequency: fOSCIN1 /2(division ratio) /8 /25 Partial frame frequency: fOSCIN1 /4(division ratio) /8 /12 Static icon frame frequency: fOSCIN2 /4(division ratio) /32 Static icon frame frequency: fOSCIN2 /4(division ratio) /32 Static icon frame frequency: fOSCIN2 /4(division ratio) /32 Static icon frame frequency: fOSCIN1 /12(division ratio) /32 Static icon frame frequency: fOSCIN1 /12(division ratio) /32 Static icon frame frequency: fOSCIN1 /12(division ratio) /32 1/38 1/25 1/12 L(OFF) OSCIN1 L (Normal) - 1/16 Static icon frame frequency: fOSCIN1 /16(division ratio) /32 1/38 1/25 1/81 to 1/96 H(ON) 1/12 1/38 1/25 1/1 OSCIN2 L(OFF) 1/1 H (Partial) 1/12 1/38 Four-level 1/25 gray scale 1/12 GRAY = L 1/38 1/25 1/12 1/38 1/25 1/97 to 1/112 1/4 1/2 1/2 OSCIN1 H(ON) 1/4 1/16 1/8 Partial frame frequency: fOSCIN2 /8 /38 Partial frame frequency: fOSCIN2 /8 /25 Partial frame frequency: fOSCIN2 /2(division ratio) /8 /12 Partial frame frequency: fOSCIN1 /2(division ratio) /8 /38 Partial frame frequency: fOSCIN1 /4(division ratio) /8 /25 Partial frame frequency: fOSCIN1 /8(division ratio) /8 /12 Static icon frame frequency: fOSCIN2 /4(division ratio) /32 Static icon frame frequency: fOSCIN2 /4(division ratio) /32 Static icon frame frequency: fOSCIN2 /4(division ratio) /32 Static icon frame frequency: fOSCIN1 /16(division ratio) /32 Static icon frame frequency: fOSCIN1 /16(division ratio) /32 Static icon frame frequency: fOSCIN1 /16(division ratio) /32 L(OFF) OSCIN1 L (Normal) - 1/16 Static icon frame frequency: fOSCIN1 /16(division ratio) /32 H(ON) 1/12 1/38 1/25 1/1 OSCIN2 L(OFF) 1/1 H (Partial) 1/12 1/38 1/25 1/4 1/2 1/2 OSCIN1 H(ON) 1/4 1/12 1/16 1/8 Partial frame frequency: fOSCIN2 /8 /38 Partial frame frequency: fOSCIN2 /8 /25 Partial frame frequency: fOSCIN2 /2(division ratio) /8 /12 Partial frame frequency: fOSCIN1 /2(division ratio) /8 /38 Partial frame frequency: fOSCIN1 /4(division ratio) /8 /25 Partial frame frequency: fOSCIN1 /8(division ratio) /8 /12 Static icon frame frequency: fOSCIN2 /4(division ratio) /32 Static icon frame frequency: fOSCIN2 /4(division ratio) /32 Static icon frame frequency: fOSCIN2 /4(division ratio) /32 Static icon frame frequency: fOSCIN1 /16(division ratio) /32 Static icon frame frequency: fOSCIN1 /16(division ratio) /32 Static icon frame frequency: fOSCIN1 /16(division ratio) /32 1/38 1/25 1/12 L(OFF) OSCIN1 L (Normal) - 1/20 Static icon frame frequency: fOSCIN1 /20(division ratio) /32 1/38 1/25 1/113 to 1/128 H(ON) 1/12 1/38 1/25 1/1 OSCIN2 L(OFF) 1/12 1/38 1/25 1/12 32 1/1 H (Partial) 1/4 1/2 1/2 OSCIN1 H(ON) 1/4 1/20 1/8 Data Sheet S15548EJ1V0DS Partial frame frequency: fOSCIN2 /8 /38 Partial frame frequency: fOSCIN2 /8 /25 Partial frame frequency: fOSCIN2 /2(division ratio) /8 /12 Partial frame frequency: fOSCIN1 /2(division ratio) /8 /38 Partial frame frequency: fOSCIN1 /4(division ratio) /8 /25 Partial frame frequency: fOSCIN1 /8(division ratio) /8 /12 Static icon frame frequency: fOSCIN2 /4(division ratio) /32 Static icon frame frequency: fOSCIN2 /4(division ratio) /32 Static icon frame frequency: fOSCIN2 /4(division ratio) /32 Static icon frame frequency: fOSCIN1 /20(division ratio) /32 Static icon frame frequency: fOSCIN1 /20(division ratio) /32 Static icon frame frequency: fOSCIN1 /20(division ratio) /32 µPD16686, 16687 Table 3-5. Setting of Division Level for Partial Display and Static Icon Display (2/2) In black/white display mode (GRAY = H, control register 2 (R1)) Display Normal Display Partial Display Mode Duty Ratio Duty Ratio Division Divider Normal/Partial Source ON/OFF OSCIN1 Select DTY CLS /OSCIN2 Partial Static Icon Division Division Ratio Ratio - 1/6 Comments 1/38 1/25 1/12 L(OFF) OSCIN1 1/38 1/25 1/1 to 1/80 L (Normal) H(ON) 1/12 1/38 1/25 1/1 OSCIN2 L(OFF) 1/1 H (Partial) 1/12 1/38 1/25 H(ON) 1/2 L (Normal) B/W OSCIN2 L(OFF) 1/1 H (Partial) 1/8 1/2 1/2 1/2 OSCIN1 H(ON) 1/4 1/12 1/8 1/8 1/38 1/25 1/12 - 1/1 1/38 GRAY = H Static icon frame frequency: fOSCIN2 /2(division ratio) /32 Static icon frame frequency: fOSCIN2 /2(division ratio) /32 Static icon frame frequency: fOSCIN2 /2(division ratio) /32 Static icon frame frequency: fOSCIN1 /6(division ratio) /32 Static icon frame frequency: fOSCIN1 /6(division ratio) /32 Static icon frame frequency: fOSCIN1 /6(division ratio) /32 Static icon frame frequency: fOSCIN1 /8(division ratio) /32 H(ON) 1/12 1/25 1/6 Partial frame frequency: fOSCIN2 /4 /38 Partial frame frequency: fOSCIN2 /4 /25 Partial frame frequency: fOSCIN2 /2(division ratio) /4 /12 Partial frame frequency: fOSCIN1 /2(division ratio) /4 /38 Partial frame frequency: fOSCIN1 /2(division ratio) /4 /25 Partial frame frequency: fOSCIN1 /4(division ratio) /4 /12 L(OFF) OSCIN1 1/25 1/12 1/38 1/25 1/2 1/4 1/38 1/25 1/12 1/38 1/2 1/2 OSCIN1 1/12 1/81 to 1/96 Static icon frame frequency: fOSCIN1 /6(division ratio) /32 Partial frame frequency: fOSCIN2 /4 /38 Partial frame frequency: fOSCIN2 /4 /25 Partial frame frequency: fOSCIN2 /2(division ratio) /4 /12 Partial frame frequency: fOSCIN1 /2(division ratio) /4 /38 Partial frame frequency: fOSCIN1 /4(division ratio) /4 /25 Partial frame frequency: fOSCIN1 /8(division ratio) /4 /12 Static icon frame frequency: fOSCIN2 /2(division ratio) /32 Static icon frame frequency: fOSCIN2 /2(division ratio) /32 Static icon frame frequency: fOSCIN2 /2(division ratio) /32 Static icon frame frequency: fOSCIN1 /8(division ratio) /32 Static icon frame frequency: fOSCIN1 /8(division ratio) /32 Static icon frame frequency: fOSCIN1 /8(division ratio) /32 L(OFF) OSCIN1 L (Normal) - 1/8 Static icon frame frequency: fOSCIN1 /8(division ratio) /32 1/38 1/97 to 1/112 1/25 1/12 H(ON) 1/38 1/25 1/1 OSCIN2 L(OFF) 1/1 H (Partial) 1/12 1/38 1/25 1/113 to 1/128 H(ON) 1/4 L (Normal) - 1/10 Static icon frame frequency: fOSCIN1 /10(division ratio) /32 H(ON) 1/1 OSCIN2 L(OFF) 1/1 H (Partial) 1/12 1/38 1/12 Static icon frame frequency: fOSCIN2 /2(division ratio) /32 Static icon frame frequency: fOSCIN2 /2(division ratio) /32 Static icon frame frequency: fOSCIN2 /2(division ratio) /32 Static icon frame frequency: fOSCIN1 /8(division ratio) /32 Static icon frame frequency: fOSCIN1 /8(division ratio) /32 Static icon frame frequency: fOSCIN1 /8(division ratio) /32 L(OFF) OSCIN1 1/38 1/25 1/8 1/8 1/25 1/12 1/25 1/2 1/2 OSCIN1 1/12 1/38 1/25 1/12 1/38 1/2 Partial frame frequency: fOSCIN2 /4 /38 Partial frame frequency: fOSCIN2 /4 /25 Partial frame frequency: fOSCIN2 /2(division ratio) /4 /12 Partial frame frequency: fOSCIN1 /2(division ratio) /4 /38 Partial frame frequency: fOSCIN1 /4(division ratio) /4 /25 Partial frame frequency: fOSCIN1 /8(division ratio) /4 /12 1/2 1/2 1/2 OSCIN1 H(ON) 1/4 1/10 1/8 Data Sheet S15548EJ1V0DS Partial frame frequency: fOSCIN2 /4 /38 Partial frame frequency: fOSCIN2 /4 /25 Partial frame frequency: fOSCIN2 /2(division ratio) /4 /12 Partial frame frequency: fOSCIN1 /2(division ratio) /4 /38 Partial frame frequency: fOSCIN1 /4(division ratio) /4 /25 Partial frame frequency: fOSCIN1 /8(division ratio) /4 /12 Static icon frame frequency: fOSCIN2 /2(division ratio) /32 Static icon frame frequency: fOSCIN2 /2(division ratio) /32 Static icon frame frequency: fOSCIN2 /2(division ratio) /32 Static icon frame frequency: fOSCIN1 /10(division ratio) /32 Static icon frame frequency: fOSCIN1 /10(division ratio) /32 Static icon frame frequency: fOSCIN1 /10(division ratio) /32 33 µPD16686, 16687 Table 3-6 shows the relationship between the CLS pin, resistors RN and RP, and the display clock circuit. Table 3-6. Relationship Between CLS Pin/Resistors and Display Clock Circuit. RN Connection RP Connection CLS Clock for Normal Display Clock for Partial Display Use Example (Figure 3-10) Connected Connected L Internal oscillator Internal oscillator A Connected Not connected H Internal oscillator Divided from oscillator clock B Not connected Connected L External clock Internal oscillator C Not connected Not connected L External clock External clock D Not connected Not connected H External clock Divided from external clock E Figure 3-10. Clock Use Examples (A) (B) OSCIN1 RN OSCIN2 OSCIN1 H or L RN OSCIN2 RP OSCOUT OSCOUT (D) (C) fN fN OSCIN1 OSCIN1 fP OSCIN2 OSCIN2 RP OSCOUT (E) fN OSCIN1 H or L Open 34 OSCIN2 OSCOUT Data Sheet S15548EJ1V0DS Open OSCOUT µPD16686, 16687 3.5 Display Timing Generator The display timing generator generates timing signals from the display clock to the line address circuit and the display data latch circuit. Display data is latched into the display data latch circuit in synch with the display clock and is output via segment driver output pins. Reading of the display data is completely independent of the CPU's accessing of the display data RAM. Consequently, there are no adverse effects (such as flicker) on the LCD panel even when the display data RAM is accessed asynchronously in relation to the LCD contents. The internal common timing is generated from the display clock. As shown in Figure 3-11, a driver waveform based on the frame AC drive method is generated for the LCD driver. Data Sheet S15548EJ1V0DS 35 µPD16686, 16687 Figure 3-11. Driver Waveform Based on Frame AC Drive Method 1 frame 1 2 3 4 5 6 7 8 126 127 128 1 2 3 4 5 6 7 8 RAM DATA VLCD VLC1 VLC2 SEG1 VLC3 VLC4 VSS VLCD VLC1 VLC2 COM1 VLC3 VLC4 VSS VLCD VLC1 VLC2 COM2 VLC3 VLC4 VSS VLCD VLC1 VLC2 COM128 VLC3 VLC4 VSS 36 Data Sheet S15548EJ1V0DS 126 127 128 µPD16686, 16687 3.6 Power Supply Circuit 3.6.1 Power supply circuit The power supply circuit supplies the voltage needed to drive the LCD. It includes a booster, voltage regulator, and voltage follower. In the power supply circuit, the power system control 1 (R32) is used to control the ON/OFF status of the power supply circuit's booster, voltage regulator (also called V regulator), and voltage follower (V/F). This makes it possible to jointly use an external power supply together with certain functions of the on-chip power supply. Table 3-7 shows the function that controls the 3-bit data in the power system control 1 (R32) and Table 3-7 shows a reference chart of combinations. Table 3-7. Control Values of Bits in Power System Control 1 Status Item 1 0 OP2 Booster control bit ON OFF OP1 Voltage regulator (V regulator) control bit ON OFF OP0 Voltage follower (V/F) control bit ON OFF Table 3-8. Reference Chart of Combinations Use Status OP2 OP1 OP0 Booster V Regulator V/F External Power Supply Input Boost-Related System Pins <1> Use on-chip power supply 1 1 1 enable enable enable VDD2 Used <2> Use V regulator and V/F only 0 1 1 disable enable enable VOUT Not connected <3> Use V/F only 0 0 1 disable disable enable VOUT, AMPOUT Not connected <4> Use external power supply 0 0 0 disable disable disable VOUT, Not connected only VLCD to VLC4 Caution The boost-related system pins are indicated as pins C1+, C1− to C9+, C9−, and C1A. 3.6.2 Booster A booster that boosts the LCD driving voltage by 2 to 9 times is incorporated in the power supply circuit. Since the booster uses signals from the on-chip oscillator, either the oscillator must be operating or a display clock must be input from an external source. The booster uses pins C1+, C1− to C9+, C9− for normal boost and pins C1A and VDD2 for boost regulation. The wire impedance should be kept as low as possible. The number of boost levels is set using the FBS2, FBS1, and FBS0 flags in power system control 3 (R34), as shown in Table 3-9. Caution If a capacitor is connected to a boost-related system pin that is not for one of these set boost levels, current consumption may increase. Therefore, do not connect any capacitors beyond the number of set boost levels. This also applies for the CA1 pin, used to regulate the boost levels. Figure 3-12 describes the connection method for boost levels and capacitors. The partial booster is settings are made using the BST1 and BST0 flags in the power system control 3 (R34), as shown in Table 3-10. Data Sheet S15548EJ1V0DS 37 µPD16686, 16687 C2− C3+ C3− C4+ C4− C5+ C5− C6+ C6− C7+ C7− C8+ C8− C9+ C9− C1A C2− C3+ C3− C4+ C4− C5+ C5− C6+ C6− C7+ C7− C8+ C8− C9+ C9− C1A C2− C3+ C3− C4+ C4− C5+ C5− C6+ C6− C7+ C7− C8+ C8− C9+ C2− C3+ C3− C4+ C4− C5+ C5− C6+ C6− C7+ C7− C8+ C8− C9+ C2− C3+ C3− C4+ C4− C5+ C5− C6+ C6− C7+ C7− C8+ C2− C3+ C3− C4+ C4− C5+ C5− C6+ C6− C7+ C7− C8+ 9x boost mode 8x boost mode 7x boost mode 6x boost mode C8− C9+ C9− C1A C9− C1A 5x boost mode open open C8− C9+ open C9− C1A open C9− C1A open C1− C2+ C1− C2+ C1− C2+ C1− C2+ C1− C2+ C1− C2+ open C1+ C1+ C1+ C1+ C1+ C1+ Figure 3-12. Connection Method for Boost Levels and Capacitors Table 3-9. Boost Level Settings for Normal Display's Booster FBS2 FBS1 FBS0 Boost Level 0 0 0 4x 0 0 1 5x 0 1 0 6x 0 1 1 7x 1 0 0 8x 1 0 1 9x 1 1 0 Prohibited 1 1 1 Prohibited Table 3-10. Boost Level Settings for Partial Display's Booster 38 BST1 BST0 Boost Level 0 0 2x 0 1 3x 1 0 4x 1 1 Prohibited Data Sheet S15548EJ1V0DS 4x boost mode µPD16686, 16687 3.6.3 Voltage regulator The boost voltage from VOUT is supplied to the voltage regulator and output as the LCD drive voltage VLCD. Since the µPD16686, 16687 has a 256-step electronic volume function and an on-chip resistor for VLCD voltage regulation, a small number of components can be used to configure a highly accurate voltage regulator. (1) When using an on-chip resistor for VLCD voltage regulation The on-chip resistor for VLCD voltage regulation and the electronic volume function can be used to regulate the contrast of the LCD contents by controlling the LCD drive voltage VLCD using commands only. In such cases, no external resistor is needed. If VLCD < VOUT, then the value for VLCD can be determined from the following equation. Example Equation VLCD < VOUT VLCD = (1 + Rb ) VEV Ra VLCD = (1 + Rb ) (1 − α ) VREG Ra 384 Remark VEV = (1 − α ) VREG 384 Figure 3-13. When Using On-Chip Resistor for VLCD Voltage Regulation + VEV (Constant voltage source + electronic volume) VLCD Rb Ra VREG is the IC's on-chip constant voltage source, for which three types of temperature characteristic curves are available. These temperature characteristic curves can be adjusted via settings in the power system control 1 (R32) (TSC1, TCS0), as shown in Table 3-11. Table 3-11 shows the VREG voltage when TA = 25°C. Table 3-11. VREG Voltage When TA = 25°°C Status Internal power supply TCS1 TCS0 Temperature Curve Unit 0 0 VREG (TYP.) Unit 0 −0.09 %, °C 1 −0.11 0.80 0.88 V 1 0 −0.12 0.75 1 1 External inputs − α is the electronic volume register (R35) value. Any of 256 statuses can be set as the fetched status for α corresponding to the data set to the 8-bit electronic control register. α values based on settings in the electronic volume register (R35: normal display mode) and partial electronic volume register (R36: partial display mode) are listed in Table 3-12 on the next page. Data Sheet S15548EJ1V0DS 39 µPD16686, 16687 Table 3-12. α Values Based on Settings in Electronic Volume Register Register α EV7 EV6 EV5 EV4 EV3 EV2 EV1 EV0 PEV7 PEV6 PEV5 PEV4 PEV3 PEV2 PEV1 PEV0 0 0 0 0 0 0 0 0 384 0 0 0 0 0 0 0 1 254 0 0 0 0 0 0 1 0 253 0 0 0 0 0 0 1 1 252 : : 1 1 1 1 1 1 0 1 2 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 Rb/Ra is an on-chip resistance factor used for the VLCD voltage regulator. This factor can be controlled at eight levels based on settings in power control 2 (R33) ([VRR2, VRR1, VRR0]: normal display mode and [PVR2, PVR1, PVR0]: partial display mode). Reference voltage values (1 + Rb/Ra) are determined based on 4-bit data set to VLCD's on-chip resistance factor register, as shown in Table 3-13. Table 3-13. Determination of Reference Voltage Values Based on Settings in On-Chip Resistance Factor Register Register 40 VRR2 VRR1 VRR0 PVR2 PVR1 PVR0 0 0 0 0 0 1 8 0 1 0 12 0 1 1 13 1 0 0 16 1 0 1 19 1 1 0 21 1 1 1 24 Data Sheet S15548EJ1V0DS 1+Rb/Ra 5 µPD16686, 16687 (2) When using an external resistor (instead of using the on-chip resistor for VLCD voltage regulation) Instead of using only the on-chip resistor setting for VLCD voltage regulation (IRS = L), resistors (Ra', Rb' and Rc') can be added between VSS and VR, between AMPOUTP and AMPOUT, and between VR and AMPOUT to set the LCD drive voltage VLCD. In such cases, the electronic volume function can be used to control the LCD drive voltage VLCD and to regulate the contrast of the LCD contents via commands. In addition, the µPD16686, 16687 enable selection between two display values (for normal display and partial display). The value is set using an external division resistor and is automatically selected by the DTY flag in the control register 2 (R1). The VLCD value can be determined using Example 1 (DTY = 0) and Example 2 (DTY = 1) if it is within the range of VLCD < VOUT. Example 1. DTY = 0, normal display mode VLCD = (1 + Rb′ ) VEV Ra′ VLCD = (1 + Rb′ ) (1 − α ) VREG Ra′ 384 Remark VEV (1 − α ) VREG 384 Example 2. DTY = 1, partial display mode Rb′ × Rc ) VEV Ra′(Rb′ + Rc) VLCD = (1+ Rb′ × Rc ) (1 − α ) VREG 384 Ra′(Rb′ + Rc) VLCD = (1+ Remark VEV = (1 − α ) VREG 384 Figure 3-14. When Using External Resistor + VLCD A VR AMPOUT B Normal/partial VLC1 regulation select circuit AMPOUTP Rb' Rc Ra' A B Normal display mode (DTY = 0) A B Partial display mode (DTY = 1) Data Sheet S15548EJ1V0DS 41 µPD16686, 16687 3.6.4 Use of op amp for level power supply control Although the µPD16686, 16687 include a circuit designed for low power consumption (HPM1, HPM0 = 0, 0), display quality problems may occur when a large-load LCD panel is used. In such cases, the display quality and power consumption level can be improved by setting. The HPM1 and HPM0 flags in the power system control 1(R32) to "0, 1" to "1, 1" to switch to the op amp driver capacity for mode settings shown in Table 3-14. Check the actual display quality before deciding which mode to set. If setting high power mode still does not sufficiently improve the display quality, the LCD drive voltage must be provided from an external power source. Table 3-14. Op Amp Mode Setting 42 HPM1 HPM0 Mode Setting 0 0 Normal mode 0 1 Low power mode 1 0 High power mode 1 1 For power activation Data Sheet S15548EJ1V0DS µPD16686, 16687 3.6.5 Application examples of power supply circuits Figures 3-15 to 3-19 show application examples of power supply circuits. Figure 3-15. IRS = H, [OP2, OP1, OP0] = [1, 1, 1] 9x boost mode VDD1 VDD2 VRS VOUT VR Open AMPOUTP C1+ AMPOUT C1 C2+ VLCD C2 C3+ VLC1 C3 - VLC2 C4+ VLC3 C4 C5+ VLC4 C5 - C6+ C6 C7+ C9+ C9 C1A C7 C8+ C8 VSS Figure 3-16. IRS = L, [OP2, OP1, OP0] = [1, 1, 1] 9x boost mode VRS VDD1 VDD2 VOUT AMPOUTP Rc VR Rb' C1+ C1 C2+ C2 C3+ C3 - AMPOUT Ra' VLCD VLC1 VLC2 C4+ C4 C5+ VLC3 VLC4 C5 - C6+ C6 C7+ C7 C8+ C9+ C9 C1A C8 VSS Data Sheet S15548EJ1V0DS 43 µPD16686, 16687 Figure 3-17. IRS = H, [OP2, OP1, OP0] = [0, 1, 1] VRS VDD1 VDD2 VR Open VOUT AMPOUTP C1+ C1 C2+ C2 C3+ C3 C4+ Open C4 C5+ AMPOUT VLCD VLC1 VLC2 VLC3 VLC4 C5 C6+ C6 C7+ C7 C8+ C9+ Open C9 C1A C8 VSS Figure 3-18. IRS = L, [OP2, OP1, OP0] = [0, 0, 1] VRS Open VR Open VDD1 VDD2 VOUT C1+ AMPOUTP C1 C2+ AMPOUT C2 C3+ C3 C4+ Open C4 C5+ VLCD VLC1 VLC2 VLC3 VLC4 C5 C6+ C6 C7+ C7 C8+ C9+ C9 C1A C8 VSS 44 Data Sheet S15548EJ1V0DS Open µPD16686, 16687 Figure 3-19. IRS = L, [OP2, OP1, OP0] = [0, 0, 0] VDD1 VDD2 VRS VOUT AMPOUTP VR Open AMPOUT C1+ C1 C2+ C2 C3+ C3 - VLCD VLC1 VLC2 C4+ Open C4 C5+ VLC3 VLC4 C5 C6+ C6 C7+ C7 C8+ C9+ C9 C1A Open C8 VSS Data Sheet S15548EJ1V0DS 45 µPD16686, 16687 3.7 LCD Display Drivers µPD16686, 16687 include both a full dot driver and a static driver icon driver. The full dot driver has a 33-level gray-scale palette (eight levels of pulse width modulation plus four-frame rate control), from which four levels of gray scale can be selected and registered as the IC's output gray-scale palette. The icon driver has a gray-scale palette with 32-level pulse width modulation, from which four levels of gray scale can be selected and registered for use as the IC's output gray-scale palette. 3.7.1 Full-dot pulse width modulation The µPD16686, 16687's pulse width modulator divides the normal LCD display signal's segment pulse width by eight and outputs in synch with the dot output timing based on the ratio (1/8 to 8/8 pulses) for the gray-scale palette that has been selected via a command. Figure 3-20. Full-Dot Pulse Width Modulation 1 frame 1 2 3 4 5 6 7 8 126 127 128 1 2 3 4 5 6 7 8 VLCD VLC1 VLC2 SEG1 VLC3 VLC4 VSS VLCD VLC1 VLC2 COM1 VLC3 VLC4 VSS Enlarged section 1 2 8/8 6/8 4/8 1/8 VLCD VLC1 VLC2 Caution There is no pulse width modulation for common outputs. 46 Data Sheet S15548EJ1V0DS 3 126 127 128 µPD16686, 16687 The output pulses are output as odd-numbered lines/even-numbered lines or as even-numbered lines/odd-numbered lines, as shown in Figure 3-21. The pulse rising edge and falling edge combinations for each frame are listed in Table 3-15. Figure 3-21. Example of Pulse Width Modulated Output 1 frame 1 2 3 4 5 6 7 8 9 10 11 12 126 127128 1 2 3 4 5 6 7 8 VLCD VLC1 VLC2 VLC3 VLC4 VSS 4/8 1 2 3 8/8 8/8 8/8 3/8 4/8 Data Sheet S15548EJ1V0DS 47 µPD16686, 16687 Table 3-15. Example of Pulse Width Modulated Output (1/3) Gray-scale COM level 1, 2 Frames 3, 4 Frames 5, 6 Frames 7, 8 Frames SEG Odd Numbered SEG Even Numbered SEG Odd Numbered SEG Even Numbered SEG Odd Numbered SEG Even Numbered SEG Odd Numbered SEG Even Numbered 0 4n+1 4n+2 4n+3 4n+4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 4n+1 4n+2 4n+3 4n+4 ↑1 0 0 0 ↓1 0 0 0 0 0 0 ↑1 0 0 0 ↓1 0 ↓1 0 0 0 ↑1 0 0 0 0 ↓1 0 0 0 ↑1 0 2 4n+1 ↑1 ↓1 0 0 ↑1 ↓1 0 0 4n+2 4n+3 4n+4 ↓1 0 0 ↑1 0 0 0 ↓1 ↑1 0 ↑1 ↓1 ↓1 0 0 ↑1 0 0 0 ↓1 ↑1 0 ↑1 ↓1 4n+1 ↑1 ↓1 ↓1 ↑1 ↑1 ↓1 0 0 4n+2 ↓1 ↑1 0 0 ↓1 ↑1 ↑1 ↓1 4n+3 ↑1 ↓1 ↓1 ↑1 0 0 ↓1 ↑1 4n+4 0 0 ↑1 ↓1 ↓1 ↑1 ↑1 ↓1 4n+1 ↑1 ↓1 ↓1 ↑1 ↑1 ↓1 ↓1 ↑1 4n+2 ↓1 ↑1 ↑1 ↓1 ↓1 ↑1 ↑1 ↓1 4n+3 4n+4 ↑1 ↓1 ↓1 ↑1 ↓1 ↑1 ↑1 ↓1 ↑1 ↓1 ↓1 ↑1 ↓1 ↑1 ↑1 ↓1 4n+1 4n+2 ↑2 ↓1 ↓2 ↑1 ↓1 ↑1 ↑1 ↓1 ↑1 ↓2 ↓1 ↑2 ↓1 ↑1 ↑1 ↓1 4n+3 4n+4 ↑1 ↓1 ↓1 ↑1 ↓1 ↑2 ↑1 ↓2 ↑1 ↓1 ↓1 ↑1 ↓2 ↑1 ↑2 ↓1 4n+1 ↑2 ↓2 ↓1 ↑1 ↑2 ↓2 ↓1 ↑1 4n+2 4n+3 4n+4 ↓2 ↑1 ↓1 ↑2 ↓1 ↑1 ↑1 ↓2 ↑2 ↓1 ↑2 ↓2 ↓2 ↑1 ↓1 ↑2 ↓1 ↑1 ↑1 ↓2 ↑2 ↓1 ↑2 ↓2 7 4n+1 4n+2 4n+3 4n+4 ↑2 ↓2 ↑2 ↓1 ↓2 ↑2 ↓2 ↑1 ↓2 ↑1 ↓2 ↑2 ↑2 ↓1 ↑2 ↓2 ↑2 ↓2 ↑1 ↓2 ↓2 ↑2 ↓1 ↑2 ↓1 ↑2 ↓2 ↑2 ↑1 ↓2 ↑2 ↓2 8 4n+1 ↑2 ↓2 ↓2 ↑2 ↑2 ↓2 ↓2 ↑2 4n+2 ↓2 ↑2 ↑2 ↓2 ↓2 ↑2 ↑2 ↓2 4n+3 4n+4 ↑2 ↓2 ↓2 ↑2 ↓2 ↑2 ↑2 ↓2 ↑2 ↓2 ↓2 ↑2 ↓2 ↑2 ↑2 ↓2 9 4n+1 4n+2 4n+3 4n+4 ↑3 ↓2 ↑2 ↓2 ↓3 ↑2 ↓2 ↑2 ↓2 ↑2 ↓2 ↑3 ↑2 ↓2 ↑2 ↓3 ↑2 ↓3 ↑2 ↓2 ↓2 ↑3 ↓2 ↑2 ↓2 ↑2 ↓3 ↑2 ↑2 ↓2 ↑3 ↓2 10 4n+1 4n+2 4n+3 4n+4 ↑3 ↓3 ↑2 ↓2 ↓3 ↑3 ↓2 ↑2 ↓2 ↑2 ↓3 ↑3 ↑2 ↓2 ↑3 ↓3 ↑3 ↓3 ↑2 ↓2 ↓3 ↑3 ↓2 ↑2 ↓2 ↑2 ↓3 ↑3 ↑2 ↓2 ↑3 ↓3 3 4 5 6 Remarks 1. n: Integer from 0 to 31. 2. ↑A: Rising edge of pulse during line A output. 3. ↓A: Rising edge of pulse at start of line A output. 4. A: PWM pulse width (A/8) 48 Data Sheet S15548EJ1V0DS µPD16686, 16687 Table 3-15. Example of Pulse Width Modulated Output (2/3) Gray-scale COM level 11 12 1, 2 Frames 3, 4 Frames 5, 6 Frames 7, 8 Frames SEG Odd Numbered SEG Even Numbered SEG Odd Numbered SEG Even Numbered SEG Odd Numbered SEG Even Numbered SEG Odd Numbered SEG Even Numbered 4n+1 ↑3 ↓3 ↓3 ↑3 ↑3 ↓3 ↓2 ↑2 4n+2 ↓3 ↑3 ↑2 ↓2 ↓3 ↑3 ↑3 ↓3 4n+3 ↑3 ↓3 ↓3 ↑3 ↑2 ↓2 ↓3 ↑3 4n+4 ↓2 ↑2 ↑3 ↓3 ↓3 ↑3 ↑3 ↓3 4n+1 ↑3 ↓3 ↓3 ↑3 ↑3 ↓3 ↓3 ↑3 4n+2 ↓3 ↑3 ↑3 ↓3 ↓3 ↑3 ↑3 ↓3 4n+3 4n+4 ↑3 ↓3 ↓3 ↑3 ↓3 ↑3 ↑3 ↓3 ↑3 ↓3 ↓3 ↑3 ↓3 ↑3 ↑3 ↓3 4n+1 ↑4 ↓4 ↓3 ↑3 ↑3 ↓3 ↓3 ↑3 4n+2 ↓3 ↑3 ↑3 ↓3 ↓4 ↑4 ↑3 ↓3 4n+3 4n+4 ↑3 ↓3 ↓3 ↑3 ↓3 ↑4 ↑3 ↓4 ↑3 ↓3 ↓3 ↑3 ↓4 ↑3 ↑4 ↓3 4n+1 ↑4 ↓4 ↓3 ↑3 ↑4 ↓4 ↓3 ↑3 4n+2 ↓4 ↑4 ↑3 ↓3 ↓4 ↑4 ↑3 ↓3 4n+3 ↑3 ↓3 ↓4 ↑4 ↑3 ↓3 ↓4 ↑4 4n+4 ↓3 ↑3 ↑4 ↓4 ↓3 ↑3 ↑4 ↓4 4n+1 ↑4 ↓4 ↓4 ↑4 ↑4 ↓4 ↓3 ↑3 4n+2 ↓4 ↑4 ↑3 ↓3 ↓4 ↑4 ↑4 ↓4 4n+3 ↑4 ↓4 ↓4 ↑4 ↑3 ↓3 ↓4 ↑4 4n+4 ↓3 ↑3 ↑4 ↓4 ↓4 ↑4 ↑4 ↓4 4n+1 ↑4 ↓4 ↓4 ↑4 ↑4 ↓4 ↓4 ↑4 4n+2 4n+3 4n+4 ↓4 ↑4 ↓4 ↑4 ↓4 ↑4 ↑4 ↓4 ↑4 ↓4 ↑4 ↓4 ↓4 ↑4 ↓4 ↑4 ↓4 ↑4 ↑4 ↓4 ↑4 ↓4 ↑4 ↓4 4n+1 4n+2 ↑5 ↓4 ↓5 ↑4 ↓4 ↑4 ↑4 ↓4 ↑4 ↓5 ↓4 ↑5 ↓4 ↑4 ↑4 ↓4 4n+3 4n+4 ↑4 ↓4 ↓4 ↑4 ↓4 ↑5 ↑4 ↓5 ↑4 ↓4 ↓4 ↑4 ↓5 ↑4 ↑5 ↓4 4n+1 4n+2 ↑5 ↓5 ↓5 ↑5 ↓4 ↑4 ↑4 ↓4 ↑5 ↓5 ↓5 ↑5 ↓4 ↑4 ↑4 ↓4 4n+3 4n+4 ↑4 ↓4 ↓4 ↑4 ↓5 ↑5 ↑5 ↓5 ↑4 ↓4 ↓4 ↑4 ↓5 ↑5 ↑5 ↓5 19 4n+1 4n+2 4n+3 4n+4 ↑5 ↓5 ↑5 ↓4 ↓5 ↑5 ↓5 ↑4 ↓5 ↑4 ↓5 ↑5 ↑5 ↓4 ↑5 ↓5 ↑5 ↓5 ↑4 ↓5 ↓5 ↑5 ↓4 ↑5 ↓4 ↑5 ↓5 ↑5 ↑4 ↓5 ↑5 ↓5 20 4n+1 4n+2 ↑5 ↓5 ↓5 ↑5 ↓5 ↑5 ↑5 ↓5 ↑5 ↓5 ↓5 ↑5 ↓5 ↑5 ↑5 ↓5 4n+3 4n+4 ↑5 ↓5 ↓5 ↑5 ↓5 ↑5 ↑5 ↓5 ↑5 ↓5 ↓5 ↑5 ↓5 ↑5 ↑5 ↓5 4n+1 4n+2 4n+3 4n+4 ↑6 ↓5 ↑5 ↓5 ↓6 ↑5 ↓5 ↑5 ↓5 ↑5 ↓5 ↑6 ↑5 ↓5 ↑5 ↓6 ↑5 ↓6 ↑5 ↓5 ↓5 ↑6 ↓5 ↑5 ↓5 ↑5 ↓6 ↑5 ↑5 ↓5 ↑6 ↓5 13 14 15 16 17 18 21 Remarks 1. n: Integer from 0 to 31. 2. ↑A: Rising edge of pulse during line A output. 3. ↓A: Rising edge of pulse at start of line A output. 4. A: PWM pulse width (A/8) Data Sheet S15548EJ1V0DS 49 µPD16686, 16687 Table 3-15. Example of Pulse Width Modulated Output (3/3) Gray-scale COM level 22 23 24 25 26 27 28 29 30 31 32 1, 2 Frames 3, 4 Frames 5, 6 Frames SEG Even Numbered SEG Odd Numbered SEG Even Numbered SEG Odd Numbered SEG Even Numbered SEG Odd Numbered SEG Even Numbered 4n+1 ↑6 ↓6 ↓5 ↑5 ↑6 ↓6 ↓5 ↑5 4n+2 4n+3 ↓6 ↑5 ↑6 ↓5 ↑5 ↓6 ↓5 ↑6 ↓6 ↑5 ↑6 ↓5 ↑5 ↓6 ↓5 ↑6 4n+4 ↓5 ↑5 ↑6 ↓6 ↓5 ↑5 ↑6 ↓6 4n+1 ↑6 ↓6 ↓6 ↑6 ↑6 ↓6 ↓5 ↑5 4n+2 4n+3 4n+4 ↓6 ↑6 ↓5 ↑6 ↓6 ↑5 ↑5 ↓6 ↑6 ↓5 ↑6 ↓6 ↓6 ↑5 ↓6 ↑6 ↓5 ↑6 ↑6 ↓6 ↑6 ↓6 ↑6 ↓6 4n+1 4n+2 4n+3 4n+4 ↑6 ↓6 ↑6 ↓6 ↓6 ↑6 ↓6 ↑6 ↓6 ↑6 ↓6 ↑6 ↑6 ↓6 ↑6 ↓6 ↑6 ↓6 ↑6 ↓6 ↓6 ↑6 ↓6 ↑6 ↓6 ↑6 ↓6 ↑6 ↑6 ↓6 ↑6 ↓6 4n+1 ↑7 ↓7 ↓6 ↑6 ↑6 ↓6 ↓6 ↑6 4n+2 4n+3 ↓6 ↑6 ↑6 ↓6 ↑6 ↓6 ↓6 ↑6 ↓7 ↑6 ↑7 ↓6 ↑6 ↓7 ↓6 ↑7 4n+4 ↓6 ↑6 ↑7 ↓7 ↓6 ↑6 ↑6 ↓6 4n+1 ↑7 ↓7 ↓6 ↑6 ↑7 ↓7 ↓6 ↑6 4n+2 ↓7 ↑7 ↑6 ↓6 ↓7 ↑7 ↑6 ↓6 4n+3 ↑6 ↓6 ↓7 ↑7 ↑6 ↓6 ↓7 ↑7 4n+4 ↓6 ↑6 ↑7 ↓7 ↓6 ↑6 ↑7 ↓7 4n+1 ↑7 ↓7 ↓7 ↑7 ↑7 ↓7 ↓6 ↑6 4n+2 ↓7 ↑7 ↑6 ↓6 ↓7 ↑7 ↑7 ↓7 4n+3 ↑7 ↓7 ↓7 ↑7 ↑6 ↓6 ↓7 ↑7 4n+4 ↓6 ↑6 ↑7 ↓7 ↓7 ↑7 ↑7 ↓7 4n+1 ↑7 ↓7 ↓7 ↑7 ↑7 ↓7 ↓7 ↑7 4n+2 ↓7 ↑7 ↑7 ↓7 ↓7 ↑7 ↑7 ↓7 4n+3 ↑7 ↓7 ↓7 ↑7 ↑7 ↓7 ↓7 ↑7 4n+4 ↓7 ↑7 ↑7 ↓7 ↓7 ↑7 ↑7 ↓7 4n+1 4n+2 8 ↓7 8 ↑7 ↓7 ↑7 ↑7 ↓7 ↑7 8 ↓7 8 ↓7 ↑7 ↑7 ↓7 4n+3 ↑7 ↓7 ↓7 ↑7 ↑7 ↓7 8 8 4n+4 ↓7 ↑7 8 8 ↓7 ↑7 ↑7 ↓7 4n+1 8 8 ↓7 ↑7 8 8 ↓7 ↑7 4n+2 4n+3 4n+4 8 ↑7 ↓7 8 ↓7 ↑7 ↑7 8 8 ↓7 8 8 8 ↑7 ↓7 8 ↓7 ↑7 ↑7 8 8 ↓7 8 8 4n+1 8 8 8 8 8 8 ↓7 ↑7 4n+2 4n+3 8 8 8 8 ↑7 8 ↓7 8 8 ↑7 8 ↓7 8 8 8 8 4n+4 ↓7 ↑7 8 8 8 8 8 8 4n+1 8 8 8 8 8 8 8 8 4n+2 4n+3 4n+4 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Remarks 1. n: Integer from 0 to 31. 2. ↑A: Rising edge of pulse during line A output. 3. ↓A: Rising edge of pulse at start of line A output. 4. A: PWM pulse width (A/8) 50 7, 8 Frames SEG Odd Numbered Data Sheet S15548EJ1V0DS µPD16686, 16687 3.7.2 Full-dot frame rate control When combined with pulse width modulation as described in Table 3-15, the µPD16686, 16687's frame speed is based on 8-frame cycles. The subsampling pattern is output based on the palette stored in the IC. Full-Dot Gray-Scale Palette (Output Pulse Width: x/8 Pulses) Gray Scale Frames 1 2 3 4 5 6 7 8 Level 0 0 0 0 0 0 0 0 0 Level 1 1 1 0 0 0 0 0 0 Level 2 1 1 0 0 1 1 0 0 Level 3 1 1 1 1 1 1 0 0 Level 4 1 1 1 1 1 1 1 1 Level 5 2 2 1 1 1 1 1 1 Level 6 2 2 1 1 2 2 1 1 Level 7 2 2 2 2 2 2 1 1 Level 8 2 2 2 2 2 2 2 2 Level 9 3 3 2 2 2 2 2 2 Level 10 3 3 2 2 3 3 2 2 Level 11 3 3 3 3 3 3 2 2 Level 12 3 3 3 3 3 3 3 3 Level 13 4 4 3 3 3 3 3 3 Level 14 4 4 3 3 4 4 3 3 Level 15 4 4 4 4 4 4 3 3 Level 16 4 4 4 4 4 4 4 4 Level 17 5 5 4 4 4 4 4 4 Level 18 5 5 4 4 5 5 4 4 Level 19 5 5 5 5 5 5 4 4 Level 20 5 5 5 5 5 5 5 5 Level 21 6 6 5 5 5 5 5 5 Level 22 6 6 5 5 6 6 5 5 Level 23 6 6 6 6 6 6 5 5 Level 24 6 6 6 6 6 6 6 6 Level 25 7 7 6 6 6 6 6 6 Level 26 7 7 6 6 7 7 6 6 Level 27 7 7 7 7 7 7 6 6 Level 28 7 7 7 7 7 7 7 7 Level 29 8 8 7 7 7 7 7 7 Level 30 8 8 7 7 8 8 7 7 Level 31 8 8 8 8 8 8 7 7 Level 32 8 8 8 8 8 8 8 8 Comments OFF data 50% 100% Remark The gradation in the Comments column are images of the gray-scale level. Data Sheet S15548EJ1V0DS 51 µPD16686, 16687 3.7.3 Line shift driver If the frame rate control is performed with equal pulse widths and the same gray scale is displayed on the LCD's full screen, problems such as flickering may occur on the LCD panel. The µPD16686, 16687 provide a line shift driver as a countermeasure against such screen image problems. Using 8 frames per cycle, the segment PWM output timing is shifted among the common outputs, as shown in Table 3-16 below. Table 3-16. Line Shift Driver Turn 1 Turn 2 Frame 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 COM1 F1 F2 F3 F4 F5 F6 F7 F8 F1 F2 F3 F4 F5 F6 F7 F8 F1 F2 F3 F4 COM2 F5 F6 F7 F8 F1 F2 F3 F4 F5 F6 F7 F8 F1 F2 F3 F4 F5 F6 F7 F8 COM3 F3 F4 F5 F6 F7 F8 F1 F2 F3 F4 F5 F6 F7 F8 F1 F2 F3 F4 F5 F6 COM4 F7 F8 F1 F2 F3 F4 F5 F6 F7 F8 F1 F2 F3 F4 F5 F6 F7 F8 F1 F2 COM5 F1 F2 F3 F4 F5 F6 F7 F8 F1 F2 F3 F4 F5 F6 F7 F8 F1 F2 F3 F4 COM6 F5 F6 F7 F8 F1 F2 F3 F4 F5 F6 F7 F8 F1 F2 F3 F4 F5 F6 F7 F8 COM7 F3 F4 F5 F6 F7 F8 F1 F2 F3 F4 F5 F6 F7 F8 F1 F2 F3 F4 F5 F6 COM8 F7 F8 F1 F2 F3 F4 F5 F6 F7 F8 F1 F2 F3 F4 F5 F6 F7 F8 F1 F2 COM9 F1 F2 F3 F4 F5 F6 F7 F8 F1 F2 F3 F4 F5 F6 F7 F8 F1 F2 F3 F4 COM10 F5 F6 F7 F8 F1 F2 F3 F4 F5 F6 F7 F8 F1 F2 F3 F4 F5 F6 F7 F8 • • • • • • • • • • • • • • • • • • • • • Remark Fx: Pulse width modulated output frame (See 3.7.2 Full-dot frame rate control). Figure 3-22. Full Dot Frame Rate Control First frame 1 2 3 4 5 Second frame 127 128 1 2 ON OFF ON OFF ON OFF COM1 COM2 COM3 ON OFF ON OFF COM4 COM5 ON OFF ON COM128 OFF COM127 SEG1 8 1 5 3 7 1 5 3 7 2 6 SEG2 8 1 5 3 7 1 5 3 7 2 6 SEG3 8 1 5 3 7 1 5 3 7 2 6 SEG4 8 1 5 3 7 1 5 3 7 2 6 SEG5 8 1 5 3 7 1 5 3 7 2 6 Remark Numerical values in the segment data correspond to the gray-scale palette's frame numbers. 52 Data Sheet S15548EJ1V0DS µPD16686, 16687 Figure 3-23. Line Shift Driver Image Turn 1, first frame SEG1 SEG3 SEG2 SEG5 SEG4 SEG7 SEG6 SEG127 SEG8 COM1 F1 COM2 F5 COM3 F3 COM4 F7 COM5 F1 COM126 F5 COM127 F3 COM128 F7 SEG126 SEG128 Turn 1, second frame SEG1 SEG3 SEG2 SEG5 SEG4 SEG7 SEG6 SEG127 SEG8 COM1 F2 COM2 F6 COM3 F4 COM4 F8 COM5 F2 COM126 F6 COM127 F4 COM128 F8 Data Sheet S15548EJ1V0DS SEG126 SEG128 53 µPD16686, 16687 3.7.4 Display size settings The µPD16686, 16687 can be set for any duty value from 1/1 to 1/128. This duty setting can be made via bits DT6 to DT0 in the duty setting register (R5), as shown in Table 3-17. Table 3-17. Duty Settings DT6 DT5 DT4 DT3 DT2 DT1 DT0 Duty 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 : 1 1 1 1 1 1 0 1 1 1 0 1 1/1 1/2 1/3 1/4 : 1/126 1/127 1/128 3.7.5 Setting of LCD AC driver's inversion cycle and AC driver's inversion position The µPD16686, 16687 enable any setting to be made for the AC driver's inversion position and the inversion position shift amount for each displayed frame via settings made in the AC driver inversion cycle register (R6) and the AC driver inversion position shift register (R7) for normal display mode or via settings made in the partial AC driver inversion cycle register (R8) and the partial AC driver inversion position shift register (R9) for partial display mode. In normal display mode, the AC driver inversion cycle can be set for any number of inverted (reverse display) lines listed in Table 3-18, based on the NID6 to NID0 bit settings in the AC driver inversion cycle register (R6). If the screen display size has been changed via settings made in the duty setting register (R5), the NIDn values are automatically overwritten by values from the corresponding DTYn bits. The shift amount for each displayed frame can be set as shown in Table 3-19 via settings made to bits MSD6 to MSD0 in the AC driver inversion position shift register (R7). Table 3-18. Settings of AC Driver Inversion Cycle Register (R6) 54 NID6 NID5 NID4 NID3 NID2 NID1 NID0 Inverted Lines 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 : 1 1 1 1 1 1 0 1 1 1 0 1 1 2 3 4 : 126 127 128 Data Sheet S15548EJ1V0DS µPD16686, 16687 Table 3-19. Settings of AC Driver Inversion Position Shift Register MSD6 MSD5 MSD4 MSD3 MSD2 MSD1 MSD0 Inversion Position Shift Amount 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 2 0 0 0 0 0 1 1 3 : : 1 1 1 1 1 0 1 125 1 1 1 1 1 1 0 126 1 1 1 1 1 1 1 127 In partial display mode, the AC driver inversion cycle can be set for any number of inverted (reverse display) lines listed in Table 3-20, based on the PID5 to PID0 bit settings in the partial AC driver inversion cycle register (R8). The shift amount for each displayed frame can be set as shown in Table 3-21 via settings made to bits PSD5 to PSD0 in the partial AC driver inversion position shift register (R9). Table 3-20. Settings of Partial AC Driver Inversion Cycle Register (R8) PID5 PID4 PID3 PID2 PID1 PID0 Inverted Lines 0 0 0 0 0 0 1 0 0 0 0 0 1 2 0 0 0 0 1 0 3 0 0 0 0 1 1 4 : : 1 0 0 0 1 1 36 1 0 0 1 0 0 37 1 0 0 1 0 1 38 Table 3-21. Setting of Partial AC Driver Inversion Position Shift Register (R9) PSD5 PSD4 PSD3 PSD2 PSD1 PSD0 Inversion Position Shift Amount 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 2 0 0 0 0 1 1 3 : : 1 0 0 0 1 1 35 1 0 0 1 0 0 36 1 0 0 1 0 1 37 Be sure to maintain the following relationship among the display size, AC inversion cycle, and AC inversion position. Display size (duty) ≥ AC inversion cycle ≥ AC inversion shift amount Caution Setting a small inversion cycle will cause a reduction in the IC's display drive capacity and an increase in the current consumption. NEC therefore recommends determining the inversion cycle after making a thorough evaluation of the actual LCD panel. Data Sheet S15548EJ1V0DS 55 µPD16686, 16687 3.8 Display Modes 3.8.1 Partial display mode The µPD16686, 16687 include a function for outputting a display that uses only part of the LCD panel. The duty setting for partial display mode can be selected as 1/12, 1/25, or 1/38. Parts of the LCD panel that are outside of the specified display area are scanned with non-select waveforms. The partial start line address register (R21) is used to select which part of the LCD panel to use for the partial display. The display area starts from the start line address and includes the number of lines (12, 25, or 38 lines) that has been specified via the partial display mode setting (R10). When entering this mode, the booster is set to the boost level number that has been set via the power system control 3 (partial display boost register) (R34) and the display start line is fixed as 00H. In addition, the bias level is automatically changed to the value that has been set via the partial display mode setting (R10). The relationship between the oscillator's frequency and the frame frequency in partial mode is also automatically changed. Figure 3-24 shows the mutual relationship between the partial line start address and the LCD display. When using the partial display mode, the blinking and reverse display functions can be used in the same way as during full-dot display mode. Caution The LCD driver voltage is lower in partial display mode, because the duty is lower than in normal display mode. There may be restrictions on the useble duty depending on the LCD panel characteristics. We recommend determining the partial duty after making a thorough evaluation of the actual LCD panel. Figure 3-24. Relationship Between Partial Line Start Address and LCD Display (in Partial Display Mode) 00H 01H 02H 03H ... 1DH 1EH 1FH Display start line (00H) 12, 25, or 38 lines Partial display start line Non-display areas Caution In partial display mode, the display start line setting (R12) command is ignored. When switching from normal display mode to partial display mode or from partial display mode to normal display mode, if an electric charge remains in the smoothing capacitor that is connected between the LCD drive voltage pins (VLCD to VLC4) and the VSS pin, abnormalities such as a brief all-black display may occur during the mode switching operation. To avoid such abnormalities, we recommend using the following power-on sequence. 56 Data Sheet S15548EJ1V0DS µPD16686, 16687 Normal display → partial display switch sequence DISP = 0 R0 Display OFF R32 High power mode settings R1 Control register 2: switch DTY flag ↓ HPM1 = 1, HPM0 = 0 ↓ Switch display mode ↓ Wait time 700 ms (stabilization time for LCD drive voltage and booster)Note ↓ HPM1 = X, HPM0 = X R32 ↓ DISP = 1 Note High power mode settings (to mode used during normal display) R0 Display ON, internal operations status This 700 ms wait time indicates the time for the VLCD level to change from 15 to 6 V and thus varies according to the panel characteristics and the capacitance value of the boost/smoothing capacitor. Our recommends determining the wait time after making a thorough evaluation of the actual device. Partial display → Normal display switch sequence DISP = 0 R0 Display OFF R32 Power ON mode settings R1 Control register 2: switch DTY flag ↓ HPM1 = 1, HPM0 = 1 ↓ Switch display mode ↓ Wait time 400 ms (stabilization time for LCD drive voltage and booster)Note ↓ HPM1 = X, HPM0 = X R32 ↓ DISP = 1 Note High power mode settings (to mode used during normal display) R0 Display ON, internal operations status This 400 ms wait time indicates the time for the VLCD level to change from 15 V to 6 V and thus varies according to the panel characteristics and the capacitance value of the boost/smoothing capacitor. We recommends determining the wait time after making a thorough evaluation of the actual device. Data Sheet S15548EJ1V0DS 57 µPD16686, 16687 3.8.2 Monochrome (black/white) display The µPD16686, 16687 provide both a four-level gray scale display mode and a monochrome display mode. To switch to the monochrome display mode, set GRAY = H. The display RAM for one screen of monochrome display mode contents is configured as 128 bits x 128 bits (16 x 8 bits). When using these IC's in monochrome display mode, two screens of data can be written to the display RAM and the two screens can be switched by setting the DSEL bit in the control register 2 (R1). Screen 1 is displayed on the LCD panel when DSEL = L and screen 2 is displayed when DSEL = H. When writing data, the display RAM uses the same X address (00H to 0FH) and Y address and the BWW bit value in the control register 2 (R1) determines which of the two screens the data will be written to: when BWW = L, data is written to screen 1 and when BWW = H, data is written to screen 2, as shown in Figure 3-25. When accessing a specified bit, specify both the X address and Y address. The display data in D0 to D7 (sent from the CPU) corresponds to the SEGx portions of the LCD display, as shown in Figure 3-26. Figure 3-27 shows the relationship between the display data in monochrome display mode and the page/column addresses. Figure 3-25. Display RAM Image in Monochrome (Black/White) Mode 00H 0FH 00H Screen 1 DSEL = L (during display) BWW = L (during write) 0FH Screen 2 DSEL = H (during display) BWW = H (during write) Figure 3-26. Relationship Between Display Data and LCD Display Data 7 0 0 0 0 0 0 0 0 6 1 1 1 1 1 1 1 0 5 0 0 1 0 0 0 0 0 4 0 0 0 1 0 0 0 0 3 0 0 0 0 1 0 0 0 2 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 7 1 0 0 1 0 0 1 0 6 1 0 0 1 0 0 1 0 5 1 0 0 1 0 0 1 0 4 1 0 0 1 0 0 1 0 3 0 0 0 0 0 0 0 0 2 0 1 1 1 1 1 0 0 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 Display data 58 LCD display Data Sheet S15548EJ1V0DS µPD16686, 16687 Figure 3-27. Relation Between the Display Data and Page/Column Address D4 D3 D2 D1 0 0 0 0 0 0 0 0 0 1 1 1 D0 0 1 1 00H 01H Data D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 0FH D7 D6 D5 D4 D3 D2 D1 D0 COM output Line address 00H COM1 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 Start Data Sheet S15548EJ1V0DS Column address ADC 0 1 D0 D0 COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127 COM128 LCD output SEG128 00 7F SEG127 01 7E SEG126 02 7D SEG125 03 7C 78 07 SEG8 79 06 SEG7 7A 05 SEG6 SEG5 7B 04 7C 03 SEG4 7D 02 SEG3 SEG2 7F 00 7E 01 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH SEG1 Page address (in Monochrome Display Mode) 59 µPD16686, 16687 3.8.3 Icon display The µPD16686, 16687 include 20 segment pins and two common pins (both output the same signal) for displaying icons, independent of the pins used to display graphics. Icons are static-driven and their contrast can be adjusted at 32 levels using phase modulation. The static icon data RAM (R41) that is used to record icon display data contains display data (DIS) and blink data (BRI) in a 20-bit x 2 configuration, as shown in Table 3-22 (where ADC = 0) and Table 3-23 (where ADC = 1). Addresses in the static icon data RAM are specified via the static icon address register (R40) and then data is written to memory. The icon blink function operates only when the display data setting is 1, the blink data setting is 1, and the IBL setting is also 1 (R1). Table 3-22. Static Icon Data RAM (ADC = 0) Static Icon Output Number (PSEGn) Address DIS BRI DIS BRI DIS BRI DIS BRI D7 D6 D5 D4 D3 D2 D1 D0 00H 1 2 3 01H 5 6 7 4 8 02H 9 10 11 12 03H 13 14 15 16 04H 17 18 19 20 Table 3-23. Static Icon Data RAM (ADC = 1) Static Icon Output Number (PSEGn) Address DIS BRI DIS BRI DIS BRI DIS BRI D7 D6 D5 D4 D3 D2 D1 D0 00H 20 19 18 17 01H 16 15 14 13 02H 12 11 10 9 03H 8 7 6 5 04H 4 3 2 1 Adjustment of contrast is controlled by phase modulation set via the static icon contrast (R42). The pulse width of the ON signal that is output in static drive mode is divided into 32 levels (1/32 to 32/32 pulse width) and the dot output's timing changes during output according to the phase modulation ratio recorded in bits ICS4 to ICS0 of the static icon contrast (R42), as shown in Table 3-24. Table 3-24. Dot Output Timing Changes 60 ICS4 ICS3 ICS2 ICS1 ICS0 Phase Modulation Ratio 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 : 1 1 0 1 1 0 0/32 1/32 2/32 3/32 : 29/32 30/32 1 1 1 1 1 31/32 Data Sheet S15548EJ1V0DS µPD16686, 16687 Figure 3-28. Phase Modulation Driver Waveforms 1 frame 31/32 to 0/32 VDD1 PSEG VSS VDD1 PCOM1 VSS Example of phase modulation amount for displaying 10H 1 frame 16/32 16/32 VDD1 PSEG ON ON VSS VDD1 PCOM1 VSS Data Sheet S15548EJ1V0DS 61 µPD16686, 16687 3.9 Reset In the µPD16686, 16687, a reset is executed when the /RES input is at low level or when a reset command is entered. The IC is reset to its default settings. These default settings are listed in the table below. /RES Reset Command Control register 1 Register R0 Enabled (DISP flag only) Enabled Control register 2 R1 Enabled (IDIS flag only) X address register R3 Disabled Y address register R4 Duty setting register R5 AC driver inversion cycle register R6 AC driver inversion position shift register R7 Partial AC driver inversion cycle register R8 Partial AC driver inversion position shift register R9 Partial display mode setting R10 Display memory access register Note R11 Disabled Display start line set R12 Enabled Blink X address register R13 Blink start line address register R14 Blink end line address register R15 Blink data memory R16 Disabled Inverted X address register R17 Enabled Inversion start line address register R18 Inversion end line address register R19 Inverted data memory R20 Disabled Partial start line address register R21 Enabled Gray scale data register 1 (0, 0) R23 Gray scale data register 2 (0, 1) R24 Gray scale data register 3 (1, 0) R25 Gray scale data register 4 (1, 1) R26 Partial gray scale data register 1 (0, 0) R27 Partial gray scale data register 2 (0, 1) R28 Partial gray scale data register 3 (1, 0) R29 Partial gray scale data register 4 (1, 1) R30 Power system control 1 R32 Power system control 2 R33 Power system control 3 R34 Electronic volume register R35 Partial electronic volume register R36 Boost adjustment register R37 Static icon address R40 Static icon data register R41 Disabled Static icon contrast R42 Enabled RAM test mode setting R44 Signature read R45 Disabled Enabled: Default value is input, Disabled: Default value is not input Note When using the /RES pin to reset, the contents of memory are not retained. Use the reset command to reset if the memory contents need to be retained. Cautions 1. Using the /RES pin to reset initializes the shift clock counter. 2. Always input the reset command as the first command after power application . 62 Data Sheet S15548EJ1V0DS µPD16686, 16687 4. COMMANDS The µPD16686, 16687 chips use a combination of RS, /RD (E), and /WR (R,/W) signals to identify data bus signals. Command interpretation and execution is performed using internal timing that does not depend on any external clock. Therefore, processing is very fast and there is usually no need to check for a busy status. The i80 series CPU interface activates read commands using a low pulse input to the /RD pin and activates write commands using a low pulse input to the /WR pin. The M68 series CPU interface sets read mode using a high level input to the R,/W pin and sets write mode using a low level input to the same pin. It activates both read and write commands using a high-level pulse input to the E pin. Thus, the M68 series CPU interface differs from the i80 series CPU interface in that /RD (E) is at high level during status read and display data read operations, as shown in the following command descriptions and command table. Command descriptions using an i80 series CPU interface are shown below. If the serial interface has been selected, data is input sequentially starting from D7. Data Sheet S15548EJ1V0DS 63 µPD16686, 16687 4.1 Control Register 1 (R0) These commands specify the µPD16686, 16687's general operation modes. RS E /RD R,/W /WR D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 RMW DISP STBY BLD IVD HALT ADC COMR RMW 0: Address is incremented after both write access and read access. 1: Read/modify/write mode (Address is incremented only after write access) DISP 0: Display OFF (All LCD output pins output the VSS level and oscillator and DC/DC converter are operating) 1: Display ON STBY 0: Normal operation BLD The blinking dots are specified via the blink start/end line address registers and data is set to blink data RAM. 1: Internal operation and oscillation are stopped. Display is off. 0: Stop blinking 1: Start blinking IVD The number of inverted dots is specified via the inversion start/end line address registers and data is set to inverted data RAM. 0: Stop inversion 1: Start inversion HALT 0: Start internal operation 1: Stop internal operation (since different display modes are used, when switching between partial and normal display modes, the LCD output pins all output the VSS level and the oscillator is operating, but the DC/DC converter is stopped) ADCNote The column address corresponding to the SEG outputs (see Table 4-1) for displaying the contents of the display data RAM. COMRNote This inverts (reverses) the scan direction for common outputs. (See Table 4-2) Note The RESET command must be executed before changing this flag's setting. Table 4-1. Relationship Between Display RAM Column Address and SEG Outputs SEG Output ADC (D1) SEG1 SEG128 0 00H → Column addresses → 7FH 1 7FH ← Column addresses ← 00H Table 4-2. Relationship Between Common Scan Circuit and Scan Direction COM Output COMR (D0) Scan Direction 0 COM1 → COM128 1 COM128 ← COM1 Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 64 Data Sheet S15548EJ1V0DS µPD16686, 16687 4.2 Control Register 2 (R1) These commands specify the µPD16686, 16687's general operation modes. RS E /RD R,/W /WR D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 FDM IBL IDIS DSEL BWW GRAY DTY INC FDM Settings for full screen display mode 0: Normal operation 1: Full screen display (set entire screen to ON) (When using four-level gray scale, gray-scale level 32 is output for full screen display). IBL Static icon blink control, icons with "1" as blink data are blinking. 0: Static icon blink OFF 1: Static icon blink ON IDIS 0: Static icon display OFF (All static LCD output pins output the VSS level and oscillator and DC/DC converter are operating) 1: Static icon display ON DSEL Selects display screen during monochrome display mode. 0: Screen 1 1: Screen 2 BWW Selects data write screen during monochrome display mode. 0: Screen 1 1: Screen 2 GRAY Note 0: 4-level gray scale display mode 1: Monochrome display mode DTY Note 0: Normal display mode (1/1 to 1/128 duty) 1: Partial display mode (1/12, 1/25, or 1/38 duty, 1/5 or 1/6 bias) INC 0: Increments X address at each access 1: Increments Y address at each access Note The HALT command must be executed before changing this flag's setting. Table 4-3. Relationship Between IC's Functions and Display Modes Item Normal Display Mode (DTY = 0) Partial Display Mode (DTY = 1) Duty 1/1 to 1/128 duty ↔ 1/12, 1/25, or 1/38 duty Booster ×4, ×5, ×6, ×7, ×8, ×9 ↔ ×2, ×3, ×4 Bias level 1/11, 1/12, 1/10, 1/9, 1/8, 1/7 ↔ 1/5, 1/6 Gray scale data Uses levels set to gray scale data registers (R23 to R26) ↔ Uses levels set to partial gray scale data registers (R27 to R30) (1+Rb/Ra) VLCD regulator resistance factor Uses values of VRR2, VRR1, and VRR0 in power system control register 2 (R33) ↔ Uses values of PVR2, PVR1, and PVR0 in power system control register 2 (R33) Electronic volume Uses value from electronic volume register (R35) ↔ Uses value from partial electronic volume register (R36) Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 Data Sheet S15548EJ1V0DS 65 µPD16686, 16687 4.3 Reset Command (R2) When this command is input, the IC's registers (R0 to R42) are reset to their initial values. Always input the reset command as the first command after power application. RS D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 0 0 1 4.4 X Address Register (R3) The X address register specifies the X address in the display RAM accessed by the CPU. This address is automatically incremented each time the display RAM is accessed (INC = 0, RMW = 0). RS D7 D6 D5 D4 D3 D2 D1 D0 1 - - - XA4 XA3 XA2 XA1 XA0 Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 - - - 0 0 0 0 0 4.5 Y Address Register (R4) The Y address register specifies the Y address in the display RAM accessed by the CPU. This address is automatically incremented each time the display RAM is accessed (INC = 1, RMW = 0). RS D7 D6 D5 D4 D3 D2 D1 D0 1 - YA6 YA5 YA4 YA3 YA2 YA1 YA0 Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 - 0 0 0 0 0 0 0 66 Data Sheet S15548EJ1V0DS µPD16686, 16687 4.6 Duty Setting Register (R5) The display duty can be set to any duty ratio between 1/1 and 1/128, as is shown in Table 4-4. Before modifying this register, be sure to use the HALT command (control register 1 (R0)) to stop internal operations. RS D7 D6 D5 D4 D3 D2 D1 D0 1 - DT6 DT5 DT4 DT3 DT2 DT1 DT0 Table 4-4. Duty Setting Register (R5) Settings DT6 DT5 DT4 DT3 DT2 DT1 DT0 Duty 0 0 0 0 0 0 0 1/1 0 0 0 0 0 0 1 1/2 0 0 0 0 0 1 0 1/3 0 0 0 0 0 1 1 1/4 1 1 1 1 1 0 1 1/126 1 1 1 1 1 1 0 1/127 1 1 1 1 1 1 1 1/128 : : Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 - 1 1 1 1 1 1 1 4.7 AC Driver Inversion Cycle Register (R6) The AC driver's line position for normal display mode can be set as shown in Table 4-5. When a DTYn value is changed in the duty setting register (R5), the NIDn value is automatically overwritten by the DTYn value. RS D7 D6 D5 D4 D3 D2 D1 D0 1 - NID6 NID5 NID4 NID3 NID2 NID1 NID0 Table 4-5. AC Driver Inversion Cycle Register (R6) Settings NID6 NID5 NID4 NID3 NID2 NID1 NID0 Inversion Line 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 2 0 0 0 0 0 1 0 3 0 0 0 0 0 1 1 4 : : 1 1 1 1 1 0 1 126 1 1 1 1 1 1 0 127 1 1 1 1 1 1 1 128 Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 - 1 1 1 1 1 1 1 Data Sheet S15548EJ1V0DS 67 µPD16686, 16687 4.8 AC Driver Inversion Position Shift Register (R7) This shifts the inversion position for each frame in normal display mode by the shift amount shown in Table 4-6. RS D7 D6 D5 D4 D3 D2 D1 D0 1 - MSD6 MSD5 MSD4 MSD3 MSD2 MSD1 MSD0 Table 4-6. AC Driver Inversion Position Shift Register (R7) Settings MSD5 MSD5 MSD4 MSD3 MSD2 MSD1 MSD0 Inversion Position Shift Amount 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 2 0 0 0 0 0 1 1 3 : : 1 1 1 1 1 0 1 125 1 1 1 1 1 1 0 126 1 1 1 1 1 1 1 127 Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 - 0 0 0 0 0 0 0 4.9 Partial AC Driver Inversion Cycle Register (R8) The AC driver's line position can be set as shown in Table 4-7. When a PDTn value is changed in the partial display mode setting register (R10), the PIDn value is automatically overwritten by the PDTn value. RS D7 D6 D5 D4 D3 D2 D1 D0 1 - - PID5 PID4 PID3 PID2 PID1 PID0 Table 4-7. Partial AC Driver Inversion Cycle Register (R8) Settings PID5 PID4 PID3 PID2 PID1 PID0 Inversion Line 0 0 0 0 0 0 1 0 0 0 0 0 1 2 0 0 0 0 1 0 3 0 0 0 0 1 1 4 : : 1 0 0 0 1 1 36 1 0 0 1 0 0 37 1 0 0 1 0 1 38 Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 - - 1 0 0 1 0 1 68 Data Sheet S15548EJ1V0DS µPD16686, 16687 4.10 Partial AC Driver Inversion Position Shift Register (R9) This shifts the inversion position for each frame by the shift amount shown in Table 4-8. RS D7 D6 D5 D4 D3 D2 D1 D0 1 - - PSD5 PSD4 PSD3 PSD2 PSD1 PSD0 Table 4-8. Partial AC Driver Inversion Position Shift Register (R9) Settings PSD5 PSD4 PSD3 PSD2 PSD1 PSD0 Inversion Position Shift Amount 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 2 0 0 0 0 1 1 3 1 0 0 0 1 1 35 1 0 0 1 0 0 36 1 0 0 1 0 1 37 : : Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 - - - 0 0 0 0 0 4.11 Partial Display Mode Setting (R10) This command specifies the operation mode to be used in the µPD16686, 16687's partial display mode. Before modifying this register, be sure to use the HALT command (control register 1 (R0)) to stop internal operations. RS D7 D6 D5 D4 D3 D2 D1 D0 1 - - - - PBIS - PDT1 PDT0 PBIS Sets bias level for partial display mode 0: 1/5 bias 1: 1/6 bias PDT1, PDT0 PDT1 PDT0 Duty in partial display mode 0 0 1/38 duty 0 1 1/25 duty 1 0 1/12 duty 1 1 Prohibited Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 - - - - 0 - 0 0 Data Sheet S15548EJ1V0DS 69 µPD16686, 16687 4.12 Display Memory Access Register (R11) The display memory access register is used when accessing the display RAM. When this register is write-accessed, data is written directly to the display RAM. When this register is read-accessed, data from the display RAM is first latched to this register before being sent to the bus during the next read operation. Accordingly, one dummy read access is required after display RAM access has been set. RS D7 D6 D5 D4 D3 D2 D1 D0 1 D7 D6 D5 D4 D3 D2 D1 D0 Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - - 4.13 Display Start Line Set (R12) Display start line set specifies the top line in the display. RS D7 D6 D5 D4 D3 D2 D1 D0 1 - DSL6 DSL5 DSL4 DSL3 DSL2 DSL1 DSL0 Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 - 0 0 0 0 0 0 0 4.14 Blink X Address Register (R13) The blink X address register specifies the X address of the blink data RAM accessed by the CPU. This address is automatically incremented each time the blink data RAM is accessed. RS D7 D6 D5 D4 D3 D2 D1 D0 1 - - - - BXA3 BXA2 BXA1 BXA0 Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 - - - - 0 0 0 0 70 Data Sheet S15548EJ1V0DS µPD16686, 16687 4.15 Blink Start Line Address Register (R14) The blink start line address register specifies the start line address of the display RAM accessed when the CPU uses blink display mode. The range of blinking lines is determined based on the contents of this register and the blink end line address register. RS D7 D6 D5 D4 D3 D2 D1 D0 Setting 1 - BSL6 BSL5 BSL4 BSL3 BSL2 BSL1 BSL0 - Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 - 0 0 0 0 0 0 0 4.16 Blink End Line Address Register (R15) The blink end line address register specifies the end line address of the display RAM accessed when the CPU uses blink display mode. The range of blinking lines is determined based on the contents of this register and the blink start line address register. RS D7 D6 D5 D4 D3 D2 D1 D0 Setting 1 - BEL6 BEL5 BEL4 BEL3 BEL2 BEL1 BEL0 - Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 - 0 0 0 0 0 0 0 4.17 Blink Data Memory (R16) The blink data memory access register is used to access the blink data RAM. When this register is write-accessed, data is written directly to the blink data RAM. RS D7 D6 D5 D4 D3 D2 D1 D0 1 D7 D6 D5 D4 D3 D2 D1 D0 Data Status 0 Normal 1 Blink Default settings (initial values set by reset command, all data) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 Data Sheet S15548EJ1V0DS 71 µPD16686, 16687 4.18 Inverted X Address Register (R17) The inverted X address register specifies the X address in the inverted data RAM accessed by the CPU. This address is incremented each time the inversion RAM is accessed. RS D7 D6 D5 D4 D3 D2 D1 D0 1 - - - - IXA3 IXA2 IXA1 IXA0 Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 - - - - 0 0 0 0 4.19 Inversion Start Line Address Register (R18) The inversion start line address register specifies the start line address in the display RAM accessed by the CPU when using reverse (inverted) display mode. The range of inverted lines is determined based on the contents of this register and the inversion end line address register. RS D7 D6 D5 D4 D3 D2 D1 D0 1 - ISL6 ISL5 ISL4 ISL3 ISL2 ISL1 ISL0 Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 - 0 0 0 0 0 0 0 4.20 Inversion End Line Address Register (R19) The inversion end line address register specifies the end line address in the display RAM accessed by the CPU when using reverse (inverted) display mode. The range of inverted lines is determined based on the contents of this register and the inversion start line address register. RS D7 D6 D5 D4 D3 D2 D1 D0 Setting 1 - IEL6 IEL5 IEL4 IEL3 IEL2 IEL1 IEL0 - Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 - 0 0 0 0 0 0 0 72 Data Sheet S15548EJ1V0DS µPD16686, 16687 4.21 Inverted Data Memory (R20) The inverted data memory access register is used when accessing the inverted data RAM. When this register is accessed, the data is written directly to the inverted data RAM. RS D7 D6 D5 D4 D3 D2 D1 D0 Setting 1 D7 D6 D5 D4 D3 D2 D1 D0 - Data Status 0 Normal 1 Inverted Default settings (initial values set by reset command, all data) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 4.22 Partial Start Line Address Register (R21) The partial start line address register specifies the start line address in the display RAM accessed by the CPU when using partial display mode. The partial display area is determined as the number of lines specified in the partial display mode setting register (R10), starting from this start line address. RS D7 D6 D5 D4 D3 D2 D1 D0 Setting 1 - PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0 - Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 - 0 0 0 0 0 0 0 Data Sheet S15548EJ1V0DS 73 µPD16686, 16687 4.23 Gray Scale Data Registers 1 to 4 (R23, R24, R25, R26) The gray scale data registers specify the gray scale level when using normal four-level gray scale display mode. Use of this register optimizes the gray scale display. Rx Data RS D7 D6 D5 D4 D3 D2 D1 D0 R23 0, 0 1 - - GD5 GD4 GD3 GD2 GD1 GD0 R24 0, 1 1 - - GD5 GD4 GD3 GD2 GD1 GD0 R25 1, 0 1 - - GD5 GD4 GD3 GD2 GD1 GD0 R26 1, 1 1 - - GD5 GD4 GD3 GD2 GD1 GD0 D7 D6 D5 D4 D3 D2 D1 D0 Gray scale level Disable Disable 0 0 0 0 0 0 Level 0 Disable Disable 0 0 0 0 0 1 Level 1 Disable Disable 0 0 0 0 1 0 Level 2 Disable Disable 0 0 0 0 1 1 Level 3 : Setting : Disable Disable 0 1 1 1 1 1 Level 31 Disable Disable 1 0 0 0 0 0 Level 32 Default settings (initial values set by reset command, for all gray scale data registers) D7 D6 D5 D4 D3 D2 D1 D0 - - 0 0 0 0 0 0 4.24 Partial Gray Scale Data Registers 1 to 4 (R27, R28, R29, R30) The partial gray scale data registers specify the gray scale level when using partial four-level gray scale display mode. Use of this register optimizes the gray scale display. Rx Data RS D7 D6 D5 D4 D3 D2 D1 D0 Setting R23 0, 0 1 - - PGD5 PGD4 PGD3 PGD2 PGD1 PGD0 - R24 0, 1 1 - - PGD5 PGD4 PGD3 PGD2 PGD1 PGD0 - R25 1, 0 1 - - PGD5 PGD4 PGD3 PGD2 PGD1 PGD0 - R26 1, 1 1 - - PGD5 PGD4 PGD3 PGD2 PGD1 PGD0 - D7 D6 D5 D4 D3 D2 D1 D0 Gray scale level Disable Disable 0 0 0 0 0 0 Level 0 Disable Disable 0 0 0 0 0 1 Level 1 Disable Disable 0 0 0 0 1 0 Level 2 Disable Disable 0 0 0 0 1 1 Level 3 : : Disable Disable 0 1 1 1 1 1 Level 31 Disable Disable 1 0 0 0 0 0 Level 32 Default settings (initial values set by reset command, for all partial gray scale data registers) D7 D6 D5 D4 D3 D2 D1 D0 - - 0 0 0 0 0 0 74 Data Sheet S15548EJ1V0DS µPD16686, 16687 4.25 Power System Control 1 (R32) This command sets the µPD16686, 16687's power system mode. E R,/W RS /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 HPM1 HPM0 - TCS2 TCS1 OP2 OP1 OP0 HPM1, HPM0 These bits set the driver mode as shown in Table 4-9. TCS1, TCS0 These bits set the value for selecting the VREG voltage's temperature curve, as shown in Table 4-10. OP2, OP1, OP0 These bits control the booster's ON/OFF status, the voltage regulator (V regulator) and voltage follower (V/F). The functions controlled via these three bits by the power control setting command are listed in Table 4-11. Table 4-9. Driver Mode Setting HPM1 HPM0 Mode Setting 0 0 Normal mode 0 1 Low-power mode 1 0 High-power mode 1 1 Power activation mode Table 4-10. Selection VREG Voltage's Temperature Curve Value TCS1 TCS0 Temperature gradient 0 0 −0.09 0 1 −0.11 1 0 −0.12 1 1 external inputs Unit VREG (TYP.) Unit 0.88 %, °C 0.80 V 0.75 - Table 4-11. Detailed Description of Functions Controlled by Bits of Power System Control 1 Status Item 1 0 ON OFF OP2 Booster control bit OP1 V regulator control bit ON OFF OP0 Voltage follower control bit ON OFF Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 0 0 - 0 0 1 1 1 Data Sheet S15548EJ1V0DS 75 µPD16686, 16687 4.26 Power System Control 2 (R33) This command sets the µPD16686, 16687's power system mode. E R,/W RS /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 Setting 1 1 0 - VRR2 VRR1 VRR0 - PVR2 PVR1 PVR0 - VRR2, VRR1, When using normal display mode, power system control 2 (VLCD regulator resistance factor setting command) can VRR0 be used to change the resistance factor at 8 levels. The three bits in power system control 2 set the values shown in Table 4-12 as reference values for (1 + Rb/Ra). PVR2, PVR1, When using partial display mode, power system control 2 (VLCD regulator resistance factor setting command) can PVR0 be used to change the resistance factor at 8 levels. The three bits in power system control 2 set the values shown in Table 4-12 as reference values for (1 + Rb/Ra). Table 4-12. Reference Values for VLCD Internal Resistance Factor Regulator Register Register VRR2 VRR1 VRR0 PVR2 PVR1 PVR0 0 0 0 5 0 0 1 8 0 1 0 12 0 1 1 13 1 0 0 16 1 0 1 19 1 1 0 21 1 1 1 24 Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 - 0 0 0 - 0 0 0 76 Data Sheet S15548EJ1V0DS 1+Rb/Ra µPD16686, 16687 4.27 Power System Control 3 (R34) This command sets the power system mode, including the bias setting for the µPD16686, 16687's normal display mode and the number of boost levels for partial display mode. RS D7 D6 D5 D4 D3 D2 D1 D0 Setting 1 BIS2 BIS1 BIS0 FBS2 FBS1 FBS0 BST1 BST0 - BIS2, BIS1, These three flags select the bias ratio as shown below. Note BIS0 BIS2 BIS1 BIS0 0 0 0 Boost level 1/12 bias 0 0 1 1/11 bias 0 1 0 1/10 bias 0 1 1 1/9 bias 1 0 0 1/8 bias 1 0 1 1/7 bias 1 1 0 Prohibited 1 1 1 Prohibited When partial display mode is set, the bias ratio set by the partial mode setting is automatically selected. FBS2, FBS1, The number of boost levels in booster for normal display mode is selected as shown below. FBS0Note BST1, BST0 FBS2 FBS1 FBS0 Boost level 0 0 0 x4 0 0 1 x5 0 1 0 x6 0 1 1 x7 1 0 0 x8 1 0 1 x9 1 1 0 Prohibited 1 1 1 Prohibited The number of boost levels in the booster for partial display mode is selected as shown below. BST1 BST0 Boost level 0 0 x2 0 1 x3 1 0 x4 1 1 Prohibited Note Be sure to execute the HALT command before changing these flag settings. Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 Data Sheet S15548EJ1V0DS 77 µPD16686, 16687 4.28 Electronic Volume Register (R35) The electronic volume register specifies the electronic volume value for adjusting the contrast when using normal display mode. Any value among 256 steps can be selected. RS D7 D6 D5 D4 D3 D2 D1 D0 Setting 1 EV7 EV6 EV5 EV4 EV3 EV2 EV1 EV0 - Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 4.29 Partial Electronic Volume Register (R36) The partial electronic volume register specifies the electronic volume value for adjusting the contrast when using partial display mode. Any value among 256 steps can be selected. RS D7 D6 D5 D4 D3 D2 D1 D0 Setting 1 PEV7 PEV6 PEV5 PEV4 PEV3 PEV2 PEV1 PEV0 - Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 4.30 Boost Adjustment Register (R37) The voltage (range: 1/8 VDD2 to 7/8 VDD2) set to this register is applied to the boost level set for the booster. RS D7 D6 D5 D4 D3 D2 D1 D0 Setting 1 - - - - - DDC2 DDC1 DDC0 - Table 4-13. Boost Adjustment Register (R37) Settings DDC2 DDC1 DDC0 Boost Adjustment Voltage 0 0 0 Regulator Circuit Stopped 0 0 1 1/8 VDD2 0 1 0 2/8 VDD2 0 1 1 3/8 VDD2 1 0 0 4/8 VDD2 1 0 1 5/8 VDD2 1 1 0 6/8 VDD2 1 1 1 7/8 VDD2 Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 - - - - - 0 0 0 78 Data Sheet S15548EJ1V0DS µPD16686, 16687 4.31 Static Icon Address (R40) The static icon address specifies the address in the static icon data RAM accessed by the CPU. This address is automatically incremented each time the static icon data RAM is accessed. RS D7 D6 D5 D4 D3 D2 D1 D0 1 - - - - - SIA2 SIA1 SIA0 Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 - - - - - 0 0 0 4.32 Static Icon Data Register (R41) The static icon data register is used when accessing the static icon data RAM. When this register is write-accessed, the data is written directly to the static icon data RAM. RS D7 D6 D5 D4 D3 D2 D1 D0 1 D7 D6 D5 D4 D3 D2 D1 D0 Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - - 4.33 Static Icon Contrast (R42) The static icon contrast adjusts the contrast of static icons using phase modulation. The pulse width of the ON signal that is output in static drive mode is divided into 32 levels (1/32 to 32/32 pulse width) and the dot output's timing changes during output according to the phase modulation ratio recorded in bits ICS4 to ICS0 of the static icon contrast (R42), as is shown in Table 4-14. RS D7 D6 D5 D4 D3 D2 D1 D0 1 - - - 0 ICS3 ICS2 ICS1 ICS0 Table 4-14. Static Icon Contrast (R42) Setting ICS4 ICS3 ICS2 ICS1 ICS0 Phase Modulation Ratio 0 0 0 0 0 0/32 0 0 0 0 1 1/32 0 0 0 1 0 2/32 0 0 0 1 1 3/32 : : 1 1 1 0 1 29/32 1 1 1 1 0 30/32 1 1 1 1 1 31/32 Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 - - - - 0 0 0 0 Data Sheet S15548EJ1V0DS 79 µPD16686, 16687 4.34 RAM Test Mode Setting (R44) The RAM test mode setting register directly writes the data for each type of display mode to the display RAM, as shown in Table 4-15. RS D7 D6 D5 D4 D3 D2 D1 D0 1 - - - - RTS3 RTS2 RTS1 RTS0 Table 4-15. RAM Test Mode Setting (R44) RTS3 RTS2 RTS1 RTS0 Write Data 0 0 0 0 Normal operation 0 1 0 0 Displays list of gray scales 1 0 0 0 all 00/pixel 1 0 0 1 all 11/pixel 1 0 1 0 Checker pattern: 00/11 1 0 1 1 Checker pattern: 11/00 1 1 0 0 Checker pattern: 01/10 1 1 0 1 Checker pattern: 10/01 1 1 1 0 Vertical striped pattern: 00/11 1 1 1 1 Horizontal striped pattern: 00/11 Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 - - - - 0 0 0 0 4.35 Signature Read (R45) This commnad is used to read the IC signature set via the SIGIN1 and SIGIN2 pins. This is a read-only register. RS D7 D6 D5 D4 D3 D2 D1 D0 1 - - - - - - SIGIN2 SIGIN1 Default settings (initial values set by reset command) D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - - 80 Data Sheet S15548EJ1V0DS µPD16686, 16687 5. LIST OF µPD16686, 16687 REGISTERS CS RS 5 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Remark Index Register 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Register Name R/W IR R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 Index Register Control register 1 Control register 2 Reset command X address register Y address register Duty setting register AC driver inversion cycle register AC driver inversion position shift register Partial AC driver inversion cycle register Partial AC driver inversion potision shift register Partial display mode setting Display memory access register Display start line set Blink X address register Blink start line address register Blink end line address register Blink data memory Inverted X address register Inversion start line address register Inversion end line address register Inverted data memory Partial start line address register 7 6 5 Data Bits 4 3 2 1 0 W IR5 IR4 IR3 IR2 IR1 IR0 R/W RMW DISP STBY BLD IVD HALT ADC COMR R/W FDM IBL IDIS DSEL BWW GRAY DTY INC CRES W R/W XA4 XA3 XA2 XA1 XA0 R/W YA6 YA5 YA4 YA3 YA2 YA1 YA0 R/W DT6 DT5 DT4 DT3 DT2 DT1 DT0 R/W NID6 NID5 NID4 NID3 NID2 NID1 NID0 W MSD6 MSD5 MSD4 MSD3 MSD2 MSD1 MSD0 W PID4 PID3 PID2 PID1 PID0 W PSD4 PSD3 PSD2 PSD1 PSD0 R/W PBIS PDT1 PDT0 R/W D7 D6 D5 D4 D3 D2 D1 D0 W DSL6 DSL5 DSL4 DSL3 DSL2 DSL1 DSL0 R/W BXA3 BXA2 BXA1 BXA0 R/W BSL6 BSL5 BSL4 BSL3 BSL2 BSL1 BSL0 R/W BEL6 BEL5 BEL4 BEL3 BEL2 BEL1 BEL0 R/W D7 D6 D5 D4 D3 D2 D1 D0 R/W IXA3 IXA2 IXA1 IXA0 R/W ISL6 ISL5 ISL4 ISL3 ISL2 ISL1 ISL0 R/W IEL6 IEL5 IEL4 IEL3 IEL2 IEL1 IEL0 R/W D7 D6 D5 D4 D3 D2 D1 D0 W PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0 Gray scale data register 1 (0, 0) Gray scale data register 2 (0, 1) Gray scale data register 3 (1, 0) Gray scale data register 4 (1, 1) Patial gray scale data register 1 (0, 0) Patial gray scale data register 2 (0, 1) Patial gray scale data register 3 (1, 0) Patial gray scale data register 4 (1, 1) W W W W W W W W Power system control 1 Power system control 2 Power system control 3 Electronic volume register Partial electronic volume register Boost adjustment register W W W W W W Static icon address Static icon data register Static icon contrast W R/W W RAM test mode setting Signature read W R HPM1 HPM0 VRR2 BIS2 BIS1 EV7 EV6 PEV7 PEV6 D7 D6 GD5 GD5 GD5 GD5 PGD5 PGD5 PGD5 PGD5 GD4 GD4 GD4 GD4 PGD4 PGD4 PGD4 PGD4 GD3 GD3 GD3 GD3 PGD3 PGD3 PGD3 PGD3 GD2 GD2 GD2 GD2 PGD2 PGD2 PGD2 PGD2 GD1 GD1 GD1 GD1 PGD1 PGD1 PGD1 PGD1 GD0 GD0 GD0 GD0 PGD0 PGD0 PGD0 PGD0 VRR1 BIS0 EV5 PEV5 TCS1 VRR0 FBS2 EV4 PEV4 TSC0 OP2 PVR2 FBS1 FBS0 EV3 EV2 PEV3 PEV2 DDC2 OP1 PVR1 BST1 EV1 PEV1 DDC1 OP0 PVR0 BST0 EV0 PEV0 DDC0 D5 SIA2 SIA1 SIA0 D4 D3 D2 D1 D0 ICS4 ICS3 ICS2 ICS1 ICS0 RTS3 RTS2 RTS1 RTS0 SIG2 SIG1 : Not to use these registers. Data Sheet S15548EJ1V0DS 81 µPD16686, 16687 6. POWER SUPPLY SEQUENCE The µPD16686, 16687 includes power supply circuitry, such as a booster and a voltage follower. When a reset is performed using the /RES pin, the reset function is restricted so as to prevent operation faults that may occur due to noise effects, etc. When electric charge remains in the smoothing capacitor that is connected between the VSS pin and the voltage pins related to the LCD driver (VLCD to VLC4), abnormalities such as a brief all-black display screen may occur when the power is switched ON or OFF. The following power-on sequence is recommended as a means to avoid such abnormalities when switching the power ON or OFF. 6.1 Power ON Sequence (When Using On-Chip Power Supply, Power Supply ON → Display ON) Turn power ON while /RES pin's status is L ↓ Power supply stabilization ↓ /RES pin = H ↓ Command reset ↓ Control register 1 DISP = 0, HALT = 1 ↓ R2 Wait at least 50 µs befor command input Register reset R0 Display OFF, internal operations stopped IC functions set via command input • Control register 1 (DISP = 0, HALT = 1 status is retained) • Control register 2 • Power control register 1 (HPM1, HPM0 = 1, 1) • Power control registers 2, 3 • Electronic volume register • Partial electronic volume register Specification of power activation mode • Boost adjustment register ↓ User-specified settings via command input Function settings for gray scale data, etc. ↓ Initialization complete ↓ Control register 1 DISP = 0, HALT = 0 ↓ R0 LCD display screen settings • Set start line for display • Write screen data, etc. + wait time ↓ Power control register 1 (Mode when HPM1, HPM0 (1, 1)) ↓ Control register 1 DISP = 1, HALT = 0 Note Display OFF, internal operations started After internal operations are started, wait at least 400 ms before turning on the LCD display.Note Cancels V/F mode for power activation R0 Display ON, internal operation start mode This 400 ms wait time varies according to the panel characteristics and the capacitance value of the boost/smoothing capacitor. We recommend determining the wait time after making a thorough evaluation of the actual device (refer to 6.5 VOUT, VLCD Voltage Sequence (Power ON → Power OFF)). 82 Data Sheet S15548EJ1V0DS µPD16686, 16687 6.2 Power OFF Sequence (When Using On-Chip Power Supply) Operation mode ↓ DISP = 0, HALT = 0 R0 Display OFF, internal operation start mode R32 Sets high power mode R35 [EV7, EV6, EV5, EV4, EV3, EV2, EV1, EV0] = [0, 0, 0, 0, 0, 0, 0, 0] R36 [PEV7, PEV6, PEV5, PEV4, PEV3, PEV2, PEV1, PEV0] = [0, 0, 0, 0, 0, 0, 0, 0] ↓ HPM1 = 1, HPM0 = 0 ↓ Set electronic volume register ↓ Set partial electronic volume register Wait at least 1200 ms before power OFF.Note ↓ Power supply OFF Note This 1200 ms wait time varies according to the panel characteristics and the capacitance value of the boost/smoothing capacitor. NEC recommends determining the wait time after making a thorough evaluation of the actual device (refer to 6.5 VOUT, VLCD Voltage Sequence (power ON → power OFF)). 6.3 Power ON Sequence (When Using External Driver Power Supply, Power ON → Display ON) VDD1, VDD2 power ON, VOUT = Hi-Z Logic power ON when /RES pin = L ↓ Power supply stabilization ↓ /RES pin = H ↓ Command reset R2 Wait at least 50 µs befor command input Register reset R0 Display OFF, internal operations stopped ↓ DISP = 0, HALT = 1 ↓ Power system control register 1 (R32) : [OP2, OP1, OP0] = [0 ,0 ,X] Initialization via command input (user-specified) Selection of IC functions, etc. ↓ DISP = 0, HALT = 0 R0 Display OFF, internal operations started ↓ VOUT power supply ON External LCD driver power supply ON ↓ Stabilization of external LCD driver power supply ↓ DISP = 1, HALT = 0 R0 Display ON, internal operations started Data Sheet S15548EJ1V0DS 83 µPD16686, 16687 6.4 Power Supply OFF Sequence (When Using External Driver Power Supply) Operation mode ↓ DISP = 0, HALT = 0 R0 Display OFF, internal operation start mode ↓ VOUT = Hi-Z External driver power supply OFF ↓ DISP = 0, HALT = 1 R0 Display OFF, internal operations stopped ↓ Logic power supply OFF 84 VDD1, VDD2, power supply OFF Data Sheet S15548EJ1V0DS µPD16686, 16687 6.5 VOUT, VLCD Voltage Sequence (Power ON → Power OFF) 0 VDD VOUT /RES pin = 0 Power ON /RES pin = 1 DISP = 0, HALT = 1 Default settings HPM = 3 HALT = 0 400 ms Select HPM = 0 to 2 DISP = 1 Normal display DISP = 0 HPM = 2 DTY = 1 700 ms VLCD = 15V 6V Select HPM = 0 to 2 DISP = 1 Partial display DISP = 0 HPM = 3 DTY = 0 400 ms Select HPM = 0 to 2 DISP = 1 Normal display DISP = 0 HPM = 2 EV = 0 1200 ms Power OFF Dotted line: VOUT Solid line: VLCD Conditions: VDD: VDD1 = VDD2 = 3.0 V Boost levels: x6 (in normal display mode), x3 (in partial display mode) Capacitors: VLCn pin to Cn+/− pin = 1 µF, AMPOUT pin, AMPOUTP pin, VRS pin = 0.1 µF Caution Connect a 0.1 µF capacitor to the AMPOUT, and AMPOUTP pins. Data Sheet S15548EJ1V0DS 85 µPD16686, 16687 7. USE OF RAM TEST MODE The µPD16686, 16687 has a test mode for writing nine types of screen data to display RAM. When using the test mode, be sure to execute via the sequence shown below. If executing the test mode by some other sequence, abnormalities may appear in the screen display. Operation mode ↓ Control register 1 DISP = 0, STBY = 1 R0 Display OFF, set to standby R44 Select RAM write data R0 Display OFF, cancel standby ↓ Set RAM test mode ↓ Control register 1 DISP = 0, STBY = 0 ↓ After internal operations are started, wait at least 1 s before turning on the LCD display.Note Wait time ↓ Control register 1 DISP = 1 R0 Display ON ↓ Settings complete Note This 1 s wait time varies according to the panel characteristics and the capacitance value of the boost/smoothing capacitor. NEC recommends determining the wait time after making a thorough evaluation of the actual device. 86 Data Sheet S15548EJ1V0DS µPD16686, 16687 8. USE OF STANDBY/HALT MODE The µPD16686, 16687 has a standby mode for reducing current consumption, and a HALT mode for switching display mode. Electrical circuits as a DC/DC converter are stopped in standby/HALT mode. When using the standby/HALT mode, be sure to execute via the sequence shown below. If executing the test mode by some other sequence, abnormalities may appear in the screen display. Operation mode ↓ Control register 1 DISP = 0, STBY = 0, HALT = 0 R0 Display OFF R0 Display OFF, set to standby (HALT) R32 Reverse sequence to normal operation R0 Display OFF, cancel standby (HALT) ↓ Control register 1 DISP = 0, STBY = 1(or HALT = 1) ↓ Standby mode ↓ Power control register 1 (HPM1, HPM0 = 1, 1) ↓ Control register 1 DISP = 0, STBY = 0(or HALT = 0) ↓ After internal operations are started, wait at least 400 ms before turning on the LCD display.Note Wait time ↓ Power control register 1 (Set except HPM1, HPM0 =1, 1) R32 Set except HPM1, HPM0 = 1,1 (power activation) mode ↓ Control register 1 DISP = 1, HALT = 0 Note Display ON, internal operation start mode This 400 ms wait time varies according to the panel characteristics and the capacitance value of the boost/smoothing capacitor. We recommends determining the wait time after making a thorough evaluation of the actual device. Data Sheet S15548EJ1V0DS 87 µPD16686, 16687 9. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = +25°C, VSS = 0 V) Parameter Symbol Ratings Unit Logic system supply voltage VDD1 −0.3 to +4.0 V Booster supply voltage VDD2 −0.3 to +4.0 V Driver supply voltage VOUT −0.3 to +20.0 V Driver reference supply input voltage VLCD, VLC1 to VLC4 −0.3 to VOUT+0.3 V Logic system input voltage VIN1 −0.3 to VDD1+0.3 V Logic system output voltage VOUT1 −0.3 to VDD1+0.3 V Logic system input/output voltage VI/O1 −0.3 to VDD1+0.3 V Driver system input voltage VIN2 −0.3 to VOUT+0.3 V Driver system output voltage VOUT2 −0.3 to VOUT+0.3 V Operating ambient temperature TA −40 to +85 °C Storage temperature Tstg −55 to +125 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range Parameter Symbol MIN. TYP. MAX. Unit Logic system supply voltage VDD1 1.7 3.6 V Booster supply voltage VDD2Note1 2.4 3.6 V Note2 Driver supply voltage VOUT 5.5 18.0 V Logic system input voltage VIN 0 VDD1 V Driver system supply voltage VLCD, VLC1 to VLC4 Note2 0 VOUT V VOUT − 0.5 V Maximum setting for LCD driver voltage Note3 VLCD Notes 1. VDD1 must be less than or equal to VDD2 2. This item is the recommended parameter when the LCD has an external driver. 3. This item is the recommended parameter when the LCD is driven by an on-chip power supply circuit. Cautions 1. When using an external LCD driver, be sure to maintain these relations: VSS < VLC4 < VLC3 < VLC2 < VLC1 < VLCD ≤ VOUT. 2. Maintain the relations shown in 6. POWER SUPPLY SEQUENCE when turning the power on or off. 3. When using an external resister (when not using an on-chip resister for VLCD adjustment), maintain supply of a voltage between 1.0 V and the VDD1 voltage to the VR and VRS pins. 88 Data Sheet S15548EJ1V0DS µPD16686, 16687 Electrical Characteristics 1 (Unless Otherwise Specified, TA = −40 to +85°°C, VDD1 = 1.7 to 3.6 V, VDD2 = 2.4 to 3.6 V) Parameter Symbol Conditions MIN. TYP.Note1 MAX. 0.8 VDD1 Unit Input voltage, high VIH V Input voltage, low VIL Input current, high IIH1 Except for D7 (SI), D6 (SCL) and D5 to D0 Input current, low IIL1 Except for D7 (SI), D6 (SCL) and D5 to D0 Output voltage, high VOH IOUT = −1 mA except OSCOUT Output voltage, low VOL IOUT = 1 mA except OSCOUT 0.5 V Leakage current, high ILOH D7 (SI), D6 (SCL) and D5 to D0, 10 µA −10 µA 4 kΩ 4 kΩ 0.2 VDD1 V 1 µA 1 µA VDD1−0.5 V VIN/OUT = VDD1 Leakage current, low ILOL D7 (SI), D6 (SCL) and D5 to D0, VIN/OUT = VSS Common output ON resistance RCOM VLCn → COMn, VOUT = 15 V, VLCD = 13 V, 1/10 bias, |IO| = 50 µA Segment output ON resistance RSEG VLCn → SEGn, VOUT = 15 V, VLCD = 13 V, 1/10 bias, |IO| = 50 µA Driver voltage (boost voltage) VOUT In x5 boost mode, VDD = 3.0 V, 13.8 V 16.6 V Checker pattern display In x6 boost mode, VDD = 3.0 V, Checker pattern display Oscillation frequency fOSCNote2 VDD1 = 3.0 V, TA = 25°C, 1/38 duty, 36 kHz 10.6 kHz in B/W mode, R = 750 kΩ VDD1 = 3.0 V, TA = 25°C, 1/38 duty, in B/W mode, R = 3 MΩ Notes 1. TYP. values are reference values when TA = 25°C. 2. This time varies according to the parasitic capacitance of the wiring capacitance, etc. We therefore recommend determining the oscillation resister's value after making a thorough evaluation of the actual device. Data Sheet S15548EJ1V0DS 89 µPD16686, 16687 Electrical Characteristics 2 (Unless Otherwise Specified, TA = −40 to +85°°C) Parameter Current consumption Symbol IDD11 (normal mode) Conditions Frame frequency = 70 Hz, MIN. TYP.Note MAX. Unit 180 290 µA 250 390 µA 300 460 µA 380 560 µA 135 220 µA 210 320 µA 95 140 µA 105 160 µA 10 µA 35 µA B/W all display OFF data output, 1/128 duty, VDD1 = VDD2 = 3.0 V, in x5 boost mode, VLCD = 13 V Frame frequency = 70 Hz, B/W checker pattern display data output, 1/128 duty, VDD1 = VDD2 = 3.0 V, in x5 boost mode, VLCD = 13 V Current consumption IDD12 (high-power mode) Frame frequency = 70 Hz, B/W all display OFF data output, 1/128 duty, VDD1 = VDD2 = 3.0 V, in x5 boost mode, VLCD = 13 V Frame frequency = 70 Hz, B/W checker pattern display data output, 1/128 duty, VDD1 = VDD2 = 3.0 V, in x5 boost mode,VLCD = 13 V Current consumption IDD13 (low-power mode) Frame frequency = 70 Hz, B/W all display OFF data output, 1/128 duty, VDD1 = VDD2 = 3.0 V, in x5 boost mode, VLCD = 13 V Frame frequency = 70 Hz, B/W checker pattern display data output, 1/128 duty, VDD1 = VDD2 = 3.0 V, in x5 boost mode, VLCD = 13 V Current consumption IDD21 (partial display mode) Frame frequency = 70 Hz, B/W all display OFF data output, 1/38 duty, VDD1 = VDD2 = 3.0 V, in x3 boost mode, VLCD = 7.0 V Frame frequency = 70 Hz, B/W checker pattern display data output, 1/38 duty, VDD1 = VDD2 = 3.0 V, VLCD = 7.0 V, in x3 boost mode Current consumption IDD22 VDD1 = VDD2 = 3.0 V (standby mode) Current consumption (display icon) IDD23 Icon frame frequency = 125 Hz, B/W all display OFF data output, VDD1 = 3.0 V Note TYP. values are reference values when TA = 25°C. 90 Data Sheet S15548EJ1V0DS 18 µPD16686, 16687 Required Timing Conditions (Unless Otherwise Specified, TA = −30 to +85°°C) (1) i80 CPU interface RS tAS8 tf tr tAH8 /CS1 (CS2=1) tCYC8 tCCLW, tCCLR /WR, /RD tCCHR, tCCHW tDS8 tDH8 D0 - D7 (Write) tOH8 tACC8 D0 - D7 (Read) When VDD1 = 1.7 V to 2.0 V Parameter Symbol Conditions Address hold time tAH8 RS Address setup time tAS8 RS System cycle time tCYC8 MIN. TYP.Note MAX. 0 Unit ns 0 ns 1000 ns Control low-level pulse width (/WR) tCCLW /WR 160 ns Control low-level pulse width (/RD) tCCLR /RD 430 ns Control high-level pulse width (/WR) tCCHW /WR 160 ns Control high-level pulse width (/RD) tCCHR /RD 160 ns Data setup time tDS8 D0 to D7 160 ns Data hold time tDH8 D0 to D7 0 /RD access time tACC8 D0 to D7, CL = 100 pF 0 470 ns Output disable time tOH8 D0 to D7, CL = 5 pF, R = 3 kΩ 0 170 ns MAX. Unit ns Note TYP. values are reference values when TA = 25°C. When VDD1 = 2.0 to 2.5 V Parameter Symbol Conditions MIN. TYP.Note Address hold time tAH8 RS 0 Address setup time tAS8 RS 0 ns ns System cycle time tCYC8 600 ns Control low-level pulse width (/WR) tCCLW /WR 120 ns Control low-level pulse width (/RD) tCCLR /RD 240 ns Control high-level pulse width (/WR) tCCHW /WR 120 ns Control high-level pulse width (/RD) tCCHR /RD 120 ns Data setup time tDS8 D0 to D7 120 ns Data hold time tDH8 D0 to D7 0 /RD access time tACC8 D0 to D7, CL = 100 pF 0 280 ns Output disable time tOH8 D0 to D7, CL = 5 pF, R = 3 kΩ 0 170 ns ns Note TYP. values are reference values when TA = 25°C. Data Sheet S15548EJ1V0DS 91 µPD16686, 16687 When VDD1 = 2.5 to 3.6 V Parameter Symbol Conditions MIN. TYP.Note MAX. Unit Address hold time tAH8 RS 0 Address setup time tAS8 RS 0 ns ns System cycle time tCYC8 250 ns Control low-level pulse width (/WR) tCCLW /WR 60 ns Control low-level pulse width (/RD) tCCLR /RD 120 ns Control high-level pulse width (/WR) tCCHW /WR 60 ns Control high-level pulse width (/RD) tCCHR /RD 60 ns Data setup time tDS8 D0 to D7 60 ns Data hold time tDH8 D0 to D7 0 /RD access time tACC8 D0 to D7, CL = 100 pF 0 140 ns Output disable time tOH8 D0 to D5, CL = 5 pF, R = 3 kΩ 0 70 ns Note TYP. values are reference values when TA = 25°C. Cautions 1. The rise and fall times of input signal (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20% or 80% of VDD1. 92 Data Sheet S15548EJ1V0DS ns µPD16686, 16687 (2) M68 CPU interface RS R,/W tAS6 tf tAH6 tr /CS1 (CS2 = H) tCYC6 tEWHR, tEWHW E tEWLR, tEWLW tDS6 tDH6 D 0 - D7 (Write) tACC6 tOH6 D0 - D 7 (Read) When VDD1 = 1.7 to 2.0 V Parameter Symbol Conditions MIN. TYP.Note MAX. Unit Address hold time tAH6 RS 0 ns Address setup time tAS6 RS 0 ns System cycle time tCYC6 1000 ns Data setup time tDS6 D0 to D7 160 ns Data hold time tDH6 D0 to D7 0 Access time tACC6 D0 to D7, CL = 100 pF 0 470 ns 0 170 ns Output disable time Enable high pulse width Enable low pulse width ns tOH6 D0 to D7, CL = 5 pF, R = 3 kΩ Read tEWHR E 430 ns Write tEWHW E 160 ns Read tEWLR E 160 ns Write tEWLW E 160 ns Note TYP. values are reference values when TA = 25°C. When VDD1 = 2.0 to 2.5 V Parameter Symbol Conditions MIN. TYP.Note MAX. tAH6 RS Address setup time tAS6 RS System cycle time tCYC6 Data setup time tDS6 D0 to D7 Data hold time tDH6 D0 to D7 0 Access time tACC6 D0 to D7, CL = 100 pF 0 280 ns 0 170 ns Output disable time 0 Unit Address hold time ns 0 ns 600 ns 120 ns ns tOH6 D0 to D7, CL = 5 pF, R = 3 kΩ tEWHR E 240 ns Write tEWHW E 120 ns Read tEWLR E 120 ns tEWLW E 120 ns Enable high pulse width Read Enable low pulse width Write Note TYP. values are reference values when TA = 25°C. Data Sheet S15548EJ1V0DS 93 µPD16686, 16687 When VDD1 = 2.5 to 3.6 V Parameter Symbol Conditions MIN. TYP.Note MAX. Unit Address hold time tAH6 RS 0 Address setup time tAS6 RS 0 ns ns System cycle time tCYC6 250 ns Data setup time tDS6 D0 to D7 60 ns Data hold time tDH6 D0 to D7 0 ns Access time tACC6 D0 to D7, CL = 100 pF 0 140 ns Output disable time tOH6 D0 to D7, CL = 5 pF, R = 3 kΩ 0 70 ns Read tEWHR E 120 ns Write tEWHW E 60 ns Read tEWLR E 60 ns Write tEWLW E 60 ns Enable high pulse width Enable low pulse width Note TYP. values are reference values when TA = 25°C. Cautions 1. The rise and fall times of input signals (tr and tf) are rated at 15 ns or less. When using a fast system cycle time, the rated value range is either (tr + tf) ≤ (tCYC6 − tEWLW − tEWHW) or (tr + tf) ≤ (tCYC6 − tEWLW − tEWHW). 2. All timing is rated based on 20% or 80% of VDD1. 94 Data Sheet S15548EJ1V0DS µPD16686, 16687 (3) Serial interface tCSS tCSH /CS1 (CS2=1) tSAS tSAH RS tSCYC tSLW SCL tf tSHW tr tSDS tSDH SI When VDD1 = 1.7 to 2.5 V Parameter Symbol Conditions MIN. TYP.Note MAX. Unit Serial clock cycle tSCYC SCL 250 ns SCL high-level pulse width tSHW SCL 100 ns SCL low-level pulse width tSLW SCL 100 ns Address hold time tSAH RS 150 ns Address setup time tSAS RS 150 ns Data setup time tSDS SI 100 ns Data hold time tSDH SI 100 ns CS - SCL time tCSS CS 150 ns tCSH CS 150 ns Note TYP. values are reference values when TA = 25°C. When VDD1 = 2.5 to 3.6 V Parameter Symbol Conditions MIN. TYP. Note MAX. Unit Serial clock cycle tSCYC SCL 150 ns SCL high-level pulse width tSHW SCL 60 ns SCL low-level pulse width tSLW SCL 60 ns Address hold time tSAH RS 90 ns Address setup time tSAS RS 90 ns Data setup time tSDS SI 60 ns Data hold time tSDH SI 60 ns CS - SCL time tCSS CS 90 ns tCSH CS 90 ns Note TYP. values are reference values when TA = 25°C. Cautions 1. The rise and fall times of input signal (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20% or 80% of VDD1. Data Sheet S15548EJ1V0DS 95 µPD16686, 16687 (4) Common Parameter Clock input 1 Symbol fN Conditions MIN. TYP.Note MAX. Unit 36 150 kHz 72 150 kHz 10.6 50 kHz 21.3 50 kHz MAX. Unit 50 µs When using OSCIN1, external clock, and on-chip divider, 1/128 duty, B/W mode When using OSCIN1, external clock, and on-chip divider, 1/128 duty, four-level gray scale mode Clock input 2 fP When using OSCIN2, external clock for partial display mode, but not using on-chip divider, B/W mode When using OSCIN2, external clock for partial display mode, but not using on-chip divider, four-level gray scale mode Note TYP. values are reference values when frame frequency = 70 Hz. Cautions 1. The rise and fall times of input signal (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20% or 80% of VDD1. (a) Reset timing tRW /RES tR Internal status During reset Reset complete When VDD1 = 1.7 to 2.5 V Parameter Symbol Reset time tR Reset low pulse width tRW Conditions /RES MIN. TYP.Note µs 50 Note TYP. values are reference values when TA = 25°C. When VDD1 = 2.5 to 3.6 V Parameter Symbol Reset time tR Reset low pulse width tRW Conditions /RES 50 Note TYP. values are reference values when TA = 25°C. Caution All timing is rated based on 20% or 80% of VDD1. 96 MIN. Data Sheet S15548EJ1V0DS TYP.Note MAX. Unit 50 µs µs µPD16686, 16687 10. CPU INTERFACE (REFERENCE EXAMPLE) The µPD16686, 16687 can be connected to either an i80 series CPU or an M68 series CPU. Also, if a serial interface connection is used, the number of signal lines can be reduced. If several µPD16686, 16687 chips are used, the display area can be enlarged. When using this method, use the chip select signal to select and access the ICs. (1) M68 series CPU VCC RS A0 VDD1 A1 to A15 Decoder C86 /CS1 D0 to D7 D0 to D7 CPU µPD16686, 16687 VIMA E E R, /W R, /W /RES /RES PSX VSS GND /RESET (2) i80 series CPU VCC RS A0 VDD1 A1 to A7 CPU Decoder C86 /CS1 µPD16686, 16687 /IORQ D0 to D7 D0 to D7 /RD /RD /WR /WR /RES /RES PSX VSS GND /RESET (3) When using serial interface A0 A1 to A7 RS Decoder Open CPU VDD1 C86 /CS1 D0 to D5 Port1 SI(D7) /Port2 SCL(D6) H or L µPD16686, 16687 VCC PSX /RES /RES VSS GND /RESET Data Sheet S15548EJ1V0DS 97 µPD16686, 16687 [MEMO] 98 Data Sheet S15548EJ1V0DS µPD16686, 16687 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S15548EJ1V0DS 99