TI PCM2706CPJTR

PCM2704C, PCM2705C
PCM2706C, PCM2707C
Burr-Brown Audio
www.ti.com
SBFS036A – AUGUST 2011 – REVISED JULY 2012
Stereo Audio DAC with USB Interface,
Single-Ended Headphone Output and S/PDIF Output
Check for Samples: PCM2704C, PCM2705C, PCM2706C, PCM2707C
FEATURES
1
• On-Chip USB Interface:
– No Dedicated Device Driver Needed
– Full-Speed Transceivers
– Fully Compliant with USB 2.0 Specification
– USB 1.1 Descriptors with USB Audio
Class Support
– Certified by USB-IF
– Partially Programmable Descriptors
– Adaptive Isochronous Transfer for
Playback
– Bus-Powered or Self-Powered Operation
• Sampling Rates: 32 kHz, 44.1 kHz, 48 kHz
• On-Chip Clock Generator with Single 12-MHz
Clock Source
• Single Power Supply:
– Bus-Powered: 5 V, Typical (VBUS)
– Self-Powered: 3.3 V, Typical
• 16-Bit Delta-Sigma Stereo DAC
– Analog Performance at 5 V (Bus-Powered),
3.3 V (Self-Powered):
– THD+N: 0.006% RL > 10 kΩ, SelfPowered
– THD+N: 0.025% RL = 32 Ω
– SNR = 98 dB
– Dynamic Range: 98 dB
– PO = 12 mW, RL = 32 Ω
– Oversampling Digital Filter
– Passband Ripple = ±0.04 dB
– Stop-Band Attenuation = –50 dB
– Single-Ended Voltage Output
– Analog LPF Included
• Multiple Functions:
23456
•
– Up to Eight Human Interface Device (HID)
Interfaces (Model and Setting Dependent)
– Suspend Flag
– S/PDIF Out with SCMS
– External ROM Interface (PCM2704C/6C)
– Serial Programming Interface
(PCM2705C/7C)
– I2S™ Interface (Selectable on
PCM2706C/7C)
Packages:
– 28-Pin SSOP (PCM2704C/5C)
– 32-Pin TQFP (PCM2706C/7C)
APPLICATIONS
•
•
•
•
•
USB Headphones
USB Audio Speaker
USB CRT/LCD Monitor
USB Audio Interface Box
USB-Featured Consumer Audio Product
DESCRIPTION
The PCM2704C/5C/6C/7C are TI's single-chip USB
stereo audio digital-to-analog converters (DACs) with
USB 2.0 compliant full-speed protocol controller and
S/PDIF. The USB-protocol controller works with no
software code, but USB descriptors can be modified
in some areas (for example, vendor ID/product ID)
through the use of an external ROM (PCM2704C/6C)
or serial peripheral interface (SPI) (PCM2705C/7C).
The PCM2704C/5C/6C/7C also employ SpAct™
architecture, TI's unique system that recovers the
audio clock from USB packet data. On-chip analog
phase-locked loops (PLLs) with SpAct enable
playback with low clock jitter.
1
2
3
4
5
6
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SpAct is a trademark of Texas Instruments.
System Two, Audio Precision are trademarks of Audio Precision, Inc.
SPI is a trademark of Motorola, Inc.
I2S, I2C are trademarks of NXP Semiconductors.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
PCM2704C, PCM2705C
PCM2706C, PCM2707C
SBFS036A – AUGUST 2011 – REVISED JULY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current specification and package information, refer to the Package Option Addendum located at
the end of this data sheet or see the respective device product folders at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range unless otherwise noted.
Supply voltage
VBUS
VALUE
UNIT
–0.3 to 6.5
V
VCCP, VCCL, VCCR, VDD
–0.3 to 4
V
Supply voltage differences
VCCP, VCCL, VCCR, VDD
±0.1
V
Ground voltage differences
PGND, AGNDL, AGNDR, DGND, ZGND
±0.1
V
–0.3 to 6.5
V
–0.3 to (VDD + 0.3) < 4
V
VCOM
–0.3 to (VCCP + 0.3) < 4
V
VOUTR
–0.3 to (VCCR + 0.3) < 4
V
VOUTL
–0.3 to (VCCL + 0.3) < 4
V
±10
mA
Ambient temperature under bias
–40 to +125
°C
Storage temperature
–55 to +150
°C
Junction temperature
+150
°C
Package temperature (IR reflow, peak)
+260
°C
HOST
Digital input voltage
Analog input voltage
D+, D–, HID0/MS, HID1/MC, HID2/MD, XTI, XTO, DOUT,
SSPND, CK, DT, PSEL, FSEL, TEST, TEST0, TEST1,
FUNC0, FUNC1, FUNC2, FUNC3
Input current (any pins except supplies)
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range.
VBUS
Supply voltage
VCCP, VCCL, VCCR, VDD
MIN
NOM
MAX
4.35
5
5.25
3
3.3
3.6
Digital input logic level
V
TTL-compatible
Digital input clock frequency
Analog output load resistance
11.994
12
16
32
Analog output load capacitance
Digital output load capacitance
Operating free-air temperature, TA
2
UNIT
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–25
12.006
MHz
Ω
100
pF
20
pF
85
°C
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
PCM2704C, PCM2705C
PCM2706C, PCM2707C
www.ti.com
SBFS036A – AUGUST 2011 – REVISED JULY 2012
ELECTRICAL CHARACTERISTICS
All specifications at TA = +25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, and 16-bit data (unless otherwise noted).
PARAMETER
TEST CONDITIONS
PCM2704CDB, PCM2705CDB
PCM2706CPJT, PCM2707CPJT
MIN
TYP
UNIT
MAX
DIGITAL INPUT/OUTPUT
Host interface
Apply USB revision 1.1, full-speed
Audio data format
USB isochronous data format
INPUT LOGIC
VIH
VIL
VIH (1)
Input logic level
VIL (1)
–0.3
0.8
2
5.5
±10
VIN = 0 V
Input logic current
±10
VIN = 3.3 V
IIL
VDC
0.8
VIN = 3.3 V
(2)
IIH
3.3
–0.3
IIH (2)
IIL
2
65
VIN = 0 V
100
μA
±10
OUTPUT LOGIC
VOH (3)
IOH = –2 mA
VOL (3)
IOL = 2 mA
VOH
Output logic level
IOH = –2 mA
VOL
2.8
0.3
2.4
IOL = 2 mA
VDC
0.4
CLOCK FREQUENCY
Input clock frequency, XTI
fS
11.994
Sampling frequency
12
12.006
MHz
32, 44.1, 48
kHz
16
Bits
1, 2
Channel
DAC CHARACTERISTICS
Resolution
Audio data channel
DC ACCURACY
Gain mismatch, channel-to-channel
±2
±8
% of FSR
Gain error
±2
±8
% of FSR
Bipolar zero error
±3
±6
% of FSR
RL > 10 kΩ, self-powered,
VOUT = 0 dB
0.006
0.01
%
RL > 10 kΩ, bus-powered,
VOUT = 0 dB
0.012
0.02
%
RL = 32 Ω, self-/
bus-powered, VOUT = 0 dB
0.025
DYNAMIC PERFORMANCE
THD+N
(4)
Total harmonic
distortion + noise
Line
(5)
Headphone
THD+N
SNR
Total harmonic distortion + noise
VOUT = –60 dB
2
%
Dynamic range
EIAJ, A-weighted
90
98
dB
Signal-to-noise ratio
EIAJ, A-weighted
90
98
dB
60
70
dB
Channel separation
(1)
(2)
(3)
(4)
(5)
%
HOST pin.
D+, D–, HOST, TEST, TEST0, TEST1, DT, PSEL, FSEL, XTI pins.
FUNC0, FUNC1, FUNC2 pins.
fIN = 1 kHz, using the System Two™ Cascade audio measurement system by Audio Precision™ in RMS mode with a 20-kHz low-pass
filter (LPF) and 400-Hz high-pass filter (HPF).
THD+N performance varies slightly, depending on the effective output load, including dummy load R7, R8 in Figure 34.
Copyright © 2011–2012, Texas Instruments Incorporated
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3
PCM2704C, PCM2705C
PCM2706C, PCM2707C
SBFS036A – AUGUST 2011 – REVISED JULY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, and 16-bit data (unless otherwise noted).
PARAMETER
TEST CONDITIONS
PCM2704CDB, PCM2705CDB
PCM2706CPJT, PCM2707CPJT
MIN
TYP
UNIT
MAX
ANALOG OUTPUT
Output voltage
0.55 VCCL, 0.55 VCCR
Center voltage
Load impedance
VPP
0.5 VCCP
Line
AC-coupling
10
Headphone
AC-coupling
16
LPF frequency response
V
kΩ
32
Ω
–3 dB
140
kHz
f = 20 kHz
–0.1
dB
DIGITAL FILTER PERFORMANCE
Passband
0.454 fS
Stop band
0.546 fS
Hz
Passband ripple
±0.04
Stop band attenuation
–50
Delay time
Hz
dB
dB
20/fS
s
POWER SUPPLY REQUIREMENTS
Voltage range
Supply current
Power dissipation
(self-powered)
Power dissipation
(bus-powered)
Internal power-supply
voltage (7)
VBUS
Bus-powered
4.35
5
5.25
VCCP, VCCL, VCCR,
VDD
Self-powered
3
3.3
3.6
Line
DAC operation
23
30
Headphone
DAC operation (RL = 32 Ω)
35
46
Line/headphone
Suspend mode
150
190
Line
DAC operation
76
108
Headphone
DAC operation (RL = 32 Ω)
116
166
Line/headphone
Suspend mode
495
684
Line
DAC operation
115
158
Headphone
DAC operation (RL = 32 Ω)
175
242
Line/headphone
Suspend mode
750
998
μW
VCCP, VCCL, VCCR,
VDD
Bus-powered
3.35
3.5
VDC
+85
°C
(6)
(6)
(6)
3.2
VDC
mA
μA
mW
μW
mW
TEMPERATURE RANGE
Operating temperature
(6)
(7)
4
–25
In USB suspended state.
VDD, VCCP, VCCL, VCCR pins. These pins work as output pins of internal power supply for bus-powered operation.
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
PCM2704C, PCM2705C
PCM2706C, PCM2707C
www.ti.com
SBFS036A – AUGUST 2011 – REVISED JULY 2012
THERMAL INFORMATION
THERMAL METRIC
PCM2704C,
PCM2705C
(1)
DB
UNITS
32 PINS
θJA
Junction-to-ambient thermal resistance
68.2
θJCtop
Junction-to-case (top) thermal resistance
27.2
θJB
Junction-to-board thermal resistance
29.5
ψJT
Junction-to-top characterization parameter
2.7
ψJB
Junction-to-board characterization parameter
29.1
θJCbot
Junction-to-case (bottom) thermal resistance
N/A
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
THERMAL INFORMATION
PCM2706C,
PCM2707C
THERMAL METRIC (1)
PJT
UNITS
32 PINS
θJA
Junction-to-ambient thermal resistance
TBD
θJCtop
Junction-to-case (top) thermal resistance
TBD
θJB
Junction-to-board thermal resistance
TBD
ψJT
Junction-to-top characterization parameter
TBD
ψJB
Junction-to-board characterization parameter
TBD
θJCbot
Junction-to-case (bottom) thermal resistance
TBD
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2011–2012, Texas Instruments Incorporated
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Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
5
PCM2704C, PCM2705C
PCM2706C, PCM2707C
SBFS036A – AUGUST 2011 – REVISED JULY 2012
www.ti.com
DEVICE INFORMATION
PCM2704C, PCM2705C
DB PACKAGE
(TOP VIEW)
XTO
1
28
XTI
CK
2
27
SSPND
DT
3
26
TEST0
PSEL
4
25
TEST1
DOUT
5
24
HID2/MD
DGND
6
23
HID1/MC
VDD
7
22
HID0/MS
D-
8
21
HOST
D+
9
20
VCCP
VBUS
10
19
PGND
ZGND
11
18
VCOM
AGNDL
12
17
AGNDR
VCCL
13
16
VCCR
VOUTL
14
15
VOUTR
6
VCOM
AGNDR
VCCR
VOUTR
VOUTL
VCCL
AGNDL
ZGND+
PCM2706C, PCM2707C
PJT PACKAGE
(TOP VIEW)
32
31
30
29
28
27
26
25
HOST
3
22
D-
FUNC3
4
21
VDD
FUNC0
5
20
DGND
HID0/MS
6
19
FUNC1
HID1/MC
7
18
FUNC2
HID2/MD
8
17
DOUT
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9
10
11
12
13
14
15
16
PSEL
D+
DT
23
CK
2
XTO
VCCP
XTI
VBUS
SSPND
24
TEST
1
FSEL
PGND
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
PCM2704C, PCM2705C
PCM2706C, PCM2707C
www.ti.com
SBFS036A – AUGUST 2011 – REVISED JULY 2012
Table 1. Pin Descriptions: DB Package (PCM2704C/PCM2705C)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AGNDL
12
—
Analog ground for headphone amplifier of L-channel
AGNDR
17
—
Analog ground for headphone amplifier of R-channel
CK
2
O
Clock output for external ROM (PCM2704C). Must be left open (PCM2705C).
D+
9
I/O USB differential input/output plus (1)
D–
8
I/O USB differential input/output minus (1)
DGND
6
—
Digital ground
DOUT
5
O
S/PDIF output
DT
3
I/O Data input/output for external ROM (PCM2704C). Must be left open with pull-up resistor (PCM2705C). (1)
HID0/MS
22
I
HID key state input (mute), active high (PCM2704C). MS input (PCM2705C). (2)
HID1/MC
23
I
HID key state input (volume up), active high (PCM2704C). MC input (PCM2705C). (2)
HID2/MD
24
I
HID key state input (volume down), active high (PCM2704C). MD input (PCM2705C). (2)
HOST
21
I
Host detection during self-powered operation (connect to VBUS). Max power select during bus-powered
operation (low: 100 mA, high: 500 mA). (3)
PGND
19
—
PSEL
4
I
Power source select (low: self-power, high: bus-power) (1)
SSPND
27
O
Suspend flag, active low (low: suspend, high: operational)
TEST0
26
I
Test pin. Must be set high (1)
TEST1
25
I
Test pin. Must be set high (1)
VBUS
10
—
Connect to USB power (VBUS) for bus-powered operation. Connect to VDD for self-powered operation.
VCCL
13
—
Analog power supply for headphone amplifier of L-channel (4)
VCCP
20
—
Analog power supply for DAC, OSC, and PLL (4)
VCCR
16
—
Analog power supply for headphone amplifier of R-channel (4)
VCOM
18
—
Common voltage for DAC (VCCP/2). Connect decoupling capacitor to PGND.
VDD
7
—
Digital power supply (4)
VOUTL
14
O
DAC analog output for L-channel
VOUTR
15
O
DAC analog output for R-channel
XTI
28
I
Crystal oscillator input (1)
Analog ground for DAC, OSC, and PLL
XTO
1
O
Crystal oscillator output
ZGND
11
—
Ground for internal regulator
(1)
(2)
(3)
(4)
LV-TTL level.
LV-TTL level with internal pulldown.
LV-TTL level, 5-V tolerant.
Connect decoupling capacitor to GND. Supply 3.3 V for self-powered applications.
Copyright © 2011–2012, Texas Instruments Incorporated
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7
PCM2704C, PCM2705C
PCM2706C, PCM2707C
SBFS036A – AUGUST 2011 – REVISED JULY 2012
www.ti.com
Table 2. Pin Descriptions: PJT Package (PCM2706C/PCM2707C)
TERMINAL
NAME
NO.
I/O
AGNDL
26
—
Analog ground for headphone amplifier of L-channel
AGNDR
31
—
Analog ground for headphone amplifier of R-channel
CK
14
O
Clock output for external ROM (PCM2706C). Must be left open (PCM2707C).
D+
23
I/O USB differential input/output plus (1)
D–
22
I/O USB differential input/output minus (1)
DGND
20
—
Digital ground
DOUT
17
O
S/PDIF output/I2S data output
DT
15
I/O Data input/output for external ROM (PCM2706C). Must be left open with pull-up resistor (PCM2707C). (1)
FSEL
9
FUNC0
5
I/O HID key state input (next track), active high (FSEL = 1). I2S LR clock output (FSEL = 0). (2)
FUNC1
19
I/O HID key state input (previous track), active high (FSEL = 1). I2S bit clock output (FSEL = 0). (2)
FUNC2
18
I/O HID key state input (stop), active high (FSEL = 1). I2S system clock output (FSEL = 0). (2)
FUNC3
4
I
HID key state input (play/pause), active high (FSEL = 1). I2S data input (FSEL = 0). (2)
HID0/MS
6
I
HID key state input (mute), active high (PCM2706C). MS input (PCM2707C). (2)
HID1/MC
7
I
HID key state input (volume up), active high (PCM2706C). MC input (PCM2707C). (2)
HID2/MD
8
I
HID key state input (volume down), active high (PCM2706C). MD input (PCM2707C). (2)
HOST
3
I
Host detection during self-powered operation (connect to VBUS). Max power select during bus-powered
operation. (low: 100 mA, high: 500 mA). (3)
PGND
1
—
PSEL
16
I
Power source select (low: self-power, high: bus-power) (1)
SSPND
11
O
Suspend flag, active low (low: suspend, high: operational)
TEST
10
I
Test pin. Must be set high (1)
VBUS
24
—
Connect to USB power (VBUS) for bus-powered operation. Connect to VDD for self-powered operation.
VCCL
27
—
Analog power supply for headphone amplifier of L-channel (4)
VCCP
2
—
Analog power supply for DAC, OSC, and PLL (4)
VCCR
30
—
Analog power supply for headphone amplifier of R-channel (4)
VCOM
32
—
Common voltage for DAC (VCCP/2). Connect decoupling capacitor to PGND.
VDD
21
—
Digital power supply (4)
VOUTL
28
O
DAC analog output for L-channel
VOUTR
29
O
DAC analog output for R-channel
XTI
12
I
Crystal oscillator input (1)
XTO
13
O
Crystal oscillator output
ZGND
25
—
Ground for internal regulator
(1)
(2)
(3)
(4)
8
I
DESCRIPTION
Function select (low: I2S data output, high: S/PDIF output) (1)
Analog ground for DAC, OSC, and PLL
LV-TTL level.
LV-TTL level with internal pulldown.
LV-TTL level, 5-V tolerant.
Connect decoupling capacitor to GND. Supply 3.3 V for self-powered applications.
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Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
PCM2704C, PCM2705C
PCM2706C, PCM2707C
www.ti.com
SBFS036A – AUGUST 2011 – REVISED JULY 2012
FUNCTIONAL BLOCK DIAGRAMS
PCM2704C/PCM2705C
VCCP
VCCL
VCCR
VDD
PGND
AGNDL
AGNDR
DGND
ZGND
Power
Manager
SSPND
5-V to 3.3-V
Voltage Regulator
VBUS
DAC
Control
Endpoint
VOUTR
XCVR
Analog
PLL
VOUTL
USB
Protocol
Controller
USB SIE
VCOM
D+
D-
S/PDIF Encoder
DOUT
EEPROM
FIFO
Buffer
ISO-Out
Endpoint
HID
Endpoint
PSEL
Interface
(1)
Serial Peripheral
Interface
(2)
CK
DT
HOST
HID0/MS
HID1/MC
HID2/MD
TEST0
TEST1
PLL (x 8)
XTI
12 MHz
96 MHz
Tracker
(SpAct)
XTO
(1)
Applies to PCM2704CDB.
(2)
Applies to PCM2705CDB.
Figure 1.
Copyright © 2011–2012, Texas Instruments Incorporated
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9
PCM2704C, PCM2705C
PCM2706C, PCM2707C
SBFS036A – AUGUST 2011 – REVISED JULY 2012
www.ti.com
PCM2706C/PCM2707C
VCCP
VCCL
VCCR
VDD
PGND
AGNDL
AGNDR
DGND
ZGND
Power
Manager
SSPND
5-V to 3.3-V
Voltage Regulator
VBUS
DAC
Control
Endpoint
VOUTR
XCVR
Analog
PLL
VOUTL
USB
Protocol
Controller
USB SIE
VCOM
D+
D-
S/PDIF
Encoder
DOUT
DOUT
FSEL
LRCK
FUNC0
BCK
FUNC1
SYSCK
FUNC2
2
IS
Interface
EEPROM
FIFO
Buffer
DIN
FUNC3
HID3: Next Track
Interface
(1)
CK
DT
HOST
(1)
HID4: Previous Track
HID5: Stop
ISO-Out
Endpoint
(1)
(1)
HID6: Play/Pause
HID
Endpoint
(1)
Serial Peripheral
Interface
(2)
HID0/MS
HID1/MC
HID2/MD
PSEL
TEST
PLL (x 8)
XTI
12 MHz
96 MHz
Tracker
(SpAct)
XTO
(1)
Applies to PCM2706CPJT.
(2)
Applies to PCM2707CPJT.
Figure 2.
10
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Product Folder Link(s): PCM2704C PCM2705C PCM2706C PCM2707C
PCM2704C, PCM2705C
PCM2706C, PCM2707C
www.ti.com
SBFS036A – AUGUST 2011 – REVISED JULY 2012
TYPICAL CHARACTERISTICS: INTERNAL FILTER
All specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, 16-bit data (unless otherwise noted).
DAC Digital Interpolation Filter Frequency Response
AMPLITUDE vs FREQUENCY
AMPLITUDE vs FREQUENCY
0.05
0
0.04
0.03
-40
Amplitude (dB)
Amplitude (dB)
-20
-60
-80
-100
0.02
0.01
0
-0.01
-0.02
-0.03
-120
-0.04
-0.05
-140
0
1
2
3
Frequency (× fS)
0
4
0.1
0.2
0.3
0.4
0.5
Frequency (× fS)
G001
Figure 3. Frequency Response
G002
Figure 4. Passband Ripple
DAC Analog Low-Pass Filter Frequency Response
AMPLITUDE vs FREQUENCY
0
-0.5
-20
Amplitude (dB)
Amplitude (dB)
AMPLITUDE vs FREQUENCY
0
-1
-60
-1.5
-2
0.01
-40
-80
0.1
1
10
Frequency (kHz)
Figure 5. Passband Characteristics
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100
G003
1
10
100
1k
10k
Frequency (kHz)
G004
Figure 6. Stop Band Characteristics
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TYPICAL CHARACTERISTICS: GENERAL
All specifications at TA = +25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, and 16-bit data (unless otherwise noted).
TOTAL HARMONIC DISTORTION + NOISE
vs FREE-AIR TEMPERATURE
TOTAL HARMONIC DISTORTION + NOISE
vs FREE-AIR TEMPERATURE
0.05
Total Harmonic Distortion + Noise (%)
Total Harmonic Distortion + Noise (%)
0.05
Bus-Powered
VOUT = 0 dB
0.04
0.03
32 W
0.02
10 kW
0.01
0
-25
0
25
50
75
Free-Air Temperature (°C)
0.03
32 W
0.02
0.01
100
10 kW
-50
-25
0
25
50
75
Free-Air Temperature (°C)
G005
100
G006
Figure 7.
Figure 8.
TOTAL HARMONIC DISTORTION + NOISE
vs SUPPLY VOLTAGE
TOTAL HARMONIC DISTORTION + NOISE
vs SUPPLY VOLTAGE
0.05
0.05
Total Harmonic Distortion + Noise (%)
Total Harmonic Distortion + Noise (%)
0.04
0
-50
Bus-Powered
VOUT = 0 dB
0.04
0.03
32 W
0.02
10 kW
0.01
0
Self-Powered
VOUT = 0 dB
0.04
0.03
32 W
0.02
0.01
10 kW
0
4
4.5
5
Supply Voltage (V)
Figure 9.
12
Self-Powered
VOUT = 0 dB
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5.5
G007
3
3.1
3.2
3.3
3.4
Supply Voltage (V)
3.5
3.6
G008
Figure 10.
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TYPICAL CHARACTERISTICS: GENERAL (continued)
All specifications at TA = +25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, and 16-bit data (unless otherwise noted).
TOTAL HARMONIC DISTORTION + NOISE
vs SAMPLING FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs SAMPLING FREQUENCY
0.05
Total Harmonic Distortion + Noise (%)
Total Harmonic Distortion + Noise (%)
0.05
Bus-Powered
VOUT = 0 dB
0.04
32 W
0.03
0.02
10 kW
0.01
0
Self-Powered
VOUT = 0 dB
0.04
0.03
32 W
0.02
0.01
10 kW
0
30
35
45
40
50
Sampling Frequency (kHz)
30
45
40
50
Sampling Frequency (kHz)
G009
G010
Figure 11.
Figure 12.
DYNAMIC RANGE and SNR
vs FREE-AIR TEMPERATURE
DYNAMIC RANGE and SNR
vs FREE-AIR TEMPERATURE
105
105
Self-Powered
Dynamic Range and SNR (dB)
Bus-Powered
Dynamic Range and SNR (dB)
35
103
101
99
Dynamic Range
97
SNR
103
101
99
Dynamic Range
97
SNR
95
95
-50
0
-25
25
50
Free-Air Temperature (°C)
100
-50
G011
75
50
100
G012
Figure 14.
DYNAMIC RANGE and SNR
vs SUPPLY VOLTAGE
DYNAMIC RANGE and SNR
vs SUPPLY VOLTAGE
105
103
101
Dynamic Range
97
25
Figure 13.
Bus-Powered
99
0
-25
Free-Air Temperature (°C)
Dynamic Range and SNR (dB)
Dynamic Range and SNR (dB)
105
75
SNR
Self-Powered
103
101
Dynamic Range
99
97
SNR
95
95
4
4.5
5
Supply Voltage (V)
Figure 15.
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5.5
G013
3
3.1
3.2
3.3
3.4
3.5
3.6
Supply Voltage (V)
G014
Figure 16.
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TYPICAL CHARACTERISTICS: GENERAL (continued)
All specifications at TA = +25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, and 16-bit data (unless otherwise noted).
DYNAMIC RANGE and SNR
vs SAMPLING FREQUENCY
DYNAMIC RANGE and SNR
vs SAMPLING FREQUENCY
105
105
Self-Powered
Dynamic Range and SNR (dB)
Dynamic Range and SNR (dB)
Bus-Powered
103
101
Dynamic Range
99
97
SNR
95
35
45
40
Sampling Frequency (kHz)
99
97
50
SNR
30
35
45
40
50
Sampling Frequency (kHz)
G015
Figure 17.
Figure 18.
SUSPEND CURRENT
vs SUPPLY VOLTAGE
SUSPEND CURRENT
vs FREE-AIR TEMPERATURE
G016
200
Suspend Current (mA)
200
Suspend Current (mA)
Dynamic Range
101
95
30
150
100
50
150
100
50
0
0
4
4.5
5
Supply Voltage (V)
Figure 19.
14
103
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5.5
-40
-20
0
20
40
60
80
100
Free-Air Temperature (°C)
G018
G017
Figure 20.
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TYPICAL CHARACTERISTICS: GENERAL (continued)
All specifications at TA = +25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, and 16-bit data (unless otherwise noted).
AMPLITUDE vs FREQUENCY
0
-20
-20
-40
-40
Amplitude (dB)
Amplitude (dB)
AMPLITUDE vs FREQUENCY
0
-60
-80
-60
-80
-100
-100
-120
-120
-140
-140
0
5
10
15
20
Frequency (kHz)
Figure 21. Output Spectrum (–60 dB, N = 8192)
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0
20
40
60
80
100
120
Frequency (kHz)
G019
G020
Figure 22. Output Spectrum (–60 dB, N = 8192)
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DETAILED DESCRIPTION
Clock and Reset
For both USB and audio functions, the PCM2704C/5C/6C/7C require a 12-MHz (±500 ppm) clock that can be
generated by the onboard oscillator using a 12-MHz crystal resonator. The 12-MHz crystal resonator must be
connected to the XTI pin (pin 28 for the PCM2704C/5C, pin 12 for the PCM2706C/7C) and the XTO pin (pin 1 for
the PCM2704C/5C, pin 13 for the PCM2706C/7C) with one large (1-MΩ) resistor and two small capacitors; the
capacitance of these components depends on the specified load capacitance of the crystal resonator. An
external clock can be supplied from XTI (pin 28 for the PCM2704C/5C, pin 12 for the PCM2706C/7C). If an
external clock is supplied, XTO (pin 1 for the PCM2704C/5C, pin 13 for the PCM2706C/7C) must be left open.
No clock disabling pin is provided; therefore, it is not recommended to use the external clock supply. SSPND (pin
27 for the PCM2704C/5C, pin 11 for the PCM2706C/7C) cannot use clock disabling.
The PCM2704C/5C/6C/7C have an internal power-on reset circuit, and it works automatically when VDD (pin 7 for
the PCM2704C/5C, pin 21 for the PCM2706C/7C) exceeds 2-V typical (1.6 V to 2.4 V), which is equivalent to
VBUS (pin 10 for the PCM2704C/5C, pin 24 for the PCM2706C/7C) exceeding 3-V typical for bus-powered
applications. Approximately 700 μs is required until an internal reset release occurs.
Operation Mode Selection
The PCM2704C/5C/6C/7C have the following mode-select pins.
Power Configuration Select/Host Detection
PSEL (pin 4 for the PCM2704C/5C, pin 16 for the PCM2706C/7C) is dedicated to selecting the power source.
This selection affects the configuration descriptor. While in bus-powered operation, the maximum power
consumption from VBUS is determined by the HOST pin (pin 21 for the PCM2704C/5C, pin 3 for the
PCM2706C/7C). For self-powered operation, the HOST pin must be connected to VBUS of the USB bus with a
pulldown resistor to detect attach and detach. (To avoid excessive suspend current, the pulldown should be a
high-value resistor.) Table 3 summarizes the power configuration select options.
Table 3. Power Configuration Select
PSEL
DESCRIPTION
0
Self-powered
1
Bus-powered
HOST
DESCRIPTION
0
Detached from USB (self-powered)/100 mA (bus-powered)
1
Attached to USB (self-powered)/500 mA (bus-powered)
Function Select (PCM2706C/7C Only)
FSEL (pin 9) determines the function of the FUNC0–FUNC3 pins (pins 4, 5, 18, and 19) and DOUT (pin 17).
When the I2S interface is required, FSEL must be low. Otherwise, FSEL must be high. Table 4 lists the
functionality of the FUNC0-FUNC3 pins, based on the FSEL pin.
Table 4. Function Select
(1)
16
FSEL
DOUT
FUNC0
FUNC1
FUNC2
FUNC3
0
Data out (I2S)
LRCK (I2S)
BCK (I2S)
SYSCK (I2S)
Data in (I2S)
1
S/PDIF data
Next track (HID)
(1)
Previous track (HID)
(1)
Stop (HID)
(1)
Play/pause (HID)
(1)
Valid on the PCM2706C only; no function assigned on the PCM2707C.
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USB Interface
Control data and audio data are transferred to the PCM2704C/5C/6C/7C via the D+ pin (pin 9 for the
PCM2704C/5C, pin 23 for the PCM2706C/7C) and D– pin (pin 8 for the PCM2704C/5C, pin 22 for the
PCM2706C/7C). D+ should be pulled up with a 1.5-kΩ (±5%) resistor. To avoid back voltage in self-powered
operation, the device must not provide power to the pull-up resistor on D+ while VBUS of the USB port is inactive.
All data to/from the PCM2704C/5C/6C/7C are transferred at full speed. The information shown in Table 5 is
provided in the device descriptor. Some parts of the device descriptor can be modified through external ROM
(PCM2704C/6C) or SPI™ (PCM2705C/7C).
Table 5. Device Descriptor
DEVICE DESCRIPTOR
DESCRIPTION
USB revision
1.1 compliant
Device class
0x00 (device defined interface level)
Device subclass
0x00 (not specified)
Device protocol
0x00 (not specified)
Max packet size for endpoint 0
8 bytes
Vendor ID
0x08BB (default value, can be modified)
Product ID
0x27C4/0x27C5/0x27C6/0x27C7 (These values correspond to the model number, and the value can
be modified.)
Device release number
1.0 (0x0100)
Number of configurations
1
Vendor strings
BurrBrown from Texas Instruments (default value, can be modified)
Product strings
USB AUDIO
Serial number
Not supported
DAC (default value, can be modified)
The information given in Table 6 is contained in the configuration descriptor. Some parts of the configuration
descriptor can be modified through external ROM (PCM2704C/6C) or SPI (PCM2705C/7C).
Table 6. Configuration Descriptor
CONFIGURATION DESCRIPTOR
DESCRIPTION
Interface
Three interfaces
Power attribute
0x80 or 0xC0 (bus-powered or self-powered, depending on PSEL; no remote wake up. This value can
be modified.)
Max power
0x0A, 0x32, or 0xFA (20 mA for self-powered, 100 mA or 500 mA for bus-powered, depending on
PSEL and HOST. This value can be modified.)
The information listed in Table 7 is contained in the string descriptor. Some parts of the string descriptor can be
modified through external ROM (PCM2704C/6C) or SPI (PCM2705C/7C).
Table 7. String Descriptor
STRING DESCRIPTOR
DESCRIPTION
#0
0x0409
#1
BurrBrown from Texas Instruments (default value, can be modified)
#2
USB AUDIO
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DAC (default value, can be modified)
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Device Configuration
Figure 23 illustrates the USB audio function topology. The PCM2704C/5C/6C/7C have three interfaces. Each
interface is enabled by different alternative settings.
Endpoint #0
Default
Endpoint
FU
Endpoint #2
(I/F #1)
IT
TID1
Audio Streaming
Interface
OT
TID2
Analog Out
UID3
Standard Audio Control Interface (I/F #0)
Endpoint #5
(I/F #2)
HID Interface
PCM2704C/5C/6C/7C
Figure 23. USB Audio Function Topology
Interface #0 (Default/Control Interface)
Interface #0 is the control interface. Setting #0 is the only possible setting for interface #0. Setting #0 describes
the standard audio control interface. The audio control interface consists of a terminal. The
PCM2704C/5C/6C/7C have three terminals:
• Input terminal (IT #1) for isochronous-out stream
• Output terminal (OT #2) for audio analog output
• Feature unit (FU #3) for DAC digital attenuator
Input terminal #1 is defined as a USB stream (terminal type 0x0101). Input terminal #1 can accept two-channel
audio streams consisting of left and right channels. Output terminal #2 is defined as a speaker (terminal type
0x0301). Feature unit #3 supports these sound control features:
• Volume control
• Mute control
The built-in digital volume controller can be manipulated by an audio-class-specific request from 0 dB to –64 dB
in steps of 1 dB. Changes are made by incrementing or decrementing one step (that is, 1 dB) for every 1/fS time
interval, until the volume level reaches the requested value. Each channel can be set to a separate value. The
master volume control is not supported. A request to the master volume is stalled and ignored. The built-in digital
mute controller can be manipulated by an audio-class-specific request. A master mute control request is
acceptable. A mute control request to an individual channel is stalled and ignored. The digital volume control
does not affect either the S/PDIF or I2S outputs (PCM2706C/7C only).
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Interface #1 (Isochronous-Out Interface)
Interface #1 is for the audio-streaming data-out interface. Interface #1 has the alternative settings described in
Table 8. Alternative setting #0 is the zero-bandwidth setting. All other alternative settings are operational settings.
Table 8. Interface #1 Parameters
ALTERNATIVE
SETTING
DATA FORMAT
00
TRANSFER
MODE
SAMPLING RATE
(kHz)
Zero bandwidth
01
16-bit
Stereo
Twos complement (PCM)
Adaptive
32, 44.1, 48
02
16-bit
Mono
Twos complement (PCM)
Adaptive
32, 44.1, 48
Interface #2 (HID Interface)
Interface #2 is the interrupt-data-in interface. The HID consumer control device consists of interface #2.
Alternative setting #0 is the only possible setting for interface #2.
On the HID device descriptor, eight HID items are reported for any model, in any configuration.
HID Items Reported
Basic HID Operation
Interface #2 can report these three key statuses for any model. These statuses can be set by the HID0–HID2
pins (PCM2704C/6C) or the SPI port (PCM2705C/7C).
• Mute (0xE2)
• Volume up (0xE9)
• Volume down (0xEA)
Extended HID Operation (PCM2705/6/7)
By using the FUNC0–FUNC3 pins (PCM2706C) or the SPI port (PCM2705C/7C), these additional conditions can
be reported to the host.
• Play/Pause (0xCD)
• Stop (0xB7)
• Previous (0xB6)
• Next (0xB5)
Auxiliary HID Status Report (PCM2705C/7C)
One additional HID status can be reported to the host though the SPI port. This status flag is defined by SPI
command or external ROM. This definition must be described as on the report descriptor with a three-byte usage
ID. AL A/V Capture (0x0193) is assigned as the default value for this status flag.
Endpoints
The PCM2704C/5C/6C/7C has three endpoints:
• Control endpoint (EP #0)
• Isochronous-out audio data-stream endpoint (EP #2)
• HID endpoint (EP #5)
The control endpoint is a default endpoint. The control endpoint controls all functions of the
PCM2704C/5C/6C/7C by standard USB request and USB audio-class-specific request from the host. The
isochronous-out audio data-stream endpoint is an audio sink endpoint that receives the PCM audio data. The
isochronous-out audio data-stream endpoint accepts the adaptive transfer mode. The HID endpoint is an
interrupt-in endpoint. The HID endpoint reports HID status every 10 ms.
The HID endpoint is defined as a consumer-control device. The HID function is designed as an independent
endpoint from the isochronous-out endpoint. This configuration means that the effect of HID operation depends
on the host software. Typically, the HID function controls the primary audio-out device.
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DAC
The PCM2704C/5C/6C/7C have a DAC that uses an oversampling technique with 128-fS, second-order, multi-bit
noise shaping. This technique provides extremely low quantization noise in the audio band, and the built-in
analog low-pass filter removes the high-frequency components of the noise-shaping signal. The DAC analog
outputs, VOUTL and VOUTR , are sent through the headphone amplifier and can provide 12 mW at 32 Ω as well as
1.8 VPP into a 10-kΩ load.
Digital Audio Interface: S/PDIF Output
The PCM2704C/5C/6C/7C employ S/PDIF output. Isochronous-out data from the host are encoded to S/PDIF
output DOUT, as well as to DAC analog outputs VOUTL and VOUTR. The interface format and timing follow the
IEC-60958 standard. Monaural data are converted to the stereo format at the same data rate. S/PDIF output is
not supported in the I2S I/F enable mode. The implementation of this feature is optional. Note that it is the
responsibility of the user to determine whether or not to implement this feature in the end application.
Channel Status Information
Channel status information is fixed, and includes consumer application, PCM mode, copyright, and digital/digital
converter data. All other bits are fixed as 0s, except for the sample frequency, which is set automatically
according to the data received through the USB.
Copyright Management
Digital audio data output always is encoded as original with SCMS control. Only one generation of digital
duplication is allowed.
Digital Audio Interface: I2S Interface Output (PCM2706C/7C)
The PCM2706C and PCM2707C can support the I2S interface, which is enabled by the FSEL pin (pin 9). In the
I2S interface-enabled mode, pins 4, 18, 19, 5, and 17 are assigned as DIN, SYSCK, BCK, LRCK, and DOUT,
respectively. These pins provide digital output/input data in the 16-bit I2S format, which also is accepted by the
internal DAC. I2S interface format and timing are shown in Figure 24, Figure 25, and Figure 26. Table 9 and
Table 10 list the audio interface timing and audio clock timing characteristics, respectively.
SYSCK
(256 fS)
1/fS
LRCK
L-Channel
R-Channel
BCK
(64 fS)
1
DOUT
2
3
14
MSB
DIN
1
2
15
16
1
LSB
3
14
15
2
3
14
MSB
16
1
2
15
16
1
LSB
3
14
15
2
MSB
16
1
2
Figure 24. Audio Data Interface Format
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50% of VDD
LRCK (Output)
t(BCH)
t(BCL)
t(BL)
50% of VDD
BCK (Output)
t(BCY)
t(BD)
t(LD)
50% of VDD
DOUT (Output)
t(DS)
t(DH)
50% of VDD
DIN (Input)
Figure 25. Audio Interface Timing
Table 9. Audio Interface Timing Characteristics (1)
SYMBOL
(1)
PARAMETER
MIN
MAX
UNIT
t(BCY)
BCK pulse cycle time
300
ns
t(BCH)
BCK pulse duration, high
100
ns
t(BCL)
BCK pulse duration, low
100
t(BL)
LRCK delay time from BCK falling edge
–20
40
ns
t(BD)
DOUT delay time from BCK falling edge
–20
40
ns
t(LD)
DOUT delay time from LRCK edge
–20
40
ns
t(DS)
DIN setup time
20
ns
t(DH)
DIN hold time
20
ns
ns
Load capacitance of LRCK, BCK, and DOUT is 20 pF.
SYSCK
(Output)
t(SLL)
t(SLH)
LRCK
(Output)
t(SBL)
t(SBH)
BCK
(Output)
Figure 26. Audio Clock Timing
Table 10. Audio Clock Timing Characteristics (1)
SYMBOL
(1)
PARAMETER
MIN
MAX
UNIT
t(SLL), t(SLH)
LRCK delay time from SYSCK rising edge
–5
10
ns
t(SBL), t(SBH)
BCK delay time from SYSCK rising edge
–5
10
ns
Load capacitance is 20 pF.
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DESCRIPTOR DATA MODIFICATION
The descriptor data can be modified through the I2C™ port by external ROM (PCM2704C/6C) or through the SPI
port by an SPI host such as an MCU (PCM2705C/7C) under a particular configuration of the PSEL and HOST
pins. Setting both the PSEL and the HOST pins high is necessary to modify the descriptor data; the D+ pin pullup resistor must not be activated before programming the descriptor data through the external ROM or SPI port
is completed. The descriptor data must be sent from an external ROM to the PCM2704C/6C or from the SPI host
to the PCM2705C/7C in LSB first format, with a specified byte order. Additionally, the power attribute and max
power contents must be consistent with the PSEL setting and the power usage from the USB VBUS of the end
application. Therefore, descriptor data modification in self-powered configuration (PSEL = low) is not supported.
External ROM Descriptor (PCM2704C/6C)
The PCM2704C/6C support an external ROM interface to override internal descriptors. Pin 3 (for the
PCM2704C) or pin 15 (for the PCM2706C) is assigned as DT (serial data), and pin 2 (for the PCM2704C) or pin
14 (for the PCM2706C) is assigned as CK (serial clock) of the I2C interface when using the external ROM
descriptor. Descriptor data are transferred from the external ROM to the PCM2704C/6C through the I2C interface
the first time when the device is activate after a power-on reset. Before completing a read of the external ROM,
the PCM2704C/6C reply with NACK for any USB command request from the host to the device itself. The
descriptor data, which can be in the external ROM, must meet these parameters:
• String descriptors must be described in ANSI ASCII code (1 byte for each character).
• String descriptors are converted automatically to unicode strings for transmission to the host.
• The device address of the external ROM is fixed as 0xA0.
The data bits must be sent from LSB to MSB on the I2C bus. This condition means that each byte of data must
be stored with its bits in reverse order. A read operation is performed at a frequency of XTI/384 (approximately
30 kHz). The power attribute and max power contents must be consistent with the end application circuit
configuration (the PSEL setting and the actual power usage from VBUS of the USB connector); otherwise, it may
cause improper or unexpected PCM2704C/6C operation.
The data must be stored from address 0x00 and must consist of 57 bytes, according to the parameters listed
below:
• Vendor ID (2 bytes)
• Product ID (2 bytes)
• Product string (16 bytes in ANSI ASCII code)
• Vendor string (32 bytes in ANSI ASCII code)
• Power attribute (1 byte)
• Max power (1 byte)
• Auxiliary HID usage ID in report descriptor (3 bytes)
22
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SBFS036A – AUGUST 2011 – REVISED JULY 2012
Figure 27 illustrates the timing for an external ROM read operation. The timing characteristics are summarized in
Table 11.
DT
CK
1-7
8
9
1-8
9
1-8
9
9
Device Address
R/W
ACK
DATA
ACK
DATA
ACK
NACK
S
P
R/W: Read operation if ‘1’; otherwise, Write operation
ACK: Acknowledgement of a byte if ‘0’
DATA: 8 bits (1 byte)
NACK: No acknowledgement if ‘1’
Start
Condition
Stop
Condition
Figure 27. External ROM Read Operation
Table 11. External ROM Read Operation Characteristics
M
M
M
S
S
M
S
M
S
M
M
S
Device address
R/W
ACK
DATA
ACK
DATA
ACK
...
NACK
P
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Figure 28 shows the timing for an external ROM read interface. The respective timing characteristics are
summarized in Table 12.
Repeated
Start
Start
Stop
t(D-HD)
t(DT-F)
t(D-SU)
t(BUF)
t(DT-R)
t(P-SU)
DT
t(CK-R)
t(LOW)
t(RS-HD)
CK
t(S-HD)
t(HI)
t(RS-SU)
t(CK-F)
Figure 28. External ROM Read Interface Timing Requirements
Table 12. External ROM Read Interface Timing Characteristics
SYMBOL
24
PARAMETER
MIN
MAX
UNIT
f(CK)
CK clock frequency
t(BUF)
Bus free time between a STOP and a START condition
4.7
μs
t(LOW)
Low period of the CK clock
4.7
μs
t(HI)
High period of the CK clock
t(RS-SU)
Setup time for START/repeated START condition
t(S-HD)
t(RS-HD)
Hold time for START/repeated START condition
t(D-SU)
Data setup time
t(D-HD)
Data hold time
t(CK-R)
100
kHz
4
μs
4.7
μs
4
μs
250
ns
0
900
ns
Rise time of CK signal
20 + 0.1 CB
1000
ns
t(CK-F)
Fall time of CK signal
20 + 0.1 CB
1000
ns
t(DT-R)
Rise time of DT signal
20 + 0.1 CB
1000
ns
t(DT-F)
Fall time of DT signal
20 + 0.1 CB
1000
ns
t(P-SU)
Setup time for STOP condition
400
pF
CB
Capacitive load for DT and CK lines
VNH
Noise margin at high level for each connected device (including hysteresis)
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μs
4
0.2 VDD
V
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SBFS036A – AUGUST 2011 – REVISED JULY 2012
External ROM Example
External ROM data (sample set)
0xBB,
0x50,
0x56,
0x72,
0x80,
0x7D,
0x0A,
0x08,
0x72,
0x65,
0x65,
0x04,
0x6F,
0x6E,
0x20,
0x27,
0x64, 0x75, 0x63, 0x74, 0x20, 0x73, 0x74, 0x72, 0x69, 0x6E, 0x67, 0x73, 0x2E,
0x64, 0x6F, 0x72, 0x20, 0x73, 0x74, 0x72, 0x69, 0x6E, 0x67, 0x73, 0x20, 0x61,
0x70, 0x6C, 0x61, 0x63, 0x65, 0x64, 0x20, 0x68, 0x65, 0x72, 0x65, 0x2E, 0x20,
0x93, 0x01
Explanation
Data are stored beginning at address 0x00.
Vendor ID: 0x08BB
Product ID: 0x2704
Product string: Product strings (16 bytes).
Vendor string: Vendor strings are placed here (32 bytes, 31 visible characters are followed by 1 space).
Power attribute (bmAttribute): 0x80 (Bus-powered).
Max power (maxPower): 0x7D (250 mA).
Auxiliary HID usage ID: 0x0A, 0x93, 0x01 (AL A/V capture).
Note that the data bits must be sent from LSB to MSB on the I2C bus. Therefore, each data byte must be stored
with its bits in reverse order.
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Serial Programming Interface (PCM2705C/7C)
The PCM2705C/7C supports a serial interface (SPI) to program the descriptor and to set the HID state.
Descriptor data are described in the External ROM Descriptor section. Figure 29 illustrates the SPI timing;
Table 13 lists the respective timing characteristics.
t(MHH)
50% of VDD
MS
t(MCL)
t(MLS)
t(MCH)
t(MLH)
50% of VDD
MC
t(MCY)
LSB
MD
50% of VDD
t(MDS)
t(MDH)
Figure 29. SPI Timing Diagram
Table 13. SPI Timing Characteristics
SYMBOL
PARAMETER
t(MCY)
MC pulse cycle time
t(MCL)
MIN
MAX
UNIT
100
ns
MC low-level time
50
ns
t(MCH)
MC high-level time
50
ns
t(MHH)
MS high-level time
100
ns
t(MLS)
MS falling edge to MC rising edge
20
ns
t(MLH)
MS hold time
20
ns
t(MDH)
MD hold time
15
ns
t(MDS)
MD setup time
20
ns
Figure 30 shows the SPI write timing sequence.
(1) Single Write Operation
16 Bits
MS
MC
MD
MSB
LSB
MSB
(2) Continuous Write Operation
16 Bits ? N Frames
MS
MC
MD
MSB
LSB
MSB
N Frames
LSB
MSB
LSB
Figure 30. SPI Write Operation
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SBFS036A – AUGUST 2011 – REVISED JULY 2012
SPI Register (PCM2705C/7C)
Table 14. SPI Register Description
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
ST
0
ADDR
0
D0
D1
D2
D3
D4
D5
D6
D7
D[7:0]
Function of the lower 8 bits depends on the value of the ST (B11) bit.
ST = 0 (HID status write)
D7
Reports MUTE HID status to the host (active high)
D6
Reports volume-up HID status to the host (active high)
D5
Reports volume-down HID status to the host (active high)
D4
Reports next-track HID status to the host (active high)
D3
Reports previous-track HID status to the host (active high)
D2
Reports stop HID status to the host (active high)
D1
Reports play/pause HID status to the host (active high)
D0
Reports extended command status to the host (active high)
ST = 1 (ROM data write)
D[7:0] Internal descriptor ROM data, D0:LSB, D7:MSB
Contents of the power attribute and max power must be consistent with the actual application circuit
configuration (the PSEL setting and the actual power usage from VBUS of the USB connector); otherwise, it may
cause improper or unexpected PCM2705C/7C operation.
ADDR
Starts write operation for internal descriptor reprogramming (active high)
This bit resets the descriptor ROM address counter and indicates that subsequent words should be ROM data
(described in the External ROM Example section). 456 bits of ROM data must be continuously followed after
this bit has been asserted. The data bits must be sent from LSB (D0) to MSB (D7).
To set ADDR high, ST must be set low. Note that the lower 8 bits are still active as an HID status write when
ST is set low.
Determines the function of the lower 8-bit data. Table 15 summarizes the functionality of ST
and ADDR bit combinations.
ST
0: HID status write
1: Descriptor ROM data write
Table 15. Functionality of ST and ADDR Bit Combinations
ST
ADDR
0
0
HIS status write
0
1
HIS status write and descriptor ROM address reset
1
0
Descriptor ROM data write
1
1
Reserved
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USB Host Interface Sequence
Power-On, Attach, and Playback Sequence
The PCM2704C/5C/6C/7C are ready for setup when the reset sequence has finished and the USB bus is
attached. After a connection has been established (through the set-up process), the PCM2704C/5C/6C/7C are
ready to accept USB audio data. While waiting for the audio data (that is, the device is in an idle state), the
analog output is set to bipolar zero (BPZ).
Upon receiving the audio data, the PCM2704C/5C/6C/7C stores the first audio packet into the internal storage
buffer. The packet contains 1 ms of audio data. The PCM2704C/5C/6C/7C start playing the audio data after
detecting the next subsequent start-of-frame (SOF) packet. Figure 31 shows the initial operation sequence for
the device.
3.3 V (typ)
VDD
2.0 V (typ)
0V
Bus Reset
First Audio Data
Set Configuration
Second Audio Data
Bus Idle
D+ / DSOF
SOF
SOF
SSPND
BPZ
VOUTL
VOUTR
Device Setup
700 ms
1 ms
Internal Reset
Ready for Setup
Ready for Playback
Figure 31. Initial Sequence
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SBFS036A – AUGUST 2011 – REVISED JULY 2012
Play, Stop, and Detach Sequence
When the host finishes or aborts playback, the PCM2704C/5C/6C/7C stop playing after the last audio data output
is complete. Figure 32 illustrates the play, stop, and detach sequence.
VBUS
Audio Data
Audio Data
Last Audio Data
D+ / DSOF
SOF
SOF
SOF
SOF
VOUTL
VOUTR
1 ms
Detach
Figure 32. Play, Stop, and Detach Sequence
Suspend and Resume Sequence
The PCM2704C/5C/6C/7C enter a suspended state after the USB bus has been in a constant idle state for
approximately 5 ms. While the PCM2704C/5C/6C/7C are in this suspended state, the SSPND flag (pin 27 for the
PCM2704C/5C, pin 11 for the PCM2706C/7C) is asserted. The PCM2704C/5C/6C/7C wake up immediately
when detecting a non-idle state on the USB bus. Figure 33 shows the operating sequence for the suspend and
resume process.
Idle
D+ / D-
SSPND
5 ms
Suspend
VOUTL
VOUTR
Active
Active
2.5 ms
Figure 33. Suspend and Resume
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EXAMPLE CIRCUITS
Operating Environment
For current information on the PCM2704C/2705C/2706C/2707C operating environments, see the Updated
Operating Environments for PCM270X, PCM290X Applications application report, SLAA374, available through
the TI website at www.ti.com.
Typical Circuit Connection 1: USB Speaker
Figure 34 illustrates a typical circuit connection for an internal-descriptor, bus-powered, 500-mA application.
X1
C1
C2
R1
External ROM
(Optional)
PCM2704CDB
(3)
1
XTO
2
CK
3
DT
XTI
28
SSPND
27
TEST0
26
TEST1
25
SUSPEND
SCL
SDA
R9
S/PDIF OUT
(2)
4
PSEL
5
DOUT
HID2/MD
24
6
DGND
HID1/MC
23
7
VDD
HID0/MS
22
8
D-
HOST
9
D+
VCCP
20
10
VBUS
PGND
19
VCOM
18
AGNDR
17
VCCR
16
VOLUMER2
USB ‘B’
Connector
VOLUME+
C7
R3
D-
(2)
R4
D+
VBUS
(3)
C3
GND
11
ZGND
12
AGNDL
13
VCCL
14
VOUTL
C6
(1)
VOUTR
(1)
MUTE
21
C4
+
C8
C5
C9
+
15
C13
+
C11
C12
+
+
C10
C14
TPA200x
Power Amp
R5
R6
R7
R8
NOTE: X1: 12-MHz crystal resonator. C1, C2: 10-pF to 33-pF capacitors (depending on load capacitance of crystal resonator). C3to C7: 1-μF
ceramic capacitors. C8: 10-μF electrolytic capacitor. C9, C10: 100-μF electrolytic capacitors (depending on tradeoff between required
frequency response and discharge time for resume). C11, C12: 0.022-μF ceramic capacitors. C13, C14: 1-μF electrolytic capacitors. R1: 1-MΩ
resistor. R2, R9: 1.5-kΩ resistors. R3, R4: 22-Ω resistors. R5, R6: 16-Ω resistors. R7, R8: 330-Ω resistors (depending on tradeoff between
required THD performance and pop-noise level for suspend).
(1) Output impedance of VOUTL and VOUTR during suspended mode or lack of power supply is 26 kΩ ±20%, which is the discharge path for
C9 and C10.
(2) Descriptor programming through external ROM is only available when PSEL and HOST are high.
(3) External ROM power can be supplied from VCCP, but any other active component must not use VCCP, VCCL, VCCR, or VDD as a power
source.
Figure 34. Bus-Powered Application
NOTE
The circuit illustrated in Figure 34 is for information only. The entire board design should
be considered to meet the USB specification as a USB-compliant product.
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SBFS036A – AUGUST 2011 – REVISED JULY 2012
Typical Circuit Connection 2: Remote Headphone
Figure 35 illustrates a typical circuit connection for a bus-powered, 100-mA headphone with seven HIDs.
C9
Headphone
+
+
C11
R5
C3
C6
C12
C10
R7
R6
R8
R9
R10
C4
26
25
VCCL
ZGND+
(1)
(1)
27
AGNDL
2
28
VOUTL
1
29
VOUTR
(3)
VCCP
30
VCCR
PGND
31
VCOM
C5
32
AGNDR
+
24
23
(2)
19
7
18
8
9
10
11
12
13
14
15
16
(2)
PSEL
HID2/MD
6
DT
VOLUME-
HID1/MC
20
CK
VOLUME+
HID0/MS
PCM2706CPJT
5
XTO
MUTE
FUNC0
21
XTI
NEXT TRACK
22
SSPND
PLAY/PAUSE
3
4
TEST
FUNC3
FSEL
HOST
USB ‘B’
Connector
R2
17
VBUS
VBUS
R3
D+
D+
D-
D-
VDD
R4
DGND
GND
C8
C7
FUNC1
PREVIOUS TRACK
FUNC2
STOP
DOUT
External ROM
(Optional)
(3)
SCL
SUSPEND
R11
SDA
R1
X1
C1
C2
NOTE: X1: 12-MHz crystal resonator. C1, C2: 10-pF to 33-pF capacitors (depending on load capacitance of crystal resonator). C3 to C5, C7,
C8: 1-μF ceramic capacitors. C6: 10-μF electrolytic capacitor. C9, C10: 100-μF electrolytic capacitors (depending on required frequency
response). C11, C12: 0.022-μF ceramic capacitors. R1: 1-MΩ resistor. R2, R11: 1.5-kΩ resistors. R3, R4: 22-Ω resistors. R5, R6: 16-Ω resistors.
R7 to R10: 3.3-kΩ resistors.
(1) Output impedance of VOUTL and VOUTR during suspend mode or lack of power supply is 26 kΩ ±20%, which is the discharge path for C9
and C10.
(2) Descriptor programming through external ROM is only available when PSEL and HOST are high.
(3) External ROM power can be supplied from VCCP, but any other active component must not use VCCP, VCCL, VCCR, or VDD as a power
source.
Figure 35. Bus-Powered Application
NOTE
The circuit illustrated in Figure 35 is for information only. The entire board design should
be considered to meet the USB specification as a USB-compliant product.
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Typical Circuit Connection 3: DSP Surround Processing Amplifier
Figure 36 illustrates a typical circuit connection for an I2S- and SPI-enabled self-powered application.
C8
Headphone
+
+
C3
C6
C10
C11
R6
R7
C9
R8
R9
R10
R11
C4
26
25
VCCL
ZGND+
(1)
(1)
27
AGNDL
2
28
VOUTL
1
VCCR
(3)
29
VOUTR
+
I S I/F
Audio Device
PGND
VCCP
30
VCOM
C5
(4)
2
31
R2
24
23
(2)
HID1/MC
MD
HID2/MD
6
19
7
18
8
9
10
11
12
13
14
15
16
(2)
MC
20
PSEL
HID0/MS
PCM2707CPJT
5
DT
MS
21
CK
FUNC0
22
XTO
LRCK
3
4
XTI
FUNC3
SSPND
DIN
TEST
HOST
FSEL
TAS300x
32
AGNDR
+
17
USB ‘B’
Connector
(3)
VBUS
VBUS
R3
D+
(3)
D+
D-
D-
VDD
R4
(3)
C7
DGND
R12
GND
FUNC1
BCK
FUNC2
DOUT
SYSTEM CLOCK
DOUT
SUSPEND
R5
R1
X1
Power
3.3 V
C1
C2
GND
NOTE: X1: 12-MHz crystal resonator. C1, C2: 10-pF to 33-pF capacitors (depending on load capacitance of crystal resonator). C3, C4: 1-μF
ceramic capacitors. C5, C7: 0.1-μF ceramic capacitor and 10-μF electrolytic capacitor. C6: 10-μF electrolytic capacitors. C8, C9: 100-μF
electrolytic capacitors (depending on required frequency response). C10, C11: 0.022-μF ceramic capacitors. R1, R12: 1-MΩ resistors. R2, R5:
1.5-kΩ resistors. R3, R4: 22-Ω resistors. R6, R7: 16-Ω resistors. R8to R11: 3.3-kΩ resistors.
(1) Output impedance of VOUTL and VOUTR during suspend mode or lack of power supply is 26 kΩ ±20%, which is the discharge path for C8
and C9.
(2) Descriptor programming through SPI is only available when PSEL and HOST are high.
(3) D+ pull-up must not be activated (high: 3.3 V) while the device is detached from USB or power supply is not applied on VDD and VCCx.
VBUS of USB (5 V) can be used to detect USB power status.
(4) MS must be high until the PCM2707C power supply is ready and the SPI host (the DSP) is ready to send data. Also, the SPI host must
handle the D+ pull-up if the descriptor is programmed through the SPI. D+ pull-up must not be activated (high = 3.3 V) before programming of
the PCM2707C through the SPI is complete.
Figure 36. Self-Powered Application
NOTE
The circuit illustrated in Figure 36 is for information only. The entire board design should
be considered to meet the USB specification as a USB-compliant product.
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SBFS036A – AUGUST 2011 – REVISED JULY 2012
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August 2011) to Revision A
Page
•
Changed product status from Mixed Status to Production Data .......................................................................................... 1
•
Changed Features section to show full compliance with USB2.0 Specification (but still using USB1.1 descriptors) .......... 1
•
Changed Description section to show USB2.0 compliance (USB1.1 was absorbed into 2.0 specification) ........................ 1
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Jul-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
PCM2704CDB
ACTIVE
SSOP
DB
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
PCM2704CDBR
ACTIVE
SSOP
DB
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
PCM2705CDB
ACTIVE
SSOP
DB
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
PCM2705CDBR
ACTIVE
SSOP
DB
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
PCM2706CPJT
PREVIEW
TQFP
PJT
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
PCM2706CPJTR
PREVIEW
TQFP
PJT
32
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
PCM2707CPJT
PREVIEW
TQFP
PJT
32
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
PCM2707CPJTR
PREVIEW
TQFP
PJT
32
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
(3)
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jul-2012
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
PCM2704CDBR
SSOP
DB
28
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
PCM2705CDBR
SSOP
DB
28
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
PCM2704CDBR
SSOP
DB
28
2000
367.0
367.0
38.0
PCM2705CDBR
SSOP
DB
28
2000
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MPQF112 – NOVEMBER 2001
PJT (S-PQFP–N32)
PLASTIC QUAD FLATPACK
0,45
0,30
0,80
0,20
M
0,20
0,09
Gage Plane
32
0,15
0,05
1
0,25
0°– 7°
7,00 SQ
0,75
0,45
9,00 SQ
1,05
0,95
Seating Plane
0,10
1,20
1,00
4203540/A 11/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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