TI TUSB9260

TUSB9260
USB 3.0 TO SATA BRIDGE
PRODUCT PREVIEW information concerns products in the formative
or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right
to change or discontinue these products without notice.
Literature Number: SLLS962A
December 2009 – Revised July 2010
PRODUCT PREVIEW
Data Manual
TUSB9260
SLLS962A – DECEMBER 2009 – REVISED JULY 2010
www.ti.com
Contents
1
2
RELATED DOCUMENTS ....................................................................................................... 5
MAIN FEATURES ................................................................................................................ 6
8
9
........................................................................................................ 6
2.2
Target Applications ......................................................................................................... 6
INTRODUCTION .................................................................................................................. 7
3.1
System Overview ........................................................................................................... 7
3.2
Device Block Diagram ...................................................................................................... 7
OPERATION ....................................................................................................................... 9
4.1
General Functionality ....................................................................................................... 9
4.2
Firmware Support ......................................................................................................... 10
4.3
GPIO/PWM LED Designations .......................................................................................... 10
4.4
Power Up and Reset Sequence ......................................................................................... 11
SIGNAL DESCRIPTIONS ..................................................................................................... 12
CLOCK CONNECTIONS ...................................................................................................... 16
6.1
Clock Source Requirements ............................................................................................. 16
6.2
Clock Source Selection Guide ........................................................................................... 16
6.3
Oscillator .................................................................................................................... 17
6.4
Crystal ....................................................................................................................... 17
ELECTRICAL SPECIFICATIONS .......................................................................................... 18
7.1
Absolute Maximum Ratings .............................................................................................. 18
7.2
Recommended Operating Conditions .................................................................................. 18
7.3
DC Electrical Characteristics for 3.3-V Digital I/O ..................................................................... 18
POWER CONSUMPTION ..................................................................................................... 19
ORDERING INFORMATION ................................................................................................. 20
2
Contents
2.1
3
4
5
6
PRODUCT PREVIEW
7
TUSB9260 Features
Copyright © 2009–2010, Texas Instruments Incorporated
TUSB9260
www.ti.com
SLLS962A – DECEMBER 2009 – REVISED JULY 2010
List of Figures
Device Block Diagram ............................................................................................................. 8
6-1
Typical Crystal Connections .................................................................................................... 16
PRODUCT PREVIEW
3-1
Copyright © 2009–2010, Texas Instruments Incorporated
List of Figures
3
TUSB9260
SLLS962A – DECEMBER 2009 – REVISED JULY 2010
www.ti.com
List of Tables
4-1
GPIO/PWM LED Designations ................................................................................................. 10
5-1
I/O Definitions ..................................................................................................................... 12
5-2
Clock and Reset Signals ........................................................................................................ 12
5-3
SATA Interface Signals .......................................................................................................... 12
5-4
USB Interface Signals ........................................................................................................... 13
5-5
Serial Peripheral Interface (SPI) Signals ...................................................................................... 13
5-6
JTAG, GPIO, and PWM Signals
5-7
6-1
6-2
8-1
8-2
...............................................................................................
Power and Ground Signals .....................................................................................................
Oscillator Specification ..........................................................................................................
Crystal Specification .............................................................................................................
SuperSpeed USB Power Consumption .......................................................................................
High Speed USB Power Consumption ........................................................................................
14
15
17
17
19
19
PRODUCT PREVIEW
4
List of Tables
Copyright © 2009–2010, Texas Instruments Incorporated
TUSB9260
www.ti.com
SLLS962A – DECEMBER 2009 – REVISED JULY 2010
USB 3.0 TO SATA BRIDGE
Check for Samples: TUSB9260
1
RELATED DOCUMENTS
TUSB9260 Implementation Guide - SLLA301
TUSB9260 Errata – SLLZ062
TUSB9260 PDK Board Guide – SLLA303
TUSB9260 Flash Burner User Guide – SLLU125
PRODUCT PREVIEW
1
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the formative
or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right
to change or discontinue these products without notice.
Copyright © 2009–2010, Texas Instruments Incorporated
TUSB9260
SLLS962A – DECEMBER 2009 – REVISED JULY 2010
2
MAIN FEATURES
2.1
TUSB9260 Features
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PRODUCT PREVIEW
• Universal Serial Bus (USB)
– SuperSpeed USB 3.0 Compliant - TID 340000007
• Integrated Transceiver Supports SS/HS/FS Signaling
– Best in Class Adaptive Equalizer
• Allows for Greater Jitter Tolerance in the Receiver
– USB Class Support
• USB Attached SCSI Protocol (UASP)
• USB Mass Storage Class Bulk-Only Transport (BOT)
• Support for Error Conditions Per the 13 Cases (Defined in the BOT Specification)
• USB Bootability Support
• USB Human Interface Device (HID)
– Supports Firmware Update Via USB, Using a TI Provided Application
• SATA Interface
– Serial ATA Specification Revision 2.6
• gen1i, gen1m, gen2i, and gen2m
– Support for Mass-Storage Devices Compatible With the ATA/ATAPI-8 Specification
• Integrated ARM Cortex M3 Core
– Customizable Application Code Loaded From EEPROM Via SPI Interface
– Two Additional SPI Port Chip Selects for Peripheral Connection
– Up to 12 GPIOs for End-User Configuration
• 2 GPIOs Have PWM Functionality for LED Blink Speed Control
– Serial Communications Interface for Debug (UART)
• General Features
– Integrated Spread Spectrum Clock Generation Enables Operation from a Single Low Cost Crystal or
Clock Oscillator
• Supports 20, 25, 30, or 40 MHz
– A JTAG Interface is Used for IEEE1149.1 and IEEE1149.6 Boundary Scan
– Available in a Fully RoHS Compliant Package
2.2
•
•
•
•
6
Target Applications
External HDD/SSD
External DVD
External CD
HDD-Based Portable Media Player
MAIN FEATURES
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3
INTRODUCTION
3.1
System Overview
SLLS962A – DECEMBER 2009 – REVISED JULY 2010
(1)
3.2
PRODUCT PREVIEW
The TUSB9260 is an ARM cortex M3 microcontroller based USB 3.0 to serial ATA bridge. It provides the
necessary hardware and firmware to implement a USB attached SCSI protocol (UASP) compliant mass
storage device suitable for bridging hard disk drives (HDD), solid state disk drives (SSD), optical drives
and other compatible SATA 1.5-Gbps or SATA 3.0-Gbps devices to a USB 3.0 bus. In addition to UASP
support, the firmware implements the mass storage class bulk-only transport (BOT), and USB human
in-terface device (HID) interfaces.
USB connection is made at either SuperSpeed or High-Speed depending on the upstream connection support.
Device Block Diagram
The major functional blocks are as follows:
• Cortex M3 microcontroller subsystem including the following peripherals:
– Time interrupt modules, including watchdog timer
– Universal asynchronous receive/transmit (SCI)
– Serial peripheral interface (SPI)
– General purpose input/output (GPIO)
– PWM for support of PWM outputs (PWM)
• USB 3.0 core (endpoint controller) and integrated SuperSpeed PHY
• AHCI compliant SATA controller and integrated SATA PHY
– Supporting gen1i, gen1m, gen2i, and gen2m
• Chip level clock generation and distribution
• Support for JTAG 1149.1 and 1149.6
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TUSB9260
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GRSTz
ROM
ARM
Cortex M3
VDD3.3
VDD1.8
RAM
Power
and
Reset
Distribution
JTAG
VDD1.1
Data Path
RAM
80 kB
XI
Clock
Generation
XO
TCK
TMS
TDO
TDI
TRST
USB 3.0
Device
Controller
SATA
AHCI
Timer
Watchdog
Timer
USB_R1RTN
USB_R1
DP/DM
USB HS/FS
PHY
VBUS
SSTX+
SSTX-
SSRX+
SSRX-
USB SS
PHY
SATARX+
SATARX-
SATA II
PHY
SATATX+
SATATX-
PWM[1:0]
GPIO[11:0]
UartRX
UarTX
GPIO
PWM
SPI
SCLK
DATA_OUT
DATA_IN
CS[2:0]
PRODUCT PREVIEW
SCI
(UART)
Figure 3-1. Device Block Diagram
8
INTRODUCTION
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4
OPERATION
4.1
General Functionality
SLLS962A – DECEMBER 2009 – REVISED JULY 2010
The TUSB9260 ROM contains boot code that executes after a global reset which performs the initial
con-figuration required to load a firmware image from an attached SPI flash memory to local RAM. In the
ab-sence of an attached SPI flash memory or a valid image in the SPI flash memory, the firmware will idle
and wait for a connection from a USB host through its HID interface which is also configured from the boot
code. The latter can be accomplished using a custom application or driver to load the firmware from a file
resident on the host system.
Once the firmware is loaded it configures the SATA advanced host controller interface host bus adapter
(AHCI) and the USB device controller. In addition, the configuration of the AHCI includes a port reset
which initiates an out of band (OOB) TX sequence from the AHCI link layer to determine if a device is
connected, and if so negotiate the connection speed with the device (3.0 Gbps or 1.5 Gbps).
After USB device controller configuration is complete, if a SATA device was detected during the AHCI
con-figuration the firmware connects the device to the USB bus when VBUS is detected. According to the
USB 3.0 specification, the TUSB9260 will initially try to connect at SuperSpeed, if successful it will enter
U0; otherwise, after the training time out it will enable the DP pull up and connect as a USB 2.0
high-speed or full-speed device depending on the speed supported by host or hub port.
When connected, the firmware presents the BOT interface as the primary interface and the UASP
inter-face as the secondary interface. If the host stack is UASP aware, it can enable the UASP interface
using a SET_INTERFACE request for alternate interface 1.
Following speed negotiation, the device should transmit a device to host (D2H) FIS with the device
signature. This first D2H FIS is received by the link layer and copied to the port signature register. When
firmware is notified of the device connection it queries the device for capabilities using the IDENTIFY
DEVICE command. Firmware then configures the device as appropriate for its interface and features
supported, for example an HDD that supports native command queuing (NCQ).
The configuration of the USB device controller includes creation of the descriptors, configuration of the
device endpoints for support of UASP and USB mass storage class bulk-only transport (BOT), allocation
of memory for the transmit request blocks (TRBs), and creation of the TRBs necessary to transmit and
receive packet data over the USB. In addition, the firmware provides any other custom configuration
required for application specific implementation, for example a HID interface for user initiated backup.
After USB device controller configuration is complete, if a SATA device was detected during the AHCI
configuration the firmware connects the device to the USB bus when VBUS is detected. According to the
USB 3.0 specification, the TUSB9260 will initially try to connect at SuperSpeed, if successful it will enter
U0; otherwise, after the training time out it will enable the DP pull up and connect as a USB 2.0
high-speed or full-speed device depending on the speed supported by host or hub port.
When connected as a SuperSpeed device, the firmware presents the UASP interface as the primary
interface, and the BOT interface as a secondary interface. If the host stack is not UASP aware, it can
enable the BOT interface using a SET_INTERFACE request for alternate interface 1.
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PRODUCT PREVIEW
The configuration of the USB device controller includes creation of the descriptors and configuration of the
device endpoints for support of UASP and USB mass storage class bulk-only transport (BOT). In addition,
the firmware provides any other custom configuration required for application specific implementation, for
example a HID interface for user initiated backup.
TUSB9260
SLLS962A – DECEMBER 2009 – REVISED JULY 2010
4.2
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Firmware Support
PRODUCT PREVIEW
Default firmware support is provided for the following:
• USB 3.0 SuperSpeed and USB 2.0 High-Speed and Full-Speed
• USB Attached SCSI Protocol (UASP)
• USB Mass Storage Class (MSC) Bulk-Only Transport (BOT)
– Including the 13 Error Cases
• USB Mass Storage Specification for Bootability
• USB Device Class Definition for Human Interface Devices (HID)
– Firmware Update and Custom Functionality (e.g. One-Touch Backup)
• Serial ATA Advanced Host Controller Interface (AHCI)
• General Purpose Input/Output (GPIO)
– LED Control and Custom Functions (e.g. One-Touch Backup Control)
• Pulse Width Modulation (PWM)
– LED Dimming Control
• Serial Peripheral Interface (SPI)
– Firmware storage and storing Custom Device Descriptors
• Serial Communications Interface (SCI)
– Debug Output Only
4.3
GPIO/PWM LED Designations
The default firmware provided by TI drives the GPIO and PWM outputs as listed in the table below.
Table 4-1. GPIO/PWM LED Designations
GPIO0
SW heartbeat
00: U3 state or default
01: U2 state
GPIO1/GPIO5
USB3 power state (U0-U3)
GPIO2
HS/FS suspend
GPIO3
Push button input on customer board
GPIO4
Not used
GPIO6
FS/HS connected
GPIO7
SS connected
PWM0
Disk activity
PWM1
U3 or HS/FS suspend state (fades high and low)
GPIO10
(SPICS1)
Not used
GPIO11
(SPICS2)
Not used
10: U1 state
11: U0 state
The LED’s on the TUSB9260 Product Development Kit (PDK) board are connected as in the table above.
Please see the TUSB9260 PDK Guide (SLLA303) for more information on GPIO LED connection and
usage. This EVM is available for purchase, contact TI for ordering information.
10
OPERATION
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4.4
SLLS962A – DECEMBER 2009 – REVISED JULY 2010
Power Up and Reset Sequence
The TUSB9260 does not have specific power sequencing requirements with respect to the core power
(VDD), I/O power (VDD33), or analog power (VDDA11, VDDA33, VDDA18, and VDDR18). The core
power (VDD) or IO power (VDD33) may be powered up for an indefinite period of time while others are not
powered up if all of these constraints are met:
• All maximum ratings and recommended operating conditions are observed.
• All warnings about exposure to maximum rated and recommended conditions are observed,
par-ticularly junction temperature. These apply to power transitions as well as normal operation.
• Bus contention while VDD33 is powered up must be limited to 100 hours over the projected life-time of
the device.
• Bus contention while VDD33 is powered down may violate the absolute maximum ratings.
A supply bus is powered up when the voltage is within the recommended operating range. It is powered
down when it is below that range, either stable or in transition.
PRODUCT PREVIEW
A minimum reset duration of 1 ms is required. This is defined as the time when the power supplies are in
the recommended operating range to the de-assertion of GRSTz.
OPERATION
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5
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SIGNAL DESCRIPTIONS
Table 5-1. I/O Definitions
I/O TYPE
DESCRIPTION
I
Input
O
Output
I/O
Input - Output
PU
Internal pull-up resistor
PD
Internal pull-down resistor
PWR
Power signal
Table 5-2. Clock and Reset Signals
TERMINAL
NAME
PIN
NO.
I/O
DESCRIPTION
PRODUCT PREVIEW
GRSTz
4
I
PU
Global power reset. This reset brings all of the TUSB9260 internal registers to their default
states. When GRSTz is asserted, the device is completely nonfunctional.
XI
52
I
Crystal input. This terminal is the crystal input for the internal oscillator. The input may alternately
be driven by the output of an external oscillator. When using a crystal a 1-MΩ feedback resistor
is required between X1 and XO.
XO
54
O
Crystal output. This terminal is the crystal output for the internal oscillator. If XI is driven by an
external oscillator this pin may be left unconnected. When using a crystal a 1-MΩ feedback
resistor is required between X1 and XO.
Frequency select. These terminals indicate the oscillator input frequency and are used to
configure the correct PLL multiplier. The field encoding is as follows:
FREQSEL[1:0]
31, 30
I
PU
FREQSEL[1]
FREQSEL[0]
INPUT CLOCK FREQUENCY
0
0
20 MHz
0
1
25 MHz
1
0
30 MHz
1
1
40 MHz
Table 5-3. SATA Interface Signals
TERMINAL
PIN
NO.
I/O
SATA_TXP
57
O
Serial ATA transmitter differential pair (positive)
SATA_TXM
56
O
Serial ATA transmitter differential pair (negative)
SATA_RXP
60
I
Serial ATA receiver differential pair (positive)
SATA_RXM
59
I
Serial ATA receiver differential pair (negative)
NAME
12
DESCRIPTION
SIGNAL DESCRIPTIONS
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Table 5-4. USB Interface Signals
TERMINAL
PIN
NO.
I/O
USB_SSTXP
43
O
USB SuperSpeed transmitter differential pair (positive)
USB_SSTXM
42
O
USB SuperSpeed transmitter differential pair (negative)
USB_SSRXP
46
I
USB SuperSpeed receiver differential pair (positive)
USB_SSRXM
45
I
USB SuperSpeed receiver differential pair (negative)
USB_DP
36
I/O
USB High-speed differential transceiver (positive)
USB_DM
35
I/O
USB High-speed differential transceiver (negative)
USB_VBUS
33
I
USB bus power
USB_R1
39
O
Precision resistor reference. A 10-kΩ ±1% resistor should be connected between R1 and R1RTN.
USB_R1RTN
40
I
Precision resistor reference return
NAME
DESCRIPTION
Table 5-5. Serial Peripheral Interface (SPI) Signals
TERMINAL
PAP
NO.
I/O
DESCRIPTION
SPI_SCLK
17
O
PU
SPI clock
SPI_DATA_OUT
18
O
PU
SPI master data out
SPI_DATA_IN
20
I
PU
SPI master data in
SPI_CS0
21
O
PU
Primary SPI chip select for Flash RAM
23
I/O
PU
SPCI chip select for additional peripherals. When not used for SPI chip select this pin may be
used as general purpose I/O.
22
I/O
PU
SPCI chip select for additional peripherals. When not used for SPI chip select this pin may be
used as general purpose I/O.
SPI_CS2/
GPIO11
SPI_CS1/
GPIO10
SIGNAL DESCRIPTIONS
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NAME
13
TUSB9260
SLLS962A – DECEMBER 2009 – REVISED JULY 2010
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Table 5-6. JTAG, GPIO, and PWM Signals
TERMINAL
NAME
I/O
PIN
NO.
DESCRIPTION
PRODUCT PREVIEW
JTAG_TCK
25
I
PD
JTAG test clock
JTAG_TDI
26
I
PU
JTAG test data in
JTAG_TDO
27
O
PD
JTAG test data out
JTAG_TMS
28
I
PU
JTAG test mode select
JTAG_TRSTz
29
I
PD
JTAG test reset
GPIO9/UART_TX
6
I/O
PU
GPIO/UART transmitter. This terminal can be configured as a GPIO or as the transmitter for a
UART channel. This pin defaults to a general purpose output.
GPIO8/UART_RX
5
I/O
PU
GPIO/UART receiver. This terminal can be configured as a GPIO or as the receiver for a UART
channel. This pin defaults to a general purpose output.
GPIO7
16
I/O
PD
GPIO6
15
I/O
PD
GPIO5
14
I/O
PD
GPIO4
13
I/O
PD
GPIO3
11
I/O
PD
GPIO2
10
I/O
PD
GPIO1
9
I/O
PD
GPIO0
8
I/O
PD
PWM0
2
O
PD (1)
PWM1
3
O
PD (1)
(1)
14
Configurable as general purpose input/outputs
Pulse Width Modulation (PWM). Can be used to drive status LED's.
PWM pull down resistors are disabled by default. A firmware modification is required to turn them on. All other internal pull up/down
resistors are enabled by default.
SIGNAL DESCRIPTIONS
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Table 5-7. Power and Ground Signals
TERMINAL
PIN
NO.
I/O
VDDR18
48, 62
PWR
1.8-V power rail
VDDA18
37
PWR
1.8-V analog power rail
VDD
1, 12,
19, 32,
38, 41,
44, 47,
49, 55,
58, 61,
63, 64
PWR
1.1-V power rail
VDD33
7, 24,
50, 51
PWR
3.3-V power rail
VDDA33
34
PWR
3.3-V analog power rail
VSSOSC
53
PWR
Oscillator ground. If using a crystal, this should not be connected to PCB ground plane. If
using an oscillator, this should be connected to PCB ground. See the Clock Source
Requirements section for more details.
VSS
65
PWR
Ground - Thermal Pad
DESCRIPTION
PRODUCT PREVIEW
NAME
SIGNAL DESCRIPTIONS
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TUSB9260
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6
CLOCK CONNECTIONS
6.1
Clock Source Requirements
www.ti.com
The TUSB9260 supports an external oscillator source or a crystal unit. If a clock is provided to XI instead
of a crystal, XO is left open and VSSOSC should be connected to the PCB ground plane. Otherwise, if a
crystal is used, the connection needs to follow the guidelines below.
Since XI and XO are coupled to other leads and supplies on the PCB, it is important to keep them as short
as possible and away from any switching leads. It is also recommended to minimize the capacitance
be-tween XI and XO. This can be accomplished by connecting the VSSOSC lead to the two external
capaci-tors CL1 and CL2 and shielding them with the clean ground lines. The VSSOSC should not be
connected to PCB ground when using a crystal.
Load capacitance (Cload) of the crystal varying with the crystal vendors is the total capacitance value of the
entire oscillation circuit system as seen from the crystal. It includes two external capacitors CL1 and CL2
in Figure 6-1. The trace length between the decoupling capacitors and the corresponding power pins on
the TUSB9260 needs to be minimized. It is also recommended that the trace length from the capacitor
pad to the power or ground plane be minimized.
PRODUCT PREVIEW
Figure 6-1. Typical Crystal Connections
6.2
Clock Source Selection Guide
Reference clock jitter is an important parameter. Jitter on the reference clock will degrade both the
trans-mit eye and receiver jitter tolerance no matter how clean the rest of the PLL is, thereby impairing
system performance. Additionally, a particularly jittery reference clock may interfere with PLL lock
detection mechanism, forcing the Lock Detector to issue an Unlock signal. A good quality, low jitter
reference clock is required to achieve compliance with supported USB3.0 standards. For example,
USB3.0 specification requires the random jitter (RJ) component of either RX or TX to be 2.42 ps (random
phase jitter calculated after applying jitter transfer function - JTF). As the PLL typically has a number of
additional jitter compo-nents, the Reference Clock jitter must be considerably below the overall jitter
budget.
16
CLOCK CONNECTIONS
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6.3
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Oscillator
XI should be tied to the 1.8-V clock source and XO should be left floating.
VSSOSC should be connected to the PCB ground plane.
A 20-, 25-, 30-, or 40-MHz clock can be used.
Table 6-1. Oscillator Specification
CXI
XI input capacitance
VIL
Low-level input voltage
VIH
High-level input voltage
Ttosc_i
Frequency tolerance
Tduty
Duty cycle
TR/TF
Rise/Fall time
RJ
Reference clock RJ
TJ
Reference clock TJ
Tp-p
Reference clock jitter
(1)
(2)
(3)
(4)
CONDITIONS
MIN
VDDIO = 1.8 V,
TJ = 25°C
TYP
MAX
UNIT
0.414
pF
0.35 x VDDR18
V
50
ppm
55
%
20% - 80 %
6
ns
JTF (1 sigma) (1) (2)
0.8
ps
JTF (total p-p) (2) (3)
25
ps
(absolute p-p) (4)
50
ps
0.65 x VDDR18
Operational temperature
V
–50
45
50
Sigma value assuming Gaussian distribution
After application of JTF
Calculated as 14.1 x RJ + DJ
Absolute phase jitter (p-p)
6.4
Crystal
A parallel, 20pF load capacitor should be used if a crystal source is used.
VSSOSC should not be connected to the PCB ground plane.
A 20-, 25-, 30-, or 40-MHz crystal can be used.
Table 6-2. Crystal Specification
PARAMETER
Ttosc_i
Frequency tolerance
Frequency stability
CL
CONDITIONS
MIN
MAX
UNIT
Operational temperature
–50
50
ppm
1 year aging
–50
50
ppm
24
pF
Load capacitance
12
TYP
20
CLOCK CONNECTIONS
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PARAMETER
TUSB9260
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7
ELECTRICAL SPECIFICATIONS
7.1
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
VDDR18/
VDDA18
Steady-state supply voltage
–0.3 to 2.45
V
VDD
Steady-state supply voltage
–0.3 to 1.4
V
VDD33/
VDDA33
Steady-state supply voltage
–0.3 to 3.8
V
7.2
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PRODUCT PREVIEW
MIN
NOM
MAX
UNIT
1.71
1.8
1.89
V
Analog 1.8 supply voltage
1.62
1.8
1.89
V
Digital 1.1 supply voltage
1.045
1.1
1.155
V
VDD33
Digital 3.3 supply voltage
3
3.3
3.6
V
VDDA33
Analog 3.3 supply voltage
3
3.3
3.6
V
VBUS
Voltage at VBUS PAD
0
1.155
V
TA
Operating free-air temperature range
0
70
°C
TJ
Operating junction temperature range
0
105
°C
HBM ESD
1000
V
CDM ESD
500
V
VDDR18
Digital 1.8 supply voltage
VDDA18
VDD
7.3
DC Electrical Characteristics for 3.3-V Digital I/O
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DRIVER
TR
Rise time
5 pF
1.5
TF
Fall time
5 pF
1.53
IOL
Low-level output current
VDD33 = 3.3 V, TJ = 25°C
6
IOH
High-level output current
VDD33 = 3.3 V, TJ = 25°C
–6
VOL
Low-level output voltage
IOL = 2 mA
VOH
High-level output voltage
IOL = –2 mA
VO
Output voltage
ns
ns
mA
mA
0.4
2.4
V
V
0
VDD33
V
RECEIVER
VI
Input voltage
0
VDD33
V
VIL
Low-level input voltage
0
0.8
V
VIH
High-level input voltage
Vhys
Input hysteresis
tT
Input transition time (TR and TF)
II
Input current
VI = 0 V to VDD33
CI
Input capacitance
VDD33 = 3.3 V, TJ = 25°C
18
2
V
200
ELECTRICAL SPECIFICATIONS
mV
0.384
10
ns
5
µA
pF
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TUSB9260
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8
SLLS962A – DECEMBER 2009 – REVISED JULY 2010
POWER CONSUMPTION
Current numbers were taken on a typical ZAW device. All transfers are to a SATA Gen II SSD. A SATA
Gen I target yields an approximate 10-mA power savings on the 1.1-V rail.
Table 8-1. SuperSpeed USB Power Consumption
POWER RAIL
TYPICAL ACTIVE CURRENT (mA) (1)
TYPICAL IDLE CURRENT
(mA) (2)
VDD11 (3)
319
308
VDD18 (4)
58
58
6
6
VDD33
(1)
(2)
(3)
(4)
(5)
(5)
Transferring data via SS USB to a SSD SATA Gen II device. No SATA power management, U0 only.
SATA Gen II SSD attached no active transfer. No SATA power management, U0 only.
All 1.1-V power rails connected together.
All 1.8-V power rails connected together.
All 3.3-V power rails connected together.
(1)
(2)
(3)
(4)
(5)
POWER RAIL
TYPICAL ACTIVE CURRENT (mA) (1)
TYPICAL IDLE CURRENT
(mA) (2)
VDD11 (3)
197
193
VDD18 (4)
45
36
VDD33 (5)
14
14
PRODUCT PREVIEW
Table 8-2. High Speed USB Power Consumption
Transferring data via HS USB to a SSD SATA Gen II device. No SATA power management.
SATA Gen II SSD attached no active transfer. No SATA power management.
All 1.1-V power rails connected together.
All 1.8-V power rails connected together.
All 3.3-V power rails connected together.
POWER CONSUMPTION
Copyright © 2009–2010, Texas Instruments Incorporated
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Product Folder Link(s): TUSB9260
19
TUSB9260
SLLS962A – DECEMBER 2009 – REVISED JULY 2010
9
www.ti.com
ORDERING INFORMATION
PACKAGE
64-pin TQFP (PAP)
64-pin TQFP (PVP)
VOLTAGE
ORDERABLE PART NUMBER
1.1-V, 1.8-V and 3.3-V power terminals
TUSB9260PAP
TUSB9260PVP
PRODUCT PREVIEW
20
ORDERING INFORMATION
Copyright © 2009–2010, Texas Instruments Incorporated
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Product Folder Link(s): TUSB9260
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