OKI Semiconductor ML9226 FEDL9226-01 Issue Date: Dec. 11, 2002 32-Bit Duplex/Triplex VFD Controller/Driver with Digital Dimming, ADC and Keyscan GENERAL DESCRIPTION The ML9226 is a full CMOS controller/driver for Duplex or Triplex vacuum fluorescent display tube. It conststs of 32-segment driver outputs and 3-grid pre-driver outputs, so that it can drive directly up to 96-segment VFD. ML9226 features a digital dimming function, a 8-ch ADC, a 5 × 5 keyscan circuit and an encoder type switch interface. ML9226 provides an interface with a microcontroller only by four signal lines: DATA I/O, CLOCK, CS. FEATURES • Supply voltage (VDISP) • Duplex/Triplex selectable • Applicable VFD tube • • • • • • • • • : 8 to 18.5V (Built-in 5V regulator for logic) : 2 Grids × 32 Anodes VFD tube : 3 Grids × 32 Anodes VFD tube 32-segment driver outputs : IOH = –5 mA at VOH = VDISP – 0.8 V (SEG1 to 22) IOH = –10 mA at VOH = VDISP – 0.8 V (SEG23 to 32) IOL = 500 uA at VOL = 2.0 V (SEG1 to 32) 3-grid pre-driver outputs : IOH = – 5.0 mA at VOH = VDISP – 0.8V IOL = 10 mA at VOL = 2.0V Built-in digital dimming circuit (10-bit resolution) Built-in 8-ch A/D converter Built-in 5 × 5 keyscan circuit 3 interface circuits for an encoder type rotary switch Built-in oscillation circuit (external R and C) Built-in Power-On-Reset circuit Package: 80-pin plastic QFP (QFP80-P-1420-0.80-BK) ( ML9226GA) 1/26 FEDL9226-01 OKI Semiconductor ML9226 BLOCK DIAGRAM SEG1 D-GND 32 Segment Driver VDISP VCC(5 V) VREG(5 V) L-GND POR 5V Regulator & Power On Reset 0H 7H Mode Select in1-3 CS CLOCK GRID1 GRID2 GRID3 SEG32 Control DATA I/O OSC0 3 Grid pre Driver POR in1-32 1H 0H POR Out1-32 Segment Latch 1 in1-32 Out1-32 96 to 32 Segment Control in1-32 in1-32 Out1-32 Segment Latch 2 in1-32 Out1-32 Segment Latch 3 in1-32 2H 0H POR Out1-3 3bit Shift Register Out1-32 32bit Shift Register POR POR 3H 0H POR 4H POR in1-10 Dimming Latch Out1-10 10bit Digital Dimming OSC POR DIM OUT SYNC OUT1 Timing Generator DUP/TRI 8ch, 8bit A/D Converter CH1 CH8 SYNC OUT2 5 × 5 Key Scan and Encoder Switch Interface 7H 5H 6H COL1 COL5 ROW1 ROW5 INT A1 B1 A2 B2 A3 B3 2/26 FEDL9226-01 OKI Semiconductor ML9226 SEG18 NC SEG17 SEG16 SEG15 68 67 66 65 SEG21 73 SEG19 SEG22 74 69 SEG23 75 70 SEG24 76 NC NC 77 SEG20 SEG25 78 71 SEG26 79 72 SEG27 80 PIN CONFIGURATION (TOP VIEW) VDISP 1 64 VDISP SEG28 2 63 SEG14 SEG29 3 62 SEG13 SEG30 4 61 SEG12 SEG31 5 60 SEG11 SEG32 6 59 SEG10 GRID1 7 58 SEG9 GRID2 8 57 SEG8 GRID3 9 56 SEG7 D-GND 10 55 SEG6 ROW1 11 54 SEG5 ROW2 12 53 SEG4 ROW3 13 52 SEG3 ROW4 14 51 SEG2 ROW5 15 50 SEG1 COL1 16 49 CH8 COL2 17 48 CH7 COL3 18 47 CH6 COL4 COL5 19 20 46 45 CH5 CH4 A3 34 35 36 37 38 39 40 CLOCK CS NC SYNC OUT2 SYNC OUT1 DIM OUT OSC0 NC 33 31 VCC L-GND DATA I/O 30 DUP/TRI 32 29 41 28 24 NC CH1 B2 INT CH2 42 27 43 23 26 22 A2 B1 CH3 25 44 A1 21 B3 Vreg NC: No connection (OPEN) 80-pin Plastic QFP 3/26 FEDL9226-01 OKI Semiconductor ML9226 PIN DESCRIPTIONS Pin Symbol Type 1, 64 VDISP — 10 D-GND — 33 L-GND — D-GND is ground pin for the VFD driver circuit. L-GND is ground pin for the logic circuit. Pins 10 and 33 should be connected externally. 30 VCC O 5 V output pin for internal logic portion and external logic circuit. 41 VREG O Reference voltage (5 V) output pin for A/D converter. 50 to 63, 65 to 67, 69 to 71, 73, 74 SEG1 to 22 O SEG23 to 32 O 7, 8, 9 GRID1 to 3 O 36 CS I 35 CLOCK I 34 DATA I/O I/O Power supply pins. Pin1 and pin64 should be connected externally. Segment (anode) signal output pins for a VFD tube. 75, 76, 78 to 80, Description These pins can be directly connected to the VFD tube. External circuit is not required. IOH ≤ –5 mA Segment (anode) signal output pins for a VFD tube. 2 to 6 These pins can be directly connected to the VFD tube. External circuit is not required. IOH ≤ –10 mA Inverted Grid signal output pins. For pre-driver, the external circuit is requiend. IOL ≤ 10 mA Chip Select input pin. Data input/output operation is valid when this pin is set at a High level. Serial clock input pin. Data is input and/or output through the DATA I/O pin at the rising edge of the serial clock. Serial data input/output pin. Data is input to/comes out from the shift register at the rising edge of the serial clock. Interrupt signal output to microcontroller. When any key of key matrix is pressed or released, key scanning is started. After the completion of the one cycle, this pin goes to high level and keeps the high level until keyscan stop mode is selected. 27 INT O 29 DUP/TRI I Duplex (1/2 duty) operation is selected when this pin is set at a VCC level. 42 to 49 CH1 to 8 I Analog voltage input pin for the 8-bit A/D converter. 21 to 26 A1 to A3 B1 to B3 I Input pin for the encoder type rotary switch. The phase of an An/Bn input is detected. Duplex/Triplex operation select input pin. Triplex (1/3 duty) operation is selected when this pin is set at a GND level. Return inputs from the key matrix. 16 to 20 COL1 to 5 I These pins are active low. When key matrix are in the inactive sate, these pins are at high level through the internal pull-up resistors. All the inputs do not have the cahttering absorption function for the keyscans. Key switch scanning outputs. 11 to 15 ROW1 to 5 O Normally low level is output through these pin. When any switch of key matrix is depressed or released, key scanning is started and is continued until keyscan stop mode is selected. When keyscan stop mode is selected, all outputs of ROW1 to 5 go back to low level. 4/26 FEDL9226-01 OKI Semiconductor ML9226 Pin Symbol Type 40 DIM OUT O 38, 39 SYNC OUT 1, 2 O Description Dimming pulse output. Connect this pin to the slave side DIM IN pin. Synchronous signal input. Connect these pins to the SYNC IN1 and SYNC IN2 pins of a slave side. RC oscillator connecting pins. 31 OSC0 I/O Oscillation frequency depends on display tubes to be used. For details refer to ELECTRICAL CHARACTERISTICS. 28,32, 37,68, 72,77 NC - VCC OSC0 R Co OPEN pins. 5/26 FEDL9226-01 OKI Semiconductor ML9226 ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Symbol Condition Rating Unit VDISP — –0.3 to +20 V Input Voltage VIN — –0.3 to +6.0 V Power Dissipation PD 263 mW Storage Temperature Output Current Ta = 85°C QFP80-P-1420-0.80-BK TSTG — –55 to +150 °C IO1 SEG1 to 22 –10.0 to +2.0 mA IO2 SEG23 to 32 –20.0 to +2.0 mA IO3 GRID1 to 3 –10.0 to +20.0 mA IO4 DIM OUT, SYNC OUT1, SYNC OUT2 –2.0 to +2.0 mA RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Min. Typ. Max. Unit VDISP — 8.0 13.0 18.5 V High Level Input Voltage VIH All inputs except OSC0 3.8 — — V Low Level Input Voltage VIL All inputs except OSC0 — — 0.8 V Clock Frequency fC — — — 2.0 MHz fOSC R = 10 kΩ ±5%, Co = 27 pF ±5% Driver Supply Voltage Oscillation Frequency Frame Frequency fFR Operating Temperature TOP 2.2 3.3 4.4 MHz R = 10 kΩ ±5% 1/3 Duty 179 269 358 Hz Co = 27 pF ±5% 1/2 Duty 268 403 538 Hz — +85 °C — –40 6/26 FEDL9226-01 OKI Semiconductor ML9226 ELECTRICAL CHARACTERISTICS DC Characteristics (Ta = –40 to +85°C, VDISP = 8.0 to 18.5 V) Parameter Symbol Applied pin Condition Min. Max. Unit High Level Input Voltage VIH *1) — 3.8 — V Low Level Input Voltage VIL *1) — — 0.8 V IIH1 *2) VIH = 3.8 V –5.0 +5.0 µA IIH2 *3) VIH = 3.8 V –70 –5.0 µA IIL1 *2) VIL = 0.0 V –5.0 +5.0 µA IIL2 *3) VIL = 0.0 V –160 –10 µA V High Level Input Current Low Level Input Current High Level Output Voltage Low Level Output Voltage VOH1 SEG1 to 22 IOH1 = –5 mA VDISP – 0.8 VOH2 SEG23 to 32 IOH2 = –10 mA VDISP – 0.8 VOH3 GRID1 to 3 IOH3 = –5 mA VDISP – 0.8 VOH4 *4) IOH4 = –200 µA 4.0 Output Open 4.5 — — — — — VOL1 SEG1 to 22 IOL1 = 500 µA — 2.0 V VOL2 SEG23 to 32 IOL2 = 500 µA — 2.0 V VOL3 GRID1 to 3 IOL3 = 10 mA — 2.0 V VOL4 *5) IOL4 = 300 µA — 0.4 V — 10 mA 4.5 5.5 V Supply Current IDISP VDISP Supply Voltage for Logic VL VCC VDISP = 9.5 V VDISP = 9.5 V R = 10 kΩ ±5%, Co = 27 pF ±5% no load C = 0.01 µF ± 10%, IO = 0 to –10 mA V V V V *1) CS, CLOCK, DATA I/O DUP/TRI, A1 to A3, B1 to B3, COL1 to 5 *2) CS, CLOCK, DATA I/O DUP/TRI, A1 to A3, B1 to B3 *3) COL1 to 5 *4) DATA I/O, INT, DIM OUT, SYNC OUT1, SYNC OUT2 *5) DATA I/O, INT, DIM OUT, SYNC OUT1, SYNC OUT2, ROW1 to 5 7/26 FEDL9226-01 OKI Semiconductor ML9226 AC Characteristics (Ta = –40 to +85°C, VDISP = 8.0 to 18.5 V) Parameter Symbol Condition Min. Max. Unit fC — — 2.0 MHz Clock Pulse Width tCW — 200 — ns Data Setup Time tDS — 200 — ns Data Hold Time tDH — 200 — ns CS Off Time tCSL R = 10 kΩ ±5%, Co = 27 pF ±5% 20 — µs CS Setup Time (CS-Clock) tCSS — 200 — ns CS Hold Time (Clock-CS) tCSH — 200 — ns DATA Output Delay Time (Clock-DATA I/O) tPD — — 1.0 µs — 2.0 µs Clock Frequency Output Slew Rate Time tR tR = 20% to 80% CL= 100 pF — 2.0 µs VDISP Rise Time tPRZ Mounted in a unit — 100 µs VDISP Off Time tPOF Mounted in a unit, VDISP = 0.0 V 5.0 — ms CS Wait Time tRSOFF — 400 — µs tF tF = 80% to 20% 8/26 FEDL9226-01 OKI Semiconductor ML9226 TIMING DIAGRAM Data Input Timing tCSL tCSS CS tCSH 1/fC tCW tCW –3.8 V –0.8 V –3.8 V CLOCK –0.8 V tDS tDH –3.8 V DATA I/O (INPUT) VALID VALID VALID VALID –0.8 V Data Output Timing –3.8 V tCSS CS tCSH –0.8 V –3.8 V CLOCK –0.8 V tPD –3.8 V DATA I/O (OUTPUT) –0.8 V Reset Timing VDISP tPOF tPRZ –0.8VDISP –0.0 V tRSOFF –3.8 V CS –0.0 V Driver Output Timing SEG1-32, GRID1-3 tR tF –0.8VDISP –0.2VDISP 9/26 FEDL9226-01 OKI Semiconductor ML9226 A/D Converter Characteristics (Ta = –40 to +85°C, VDISP = 8.0 to 18.5 V) Parameter Condition Min. Typ. Max. Unit Reference Voltage (VREG) — 4.5 5.0 5.5 V Output Current — — — –10 mA Input Voltage Range — GND — VREG V R = 10 kΩ ±5%, C2 = 27 pF ±5% 256 310 394 µs Conversion Time/Channel Resolution — — 8 bit Linearity error — — ±2.0 LSB Differentiation linearity error — — ±2.0 LSB Zero scale error — — +2.0 LSB Full-scale error — — -2.0 LSB Terminological definition Resolution The minimum input analog value which can be recognized. It can decompose into 28= 256,(VRH-VRL)/256,in 8 bits. Linearity error The deviation between the ideal conversion characteristic as a 8-bit A/D converter and the actual conversion characteristic is said. (Therefore, a quantization error is not included.) The ideal conversion characteristic means the step which divided the voltage between VRH to VRL into 256 division into equal parts. Differentiation linearity error The smoothness of the conversion characteristic is shown, and ideally, the width of the analog input voltage corresponding to change for 1 bit of digital outputs is 1LSB= (VRH-VRL)/256, and says the deviation of this ideal bit size and the bit size in the arbitrary points of the conversion range. Zero scale error Digital output "000H" to "001H" changes, and the deviation of the ideal conversion characteristic of a point and the actual conversion characteristic is said. Full scale error Digital output "0FEH" to "0FFH" changes, and the deviation of the ideal conversion characteristic of a point and the actual conversion characteristic is said. 10/26 FEDL9226-01 OKI Semiconductor ML9226 Keyscan Characteristics (Ta = –40 to +85°C, VDISP = 8.0 to 18.5 V) Parameter Condition Min. Typ. Max. Unit Keyscan Cycle Time R = 10 kΩ ±5%, Co = 27 pF ±5% 160 194 246 µs Keyscan Pulse Width R = 10 kΩ ±5%, Co = 27 pF ±5% 32 39 49 µs Rotary switch characteristic (Ta = –40 to +85°C, VDISP = 8.0 to 18.5 V) Parameter Sign Condition Min. Typ. Max. Unit Phase input time tABW Phase input fixed time R = 10 kΩ ±5%, CO = 27 pF ±5% 950 — — tABH µs Rotary switch input timing A B tABW tABH tABW tABH tABW tABW Keyscan Timing Keyscan Cycle Time ROW1 Keyscan Pulse Width ROW2 ROW3 ROW4 ROW5 11/26 FEDL9226-01 OKI Semiconductor ML9226 Output Timing (Duplex Operation) *1 bit time = 4/fOSC Solid line : The dimming data is 1016/1024 Dotted line : The dimming data is 64/1024 2048 bit times(1 display cycle) GRID1 1016 bit times 8 bit times GRID2 VDISP 1016 bit times 8 bit times 8 bit times D-GND VDISP 1016 bit times D-GND VDISP GRID3 64 bit times 64 bit times D-GND 64 bit times VDISP SEG1-32 D-GND 5V DIM OUT L-GND 5V SYNC OUT1 L-GND 5V SYNC OUT2 L-GND Output Timing (Triplex Operation) *1 bit time = 4/fOSC Solid line : The dimming data is 1016/1024 Dotted line : The dimming data is 64/1024 3072 bit times(1 display cycle) GRID1 VDISP 1016 bit times 8 bit times 8 bit times D-GND VDISP 1016 bit times GRID2 8 bit times D-GND 1016 bit times GRID3 64 bit times 64 bit times 64 bit times VDISP D-GND VDISP SEG1-32 D-GND 5V DIM OUT L-GND 5V SYNC OUT1 L-GND 5V SYNC OUT2 L-GND 12/26 FEDL9226-01 OKI Semiconductor ML9226 FUNCTIONAL DESCRIPTION Power-on Reset When power is turned on, ML9226 is initialized by the internal power-on reset circuit. The status of the internal circuit after initialization is as follows: • The contents of the shift registers and latches are set to “0”. • The digital dimming duty cycle is set to “0”. • All segment outputs are set to Low level. • GRID1 outputs are set to Low level. • GRID2 to 3 outputs are set to High level. • All the ROW outputs are set to Low level. • INT output is set to Low level. Mode Data ML9226 has the seven function modes. The function mode is selected by the mode data (M0 to M2). The relation between function mode and mode data (M0 to M2) is as follows: FUNCTION MODE OPERATING MODE FUNCTION DATA M0 M1 M2 0 Segment Data for GRID1-3 Input 0 0 0 1 Segment Data for GRID1 Input 1 0 0 2 Segment Data for GRID2 Input 0 1 0 3 Segment Data for GRID3 Input 1 1 0 4 Digital Dimming Data Input 0 0 1 5 Keyscan Stop 1 0 1 6 Switch Data Output 0 1 1 7 A/D Data Output 1 1 1 Data Input and Output Data input and output through the DATA I/O pin is valid only when the CS pin is set at a High level. The input data to DATA I/O pin is shifted into the shift register at the rising edge of the serial clock. The data is automatically loaded to the latches when the CS pin is set at a Low level. 10-bit dimming data (D1 to D10) and 32-bit segment data (S1 to S32) are used for inputting of dimming data and display data. To transfer these two data, the mode data (M0 to M2) must be sent after each of these data succeddingly. The output data from the DATA I/O pin is output from the shift register at the rising edge of the serial clock. ML9226 outputs 64-bit (8 ch × 8 bits) A/D data (A11 to A88) and 37-bit key data (S11 to S55, R1, Q11 to Q13, R2, Q21 to Q23, R3 and Q31 to Q33). To receive these data, the mode data (M0 to M2) mast be sent first and then CS must be set once to Low level and set again to High level. Then inputting serial clocks, these data are output from the DATA I/O pin. When the CS pin is set at a Low level, the DATA I/O pin returns to an input pin. To stop the keyscan, the only mode data (M0 to M2) must be sent. After the mode data transfer, the key scanning is stopped immediately. 13/26 FEDL9226-01 OKI Semiconductor ML9226 Segment Data Input [Function Mode: 0 to 3] • ML9226 receives the segment data when function mode 0 to 3 are selected. • The same segment data is transferred to the 3 segment data latch correspond to GRID1 to 3 at the same time when the function mode 0 is selected. • The segment data is transferred to only one segment data latch that is selected by mode data, when the function mode is 1, 2 or 3 is selected. • Segment output (SEG1 to 32) becomes High level when the segment data (S1 to 32) is High level. [Data Format] Input Data Segment Data Mode Data : 35 bits : 32 bits : 3 bits Bit 1 2 3 4 Input Data S1 LSB S2 S3 S4 29 30 31 32 33 34 35 S29 S30 S31 S32 M0 M1 M2 MSB Mode Data Segment Data (32 bits) (3 bits) [Bit correspondence between segment output and segment data] SEG n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Segment data S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 SEG n 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Segment data S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 14/26 FEDL9226-01 OKI Semiconductor ML9226 Digital Dimming Data Input [Function Mode: 4] • ML9226 receives the digital dimming data when function mode 4 is selected. • The output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid. • The 10-bit digital dimming data is input from LSB. [Data Format] Input Data : 13 bits Digital Dimming Data : 10 bits Mode Data : 3 bits Bit 1 Input Data 2 D1 D2 LSB 3 4 5 6 7 8 D3 D4 D5 D6 D7 D8 9 10 11 12 13 D9 D10 M0 M1 M2 MSB Mode Data Digital Dimming Data (10 bits) (3 bits) (LSB) Dimming Data (MSB) Duty Cycle D2 D3 D4 D5 D6 D7 D8 D9 D10 0 0 0 0 0 0 0 0 0 0 0/1024 1 0 0 0 0 0 0 0 0 0 1/1024 1 1 1 0 1 1 1 1 1 1 1015/1024 0 0 0 1 1 1 1 1 1 1 1016/1024 1 0 0 1 1 1 1 1 1 1 1016/1024 1 1 1 1 1 1 1 1 1 1016/1024 1 … … … … D1 Keyscan Stop [Function Mode: 5] • ML9226 stops a key scanning when function mode 5 are selected. • To select this mode, the only mode data (M0 to M2) is needed. • The actual time lag range between receipt of the keyscan stop command and the ceasing of scanning is 2.4 µs to 3.6 µs [Input Data Format] Input Data Mode Data : 3 bits : 3 bits Bit 28 29 30 Input Data M0 M1 M2 Mode Data (3 bits) 15/26 FEDL9226-01 OKI Semiconductor ML9226 Switch Data Output [Function Mode: 6] • • • • • • • • ML9226 output the switch data when function mode 6 is selected. To select this mode, the only mode data (M0 to M2) is needed. When ML9226 recieves this mode, the DATA I/O pin is changed to an output pin. 37-bit switch data come out from the DATA I/O pin synchronizing with the rise edge of the clock. When the CS pin is set at the low level, the DATA I/O pin returns to an input pin. R1, R2, R3 = 0, implies Right rotation of the knob (Clockwise) R1, R2, R3 = 1, implies Left rotation of the knob (Counter Clockwise) Contact Count bits are Q11 (LSB) to Q13 (MSB), Q21 (LSB) to Q23 (MSB) and Q31 (LSB) to Q33 (MSB) [Input Data Format] Input Data Mode Data : 3 bits : 3 bits Bit 28 Input Data M0 29 30 M1 M2 Mode Data (3 bits) [Output Data Format] Output Data : 37 bits 5 × 5 push swithc Data : 25 bits Encoder switch Data : 12 bits Bit 1 2 3 4 5 6 7 8 9 10 11 Output S11 S12 S13 S14 S15 S21 S22 S23 S24 S25 S31 Data Bit 26 27 28 29 30 31 32 33 34 35 36 Output R1 Q11 Q12 Q13 R2 Q21 Q22 Q23 R3 Q31 Q32 Data 12 13 14 15 16 17 18 19 20 21 22 23 24 25 S32 S33 S34 S35 S41 S42 S43 S44 S45 S51 S52 S53 S54 S55 37 Q33 Sij: i = ROW1 to 5, j = COL1 to 5 Sij = 1: Switch ON Sij = 0: Switch OFF [5x5 Push switch] ROW1 ROW2 ROW3 ROW4 ROW5 COL1 COL2 COL3 = COL4 COL5 16/26 FEDL9226-01 OKI Semiconductor ML9226 Keyscan Keyscanning is started only when depression or release of any key is detected in order to minimize noise caused by scanning signal. Then, keyscanning is continued until the keyscan stop mode is sent from a microcomputer. The INT pin goes to the high level at the completion of 1-cycle scanning after the keyscan start, so the (high level) signal sent from the INT pin can be used as an interrupt signal. [Keyscan Timing] ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 1 Cycle INT Depress/Release Note: Keyscan stop mode is selected. Keyscanning cannot be stopped by selecting the keyscan stop mode only once if: - keyscanning is started after depression or release of any key is detected, and then - a key is depressed or released again before the keyscan stop mode is selected. To stop keyscanning, it is required to select the keyscan stop mode once again. Depress INT CS Depress Keyscan MODE5 Release Keyscan MODE5 MODE5 MODE5 : Keyscan stop 17/26 FEDL9226-01 OKI Semiconductor ML9226 A/D Data Output [Function Mode: 7] • • • • • ML9226 output the A/D data when function mode 7 is selected. To select this mode, the only mode data (M0 to M2) is needed. When ML9226 recieves this mode, the DATA I/O pin is changed to an output pin. 64-bit A/D data come out from the DATA I/O pin synchronizeing with the rise edge of the clock. When the CS pin is set at the low level, the DATA I/O pin returns to an input pin. [Input Data Format] Input Data Mode Data : 3 bits : 3 bits Bit 28 Input Data M0 29 30 M1 M2 Mode Data (3 bits) [Output Data Format] Output Data A/D Data Bit Output Data A/D Bit Output Data A/D Bit Output Data A/D Bit Output Data A/D : 64 bits : 64 bits 1 A11 (LSB) 2 A12 3 A13 4 A14 5 A15 6 A16 7 A17 8 9 A18 A21 (MSB) (LSB) 10 A22 11 A23 12 A24 13 A25 14 A26 15 A27 16 A28 (MSB) 17 A31 (LSB) 18 A32 19 A33 CH1 20 21 A34 A35 22 A36 23 A37 24 25 A38 A41 (MSB) (LSB) 26 A42 27 A43 CH2 28 29 A44 A45 30 A46 31 A47 32 A48 (MSB) 33 A51 (LSB) 34 A52 35 A53 CH3 36 37 A54 A55 38 A56 39 A57 40 41 A58 A61 (MSB) (LSB) 42 A62 43 A63 CH4 44 45 A64 A65 46 A66 47 A67 48 A68 (MSB) 49 A71 (LSB) 50 A72 51 A73 CH5 52 53 A74 A75 54 A76 55 A77 56 57 A78 A81 (MSB) (LSB) 58 A82 59 A83 CH6 60 61 A84 A85 62 A86 63 A87 64 A88 (MSB) CH7 CH8 18/26 FEDL9226-01 OKI Semiconductor ML9226 The rotary encoder switch function. As figure 1 shows, the rotary encoder switch circuit is consisted of Phase detection, Interrupt generation, Up/down counter, Direction latch and Parallel-in serial-out shift register. A B Phase Detection UP DOWN Interrupt Generation UP/DOWN Counter Q3 Q2 Q1 for INT Direction Latch R1 P-in/S-out Shift Registor Output data Fig.1 The Rotary Encoder Switch Circuit 1) Phase detection 1-1) Clockwise When signal A and B input as fig. 2, the phase detection circuit outputs UP signal after the chattering absorption period. At this time, the output INT also goes to high level, so this signal can be used as an interrupt. The INT stays High level until the key scan stop mode is selected. A B chattering absorption time UP (internal) INT Fig.2 The Input and Output Timing in Case of Clockwise. 19/26 FEDL9226-01 OKI Semiconductor ML9226 1-2) counter clockwise When signal A and B input as fig. 3, the phase detection circuit outputs Down signal after the chattering absorption period. At this time, the output INT also goes to High level. The INT stays High level until the key scan stop mode is selected. A B chattering absorption time DOWN (internal) INT Fig.3 The Input and Output Timing in Case of Counter Clockwise. 2) UP/DOWN COUNTER When the UP/DOWN COUNTER is input UP, it counts up and when it is input DOWN, it counts down. But if overcounte of “111” occurs the UP/DOWN COUNTER stays “111”. A B Q1, Q2, Q3 100 010 110 001 101 011 111 111 Fig.4 3) Direction latch When the Direction latch is input DOWN the output R goes “1”. But if the UP pulse is input and the counts value change to plus value, the output R goes to “0”. A B R1 Q1, Q2, Q3 100 010 100 000 100 010 Fig.5 20/26 FEDL9226-01 OKI Semiconductor ML9226 4) P-in/S-out shift resistor When the key scan stop mode is selected and SC goes L, INT signal goes “L”. CS Data I/O C1 C2 C3 C4 C5 C1 C2 C3 C4 C5 ROW1 ROW2 C1 C2 C3 C4 C5 R1 Q11 Q12 Q13 ROW5 R2 Q21 Q22 Q23 R3 Q31 Q32 Q33 Rotary CLOCK INT INT signal goes “L”. Fig.6 21/26 GND VDISP GND GND 5×5 Key matrix L-GND CS DATA I/O CLOCK VCC OSC0 SYNC OUT 2 SYNC OUT 1 DIM OUT ROW1 to 5 COL1 to 5 CH1 to 8 VREG DUP/TRI (MASTER) SEG32 GRID1 GRID2 GRID3 VDISP SEG1 ML9226 VCC GND GND GRID1 GRID2 GRID3 L-GND OSC 0 SYNC IN 2 SYNC OUT 2 SYNC IN 1 SYNC OUT 1 DIM IN DIM OUT CS DATA IN CLOCK OSC 1 M/S DUP/TRI (SLAVE) SEG56 VDISP ML9213 SEG1 VDD S62 S63 S64 Ef G1 Duplex VFD Tube G2 S1S2 S3 FEDL9226-01 OKI Semiconductor ML9226 APPLICATION CIRCUITS 1. Circuit for the duplex VFD tube with 128 segments (2 Grid × 64 Anode) Microcontroller 22/26 GND 5×5 Key matrix GND L-GND GND GRID3 GRID2 GND GRID1 GRID2 GRID3 GRID1 DUP/TRI SYNC OUT 2 SYNC OUT 1 DIM OUT CS DATA I/O CLOCK VCC OSC0 COL1 to 5 ROW1 to 5 CH1 to 8 VREG L-GND OSC 0 SYNC IN 2 SYNC OUT 2 SYNC IN 1 SYNC OUT 1 DIM IN DIM OUT CS DATA IN CLOCK OSC 1 DUP/TRI M/S ML9213 (SLAVE) SEG56 G1 G2 G3 S62 S63 S64 Ef Triplex VFD Tube S1 S2 S3 OKI Semiconductor GND VDISP VDISP SEG1 VDD SEG1 VDISP ML9226 (MASTER) SEG32 VCC FEDL9226-01 ML9226 2. Circuit for the triplex VFD tube with 192 segments (3 Grid × 64 Anode) Microcontroller 23/26 FEDL9226-01 OKI Semiconductor ML9226 PACKAGE DIMENSIONS (Unit: mm) QFP80-P-1420-0.80-BK Mirror finish 5 Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5µm) 1.27 TYP. 4/Nov. 28, 1996 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 24/26 FEDL9226-01 OKI Semiconductor ML9226 REVISION HISTORY Document No. Date FEDL9226-01 Dec. 11, 2002 Page Previous Current Edition Edition – – Description Preliminary edition 1 25/26 FEDL9226-01 OKI Semiconductor ML9226 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd. 26/26