OKI Semiconductor ML7029 FEDL7029-03 Issue Date: Feb. 18, 2004 Multifunction ADPCM CODEC GENERAL DESCRIPTION The ML7029 is a single channel ADPCM CODEC IC which performs mutual transcoding between the analog voice band signal and 32 kbps ADPCM serial data. FEATURES • Single 3 V Power Supply Operation (VDD: 2.7 to 3.6 V) • ADPCM Algorithm: ITU-T G.726 (32 kbps, 24 kbps, 16 kbps) • Full-Duplex Transmit/Receive Operation • Transmit/Receive Synchronous Mode Only • PCM Data Format: µ-law • Serial PCM/ADPCM Transmission Data Rate: 64 kbps to 2048 kbps (when SYNC = 8 kHz) • Low Power Consumption Operating Mode: 18 mW Typ. (VDD = 3.0 V, SYNC = 8 kHz) Power-Down Mode: 0.03 mW Typ. (VDD = 3.0 V, SYNC = 8 kHz) • Sampling Frequency: 6 kHz to 21 kHz selectable (However, there are limitations to 16 kHz or higher frequencies) • Master Clock Frequency: Sampling frequency × 1296 When SYNC = 8 kHz: 10.368 MHz • Transmit/Receive Mute, Transmit/Receive Programmable Gain Control • Side Tone Path with Programmable Attenuation (8-Step Level Adjustment) • Serial MCU Interface Control • Package: 30-pin plastic SSOP (SSOP30-P-56-0.65-K) (ML7029) 1/29 FEDL7029-03 OKI Semiconductor ML7029 BLOCK DIAGRAM CR2-B7 A/D Conv. AIN– CR2-B6 to B4 BPF/ LPF TXON/ OFF PCM Compander PCMSO 20 kΩ GSX PCMSI ADPCM IR CR3-B7 to B5 PCMRO CR2-B3 PCM Expander PCMRI VREF BCLK SYNC EXCK DEN DIN DOUT PDN MCK AG MCU I/F DG SG RXON/ OFF LPF CR2-B2 to B0 VD 20 kΩ D/A Conv. VA VFRO IS 2/29 FEDL7029-03 OKI Semiconductor ML7029 PIN CONFIGURATION (TOP VIEW) GSX NC AIN– NC SG NC VA NC AG NC VFRO NC NC DG PDN 1 30 2 29 3 28 4 27 5 26 6 25 7 24 8 23 9 22 10 21 11 20 12 19 13 18 14 17 15 16 VD BCLK SYNC PCMSO PCMSI IS IR PCMRO PCMRI NC MCK DEN EXCK DIN DOUT NC: No Connection 30-Pin Plastic SSOP 3/29 FEDL7029-03 OKI Semiconductor ML7029 PIN FUNCTIONAL DESCRIPTIONS AIN–, GEX Transmit analog input and transmit level adjustment. AIN– is connected to the inverting input of the transmit amplifier. GSX is connected to the transmit amplifier output. During power-down mode, the GSX output is a high impedance state. VFRO Receive analog output. During power-down mode, the VFRO output is in a high impedance state. SG Analog signal ground. The output voltage of this pin is approximately 1.4 V. Put 10 µF plus 0.1 µF (ceramic type) bypass capacitors between this pin and AG. During power-down, this output voltage is 0 V. This pin should be used via a buffer if used externally. AG Analog ground. DG Digital ground. This ground is separated from the analog signal ground pin (AG). The DG pin must be kept as close as possible to AG on the PCB. Va Analog +3 V power supply. VD Digital +3 V power supply. This power supply is separated from the analog signal power supply pin (VA). The VD pin must be kept as close as possible to VA on the PCB. PDN Power-down and reset control input. A “0” level makes the IC enter a power-down state. At the same time, all control register data are reset to the initial state. Set this pin to “1” during normal operating mode. The power-down state is controlled by a logical OR with CR0-B5 of the control register. When using PDN for power-down and reset control, set CR0-B5 to digital “0”. The reset width (a “L” level period) should be 200 ns or more. Be sure to reset the control registers by executing this power down to keep this pin to digital “0”level for 200 ns or longer after the power is turned on and VDD exceeds 2.7 V. 4/29 FEDL7029-03 OKI Semiconductor ML7029 MCK Master clock input. The frequency is 1296 times the SYNC signal. For example, it is 10.368 MHz when the SYNC signal is 8 kHz. The master clock signal may be asynchronous with BCLK and SYNC. PCMSO Transmit PCM data output. PCM is output from MSB in synchronization with the rising edge of BCLK and XSYNC. Refer to Figure 1. During power-down, the PCMSO output is at “L” level. PCMSI Transmit PCM data input. This signal is converted to the transmit ADPCM data, PCM is shifted in synchronization with the falling edge of BCLK. Normally, this pin is connected to PCMSO. Refer to Figure 1. PCMRO Receive PCM data output. PCM is the output signal after ADPCM decoder processing. This signal is output serially from MSB in synchronization with the rising edge of BCLK and RSYNC. Refer to Figure 1. During power-down, the PCMRO output is at “L” level. PCMRI Receive PCM data input. PCM is shifted on the rising edge of the BCLK and input from MSB. Normally, this pin is connected to PCMRO. Refer to Figure 1. IS Transmit ADPCM signal output. After having encoded PCM with ADPCM, the signal is output from MSB in synchronization with the rising edge of BCLK and XSYNC. Refer to Figure 1. This pin is at “H” level during power-down. IR Receive ADPCM signal input. This input signal is shifted serially on the falling edge of BCLK and SYNC and input from MSB. Refer to Figure 1. BCLK Shift clock input for the PCM and ADPCM data. The frequency is set in the range of 8 to 256 times the SYNC frequency. Refer to Figure 1. 5/29 FEDL7029-03 OKI Semiconductor ML7029 SYMC Sampling input for the PCM and ADPCM data. The frequency is 8 kHz or 11.025 kHz and is selected by the control register data CR3-B1. Synchronize this signal with BCLK signal. SYNC is used to indicate the MSB of the PCM data stream. Refer to Figure 1. 125 µs (SYNC = 8 kHz) SYNC BCLK PCMSO/PCMSI/ PCMRO/PCMRI IS/IR MSB MSB LSB LSB Figure 1 PCM and ADPCM Interface Basic Timing 6/29 FEDL7029-03 OKI Semiconductor ML7029 DEN, EXCK, DIN, DOUT Serial control ports for MCU interface. Reading and writing data are performed by an external MCU through these pins. The 8-byte cotrol registers (CR0 to 7) are provided on the device. DEN is the “Enable” control signal input, EXCK is the data shift clock input, DIN is the address and data input, and DOUT is the data output. Figures 2-1 and 2-2 show the input/output timing diagram. During power-down, the DOUT output is in a high impedance state. DEN EXCK DIN W A2 A1 DOUT B7 B6 B5 A0 High Impedance B4 B3 B2 B1 B0 B4 B3 B2 B1 B0 (a) Data Write Timing Diagram DEN EXCK DIN R A2 High Impedance DOUT A1 A0 B7 B6 B5 (b) Data Read Timing Diagram Figure 2-1 MCU Interface Input/Output Timing (DIN = 12 bits) DEN EXCK DIN W A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 B1 B0 High Impedance DOUT (a) Data Write Timing Diagram DEN EXCK DIN DOUT R A2 A1 High Impedance A0 B7 B6 B5 B4 B3 B2 (b) Data Read Timing Diagram Figure 2-2 MCU Interface Input/Output Timing (DIN = 16 bits) 7/29 FEDL7029-03 OKI Semiconductor ML7029 Table 1 shows the register map. Table 1 Control Register Map Name Address A2 A1 A0 CR0 0 0 0 CR1 0 0 1 CR2 0 1 0 CR3 0 1 1 B7 B6 — — MODE 1 MODE 0 Control and Detect Data B5 B4 B3 B2 PDN ALL TX RESET B1 B0 — — — — — RX RESET TX MUTE RX MUTE — RX PAD TX TX TX TX RX RX RX RX ON/OFF GAIN2 GAIN1 GAIN0 ON/OFF GAIN2 GAIN1 GAIN0 — — — Side Tone Side Tone Side Tone GAIN2 R/W : Read/Write enable GAIN1 GAIN0 HPF HPF 8k/11k ON/OFF R/W R/W R/W R/W R/W 8/29 FEDL7029-03 OKI Semiconductor ML7029 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Power Supply Voltage VDD — –.3 to +5.0 V Analog Input Voltage VAIN — –0.3 to VDD+0.3 V Digital Input Voltage VDIN — –0.3 to VDD+0.3 V Storage Temperature Tstg — –55 to +150 °C RECOMMENDED OPERATION CONDITIONS Parameter Symbol Condition Min. Typ. Max. Unit Power Supply Voltage VDD Voltage must be fixed +2.7 3.0 +3.6 V Operating Temperature Range Ta — –25 +25 +70 °C Digital Input High Voltage VIH Digital Input Pins 0.45 × VDD — VDD V Digital Input Low Voltage VIL Digital Input Pins 0 — 0.16 × VDD V Master Clock Frequency fMCK1 MCK 7.776 10.368 20.736 MHz +0.01% MHz SYNC × 256 kHz Master Clock Frequency Accuracy fMCK2 MCK –0.01% SYNC × 1296 Bit Clock Duty fBCK BCLK SYNC × 8 — Sampling Frequency (*1) fSYNC SYNC 6.0 8.0 16 kHz Master Clock Duty Ratio DMCK MCK (≤20.736 MHz) 30 50 70 % Clock Duty Ratio DCLK BCLK, EXCK 30 50 70 % Digital Input Rise Time tir Digital Input Pins — — 50 ns Digital Input Fall Time tif Digital Input Pins — — 50 ns PCM Sync Signal Setting Time (Continuous BCLK) tBS BCLK ↔ SYNC (see Fig. 3-1) 100 — — ns PCM Sync Signal Setting Time (Burst Mode Clock) tSB BCLK ↔ SYNC (see Fig. 3-2) 0 — 20 µs SYNC Signal Width (Continuous BCLK) tWS SYNC (see Fig. 3-1) 1BCLK — SYNC –1 BCLK µs SYNC Signal Width (Burst Mode Clock) tWSB SYNC (see Fig. 3-2) 1BCLK — Burst Clock –1 µs tDS — 100 — — ns PCM, ADPCM Setup Time PCM, ADPCM Hold Time tDH — 100 — — ns Digital Output Load CDL Digital Output Pins — — 100 pF Bypass Capacitors for SG CSG SG to AG 10+0.1 — — µF *1: Refer to the Appendix. 9/29 FEDL7029-03 OKI Semiconductor ML7029 ELECTRICAL CHARACTERISTICS DC Characteristics (VDD = 2.7 to 3.6 V, Ta = –25 to +70°C) Parameter Power Supply Current (VDD = 3.0 V, SYNC = 8 kHz) Input Leakage Current Symbol Condition Min. Typ. Max. Unit IDD1 Operating Mode No Signal — 6.0 12 mA IDD2 Power Down Mode (Input pins are fixed) — 0.01 0.1 mA IIH VI = VDD — — 2.0 µA IIL VI = 0 V — — 0.5 µA Output High Voltage VOH IOH = 4 mA 2.4 — — V Output Low Voltage VOL IOL = –4 mA — — 0.4 V Input Capacitance CIN — — 5 — pF Symbol Condition Analog Interface Characteristics (VDD= 2.7 to 3.6 V, Ta = –25 to +70°C) Parameter Min. Typ. Max. Unit Input Resistance RIN AIN– — 10 — MΩ Output Load Resistance RL GSX, VFRO 20 — — kΩ Output Load Capacitance CL GSX, VFRO — — 100 pF Output Amplitude (*2) VO1 GSX, VFRO (RL = 20 kΩ) — — 1.3 VPP Offset Voltage VOF GSX, VFRO –100 — +100 mV SG Output Voltage VSG SG — 1.4 — V SG Output Resistance RSG SG — 40 — kΩ SG Warm-up Time TSG SG↔AG 10+0.1µF (Rise time to max. 90% level) — 700 — ms *2: –7.7 dBm (600Ω) = 0 dBm0, +3.17 dBm0 = 1.3 VPP 10/29 FEDL7029-03 OKI Semiconductor ML7029 AC Characteristics (VDD = 2.7 to 3.6 V, Ta = –25 to +70°C) Parameter Symbol LB8T1 Transmit Frequency Response SYNC = 8 kHz BPF LB8T2 LB8T3 LB8T4 LB8T5 LB11T1 Transmit Frequency Response SYNC = 11.025 kHz BPF LB11T2 LB11T3 LB11T4 LB11T5 Transmit Frequency Response SYNC = 8 kHz LPF LL8T1 Transmit Frequency Response SYNC = 11.025 kHz LPF LL11T1 Receive Frequency Response SYNC = 8 kHz LPF LL8R1 Receive Frequency Response SYNC = 11.025 kHz LPF LL11R1 Transmit S/N Ratio SYNC = 8 kHz (*3) SD8T1 Receive S/N Ratio SYNC = 8 kHz (*3) SD8R1 Transmit S/N Ratio SYNC = 16 kHz (*3) SD16T1 Receive S/N Ratio SYNC = 16 kHz (*3) SD16R1 Idle Channel Noise SYNC = 8 kHz (*3) NIDLT NIDLR NIDLT NIDLR AVT AVR Idle Channel Noise SYNC = 16 kHz (*3) Absolute Signal Amplitude (*5) LL8T2 LL8T3 LL8T4 LL11T2 LL11T3 LL11T4 LL8R2 LL8R3 LL8R4 LL11R2 LL11R3 LL11R4 SD8T2 SD8R2 SD16T2 SD16R2 Condition Freg. (Hz) 60 300 1015 3400 3970 60 300 1400 4690 5470 300 1015 3400 3970 300 1400 4690 5470 300 1015 3400 3970 300 1400 4690 5470 f = 1015 Hz f = 1015 Hz f = 1015 Hz f = 1015 Hz — — 1015 Hz(GSX) SYNC = 8 kHz 1015 Hz(VFRO) SYNC = 8 kHz Level (dBm0) Min. 30 –0.5 0 0 0 0 0 0 3 –40 3 –40 3 –40 3 –40 AIN– = SG (*4) AIN– = SG (*4) 0 0 Typ. — — Reference –0.5 — 12 — 30 — –0.5 — Reference –0.5 — 12 — –0.5 — Reference –0.5 — 12 — –0.5 — Reference –0.5 — 12 — –0.5 — Reference –0.5 — 12 — –0.5 — Reference –0.5 — 12 — 35 — 28 — 35 — 28 — 35 — 28 — 35 — 28 — — — — — — — — — 0.285 0.320 0.285 0.320 Max. Unit — 1.5 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 1.0 — — 1.5 1.0 — 0.5 1.0 — 0.5 1.0 — 0.5 1.0 — 0.5 1.0 — — — — — — — — — –68 –72 –68 –72 0.359 0.359 dBm0pP dBm0pP dBm0pP dBm0pP Vrms Vrms *3: Use the P-message weighted filter *4: PCMRI input code “11111111” (µ-law) *5: 0.320 Vrms = 0 dBm0 = –7.7 dBm (600Ω) 11/29 FEDL7029-03 OKI Semiconductor ML7029 Digital Interface Parameter Symbol Condition (VDD = 2.7 to 3.6 V, Ta = –20 to +70°C) Reference Min. Typ. Max. Unit 0 — 200 ns Fig. 3-1 0 — 200 ns Fig. 3-2 0 — 200 ns tXD3, tRD3 0 — 200 ns t1 50 — — ns t2 50 — — ns t3 50 — — ns t4 50 — — ns tSDX, tSDR Digital Input/Output Setting Time Serial Port Digital Input/Output Setting Time tXD1, tRD1 tXD2, tRD2 1LSTTL+100 pF t5 100 — — ns 50 — — ns 50 — — ns t8 0 — 50 ns t9 50 — — ns t10 50 — — ns t11 0 — 50 ns — — 10 MHz CL= 50 pF t6 t7 Shift Clock Frequency fEXCK EXCK Fig. 4-1 Fig. 4-2 EXCK AC Characteristics (Programmable Gain Stages) (VDD = 2.7 to 3.6 V, Ta = -25 to +70°C) Parameter Gain Accuracy Symbol Condition Min. Typ. Max. Unit DG All stages, to programmed value SYNC = 8 kHz –1 0 +1 dB 12/29 FEDL7029-03 OKI Semiconductor ML7029 TIMING DIAGRAM Transmit Side PCM/ADPCM Data Interface BCLK tBS tBS SYNC tWS tXD1 tXD2 tXD3 LSB MSB PCMSO tSDX tXD3 IS MSB tSDX LSB Receive Side PCM/ADPCM Data Interface BCLK tBS tWS tBS SYNC tRD2 tRD1 MSB PCMRO tSDR IR tRD3 tDS MSB LSB tDH tRD3 LSB Figure 3-1 PCM/ADPCM Data Interface (Continuous BCLK) 13/29 FEDL7029-03 OKI Semiconductor ML7029 Transmit Side PCM/ADPCM Data Interface BCLK tSB SYNC tWSB tXD2 tXD1 tXD3 MSB PCMSO LSB tXD3 IS LSB MSB Receive Side PCM/ADPCM Data Interface BCLK tSB tWSB SYNC PCMRO tRD2 tRD1 MSB tDS IR tRD3 MSB LSB tDH tRD3 LSB Figure 3-2 PCM/ADPCM Data Interface (Burst Mode Clock) 14/29 FEDL7029-03 OKI Semiconductor ML7029 Serial Port Data Transfer for MCU Interface DEN 1 EXCK t1 DIN 3 2 t3 t 10 t5 t2 t4 t6 W/R A2 5 4 6 11 12 t9 t7 A1 A0 B7 t8 DOUT B6 B1 B0 t 11 B7 B6 B1 B0 Figure 4-1 Serial Control Port Interface (DIN = 12 bits) DEN t2 1 EXCK t5 2 3 t4 t6 4 5 12 6 13 15 14 t1 t3 DIN W/R A2 t9 t7 A1 A0 16 B7 B6 B0 0 t8 DOUT B7 B6 B0 0 Figure 4-2 Serial Control Port Interface (DIN = 16 bits) 15/29 FEDL7029-03 OKI Semiconductor ML7029 FUNCTIONAL DESCRIPTION Control Registers (1) CR0 (Basic operating mode setting) B7 B6 B5 B4 B3 B2 B1 B0 CR0 — — PDN ALL — — — — — Initial Value * * 0 * * * * * Note: Initial Value: Reset state by PDN (*: Don’t care) B7, B6, B4 to B0: Not used (These pins are used to test the device. They should be set to “0” during normal operation.) B5: Power-down (entire system); 0/Power-on, 1/Power-down 0 Red with the inverted external power-down signals. When using this data, set the RDN pin to “1”. (2) CR1 (ADPCM operating mode setting) B7 B6 CR1 MODE1 MODE0 Initial Value 0 0 B7, B6: B5: B4: B3: B2: B1: B0: B5 B4 B3 B2 TX RESET RX RESET TX MUTE RX MUTE 0 0 0 0 B1 B0 — RX PAD * 0 ADPCM data compression algorithm select (output bit select); (0, 0): 4-bit output (32 kbps) (0, 1): 8-bit output (64 kbps) (1, 0): 3-bit output (24 kbps) (1, 1): 2-bit output (16 kbps) Data rates in parentheses: when SYNC = 8 kHz ADPCM of transmit reset (specified by G.726); 1/Reset* ADPCM of receive reset (specified by G.726); 1/ Reset* ADPCM transmit data mute; 1/Mute ADPCM receive data mute; 1/Mute Not used (This pin is used to test the device. It should be set to “0” during normal operation. Receive side PAD; 1/inserted in the receive side voice path, 12 dB loss 0/no PAD * The reset width should be 1/f sample µs or more. The transmit and receive sides cannnot be reset separately. They must be reset at the same time. 16/29 FEDL7029-03 OKI Semiconductor ML7029 (3) CR2 (PCM CODEC operating mode setting and transmit/receive gain adjustment) B7 CR2 B5 B4 B3 TX ON/OFF TX GAIN2 TX GAIN1 TX GAIN0 Initial Value B7: B6 0 0 1 Transmit PCM signal ON/OFF; 1 B2 RX ON/OFF 0 B1 B0 RX GAIN2 RX GAIN1 RX GAIN0 0 1 1 0/ON, 1/OFF B6, B5, B4: Transmit signal gain adjustment, refer to Table 2. B3: Receive PCM signal ON/OFF; 0/ON, 1/OFF B2, B1, B0: Receive signal gain adjustment, refer to Table 2. Table 2 Transmit/Receive Gain Setting (when SYNC = 8 kHz) B6 B5 B4 Transmit Gain B2 B1 B0 Receive Gain 0 0 0 –6 dB 0 0 0 –6 dB 0 0 1 –4 dB 0 0 1 –4 dB 0 1 0 –2 dB 0 1 0 –2 dB 0 1 1 0 dB 0 1 1 0 dB 1 0 0 +2 dB 1 0 0 +2 dB 1 0 1 +4 dB 1 0 1 +4 dB 1 1 0 +6 dB 1 1 0 +6 dB 1 1 1 +8 dB 1 1 1 +8 dB 17/29 FEDL7029-03 OKI Semiconductor ML7029 (4) CR3 (Side tone gain setting) B7 CR3 Initial Value B6 B5 B4 Side Tone Side Tone Side Tone GAIN2 GAIN1 GAIN0 0 0 0 B3 B2 B1 B0 HPF ON/OFF 0 — — — HPF 8k/11k * * * 0 B7, B6, B5: Side tone path gain setting. Refer to Table 3. B4 to B2: Not used (These pins are used to test the device. They should be set to “0” during normal operation.) Table 3 Side Tone Pash Gain Setting (when SYNC = 8 kHz) B7 B1: B0: B6 B5 Side Tone Path Gain 0 0 0 OFF 0 0 1 –21 dB 0 1 0 –19 dB 0 1 1 –17 dB 1 0 0 –15 dB 1 0 1 –13 dB 1 1 0 –11 dB 1 1 1 –9 dB Transmit HPF cut-off frequency select; 0/The cut-off frequency of the transmit HPF is the sampling frequency × 0.0275. When SYNC = 8 kHz: 220 Hz, when SYNC = 11.025 kHz: 300 Hz. The transmit frequency characteristics are not guaranteed when selecting SYNC = 11.025 kHz. 1/The cut-off frequency of the transmit HPF is the sampling frequency × 0.0200. When SYNC = 8 kHz: 160 Hz, when SYNC = 11.025 kHz: 220 Hz. The transmit frequency characteristics are not guaranteed when selecting SYNC = 8 kHz. Transmit HPF ON/OFF; 0/ON, 1/OFF For the frequency characteristics, refer to Figures 9 to 12 in the Reference Data. 18/29 FEDL7029-03 OKI Semiconductor ML7029 APPLICATION CIRCUIT VDD R2 1 R1 2 3 4 5 10 µF 6 7 8 9 0.1 µF 10 µF 10 11 12 13 Power-down 14 15 GSX NC AIN– NC SG NC VA NC AG NC VFRO NC NC DG PDN ML7029 VD BCLK SYNC PCMSO PCMSI IS IR PCMRO PCMRI NC MCK DEN EXCK DIN DOUT 30 29 PCM I/F 28 27 26 25 ADPCM DATA 24 23 22 21 20 Master Clock 19 18 17 16 MCU I/F 19/29 FEDL7029-03 OKI Semiconductor ML7029 APPLICATION INFORMATION Burst Mode Clock This device can be operated by a burst mode clock (see below). BCLK 1 2 3 4 5 6 7 8 SYNC 1/fsample µs SYNC Signal Pulse Width : MIN. 1-bit clock : MAX. (Number of clocks in burst mode)–1 Figure 5 Example of Burst Mode Clock Relationship between SYNC and BLCK Transmit Side 1/fsample µs SYNC BCLK 1 2 3 4 5 6 7 8 Ts PCMSI (1) PCM Data Input A 0.83/fsample µs 1µs (Range of Data Slip Occurrence) Figure 6 Receive Side 1/fsample µs SYNC BCLK 1 2 3 4 5 6 7 8 Tr IR (2) ADPCM Data Input 1 µs (Range of Data Slip Occurrence) 0.52/fsample µs B Figure 7 20/29 FEDL7029-03 OKI Semiconductor ML7029 (1) PCMSI S/P Latch ADPCM COD Latch P/S IS S/P IR A SYNC Internal Clock Generation BCLK B (2) PCMRO P/S ADPCM DEC Latch Latch (1): PCM data serial to parallel conversion output (2): ADPCM data serial to parallel conversion output A: (1) Data internal latch timing B: (2) Data internal latch timing Figure 8 In this device, internal operating timing is generated according to the SYNC signal (see Figure 8). Therefore, a data slip may occur in the following timing when the PCM and ADPCM data is input. 1. When the PCM signal (PCMSI) is captured If TS: PCM signal output (1) after serial/parallel conversion and A: internal latch timing in Figure 6 overlap, a data slip occurs. 2. When the ADPCM signal (IR) is captured If Tr: ADPCM signal output (2) after serial/parallel conversion and B: internal latch timing in Figure 7 overlap, a data slip occurs. The data slip occurs at the timing of 1 and 2 above. Therefore, taking internal clock jitters and IC internal delay into consideration, the timing of SYNC and BCLK signals should not be set up in the range of about 1 µs from the timing A and B. 21/29 FEDL7029-03 OKI Semiconductor ML7029 REFERENCE DATA Transmit Frequency Characteristics Fs = 8 kHz Transmit BPF Characteristic 10 0 -10 Gain (dB) -20 -30 -40 -50 -60 -70 -80 100 1000 10000 Frequency (Hz) Figure 9 Transmit Bandpass Filter Characteristic (Fs = 8 kHz, CR3-B1, B0 = (0, 0)) Fs = 8kHz Transmit LPF Characteristic 10 0 -10 Gain (dB) -20 -30 -40 -50 -60 -70 -80 100 1000 10000 Frequency (Hz) Figure 10 Transmit Lowpass Filter Characteristic (Fs = 8 kHz, CR3-B1, B0 = (0, 1)) 22/29 FEDL7029-03 OKI Semiconductor ML7029 Fs = 11.025 kHz Transmit BPF Characteristic 10 0 -10 Gain (dB) -20 -30 -40 -50 -60 -70 -80 100 1000 10000 Frequency (Hz) Figure 11 Transmit Bandpass Filter Characteristic (Fs = 11.025 kHz, CR3-B1, B0 = (1, 0)) Fs = 11.025 kHz Transmit LPF Characteristic 10 0 -10 Gain (dB) -20 -30 -40 -50 -60 -70 -80 100 1000 10000 Frequency (Hz) Figure 12 Transmit Lowpass Filter Characteristic (Fs = 11.025 kHz, CR3-B1, B0 = (1, 1)) 23/29 FEDL7029-03 OKI Semiconductor ML7029 Receive Frequency Characteristics Fs = 8 kHz Receive LPF Characteristic 10 0 -10 Gain (dB) -20 -30 -40 -50 -60 -70 -80 100 1000 10000 Frequency (Hz) Figure 13 Receive Lowpass Filter Characteristic (Fs = 8 kHz, CR3-B1, B0 = (0, *)) Fs = 11.025 kHz Receive LPF Characteristic 10 0 -10 Gain (dB) -20 -30 -40 -50 -60 -70 -80 100 1000 10000 Frequency (Hz) Figure 14 Receive Lowpass Filter Characteristic (Fs = 11.025 kHz, CR3-B1, B0 = (1, *)) 24/29 FEDL7029-03 OKI Semiconductor ML7029 APPENDIX When the Sampling Frequency is 16 kHz or Higher: This device enables the operation at 16 kHz or higher sampling frequencies under conditions below. However, be aware that the AC characteristics are not guaranteed under these conditions. Operating Conditions at Sampling Frequency = 19 kHz Parameter Symbol Condition Min. Typ. Max. Unit Power Supply Voltage VDD Voltage must be fixed 3.0 — 3.6 V Operating Temperature Range Ta — –25 — +50 °C Digital Input High Voltage VIH Digital input pin 0.95 × VDD — VDD V Digital Input Low Voltage VIL Digital input pin 0 0.05 × VDD V Master Clock Frequency fMCK1 MCK — 24.624 — MHz Master Clock Frequency Accuracy fMCK2 MCK –0.01% SYNC × 1296 +0.01 MHz Sampling Frequency fSYNC SYNC — 19 — kHz Master Clock Duty Ratio DMCK — 40 — 70 % Transmit S/N Ratio (at 3 dBm0 input) SD19T1 — — 46.2 — dB Transmit S/N Ratio (at –40 dBm0 input) SD19T2 — — 24.8 — dB Receive S/N Ratio (at 3 dBm0 input) SD19R1 — — 45.4 — dB Receive S/N Ratio (at –40 dBm0 input) SD19R2 — — 38.0 — dB 25/29 FEDL7029-03 OKI Semiconductor ML7029 Operating Conditions at Sampling Frequency = 21 kHz Parameter Symbol Condition Min. Typ. Max. Unit Power Supply Voltage VDD Voltage must be fixed 3.3 — 3.6 V Operating Temperature Range Ta — –25 — +50 °C Digital Input High Voltage VIH Digital input pin 0.95 × VDD — VDD V Digital Input Low Voltage VIL Digital input pin 0 0.05 × VDD V Master Clock Frequency fMCK1 MCK — 27.216 — MHz Master Clock Frequency Accuracy fMCK2 MCK –0.01% SYNC × 1296 +0.01 MHz Sampling Frequency fSYNC SYNC — 21 — kHz Master Clock Duty Ratio DMCK — 40 — 70 % Transmit S/N Ratio (at 3 dBm0 input) SD19T1 — — 46.1 — dB Transmit S/N Ratio (at –40 dBm0 input) SD19T2 — — 20.2 — dB Receive S/N Ratio (at 3 dBm0 input) SD19R1 — — 44.8 — dB Receive S/N Ratio (at –40 dBm0 input) SD19R2 — — 37.8 — dB 26/29 FEDL7029-03 OKI Semiconductor ML7029 PACKAGE DIMENSIONS (Unit: mm) SSOP30-P-56-0.65-K Mirror finish 5 Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5µm) 0.19 TYP. 5/Dec. 5, 1996 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 27/29 FEDL7029-03 OKI Semiconductor ML7029 REVISION HISTORY Document No. FEDL7029-02 FEDL7029-03 Date Nov. 2001 Page Previous Current Edition Edition Description – – Final edition 2 – – Final edition 3 9 9 Changed “Symbol” of Setup Time and Hold Time for PCM/ ADPCM. Feb.18, 2004 28/29 FEDL7029-03 OKI Semiconductor ML7029 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2004 Oki Electric Industry Co., Ltd. 29/29