PCM4202-EP SGLS388 – JUNE 2007 www.ti.com High-Performance, 24 Bit, 216 kHz Sampling, Stereo Audio Analog-to-Digital Converter Check for Samples: PCM4202-EP FEATURES 1 • 2 • • • • Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C to 85°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. • • • Two High-Performance, Delta-Sigma Analog-to-Digital Converters – 24 Bit Linear PCM or 1 Bit Direct Stream Digital (DSD) Output Data – Supports PCM Output Sampling Rates up to 216 kHz – Supports 64 fS and 128 fS DSD Output Data Rates Dynamic Performance: PCM Output – Dynamic Range (VIN = –60 dBFS, fIN = 1 kHz, A-Weighted): 118 dB – THD+N (VIN = –0.5 dB, fIN = 1 kHz): –105 dB Dynamic Performance: DSD Output, 64 fS – Dynamic Range (A-Weighted): 115 dB • • • • • • • – THD+N (VIN = –0.5 dB, fIN = 1 kHz): –102 dB Audio Serial Port – 24 Bit Linear PCM Output Data – Master or Slave Mode Operation – Supports Left-Justified, Right-Justified, and I2S® Data Formats Additional PCM Output Features: – Linear-Phase Digital Decimation Filter – Digital High-Pass Filter for DC Removal – Clipping Flag Output for Each Channel Power Supplies: 5 V Analog and 3.3 V Digital Power Dissipation: – fS = 48 kHz: 308 mW typical – fS = 96 kHz: 338 mW typical – fS = 192 kHz: 318 mW typical Power-Down Mode Available in a SSOP-28 Package Pin- and Function-Compatible with the PCM1804 APPLICATIONS • • • • • Digital Recorders and Mixing Desks Digital Audio Effects Processors Broadcast Studio Equipment Surround-Sound Encoders High-End A/V Receivers 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. I2S is a registered trademark of Royal Philips Electronics B.V., The Netherlands. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated PCM4202-EP SGLS388 – JUNE 2007 www.ti.com DESCRIPTION The PCM4202 is a high-performance, stereo audio analog-to-digital (A/D) converter designed for professional and broadcast audio applications. The PCM4202 architecture utilizes a 1 bit delta-sigma modulator per channel, incorporating a novel density modulated dither scheme for improved dynamic performance. The PCM4202 supports 24 bit linear PCM output data, with sampling frequencies up to 216 kHz. The PCM4202 can also be configured to output either 64× or 128× oversampled, 1 bit direct stream digital (DSD) data for each channel. Support for PCM and DSD output formats makes the PCM4202 suitable for a variety of digital audio recording and processing applications. The PCM4202 includes a flexible audio serial port interface, which supports standard audio data formats. Audio data format selection, sampling mode configuration, and high-pass filter functions are all programmed using dedicated control pins. The PCM4202 operates from a 5 V analog power supply and a 3.3 V digital power supply. The digital I/O pins are compatible with 3.3 V logic families. The PCM4202 is available in a small SSOP-28 package. ORDERING INFORMATION (1) PRODUCT PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY PCM4202 SSOP-28 DB –40°C to 85°C PCM4202EP PCM4202IDBREP Tape and Reel, 1000 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) PCM4202 UNIT VCC 6.0 V VDD 3.6 V Ground voltage difference Any AGND to DGND ±0.1 V Digital input voltage FMT0, FMT1, S/M, FS0, FS1, FS2, SCKI, RST, HPFD, BCK, LRCK –0.3 to (VDD + 0.3) V Analog input voltage VINL+, VINL–, VINR+, VINR– –0.3 to (VCC + 0.3) V ±10 mA Operating temperature range –40 to 85 °C Storage temperature range, TSTG –65 to 150 °C Supply voltage Input current (any pin except supplies) (1) 2 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCM4202-EP PCM4202-EP SGLS388 – JUNE 2007 www.ti.com ELECTRICAL CHARACTERISTICS All parameters are specified at TA = 25°C with VCC = 5 V, VDD = 3.3 V (unless otherwise noted), and a measurement bandwidth from 20 Hz to 20 kHz, unless otherwise noted. System clock frequency is equal to 256 fS for Single and Dual Rate sampling modes, and 128 fS for Quad Rate sampling mode. PARAMETER TEST CONDITIONS PCM4202 MIN RESOLUTION TYP MAX UNIT 24 Bits AUDIO DATA FORMAT Linear PCM interface formats Two’s complement, MSB first data I2S, Left or Right Justified Linear PCM word length Direct Stream Digital (DSD) output 24 Bits 1 Bit DIGITAL CHARACTERISTICS Input logic level Output logic level Input current Input current (1) VIH 0.7 × VDD VDD V VIL 0 0.3 × VDD V VOH IOH = –2 mA VOL IOL = 2 mA IIH V 0.2 × VDD V VIN = VDD ( – 40°C to 85°C) 10 μA IIL VIN = 0 V ( – 40°C to 85°C) –10 μA IIH VIN = VDD ( – 40°C to 85°C) 25 μA IIL VIN = 0 V ( – 40°C to 85°C) –25 μA Single rate Sampling frequency (2) 0.8 × VDD fS 8 54 Dual rate 54 108 Quad rate 108 216 System clock duty cycle System clock frequency (2) 45 50 kHz 55 % Single rate, SCKI = 256fS 2.048 13.824 MHz Single rate, SCKI = 384fS 3.072 20.736 MHz Single rate, SCKI = 512fS 4.096 27.648 MHz Single rate, SCKI = 768fS 6.144 38.4 MHz Dual rate, SCKI = 256fS 13.824 27.648 MHz Dual rate, SCKI = 384fS 20.736 38.4 MHz Quad rate, SCKI = 128fS 13.824 27.648 MHz Quad rate, SCKI = 192fS 20.736 38.4 MHz ANALOG INPUTS Input voltage, full-scale Differential input Input impedance Common-mode rejection 6 VPP 3 kΩ 85 dB DC PERFORMANCE ±4 % of FSR Gain error ±4 % of FSR Gain mismatch channel-to-channel ±3 % of FSR Output offset error (1) (2) HPFD = 1 Applies to the RST input, pin 19. Single, Dual, and Quad Rate sampling modes are described within this data sheet. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCM4202-EP 3 PCM4202-EP SGLS388 – JUNE 2007 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All parameters are specified at TA = 25°C with VCC = 5 V, VDD = 3.3 V (unless otherwise noted), and a measurement bandwidth from 20 Hz to 20 kHz, unless otherwise noted. System clock frequency is equal to 256 fS for Single and Dual Rate sampling modes, and 128 fS for Quad Rate sampling mode. PARAMETER TEST CONDITIONS PCM4202 MIN TYP MAX –105 –95 UNIT DYNAMIC PERFORMANCE (3) fS = 48 kHz, Single Rate BW = 20 Hz to 20 kHz VIN = –0.5 dBFS, fIN = 1 kHz Total harmonic distortion + noise THD+N Dynamic range VIN = –0.5 dBFS, fIN = 1 kHz (–40°C to 85°C) –90 VIN = –60 dBFS, fIN = 1 kHz, A-Weighted 112 VIN = –60 dBFS, fIN = 1 kHz, A-Weighted (–40°C to 85°C) 108 118 dB VIN = –60 dBFS, fIN = 1 kHz Dynamic range, no weighting dB 116 dB 120 dB VIN = –0.5 dBFS, fIN = 1 kHz –105 dB Dynamic range VIN = –60 dBFS, fIN = 1 kHz, A-Weighted 118 dB Dynamic range, no weighting VIN = –60 dBFS, fIN = 1 kHz 112 dB 120 dB Channel separation (–40°C to 85°C) fS = 96 kHz, Dual Rate Total harmonic distortion + noise 100 BW = 20 Hz to 40 kHz THD+N Channel separation fS = 192 kHz, Quad Rate BW = 20 Hz to 40 kHz –103 dB Dynamic range VIN = 0 VRMS, A-Weighted 117 dB Dynamic range, no weighting VIN = 0 VRMS 108 dB 120 dB VIN = –0.5 dBFS, fIN = 1 kHz –102 dB VIN = –60 dBFS, fIN = 1 kHz, A-Weighted 115 dB 120 dB VIN = –0.5 dBFS, fIN = 1 kHz –105 dB VIN = –60 dBFS, fIN = 1 kHz, A-Weighted 118 dB 120 dB Total harmonic distortion + noise THD+N VIN = –0.5 dBFS, fIN = 1 kHz Channel separation DSD Output, 64 fS Rate Total harmonic distortion + noise DSDBCK = 2.8224 MHz THD+N Dynamic range Channel separation DSD Output, 128 fS Rate Total harmonic distortion + noise DSDBCK = 5.6448 MHz THD+N Dynamic range Channel separation DIGITAL DECIMATION FILTER Passband edge Single and Dual Rate 0.453 fS Hz Passband ripple Single and Dual Rate �0.005 dB Passband edge Single and Dual Rate 0.547 fS Stop band attenuation Single and Dual Rate –100 Group delay Single and Dual Rate Passband edge (–0.005 dB) Quad Rate 0.375 fS Hz –3 dB cutoff frequency Quad Rate 0.490 fS Hz Passband ripple Quad Rate ±0.005 dB Passband edge Quad Rate 0.770 fS Hz Stop band attenuation Quad Rate –135 dB (3) 4 Hz dB 37/fS sec Dynamic performance parameters are measured using an Audio Precision System Two Cascade or Cascade Plus test system. The measurement bandwidth is limited by using the Audio Precision 22 Hz high-pass filter in combination with the Audio Precision 20 kHz, fS/2, or a user-defined 40 kHz low-pass filter. All A-weighted measurements are performed using the Audio Precision A-weighting filter in combination with the previously mentioned filters. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCM4202-EP PCM4202-EP SGLS388 – JUNE 2007 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All parameters are specified at TA = 25°C with VCC = 5 V, VDD = 3.3 V (unless otherwise noted), and a measurement bandwidth from 20 Hz to 20 kHz, unless otherwise noted. System clock frequency is equal to 256 fS for Single and Dual Rate sampling modes, and 128 fS for Quad Rate sampling mode. PARAMETER TEST CONDITIONS Group delay PCM4202 MIN Quad Rate TYP MAX UNIT 9.5/fS sec fS/48000 Hz DIGITAL HIGH PASS FILTER Frequency response (–3 dB) POWER SUPPLY Voltage range VCC 4.75 5 5.25 V VDD 3 3.3 3.6 V 55 65 VCC = 5 V, VDD = 3.3 V fS = 48 kHz, Single Rate fS = 48 kHz, Single Rate (–40°C to 85°C) ICC fS = 96 kHz, Dual Rate 70 55 fS = 96 kHz, Dual Rate (–40°C to 85°C) fS = 192 kHz, Quad Rate Operating supply current IDD 65 70 55 fS = 192 kHz, Quad Rate(–40°C to 85°C) mA mA 65 mA 70 mA VCC = 5 V, VDD = 3.3 V fS = 48 kHz, Single Rate(–40°C to 85°C) 10 12 mA fS = 96 kHz, Dual Rate(–40°C to 85°C) 19 25 mA fS = 192 kHz, Quad Rate(–40°C to 85°C) 13 15 mA VCC = 5 V, VDD = 3.3 V, RST = 0 Power–down mode current ICC Clocks applied (–40°C to 85°C) 10 mA IDD Clocks applied (–40°C to 85°C) 2 mA VCC = 5 V, VDD = 3.3 V Total power dissipation fS = 48 kHz, Single Rate 308 365 mW fS = 96 kHz, Dual Rate 338 408 mW fS = 192 kHz, Quad Rate 318 375 mW Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCM4202-EP 5 PCM4202-EP SGLS388 – JUNE 2007 www.ti.com PIN ASSIGNMENTS DB PACKAGE (TOP VIEW) V REF L 1 28 V REF R AGNDL 2 27 AG NDR V C OM L 3 26 V CO M R V IN L+ 4 25 V IN R+ V IN L - 5 24 V IN R - FMT0 6 23 AG ND FMT1 7 22 VCC P C M 420 2 6 S/M 8 21 CLIPL FS0 9 20 CLIPR FS1 10 19 RST FS2 11 18 SCKI HPFD 12 17 LRCK or DSDBCK DG ND 13 16 BCK or DSDL V DD 14 15 DATA or DSDR Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCM4202-EP PCM4202-EP SGLS388 – JUNE 2007 www.ti.com TERMINAL FUNCTIONS TERMINAL PIN NO. NAME I/O DESCRIPTION 1 VREFL Output Left Channel Voltage Reference 2 AGNDL Ground Left Channel Reference Ground 3 VCOML Output Left Channel DC Common-mode Voltage, 2.5 V Typical 4 VINL+ Input Left Channel Non-inverting Analog Input 5 VINL– Input Left Channel Inverting Analog Input 6 FMT0 Input Audio Data Format Selection 7 FMT1 Input Audio Data Format Selection 8 S/M Input Audio Serial Port Slave/Master Mode Selection (0 = Master, 1 = Slave) 9 FS0 Input Sampling Mode Selection 10 FS1 Input Sampling Mode Selection 11 FS2 Input Sampling Mode Selection 12 HPFD Input High-pass Filter Disable (Active High) 13 DGND Ground Digital Ground 14 VDD Power Digital Power Supply, 3.3 V 15 DATA or DSDR Output Audio Serial Port Left and Right Channel PCM Data or Right Channel DSD Data 16 BCK or DSDL I/O 17 LRCK or DSDBCK I/O 18 SCKI Input System Clock Reset/Power-down (Active Low with internal pull-up) Audio Serial Port Bit (or Data) Clock or Left Channel DSD Data Output Audio Serial Port Left/Right (or Word) Clock or DSD Data Clock Output 19 RST Input 20 CLIPR Output Right Channel Clipping Flag (Active High) 21 CLIPL Output Left Channel Clipping Flag (Active High) 22 VCC Power Analog Power Supply, 5 V 23 AGND Ground Analog Ground 24 VINR– Input Right Channel Inverting Analog Input 25 VINR+ Input Right Channel Non–inverting Analog Input 26 VCOMR Output Right Channel DC Common–mode Voltage, 2.5 V Typical 27 AGNDR Ground Right Channel Reference Ground 28 VREFR Output Right Channel Voltage Reference Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCM4202-EP 7 PCM4202-EP SGLS388 – JUNE 2007 www.ti.com TYPICAL CHARACTERISTICS All parameters are specified at TA = 25°C with VCC = 5 V, VDD = 3.3 V, and a measurement bandwidth from 20 Hz to 20 kHz, unless otherwise noted. OVERALL C HARACTERISTICS SINGLE R ATE FILTER STOP BAN D ATTENUATIO N CHARACTERISTICS SING LE RATE FILTER 50 0 0 Normalized Frequency (f S ) Amplitude (dB) f S = 48 kHz –50 – 100 – 1 50 – 200 0 0 .5 1.0 1 .5 2 .0 2 .5 3.0 3 .5 – 10 – 20 – 30 – 40 – 50 – 60 – 70 – 80 – 90 – 1 00 – 1 10 – 1 20 – 1 30 – 1 40 – 1 50 4 .0 fS = 48 kHz 0 1 0 .7 5 N o rm a liz e d F re q ue n c y (f S ) TRANSIENT BAND CHARACTERISTICS SIN GLE RATE FILTER PASSBAND RIPPLE CHARACTERISTICS SINGLE RATE FILTER 0 0.02 fS = 48 kHz fS = 48 kHz -1 0 -2 Am plitude (dB) Amplitude (dB) 0 .5 0.2 5 Normalized Frequency (fS) – 0.02 – 0 .0 4 – 0 .0 6 -3 -4 -5 -6 -7 -8 – 0 .0 8 -9 - 10 – 0 .1 0 0 .1 0 .2 0 .4 0.3 0 .6 0 .5 0 .4 5 0.4 7 0 .4 9 N o rm a liz e d F re q ue n c y (f S ) OVERALL CH AR ACTERISTICS D UAL RATE FILTER 0 .5 5 0 f S = 96 kHz Amplitude (dB) 0 Amplitude (dB) 0 .5 3 STO P BAND ATTENUATION CH AR AC TERISTICS DUAL RATE FILTER 50 - 50 -100 -150 -200 0 0 .2 0.4 0.6 0 .8 1 .0 1 .2 1 .4 1 .6 1 .8 2 .0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 - 130 - 140 - 150 f S = 96 kHz 0 0.25 0.5 0.75 1 Normalized Frequency (f S ) Normalized Frequency (f S ) 8 0.5 1 Normalized Frequency (f S ) Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCM4202-EP PCM4202-EP SGLS388 – JUNE 2007 www.ti.com TYPICAL CHARACTERISTICS (continued) All parameters are specified at TA = 25°C with VCC = 5 V, VDD = 3.3 V, and a measurement bandwidth from 20 Hz to 20 kHz, unless otherwise noted. PASSBAND RIPPLE C HARACTERISTICS DUAL RATE FILTER TRANSIENT BAND CHARACTERISTIC S DUAL RATE FILTER 0 0.02 f S = 96 kHz 0 -2 Amplitude (dB) Amplitude (dB) f S = 96 kHz -1 – 0.02 – 0 .0 4 – 0 .0 6 -3 -4 -5 -6 -7 -8 – 0 .0 8 -9 - 10 – 0 .1 0 0 .2 0 .1 0 .4 0 .3 0 .6 0 .5 0 .45 0 .4 7 0 .4 9 N o rm a liz e d F re q u e n cy (f S ) OVERALL CHARACTERISTICS QUAD RATE FILTER 0.5 5 0 f S = 192 kHz Am plitude (dB) 0 Am plitude (dB) 0 .5 3 STOP BAND ATTENUATION CHARACTERISTICS QUAD RATE FILTER 50 - 50 - 100 - 150 - 200 0 0.1 0 .2 0 .3 0 .4 0 .5 0.6 0.7 0 .8 0 .9 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 - 110 - 120 - 130 - 140 - 150 1 f S = 192 kHz 0 0.5 0.25 0.75 1 Norm alized Frequency (f S ) Normalized Frequency (f S ) PASSBAND RIPPLE CHARACTERISTICS QUAD RATE FILTER TRANSIENT BAND CHARACTERISTICS QUAD RATE FILTER 0 0.02 f S = 192 kH z f S = 192 kHz -1 0 -2 Am plitude (dB) Amplitude (dB) 0 .5 1 Normalized Frequency (f S ) - 0.02 - 0 .0 4 - 0 .0 6 - 3 .9 0 dB a t 0 .5 f S -3 -4 -5 -6 -7 -8 - 0 .0 8 -9 -10 - 0.1 0 0 .1 0.2 0 .3 0 .4 0 .5 0.6 0.4 5 N orm a liz e d F re qu en c y (f S ) 0 .4 7 0 .4 9 0 .5 1 0 .5 3 0.5 5 Normalized Frequency (f S ) Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCM4202-EP 9 PCM4202-EP SGLS388 – JUNE 2007 www.ti.com TYPICAL CHARACTERISTICS (continued) All parameters are specified at TA = 25°C with VCC = 5 V, VDD = 3.3 V, and a measurement bandwidth from 20 Hz to 20 kHz, unless otherwise noted. HIGH PASS FILTER STOP BAND CHARACTERISTICS HIGH PASS FILTER PASSBAND CH AR AC TERISTICS 5 0.02 0 Amplitude (dB) Amplitude (dB) - 20 - 40 - 60 - 80 - 0.02 - 0 .04 - 0 .06 - 0 .08 - 1 00 - 0 .1 0 0 .1 0 .2 0 .3 0 .4 0 0.5 1 0 – 20 - 40 – 40 - 60 – 60 Am plitude (dB) Amplitude (dB) 0 - 20 - 80 - 100 - 120 - 140 2.5 3 3.5 4 10k 20k – 80 – 100 – 120 – 140 – 160 - 160 - 180 – 180 20 100 1k 10k 20k 20 10 0 1k Frequency (Hz) Frequency (Hz) FFT PLO T (f S = 48 kHz, No Input [Idle]) FFT PLOT (f S = 96 kHz, f IN = 997 Hz at - 20 d B) 0 0 - 20 - 20 -40 - 40 -60 - 60 Amplitude (dB) Amplitude (dB) 2 FFT PLOT (fS = 48 kHz, f IN = 997 Hz at - 60 dB) FFT PLO T (f S = 48 kHz, f IN = 997 Hz at - 20 dB) -80 - 10 0 - 12 0 - 14 0 - 80 - 100 - 120 - 140 - 160 - 16 0 - 180 - 18 0 20 1 00 1k 10k 20k 20 Frequency (Hz) 10 1.5 N o rm a liz ed F re q u e n c y (f S /1000) Normalized Frequency (f S /1000) 100 1k 10 k 40k Frequency (Hz) Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCM4202-EP PCM4202-EP SGLS388 – JUNE 2007 www.ti.com TYPICAL CHARACTERISTICS (continued) All parameters are specified at TA = 25°C with VCC = 5 V, VDD = 3.3 V, and a measurement bandwidth from 20 Hz to 20 kHz, unless otherwise noted. FFT PLOT (f S = 96 kHz, No Input [Idle]) 0 0 - 20 - 20 - 40 - 40 - 60 - 60 Amplitude (dB) Amplitude (dB) FFT PLOT (fS = 96 kHz, f IN = 997 Hz at - 60 dB) - 80 - 100 - 120 - 140 - 160 - 120 - 140 - 160 - 180 - 180 20 100 1k 10k 4 0k 20 100 1k Frequency (Hz) FFT PLOT (f S = 192 kHz, f IN = 997 Hz at - 20 dB) FFT PLOT (f S = 192 kHz, f IN = 997 Hz at - 60 dB) 0 0 - 20 - 20 - 40 - 40 - 60 - 60 - 80 - 100 - 120 - 140 - 160 40k - 80 - 100 - 120 - 140 - 160 - 180 - 180 20 100 1k 10k 10 0k 20 10 0 1k Frequency (Hz) -20 -40 -60 THD+N (dB) -80 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 100 1k 1 0 0k THD+N vs AM PLITUDE (f S = 48 kHz, f IN = 1 kHz, BW = 10 Hz to 20 kHz) 0 20 10k Frequency (Hz) FFT PLOT (f S = 192 kHz, No Input [Idle]) Amplitude (dB) 10k Frequency (Hz) Am plitude (dB) Amplitude (dB) - 80 - 100 10k 100k - 90 - 92 - 94 - 96 - 98 -100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120 – 14 0 Frequency (Hz) – 120 – 100 – 80 –60 –40 –20 0 Input Amplitude (dB) Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCM4202-EP 11 PCM4202-EP SGLS388 – JUNE 2007 www.ti.com TYPICAL CHARACTERISTICS (continued) All parameters are specified at TA = 25°C with VCC = 5 V, VDD = 3.3 V, and a measurement bandwidth from 20 Hz to 20 kHz, unless otherwise noted. THD+N vs AM PLITUDE (fS = 96 kHz, f IN = 1 kHz, BW = 10 H z to 40 kHz) – 90 – 92 – 94 – 96 – 98 – 100 – 102 – 104 – 106 – 108 – 110 – 112 – 114 – 116 – 118 – 120 THD+N (dB) THD+N (dB) THD+N vs FR EQ UENCY (f S = 48 kHz, Input Am plitude = - 0.5 dB, BW = 10 Hz to 20 kHz) – 90 – 92 – 94 – 96 – 98 – 1 00 – 1 02 – 1 04 – 1 06 – 1 08 – 1 10 – 1 12 – 1 14 – 1 16 – 1 18 – 1 20 – 14 0 20 100 1k 10k – 120 – 100 2 0k – 80 –60 –40 –20 0 Input Amplitude (dB) Input Frequency (Hz) THD+N vs AM PLITUDE (f S = 192 kHz, f IN = 1 kHz, BW = 10 Hz to 40 kHz) – 90 –92 –94 –96 –98 – 10 0 – 10 2 – 10 4 – 10 6 – 10 8 – 11 0 – 11 2 – 11 4 – 11 6 – 11 8 – 12 0 THD+N (dB) THD+N (dB) THD+N vs FREQUENCY (f S = 96 kHz, Input Amplitude = - 0.5 dB, BW = 10 Hz to 40 kHz) - 90 - 92 - 94 - 96 - 98 - 1 00 - 1 02 - 1 04 - 1 06 - 1 08 - 1 10 - 1 12 - 1 14 - 1 16 - 1 18 - 1 20 - 14 0 20 100 1k 10k - 12 0 40k - 100 - 80 - 60 - 40 - 20 0 Input Amplitude (dB) Input Frequency (Hz) THD+N (dB) THD+N vs FREQUENCY (f S = 192 kHz, Input Amplitude = - 0.5 dB, BW = 10 Hz to 40 kHz) - 90 - 92 - 94 - 96 - 98 - 100 - 102 - 104 - 106 - 108 - 110 - 112 - 114 - 116 - 118 - 120 20 100 1k 10k 80 k Input Frequency (Hz) 12 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCM4202-EP PCM4202-EP SGLS388 – JUNE 2007 www.ti.com PRODUCT OVERVIEW The PCM4202 is a high-performance, stereo audio analog-to-digital (A/D) converter designed for use in professional and broadcast audio applications. The PCM4202 features 24 bit linear PCM or 1 bit Direct Stream Digital (DSD) data output capability for both channels. Sampling rates up to 216 kHz are supported for PCM output formats, while 64× or 128× oversampled 1 bit data is supported for DSD output mode. Native support for both PCM and DSD data formats makes the PCM4202 ideal for use in a wide variety of audio recording and processing applications. The PCM4202 features 1 bit delta-sigma modulators employing density modulated dither for improved dynamic performance. Differential voltage inputs are utilized for the modulators, providing excellent common-mode rejection. On-chip voltage references are provided for the modulators, in addition to generating DC common-mode bias voltage outputs for use with external input circuitry. Linear phase digital decimation filtering is provided for the 24 bit PCM data outputs, with a minimum stop band attenuation of –100 dB for all sampling modes. The PCM output mode features clipping flag outputs for each channel, as well as a digital high-pass filter for DC removal. The PCM4202 may be configured using dedicated input pins for sampling mode and audio data format selection, high-pass filter enable/disable, and reset/power-down operation. A 5 V power supply is required for the analog section of the device, while a 3.3-V power supply is required for the digital circuitry. Figure 1 shows the functional block diagram for the PCM4202. V IN R+ V IN R - Delta- Sigma Modulator Decim ation Filter LRCK or DSDBCK HPF BCK or DSDL V CO M R AGNDR V R EF R V RE F L AGND L DATA or DSDR Voltage Reference Audio Serial Port Voltage Reference CLIPR CLIPL V COM L S/M FMT0 V IN L - Delta- Sigma Modulator Decim ation Filter FMT1 HPF VIN L+ HPFD FS0 Reset Logic Power Clock Control FS1 FS2 SCKI RST V CC AGND V DD DGND Figure 1. PCM4202 Functional Block Diagram Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCM4202-EP 13 PCM4202-EP SGLS388 – JUNE 2007 www.ti.com ANALOG OUTPUTS The PCM4202 includes two channels of A/D conversion, each with its own pair of differential voltage input pins. The VINL+ (pin 4) and VINL– (pin 5) inputs correspond to Left channel input, while VINR+ (pin 25) and VINR– (pin 24) correspond to the Right channel input. The average input impedance of each input pin is 3 kΩ. Each analog input pair accepts a full-scale input voltage of approximately 6 VPP differential, which corresponds to a 2.12 VRMS or 8.75 dBu input swing. The analog input should not swing below analog ground or above the VCC power supply by more than 300 mV. Refer to the Applications Information section of this datasheet for an example input buffer circuit. VOLTAGE REFERENCES AND COMMON MODE BIAS VOLTAGES OUTPUTS The PCM4202 includes two on-chip voltage references, one each for the Left and Right channels. The VREFL (pin 1) and VREFR (pin 28) outputs correspond to high reference outputs for Left and Right channels, respectively. De-coupling capacitors are connected between each of these pins and the corresponding reference ground pin, either AGNDL (pin 2) for the VREFL output or AGNDR (pin 27) for the VREFR output. It is recommended to have at least a 0.1 μF X7R ceramic chip capacitor connected in parallel with a 33 μF low ESR tantalum chip capacitor for de-coupling purposes. The VREFL and VREFR outputs should not be utilized to bias external circuitry, because they are not buffered. Use the VCOML (pin 3) and VCOMR (pin 26) outputs to bias external circuitry, as described in the following paragraphs. Refer to the Applications Information section of this datasheet for the recommended voltage reference pin connections. The PCM4202 analog inputs are internally biased to approximately VCC/2. This bias voltage is referred to as the common mode voltage, and is output at VCOML (pin 3) and VCOMR (pin 26), corresponding to the Left and Right channels, respectively. These outputs provide a level shifting voltage for biasing external input buffer circuitry. Although the VCOML and VCOMR outputs are internally buffered, the output current is limited to a few hundred μA. It is recommended to connect these pins to external nodes with greater than 1 MΩ impedance, or to buffer the outputs with a voltage follower circuit when driving multiple external or low impedance nodes. Refer to the Applications Information section of this datasheet for an example input buffer circuit that utilizes the common-mode bias voltage outputs. SYSTEM CLOCK INPUT The PCM4202 requires an external system clock, from which the modulator oversampling and digital sub-system clocks are derived. The system clock is applied at the SCKI input (pin 18). The frequency of the system clock is dependent upon the desired PCM output sampling frequency or DSD data rate, along with the sampling mode selection. Table 1 shows the corresponding system clock frequencies for common output sampling and data rates, along with the corresponding sampling modes. Timing requirements for the system clock are shown in Figure 2. Table 1. System Clock Frequencies for Common Output Sampling and Data Rates SAMPLING MODE SAMPLING�FREQUENCY,�f S SYSTEM CLOCK FREQUENCY (MHz) (kHz) 128 fS 192 fS 256 fS 384 fS 512 fS 768 fS Single Rate 32 n/a n/a 8.192 12.288 16.384 24.576 Single Rate 44.1 n/a n/a 11.2896 16.9344 22.5792 33.8688 Single Rate 48 n/a n/a 12.288 18.432 24.576 36.864 Dual Rate 88.2 n/a n/a 22.5792 33.8688 n/a n/a Dual Rate 96 n/a n/a 24.576 36.864 n/a n/a Quad Rate 176.4 22.5792 33.8688 n/a n/a n/a n/a Quad Rate 192 24.576 36.864 n/a n/a n/a n/a DSD Output 128 fS Data (Single Rate) n/a n/a 11.2896 16.9344 22.5792 33.8688 DSD Output 64 fS Data (Dual Rate) n/a n/a 11.2896 16.9344 n/a n/a 14 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCM4202-EP PCM4202-EP SGLS388 – JUNE 2007 www.ti.com t SCKIH SCKI t SCK IL t SCK I PA R A M E TE R D E S C R IP TIO N M IN t SCK I System Clock Period 26 ns t SC K IH System Clock High Pulse Time 12 ns t S C K IL System Clock Low Pulse Tim e 12 ns MAX U N IT S Figure 2. System Clock Timing Requirements SAMPLING MODES The PCM4202 may be operated in one of three PCM sampling modes, or at one of two DSD output data rates. The PCM sampling modes are referred to as Single Rate, Dual Rate, and Quad Rate. Single Rate mode is utilized for sampling rates up to 54 kHz. The delta-sigma modulator oversamples the analog input signal by a rate equal to 128 times the desired output sampling rate. Dual Rate mode is utilized for sampling rates higher than 54 kHz and up to 108 kHz. The delta-sigma modulator oversamples the analog input signal by a rate equal to 64 times the desired output sampling rate. Quad Rate mode is utilized for sampling frequencies higher than 108 kHz and up to 216 kHz. The delta-sigma modulator oversamples the analog input signal by a rate equal to 32 times the desired output sampling rate. For DSD output data, the user may select either 64 fS or 128 fS oversampled data rates, where fS is the base sampling rate, which is 44.1 kHz for Super Audio CD (SACD) applications. The 64 fS data rate is analogous to the Dual Rate PCM sampling mode, where the analog input signal is oversampled by a rate equal to 64 times the base sampling rate. The 128 fS data rate corresponds to the Single Rate PCM sampling mode, where the analog input signal is oversampled by a rate equal to 128 times the base sampling rate. Table 1 indicates the sampling mode utilized for common system clock and sampling rate combinations. The FS0 (pin 9), FS1 (pin 10), and FS2 (pin 11) inputs are utilized to select the sampling mode for the PCM4202. If the state of the sampling mode pins is changed any time after power-up reset initialization, the user should issue an external forced reset to re-initialize the PCM4202. Table 2, Table 3, and Table 4 indicate the sampling mode selections for PCM Master and Slave mode operation, as well as the DSD Output mode. Table 2. Sampling Mode Selection for PCM Master Mode Operation FS2 FS1 FS0 0 0 0 SAMPLING MODE WITH SYSTEM CLOCK RATE Single Rate with fSCKI = 768 fS 0 0 1 Single Rate with fSCKI = 512 fS 0 1 0 Single Rate with fSCKI = 384 fS 0 1 1 Single Rate with fSCKI = 256 fS 1 0 0 Dual Rate with fSCKI = 384 fS 1 0 1 Dual Rate with fSCKI = 256 fS 1 1 0 Quad Rate with fSCKI = 192 fS 1 1 1 Quad Rate with fSCKI = 128 fS Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCM4202-EP 15 PCM4202-EP SGLS388 – JUNE 2007 www.ti.com Table 3. Sampling Mode Selection for PCM Slave Mode Operation FS2 FS1 FS0 0 0 0 Single Rate with Clock Auto-Detection SAMPLING MODE 0 0 1 Dual Rate with Clock Auto-Detection 0 1 0 Quad Rate with Clock Auto-Detection 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved Table 4. Sampling Mode Selection for DSD Output Mode Operation FS2 FS1 FS0 0 0 0 128 fS DSD Output Rate with fSCKI = 768 fS SAMPLING MODE 0 0 1 128 fS DSD Output Rate with fSCKI = 512 fS 0 1 0 128 fS DSD Output Rate with fSCKI = 384 fS 0 1 1 128 fS DSD Output Rate with fSCKI = 256 fS 1 0 0 64 fS DSD Output Rate with fSCKI = 384 fS 1 0 1 64 fS DSD Output Rate with fSCKI = 256 fS 1 1 0 Reserved 1 1 1 Reserved AUDIO DATA FORMATS As mentioned previously, the PCM4202 supports 24 bit linear PCM output data, as well as 1 bit DSD output data. The available data formats are dependent upon whether the PCM4202 is configured in Slave or Master mode. The S/M (pin 8), FMT0 (pin 6), and FMT1 (pin 7) inputs are utilized to select either Slave or Master mode and the corresponding audio data format. In Slave mode, the PCM bit and left/right clocks (BCK and LRCK) are configured as input pins. DSD data formats are not supported in Slave mode. Slave mode supports commonly used PCM audio data formats, including Left Justified, Right Justified, and Philips I2S. In Master mode, the PCM bit and left/right clocks (BCK and LRCK respectively) are configured as output pins, and are derived from the system clock input (SCKI). Alternatively, the DSD output data may be provided at the port output. Table 5 shows the available data format selections. Figure 3 and Figure 4 illustrate the PCM and DSD data formats. Table 5. Audio Data Format Selection 16 FMT1 FMT0 0 0 AUDIO DATA FORMAT 24 bit Left Justified 0 1 24 bit I2S 1 0 24 bit Right Justified 1 1 1 bit DSD (Master Mode Only) Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCM4202-EP PCM4202-EP SGLS388 – JUNE 2007 www.ti.com Right Channel Left Channel LRCKI BCKI DATA MSB LS B MSB LSB (a) Left Justified Data Form at LRCKI BCKI DATA MSB LSB MSB LSB (b) Right Justified Data Form at LRCKI BCKI DATA MSB LS B MS B LSB (c) I 2 S Data Form at 1/f S Figure 3. PCM Data Formats: Left Justified, Right Justified, and Philips I2S DSDBCK D SD L DSDR D N -3 D N-2 D N-1 D N D N+1 D N+2 D N+ 3 D N+4 Figure 4. DSD Output Data Format AUDIO SERIAL PORT OPERATION This section provides additional details regarding the PCM4202 audio serial port, utilized for 24 bit linear PCM or 1 bit DSD output data. PCM output operation will be described in this section, while DSD output mode operation will be described in the following section. For PCM data formats, the serial port is comprised of three signals: BCK (pin 16), LRCK (pin 17), and DATA (pin 15). The BCK signal functions as the data (or bit) clock for the serial audio data. The LRCK is the left/right word clock for the audio serial port. The LRCK and BCK clocks must be synchronous. The DATA signal is the serial audio data output, with data being clocked out on the falling edge of the BCK signal. DATA carries audio data for both the Left and Right channels. As mentioned in the Audio Data Format section of this datasheet, the audio serial port can operate in Master or Slave mode. In Master mode, the BCK and LRCK clock signals are outputs, derived from the system clock input, SCKI. The BCK clock is fixed at 128 fS for Single Rate sampling mode, and at 64 fS for Dual or Quad Rate sampling modes. The LRCK clock operates at fS, the output sampling rate (that is, 48 kHz, 96 kHz, etc.). Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCM4202-EP 17 PCM4202-EP SGLS388 – JUNE 2007 www.ti.com In Slave mode, the BCK and LRCK signals are inputs, with the clocks being generated by a master timing source, such as a DSP serial port, PLL clock synthesizer, or a crystal oscillator/divider circuit. The BCK rate is typically equal to 128 fS in Single Rate sampling mode, and 64 fS in Dual or Quad Rate sampling modes. Although other BCK clock rates are possible, they are not recommended as a result if potential clock phase sensitivity issues, which can degrade the dynamic performance of the PCM4202. The LRCK clock must be operated at fS, the output sampling rate. Figure 5 illustrates the typical audio serial port connections between a PCM4202 and an audio signal processor when using the PCM output data formats. Figure 6 illustrates the audio serial port timing for both the Master and Slave modes of operation. DSP P C M 4202 FSX LRCK C LKR BC K DR DATA SC KI System C lock Figure 5. Typical Audio Serial Port Connections for Left Justified, Right Justified, and I2S Data Formats tLRCKHL tLRCKHL tLRCKHL LRCK BCK tBCKP tBCKHL DATA tBCKDO D E S C R IP T IO N PARAM ETER M IN MAX U N IT S tLRCKP LRCK P e riod 5 tLRCKHL LRCK High/Low Tim e 2.25 µs BCK P e riod 78 ns BCK High/Low Time 35 tBCKP tBCKHL tBCKDO S DOUT Da ta Output De la y from BCK Fa lling Edge µs ns 10 ns Figure 6. Master and Slave Mode Audio Serial Port Timing: Left Justified, Right Justified, and Philips I2S DSD OUTPUT MODE OPERATION The output port DSD mode operation consists of a single DSD data clock signal, DSDBCK (pin 17), along with two synchronous DSD data lines, DSDR (pin 15) and DSDL (pin 16). The data lines correspond to Right and Left channels, respectively. The DSD output rate is determined by the sampling mode settings for the device, discussed in the Sampling Modes section of this datasheet. For DSD output data, the serial port is configured in Master mode, with the DSDBCK derived from the system clock input, SCKI. The DSDBCK is equivalent to the oversampling clock supplied to the delta-sigma modulators. The DSD data outputs, DSDR through DSDL, are synchronous to the DSDBCK. The clock and data lines are then connected to a data capture or processing device. Figure 7 illustrates the DSD port timing for both the DSD output mode. 18 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCM4202-EP PCM4202-EP SGLS388 – JUNE 2007 www.ti.com DSDBCK t D CKP t DCK HL DSDL DSD R t DCKD O D E S C R IP T IO N M IN t DCK P LRCK pulse width 156 t DCK P LRCK active edge to BCK sampling edge delay 70 t DCK P Data setup time PARA M ETER MAX U N IT S ns ns 10 ns Figure 7. DSD Data Port Timing HIGH-PASS FILTER A digital high-pass filter is available for removing the DC component of the digitized input signal. The filter is located at the output of the digital decimation filter, and is available only when using PCM output data formats. The high-pass filter can be enabled or disabled for both the Left and Right channels using the HPFD input (pin 12). Driving the HPFD input low enables the high-pass filter. Driving the HPFD input high disables the high-pass filter. The –3 dB corner frequency for the high-pass filter scales with the output sampling rate, where f–3 where fS is the output sampling rate. dB = fS/48000, CLIPPING FLAGS The PCM4202 includes a clipping flag output for each channel. The outputs are designated CLIPL (pin 21) and CLIPR (pin 20), corresponding to the Left and Right channels, respectively. The clipping flags are only available when using PCM output data formats. A clipping flag is forced high as soon as the digital output of the decimation filter exceeds the full-scale range for the corresponding channel. The clipping flag output is held high for a maximum of (256 × N) / fS seconds, where N = 128 for Single Rate sampling mode, 256 for Dual Rate sampling mode, and 512 for Quad Rate sampling mode. If the decimation filter output does not exceed the full-scale range during the initial hold period, the output returns to a low state upon termination of the hold period. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCM4202-EP 19 PCM4202-EP SGLS388 – JUNE 2007 www.ti.com RESET OPERATION The PCM4202 includes two reset functions: power-on and externally controlled. This section describes the operation of each of these functions. On power-up, the internal reset signal is forced low, forcing the PCM4202 into a reset state. The power-on reset circuit monitors the VDD (pin 14) and VCC (pin 22) power supplies. When the VDD supply exceeds 2 V (±400 mV) and the VCC supply exceeds 4 V (±400 mV), the internal reset signal is forced high. The PCM4202 then waits for the system clock input (SCKI) to become active. Once the system clock has been detected, the initialization sequence begins. The initialization sequence requires 1024 system clock periods for completion. During the initialization sequence, the ADC output data pins are forced low. Once the initialization sequence is completed, the PCM4202 output is enabled. Figure 8 shows the power-on reset sequence timing. The user may force a reset initialization sequence at any time while the system clock input is active by utilizing the RST input (pin 19). The RST input is active low, and requires a minimum low pulse width of 40 ns. The low-to-high transition of the applied reset signal forces an initialization sequence to begin. As in the case of the power-on reset, the initialization sequence requires 1024 system clock periods for completion. Figure 9 illustrates the reset sequence initiated when using the RST input. Figure 10 shows the state of the audio data outputs for the PCM4202 before, during and after the reset operations. ~ 4.0V V CC 0V V DD ~ 2.0V 0V Internal Reset 1024 System Clock Periods Required for Initialization 0V SCKI 0V System Clock Indeterminate or Inactive Figure 8. Power-Up Reset Timing 20 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCM4202-EP PCM4202-EP SGLS388 – JUNE 2007 www.ti.com t RSTL > 40ns RST 0V 1024 System Clock Periods Required for Initialization Internal Reset 0V SCKI 0V Figure 9. External Reset Timing Internal Reset Output Data Pins HI LO Valid Output Data Outputs are Forced Low Outputs are Forced Low for 1024 SCKI Periods Valid Output Data Initialization Period Figure 10. ADC Digital Output State for Reset Operations POWER-DOWN OPERATION The PCM4202 can be forced to a power-down state by applying a low level to the RST input (pin 19) for a minimum of 65,536 system clock cycles. In power-down mode, all internal clocks are stopped, and output data pins are forced low. The system clock may then be removed to conserve additional power. Before exiting power-down mode, the system and audio clocks should be restarted. Once the clocks are active, the RST input may be driven high, which initiates a reset initialization sequence. Figure 11 illustrates the state of the output data pins during before, during, and upon exiting the power-down state. APPLICATIONS INFORMATION A typical connection diagram for the PCM4202 is shown in Figure 12. Capacitors for power supply and reference bypassing are shown with recommended values. Bypass capacitors should be located as close as possible to the power supply and reference pins of the PCM4202. Due to its small size, the 0.1 μF capacitor can be located on the component (top) side of the board, while the larger 33 μF capacitor can be located on the solder (bottom) side of the board. A single ground plane is utilized for the analog and digital ground connections. This approach ensures a low impedance connection between the analog and digital ground pins. The 5 V analog and 3.3 V digital power connections are provided from separate supplies. Figure 13 illustrates an example input buffer circuit, designed for balanced differential input signals. This circuit is utilized on the PCM4202EVM evaluation board. The 2.7 nF and 100 pF capacitors shown at the output of the buffer should be located as close as possible to the analog input pins of the PCM4202. The buffer shown in Figure 13 can be easily made to function as a single ended to differential converter by simply grounding the (–) input terminal of the buffer circuit. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCM4202-EP 21 PCM4202-EP SGLS388 – JUNE 2007 www.ti.com The input impedance for the VCOMIN pin of the OPA1632 is relatively low and will load down the VCOML or VCOMR outputs from the PCM4202. A voltage follower circuit is required to buffer these outputs, with a typical circuit configuration shown in Figure 14. An OPA227 is utilized as the buffer for the PCM4202EVM evaluation board. However, alternative op amps with comparable performance may be substituted. HI RST LO Output Data Pins Outputs are Forced Low Valid Output Data 65,536 SCKI Periods O utputs are Forced Low Outputs are Forced Low Valid Output Data 1024 SCKI Periods Required for Initialization Enter Power- Down State Figure 11. ADC Digital Output State for Power-Down Operations 33 µF 33 µF + + 0.1 µF 0.1 µF 1 28 V REF R V REF L 2 27 AGNDR AGNDL 0 .1 µF 3 In pu t Bu ffe r V CO M R V IN L+ V IN R+ V IN L - V IN R - FMT0 AG ND 4 Le ft C ha n ne l An a log Inp u t 25 5 R ig ht C h a n n e l An a lo g In pu t 24 6 23 7 +5 V 22 FMT1 VCC P C M 4202 8 F rom Log ic, µP , or Ha rd wire d C o nn e ction 0.1 µF 26 V COM L CLIPL FS0 CLIPR FS1 R ST 9 20 10 19 11 18 FS2 0.1 µF 21 S/M SCKI 12 + 3 3µF To C lipp in g In dica tors To A/D o r S ys te m R e s e t To Aud io S ys te m C lo ck 17 HPFD LRCK or DSDBCK DGND BCK or D SDL 13 Digita l Au dio Tra ns m itte r or P roc e s s o r 16 0 .1µF 14 15 V DD DATA or DSDR 33 µF + +3 .3V Figure 12. Typical Connection Diagram 22 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCM4202-EP PCM4202-EP SGLS388 – JUNE 2007 www.ti.com 27 0 W 1nF - 15V 10 µF + 0 .0 1µF 6 7 (+) Diffe re n tia l An a log Inp u t (- ) 1k W 8 EN 5 O P A 1632 1k W 1 VO CM 40.2 W 100pF To V IN - 4 0 .2 W 2 .7 n F To V IN + 4 1 00 p F 2 3 From Buffered V CO M in Figure 14. 1kW 0 .0 1µF 0 .1 µF 10 µF + +1 5V 1nF 27 0 W Figure 13. Example Input Buffer Circuit O P A 22 7 or equivalent P C M 4202 V CO M L 0.1 µ F or V COM R To Buffered V C OM in Figure 13. Figure 14. Example Buffer Circuit for VCOML and VCOMR COMPATIBILITY WITH THE PCM1804 Although the PCM4202 and PCM1804 are pin- and function-compatible, there are a few differences between the two devices that the designer should be aware of. These differences are noted here for clarity. • The full-scale input of the PCM4202 is 6 VPP differential, while it is 5 VPP for the PCM1804. This is a result of the PCM4202 having an internal 3-V voltage reference, and the PCM1804 having an internal 2.5-V voltage reference. • The PCM1804 includes 5-V tolerant digital inputs. The PCM4202 does not include these because the digital inputs are designed for interfacing to 3.3 V logic. • The reset pin (RST) pin of the PCM4202 has an internal pull-up resistor. For the PCM1804, this pin has an internal pull-down resistor. • When operating in Master mode with Single Rate sampling selected, the audio serial port bit clock (BCK) is equal to 64 fS for the PCM1804, while the BCK rate is equal to 128 fS for the PCM4202. • The following pins on the PCM4202 and PCM1804 have different names, but they perform the same functions. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCM4202-EP 23 PCM4202-EP SGLS388 – JUNE 2007 www.ti.com Table 6. PINS 24 TERMINAL NUMBER PCM4202 TERMINAL NAME PCM1804 TERMINAL NAME 9 FS0 OSR0 10 FS1 OSR1 11 FS2 OSR2 12 HPFD BYPAS 20 CLIPR OVFR 21 CLIPL OVFL Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCM4202-EP PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty PCM4202IDBREP ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/07642-01XE ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF PCM4202-EP : • Catalog: PCM4202 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device PCM4202IDBREP Package Package Pins Type Drawing SSOP DB 28 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 8.2 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.5 2.5 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM4202IDBREP SSOP DB 28 2000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such components to meet such requirements. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated