OKI MSM9200-XX

E2C0035-27-Y4
el
Pr
5 ¥ 7 Dot Character ¥ 16-Digit Display Controller/Driver with Character RAM
GENERAL DESCRIPTION
The MSM9200-xx is a dot matrix vacuum fluorescent display tube controller driver IC which
displays characters, numerics and symbols.
Dot matrix vacuum fluorescent display tube drive signals are generated by serial data sent from
a microcontroller. A display system is easily realized by internal ROM and RAM for character
display.
The MSM9200-xx has low power consumption because it is munufactured in CMOS process
technology.
-01 and -02 are available as general codes.
Custom codes are provided if necessary.
FEATURES
• Logic power supply (VDD)
: 3.3 V±10%/5.0 V±10%
• Fluorescent display tube drive power supply (VDISP) : 3.3 V±10%/5.0 V±10%
• Fluorescent display tube drive power supply (VFL)
: –20 to –60 V
• VFD driver output current
(VFD driver output can directly be connected to the fluorescent display tube. No pull-down
resistor is required.)
- Segment driver (SEG1 to SEG35)
: –5 mA
(VFL=–60V)
- Segment driver (AD1 to AD8)
: –10 mA
(VFL=–60V)
- Grid driver (COM1 to COM16)
: –30 mA
(VFL=–60V)
• General output port output current
- Output driver (P1-4)
: ±1 mA (VDD=3.3V±10%)
±2 mA (VDD=5.0V±10%)
• Content of display
- CGROM
5¥7 dots, 224 types
(character data)
- CGRAM
5¥7 dots, 32 types
(character data)
- ADRAM
16 (display digit) ¥8 bits (symbol data)
- DCRAM
64 (stored digit) ¥8 bits (register for character data display)
- General output port
4 bits (static mode)
• Display control function
- Display digit
: 1 to 16 digits
- Display duty (contrast adjustment)
: 16 stages
- Display blink position specification : Blinking time is input externally
- Display shift (left and right)
: Can be set only for SEG output
- All lights ON/OFF
• 4 interfaces with microcontroller
: DA, CS, CP, and BLINK (5 interfaces when RESET is
added)
• 1 byte instruction execution (excluding data write to RAM and display blink position
specification)
• Oscillation circuit included (external C and R)
• Package:
80-pin plastic QFP (QFP80-P-1414-0.65-K)
(Product name: MSM9200-xxGS-K)
xx indicated the code number.
1/34
y
ar
This version:MSM9200-xx
Nov. 1997
Previous version: Jul. 1996
in
¡ Semiconductor
MSM9200-xx
im
¡ Semiconductor
¡ Semiconductor
MSM9200-xx
BLOCK DIAGRAM
VDISP
VDD
GND
VFL
BLINK
DCRAM
64w¥8b
SEG1
CGROM
224w¥35b
Segment
Driver
CGRAM
32w¥35b
RESET
DA
CP
CS
8-bit
Shift
Register
ADRAM
16w¥8b
DCRAM
Address
Counter
SEG35
AD1
AD
Driver
AD8
Address
Selector
Command
Decoder
Write
Address
Counter
Read
Address
Counter
P1
Port
Driver
Control
Circuit
P4
Digit
Control
Duty
Control
Timing
Generator 1
COM1
Grid
Driver
COM16
Timing
Generator 2
OSC0
Oscillator
OSC1
2/34
¡ Semiconductor
MSM9200-xx
INPUT AND OUTPUT CONFIGURATION
Schematic Diagrams of Logic Portion Input and Output Circuits
Input Pin
VDD
VDD
INPUT
GND
GND
Output Pin
VDD
VDD
OUTPUT
GND
GND
Schematic Diagram of Driver Output Circuit
VDISP
VDISP
OUTPUT
VFL
VFL
3/34
¡ Semiconductor
MSM9200-xx
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
VFL2
NC
VDISP3
NC
P4
P3
P2
P1
GND
OSC0
OSC1
RESET
BLINK
DA
CP
CS
VDD
VDISP2
NC
VFL1
PIN CONFIGURATION (TOP VIEW)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
SEG35
SEG34
SEG33
SEG32
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VDISP1
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
NC: No connection
80-Pin Plastic QFP
4/34
¡ Semiconductor
MSM9200-xx
PIN DESCRIPTION
Pin
Symbol
Type Connects to:
Description
Fluorescent Fluorescent display tube anode electrode drive output.
10 to 44
SEG1-35
O
tube grid
Directly connected to fluorescent display tube and a pull-down
electrode
resistor is not necessary. IOH>–5 mA
Fluorescent Fluorescent display tube grid electrode drive output.
45 to 60
COM1-16
O
tube grid
Directly connected to fluorescent display tube and a pull-down
electrode
resistor is not necessary. IOH>–30 mA
Fluorescent Fluorescent display tube grid electrode drive output.
1 to 8
73 to 76
64
AD1-8
P1-4
VDD
O
O
tube grid
Directly connected to fluorescent display tube and a pull-down
electrode
resistor is not necessary. IOH>–10 mA
LED drive
General port output.
control
Output of these pins in static mode, so control for LED driving is
terminals
performed through these pins.
—
Power
VDD-GND are power supplies for internal logic.
supply
VDISP-VFL are power supplies for driving fluorescent tubes.
9, 63, 78
VDISP1-3
—
72
GND
—
Use the same power supply for VDD and VDISP.
61, 80
VFL1-2
—
Apply VFL after VDD and VDISP are applied.
67
DA
I
66
65
CP
CS
I
I
Micro-
Serial data input (positive logic).
controller
Input from LSB.
Micro-
Shift clock input.
controller
Serial data is shifted on the rising edge of CP.
Micro-
Chip select input.
controller
"H" disables serial data transfer.
Display blink frequency input (square wave).
Only the position specified by the display blink position set command
68
BLINK
I
Microcontroller
is validated.
The time of "High" (light ON) and "Low" (light OFF) level of the signal
frequency to be input to BLINK is the blink time.
Fix BLINK pin to the VDD or GND pin when the display blink control
is not used.
5/34
¡ Semiconductor
Pin
Symbol
MSM9200-xx
Type Connects to:
Description
Reset input (pull-up resistor included).
"Low" initializes all the functions.
Initial status is as follows.
Micro69
RESET
I
• Address of each RAM
address "00"H
• Data of each RAM
Content is undefined
• Display digit
16 digits
controller • Contrast adjusment
or
C2, R2
0/16
• Display blink
Blinking is disabled for all outputs
• All lights ON or OFF
OFF mode
• All outputs
"Low" level
RESET
(Circuit when R and C are
connected externally)
C2
R2
See Application Circuit.
External RC pin for RC oscillation.
71
OSC0
Connect R and C externally. The RC time constant depends on the
I
C1, R1
VDD voltage used. Set the target oscillation frequency to 2 MHz.
OSC0
70
OSC1
O
(RC oscillation circuit)
R1
OSC1
C1
See Application Circuit.
6/34
¡ Semiconductor
MSM9200-xx
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Rating
Unit
VDD
(*1)
–0.3 to 6.5
V
VDISP
(*1)
–0.3 to 6.5
V
Supply Voltage 2
VFL
—
–80 to VDISP+0.3
V
Input Voltage
VIN
—
–80 to VDD+0.3
V
Power Dissipation
PD
Ta£25°C
565
mW
TSTG
—
–55 to 150
°C
IO1
COM1-COM16
–40 to 0.0
IO2
AD1-AD8
–20 to 0.0
IO3
SEG1-SEG35
–10 to 0.0
IO4
P1-P4
–4.0 to 4.0
Supply Voltage 1
Storage Temperature
Output Current
mA
*1 Use the same power supply for VDD and VDISP.
RECOMMENDED OPERATING CONDITIONS-1
When the power supply voltage is 5V (typ).
Parameter
Supply Voltage 1
Symbol
VDD
VDISP
Condition
Min.
Typ.
Max.
Unit
—
4.5
5.0
5.5
V
—
–60
—
–20
V
—
—
V
—
0.3VDD
V
Supply Voltage 2
VFL
High Level Input Voltage
VIH
All input pins excluding OSC0 pin 0.7VDD
Low Level Input Voltage
VIL
All input pins excluding OSC0 pin
CP Frequency
—
fC
—
—
—
1.0
MHz
fOSC
R1=3.3kW, C1=47pF
1.5
2.0
2.5
MHz
Frame Frequency
fFR
DIGIT=1–16, R1=3.3kW, C1=47pF
183
244
305
Hz
RESET Input Time
tRSON
R2=1.0kW, C2=0.1PF
0
—
200
µs
TOP
—
–40
—
85
°C
Oscillation Frequency
Operating Temperature
7/34
¡ Semiconductor
MSM9200-xx
RECOMMENDED OPERATING CONDITIONS-2
When the power supply voltage is 3.3V (typ).
Parameter
Supply Voltage 1
Symbol
VDD
VDISP
Condition
Min.
Typ.
Max.
Unit
—
3.0
3.3
3.6
V
—
–60
—
–20
V
—
—
V
—
0.2VDD
V
Supply Voltage 2
VFL
High Level Input Voltage
VIH
All input pins excluding OSC0 pin 0.8VDD
Low Level Input Voltage
VIL
All input pins excluding OSC0 pin
CP Frequency
—
fC
—
—
—
1.0
MHz
fOSC
R1=3.3kW, C1=39pF
1.5
2.0
2.5
MHz
Frame Frequency
fFR
DIGIT=1–16, R1=3.3kW, C1=39pF
183
244
305
Hz
RESET Input Time
tRSON
R2=1.0kW, C2=0.1µF
0
—
200
µs
TOP
—
–40
—
85
°C
Oscillation Frequency
Operating Temperature
8/34
¡ Semiconductor
MSM9200-xx
ELECTRICAL CHARACTERISTICS
DC Characteristics-1
(VDD=VDISP=5.0V±10%, VFL=–60V, Ta=–40 to +85°C, unless otherwise specified)
Parameter
Symbol
Applied pin
CS, CP, BLINK,
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
High Level Input Current
IIH
Low Level Input Current
IIL
DA, RESET
DA, RESET
CS, CP, BLINK,
DA, RESET
CS, CP, BLINK,
DA, RESET
CS, CP, BLINK,
Condition
Min.
Max.
Unit
—
0.7VDD
—
V
—
—
0.3VDD
V
VIH=VDD
–1.0
1.0
µA
VIL=0.0V
–1.0
1.0
µA
VOH1
COM1-16
IOH1=–30mA
VDISP–1.5
—
V
High Level Output
VOH2
AD1-8
IOH2=–10mA
VDISP–1.5
—
V
Voltage
VOH3
SEG1-35
IOH3=–5mA
VDISP–1.5
—
V
VOH4
P1-4
IOH4=–2mA
VDD–1.0
—
V
—
—
VFL+1.0
V
IOL1=2mA
—
1.0
V
—
4
mA
—
3
mA
COM1-16
Low Level Output
VOL1
AD1-8
SEG1-35
Voltage
VOL2
P1-4
Duty=15/16
IDD1
fOSC=
VDD, VDISP
Current Consumption
IDD2
2MHz
no load
Digit=1–16
All output lights ON
Duty=8/16
Digit=1–9
All output lights OFF
9/34
¡ Semiconductor
MSM9200-xx
DC Characteristics-2
(VDD=VDISP=3.3V±10%, VFL=–60V, Ta=–40 to +85°C, unless otherwise specified)
Parameter
Symbol
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
High Level Input Current
IIH
Low Level Input Current
IIL
Applied pin
CS, CP, BLINK,
DA, RESET
CS, CP, BLINK,
DA, RESET
CS, CP, BLINK,
DA, RESET
CS, CP, BLINK,
DA, RESET
Condition
Min.
Max.
Unit
—
0.8VDD
—
V
—
0.0
0.2VDD
V
VIH=VDD
–1.0
1.0
µA
VIL=0.0V
–1.0
1.0
µA
VOH1
COM1-16
IOH1=–30mA
VDISP–1.5
—
V
High Level Output
VOH2
AD1-8
IOH2=–10mA
VDISP–1.5
—
V
Voltage
VOH3
SEG1-35
IOH3=–5mA
VDISP–1.5
—
V
VOH4
P1-4
IOH4=–1mA
VDD–1.0
—
V
—
—
VFL+1.0
V
IOL1=1mA
—
1.0
V
—
3
mA
—
2
mA
COM1-16
Low Level Output
VOL1
AD1-8
SEG1-35
Voltage
VOL2
P1-4
Duty=15/16
IDD1
fOSC=
VDD, VDISP
Current Consumption
IDD2
2MHz
no load
Digit=1–16
All output lights ON
Duty=8/16
Digit=1–9
All output lights OFF
10/34
¡ Semiconductor
MSM9200-xx
AC Characteristics-1
(VDD, VDISP=5.0V±10%, VFL=–60V, Ta=–40 to +85°C, unless otherwise specified)
Parameter
CP Frequncy
Symbol
Condition
Min.
Max.
Unit
fC
—
—
1.0
MHz
CP Pulse Width
tCW
—
300
—
ns
DA Setup Time
tDS
—
300
—
ns
DA Hold Time
tDH
—
300
—
ns
CS Setup Time
tCSS
—
300
—
ns
CS Hold Time
tCSH
R1=3.3kW, C1=47PF
16
—
ms
CS Wait Time
tCSW
—
300
—
ns
Data Processing Time
tDOFF
R1=3.3kW, C1=47PF
8
—
ms
RESET Pulse Width
tRSON
When RESET signal is input externally
300
—
ns
Waite DA Time
tRSOFF
—
All Output Slow Rate
tR
Cl=100pF
300
—
ms
tR=20% to 80%
—
4.0
ms
tF=80% to 20%
—
4.0
ms
VDD Rise Time
tPRZ
When mounted in the unit
—
100
ms
VDD Off Time
tPOF
When mounted in the unit, VDD=0.0V
5.0
—
ms
tF
AC Characteristics-2
(VDD, VDISP=3.3V±10%, VFL=–60V, Ta=–40 to +85°C, unless otherwise specified)
Parameter
CP Frequncy
Symbol
Condition
Min.
Max.
Unit
fC
—
—
1.0
MHz
tCW
—
300
—
ns
DA Setup Time
tDS
—
300
—
ns
DA Hold Time
tDH
—
300
—
ns
CP Pulse Width
CS Setup Time
tCSS
—
300
—
ns
CS Hold Time
tCSH
R1=3.3kW, C1=39PF
16
—
ms
CS Wait Time
tCSW
—
300
—
ns
Data Processing Time
tDOFF
R1=3.3kW, C1=39PF
8
—
ms
RESET Pulse Width
tWRES
When RESET signal is input externally
300
—
ns
DA Wait Time
tRSOFF
—
300
—
ms
—
4.0
ms
All Output Slew Rate
tR
Cl=100pF
tR=20% to 80%
—
4.0
ms
VDD Rise Time
tPRZ
When mounted in the unit
—
100
ms
VDD Off Time
tPOF
When mounted in the unit, VDD=0.0V
5.0
—
ms
tF
tF=80% to 20%
11/34
¡ Semiconductor
MSM9200-xx
TIMING DIAGRAM
• Data Timing
tCSS
tCSW
CS
tC
tDOFF
CP
VIH
VIL
tCSH
fC
tCW tCW
VIH
VIL
tDH
tDS
DA
VALID
VALID
VALID
VIH
VIL
VALID
• Reset Timing
VDD
tPRZ
tRSON
When input externally
tWRES
tRSOFF
=
RESET
tOF
When external
R and C are
connected.
tRSOFF
DA
0.8 VDD
0.0 V
VIH
0.5 VDD
VIL
VIH
VIL
• Output Timing
tR
All outputs
tF
0.8 VDISP
0.2 VFL
Symbol
VDD=3.3V±10%
VDD=5.0V±10%
VIH
0.8 VDD
0.7 VDD
VIL
0.2 VDD
0.3 VDD
12/34
¡ Semiconductor
MSM9200-xx
FUNCTIONAL DESCRIPTION
Command List
1st byte
LSB
B1
B2
B3
B4
B5
B6
B7
B0
B1
B2
B3
B4
B5
B6
B7
1 DCRAM data write 1
X0
X1
X2
X3
1
0
0
0
C0
C1
C2
C3
C4
C5
C6
C7
2 DCRAM data write 2
X0
X1
X2
X3
0
1
0
0
C0
C1
C2
C3
C4
C5
C6
C7
3 DCRAM data write 3
X0
X1
X2
X3
1
1
0
0
C0
C1
C2
C3
C4
C5
C6
C7
4 DCRAM data write 4
X0
X1
X2
X3
0
0
1
0
C0
C1
C2
C3
C4
C5
C6
C7
C0
C5 C10 C15 C20 C25 C30
C1
C6 C11 C16 C21 C26 C31
C2
C7 C12 C17 C22 C27 C32
C3
C8 C13 C18 C23 C28 C33
C4
C9 C14 C19 C24 C29 C34
C0
C5 C10 C15 C20 C25 C30
C1
C6 C11 C16 C21 C26 C31
C2
C7 C12 C17 C22 C27 C32
C3
C8 C13 C18 C23 C28 C33
C4
C9 C14 C19 C24 C29 C34
*
*
*
*
*
*
*
*
*
*
C0
C1
C2
C3
C4
C5
C6
C7
G1
G2
G3
G4
G5
G6
G7
G8 2nd byte
5 CGRAM data write 1
6 CGRAM data write 2
7 ADRAM data write
LSB
2nd byte
MSB
B0
Command
X0
X0
X1
X1
X2
X2
X3
X3
1
0
0
1
1
1
0
0
X0
X1
X2
X3
1
1
1
0
SG
AD
*
*
0
0
0
1
9 DCRAM address shift
S
*
*
0
0
1
*
*
*
1
A DCRAM address reset
*
*
0
1
0
1
8
Display blink position
set
B General output port set P1
P2
P3
P4
1
1
0
1
C Display duty set
D0
D1
D2
D3
0
0
1
1
D Number of digits set
K0
K1
K2
K3
1
0
1
1
E All lights ON/OFF
L
H
*
*
0
1
1
1
Test mode
When data is written to RAM (DCRAM, CGRAM, ADRAM) continuously,
addresses are internally incremented automatically.
Therefore it is not necessary to specify the 1st byte to write RAM data
for the 2nd and later bytes.
MSB
2nd byte
3rd byte
4th byte
5th byte
6th byte
2nd byte
3rd byte
4th byte
5th byte
6th byte
G9 G10 G11 G12 G13 G14 G15 G16 3rd byte
*
Xn
Cn
SG
AD
Gn
S
Pn
Dn
Kn
H
L
:
:
:
:
:
:
:
:
:
:
:
:
Don't care
Address specification for each RAM
Character code specification for each RAM
SEG display area specification
AD display area specification
Display blink position specification
Left and right display shift specification
General output port status specification
Display duty specification
Number of digits specification
All lights ON instruction
All lights OFF instruction
Note: The test mode is used for inspection before shipment.
It is not a user function.
13/34
¡ Semiconductor
MSM9200-xx
Positional Relationship Between SEGn and ADn (one digit)
CGRAM written data. Corresponds to 2nd byte
CGRAM written data. Corresponds to 3rd byte
CGRAM written data. Corresponds to 4th byte
C0
C1
C2
C3
AD1
AD2
AD3
AD4
C4
C5
C6
C7
AD5
AD6
AD7
AD8
Area for the ADRAM data to
be output
C0
C1
C2
C3
C4
SEG1
SEG2
SEG3
SEG4
SEG5
C5
C6
C7
C8
C9
SEG6
SEG7
SEG8
SEG9
SEG10
C10
C11
C12
C13
C14
SEG11
SEG12
SEG13
SEG14
SEG15
C15
C16
C17
C18
C19
SEG16
SEG17
SEG18
SEG19
SEG20
C20
C21
C22
C23
C24
SEG21
SEG22
SEG23
SEG24
SEG25
C25
C26
C27
C28
C29
SEG26
SEG27
SEG28
SEG29
SEG30
C30
C31
C32
C33
C34
SEG31
SEG32
SEG33
SEG34
SEG35
CGRAM written data. Corresponds to 6th byte
CGRAM written data. Corresponds to 5th byte
14/34
¡ Semiconductor
MSM9200-xx
Data Transfer System and Command Write System
Display control command and data are written by an 8-bit serial transfer.
Write timing is shown in the figure below.
Setting the CS pin to "Low" level enables a data transfer.
Data is 8 bits and is sequentially input into the DA pin from LSB (LSB first).
As shown in the figure below, data is read by the shift register at the rising edge of the shift clock,
which is input into the CP pin. If 8-bit data is input, internal load signals are automatically
generated and data is written to each register and RAM.
Therefore it is not necessary to input load signals from the outside.
Setting the CS pin to "High" disables data transfer. Data input from the point when the CS pin
changes from "High" to "Low" is recognized in 8-bit units.
tDOFF
CS
tCSH
CP
DA
B0 B1 B2 B3 B4 B5 B6 B7
B0 B1 B2 B3 B4 B5 B6 B7
B0 B1 B2 B3 B4 B5 B6 B7
LSB
LSB
LSB
1st byte
MSB
When data is written to DCRAM* Command and address data
*
2nd byte
MSB
Character code data
2nd byte
MSB
Character code data of the
next address
When data is written to RAM (DCRAM, ADRAM, CGRAM) continuously, addresses are
internally incremented automatically.
Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd and later
bytes.
Reset Function
Reset is executed when the RESET pin is set to "L", (when turning power on, for example,) and
initializes all functions.
Initial status is as follows.
• Address of each RAM .................. address "00"H
• Data of each RAM ........................ All contents are undefined
• Display blink ................................. Blinking is disabled for all outputs
• General output port ..................... All general output ports go "Low"
• Display digit .................................. 16 digits
• Contrast adjustment ..................... 0/16
• All display lights ON or OFF ..... OFF mode
• Segment output ............................ All segment outputs go "Low"
• AD output ..................................... All AD outputs go "Low"
Reset again according to "Initial Setting Flowchart" after reset.
15/34
¡ Semiconductor
MSM9200-xx
Description of Commands and Functions
1. DCRAM data write 1
(Specifies the address (00H to 0FH) of DCRAM and writes the character code of CGROM and
CGRAM.)
2. DCRAM data write 2
(Specifies the address (10H to 1FH) of DCRAM and writes the character code of CGROM and
CGRAM.)
3. DCRAM data write 3
(Specifies the address (20H to 2FH) of DCRAM and writes the character code of CGROM and
CGRAM.)
4. DCRAM data write 4
(Specifies the address (30H to 3FH) of DCRAM and writes the character code of CGROM and
CGRAM.)
DCRAM (Data Control RAM) has a 6-bit address to store character code of CGROM and
CGRAM. (4 bits can be set by the user and the 2 bits on the MSB side are automatically set.)
The character code specified by DCRAM is converted to a 5¥7 dot matrix character pattern via
CGROM or CGRAM.
The capacity is 64¥8 bits, which can store 64 characters.
Note: The addresses 00H to 3FH of DCRAM are automatically incremented.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
(1st)
X0 X1 X2 X3
LSB
1
0
0
0
MSB
: selects DCRAM data write mode and specifies DCRAM
address
(Ex: Specifies DCRAM address 00H)
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(2nd)
C0 C1 C2 C3 C4 C5 C6 C7
: specifies character code of CGROM and CGRAM
: written into DCRAM address 00H
To specify the character code of CGROM and CGRAM continuously to the next address, specify
only character code as follows.
The addresses of DCRAM are automatically incremented. Specification of an address is
unnecessary.
16/34
¡ Semiconductor
MSM9200-xx
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(3rd)
C0 C1 C2 C3 C4 C5 C6 C7
LSB
: specifies character code of CGROM and CGRAM
: written into DCRAM address 01H
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(4th)
C0 C1 C2 C3 C4 C5 C6 C7
LSB
: specifies character code of CGROM and CGRAM
: written into DCRAM address 02H
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(17th)
C0 C1 C2 C3 C4 C5 C6 C7
LSB
: specifies character code of CGROM and CGRAM
: written into DCRAM address 0FH
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(18th)
C0 C1 C2 C3 C4 C5 C6 C7
LSB
: specifies character code of CGROM and CGRAM
: written into DCRAM address 10H
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(65th)
C0 C1 C2 C3 C4 C5 C6 C7
LSB
: specifies character code of CGROM and CGRAM
: written into DCRAM address 3FH
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(66th)
C0 C1 C2 C3 C4 C5 C6 C7
: specifies character code of CGROM and CGRAM
: DCRAM address 00H is rewritten
X0 (LSB) to X3 (MSB): DCRAM addresses (4 bits: 16 characters)
Note: A total of 64 characters for the four specifications
C0 (LSB) to C7 (MSB): Character code of CGROM and CGRAM (8 bits: 256 character)
[COM positions and set DCRAM addresses]
The states when RESET is input and DCRAM address reset commands are executed
Command
No.
HEX K0 K1 K2 K3
COM
Command
position
No.
HEX K0 K1 K2 K3
00
0
0
0
0
COM1
20
0
0
0
0
01
1
0
0
0
COM2
21
1
0
0
0
2E
1
1
1
1
1
COM
position
3
0E
1
1
1
1
COM15
COM16
0F
1
1
1
1
2F
1
1
1
1
10
0
0
0
0
30
0
0
0
0
11
1
0
0
0
31
1
0
0
0
2
4
1E
0
1
1
1
3E
0
1
1
1
1F
1
1
1
1
3F
1
1
1
1
17/34
¡ Semiconductor
MSM9200-xx
5. CGRAM data write 1
(Specifies the addresses 00H to 0FH of CGRAM and writes character pattern data.)
6. CGRAM data write 2
(Specifies the addresses 10H to 1FH of CGRAM and writes character pattern data.)
CGRAM (Character Generator RAM) has a 5-bit address to store 5¥7 dot matrix character
patterns. (4 bits can be set by the user and the 1 bit on the MSB is automatically set.)
A character pattern stored in CGRAM can be displayed by specifying the character code
(address) by DCRAM.
The address of CGRAM is assigned to 00H to 1FH. (All the other addresses are the CGROM
addresses.)
Capacity is (16¥2)¥35¥8 bits, which can store 32 types of character patterns.
Note: The addresses 00H to 1FH of CGRAM are automatically incremented.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
(1st)
X0 X1 X2 X3
1
0
1
LSB
0
MSB
: selects CGRAM data write mode and specifies
CGRAM address.
(Ex: specifies CGRAM address 00H)
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(2nd)
C0 C5 C10 C15 C20 C25 C30
LSB
*
: specifies 1st column data
: rewritten into CGRAM address 00H
MSB
B0 B1 B2 B3 B4 B5 B6 B7
3rd byte
(3rd)
C1 C6 C11 C16 C21 C26 C31
LSB
*
: specifies 2nd column data
: rewritten into CGRAM address 00H
MSB
B0 B1 B2 B3 B4 B5 B6 B7
4th byte
(4th)
C2 C7 C12 C17 C22 C27 C32
LSB
*
: specifies 3rd column data
: rewritten into CGRAM address 00H
MSB
B0 B1 B2 B3 B4 B5 B6 B7
5th byte
(5th)
C3 C8 C13 C18 C23 C28 C33
LSB
*
: specifies 4th column data
: rewritten into CGRAM address 00H
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(6th)
C4 C9 C14 C19 C24 C29 C34
*
: specifies 5th column data
: rewritten into CGRAM address 00H
To specify character pattern data continuously to the next address, specify only character pattern
data as follows.
The addresses of CGRAM are automatically incremented. Specification of an address is
therefore unnecessary.
The 2nd to 6th byte (character pattern data) are regarded as one data item, so 300 ns is sufficient
for tDOFF time between bytes.
18/34
¡ Semiconductor
LSB
MSM9200-xx
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(7th)
C0 C5 C10 C15 C20 C25 C30
LSB
*
: specifies 1st column data
: rewritten into CGRAM address 01H
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(11th)
C4 C9 C14 C19 C24 C29 C34
LSB
*
MSB
: specifies 5th column data
: rewritten into CGRAM address 01H
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(12th)
C0 C5 C10 C15 C20 C25 C30
LSB
*
: specifies 1st column data
: rewritten into CGRAM address 02H
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(16th)
C4 C9 C14 C19 C24 C29 C34
LSB
*
: specifies 5th column data
: rewritten into CGRAM address 02H
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(77th)
C0 C5 C10 C15 C20 C25 C30
LSB
*
: specifies 1st column data
: rewritten into CGRAM address 0FH
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(81th)
C4 C9 C14 C19 C24 C29 C34
LSB
*
MSB
: specifies 5th column data
: rewritten into CGRAM address 0FH
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(82th)
C0 C5 C10 C15 C20 C25 C30
LSB
*
: specifies 1st column data
: rewritten into CGRAM address 10H
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(86th)
C4 C9 C14 C19 C24 C29 C34
LSB
*
: specifies 5th column data
: rewritten into CGRAM address 10H
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(157th)
C0 C5 C10 C15 C20 C25 C30
LSB
*
: specifies 1st column data
: rewritten into CGRAM address 1FH
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(161th)
C4 C9 C14 C19 C24 C29 C34
LSB
*
MSB
: specifies 5th column data
: rewritten into CGRAM address 1FH
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(162th)
C0 C5 C10 C15 C20 C25 C30
LSB
*
: specifies 1st column data
(CGRAM address 00H is rewritten)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(167th)
C4 C9 C14 C19 C24 C29 C34
*
: specifies 5th column data
(CGRAM address 00H is rewritten)
X0 (LSB) to X3 (MSB): CGRAM addresses (4 bits: 16 characters)
Note: A total of 32 characters for the two specifications.
C0 (LSB) to C34 (MSB): Character pattern data (35 bits: 35 outputs per digit)
19/34
¡ Semiconductor
MSM9200-xx
Positional relationship between the output area of CGROM and that of CGRAM
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
area that corresponds to 2nd byte (1st column)
area that corresponds to 3rd byte (2nd column)
area that corresponds to 6th byte (5th column)
area that corresponds to 5th byte (4th column)
area that corresponds to 4th byte (3rd column)
Note: CGROM (Character Generator ROM) has an 8-bit address to generate 5¥7 dot matrix
character patterns.
The capacity is 224¥35¥8 bits, which can store 224 types of character patterns.
2 types of general-purpose code are availble (see ROM CODE list) and custom codes are
provided on customer's request.
[CGROM addresses and set CGRAM addresses]
Refer to ROMCODE table
Command
No.
2
HEX K0 K1 K2 K3
CGROM
Command
address
No.
HEX K0 K1 K2 K3
CGROM
address
00
0
0
0
0
RAM00(00000000B)
10
0
0
0
0
RAM10(00010000B)
01
1
0
0
0
RAM01(00000001B)
11
1
0
0
0
RAM11(00010001B)
02
0
1
0
0
RAM02(00000010B)
12
0
1
0
0
RAM12(00010010B)
03
1
1
0
0
RAM03(00000011B)
13
1
1
0
0
RAM13(00010011B)
04
0
0
1
0
RAM04(00000100B)
14
0
0
1
0
RAM14(00010100B)
05
1
0
1
0
RAM05(00000101B)
15
1
0
1
0
RAM15(00010101B)
06
0
1
1
0
RAM06(00000110B)
16
0
1
1
0
RAM16(00010110B)
07
1
1
1
0
RAM07(00000111B)
17
1
1
1
0
RAM17(00010011B)
08
0
0
0
1
RAM08(00001000B)
18
0
0
0
1
RAM18(00011000B)
09
1
0
0
1
RAM09(00001001B)
19
1
0
0
1
RAM19(00011001B)
0A
0
1
0
1 RAM0A(00001010B)
1A
0
1
0
1 RAM1A(00011010B)
4
0B
1
1
0
1 RAM0B(00001011B)
1B
1
1
0
1 RAM1B(00011011B)
0C
0
0
1
1 RAM0C(00001100B)
1C
0
0
1
1 RAM1C(00011100B)
0D
1
0
1
1 RAM0D(00001101B)
1D
1
0
1
1 RAM1D(00011101B)
0E
0
1
1
1
RAM0E(00001110B)
1E
0
1
1
1
RAM1E(00011110B)
0F
1
1
1
1
RAM0F(00001111B)
1F
1
1
1
1
RAM1F(00011111B)
20/34
¡ Semiconductor
MSM9200-xx
7. ADRAM data write
(specifies address of ADRAM and writes symbol data)
ADRAM (Additional Data RAM) has a 4-bit address to store symbol data.
Symbol data specified by ADRAM is directly output without CGROM and CGRAM.
The capacity is 8¥16 bits, which can store 8 types of symbol patterns for each digit.
The terminal to which the contents of ADRAM are output can be used as a cursor.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
(1st)
X0 X1 X2 X3
LSB
1
1
1
0
MSB
: selects ADRAM data write mode and specifies ADRAM
address
(Ex: specifies ADRAM address 0H)
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(2nd)
C0 C1 C2 C3 C4 C5 C6 C7
: sets symbol data
(written into ADRAM address 0H)
To specify symbol data continuously to the next address, specify only symbol data as follows.
The address of ADRAM is automatically incremented. Specification of addresses is therefore
unnecessary.
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(3rd)
C0 C1 C2 C3 C4 C5 C6 C7
LSB
MSB
: sets symbol data
(written into ADRAM address 1H)
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(4th)
C0 C1 C2 C3 C4 C5 C6 C7
LSB
: sets symbol data
(written into ADRAM address 2H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(17th)
C0 C1 C2 C3 C4 C5 C6 C7
LSB
MSB
: sets symbol data
(written into ADRAM address FH)
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(18th)
C0 C1 C2 C3 C4 C5 C6 C7
: sets symbol data
(ADRAM address 00H is rewritten.)
X0 (LSB) to X3 (MSB): ADRAM addresses (4 bits: 16 characters)
C0 (LSB) to C7 (MSB): Symbol data (8-symbol data per digit)
21/34
¡ Semiconductor
MSM9200-xx
[COM positions and ADRAM addresses]
HEX D0 D1 D2 D3
COM position
HEX D0 D1 D2 D3
COM position
0
0
0
0
0
COM1
8
0
0
0
1
COM9
1
1
0
0
0
COM2
9
1
0
0
1
COM10
2
0
1
0
0
COM3
A
0
1
0
1
COM11
3
1
1
1
0
COM4
B
1
1
0
1
COM12
4
0
0
1
0
COM5
C
0
0
1
1
COM13
5
1
0
1
0
COM6
D
1
0
1
1
COM14
6
0
1
1
0
COM7
E
0
1
1
1
COM15
7
1
1
1
0
COM8
F
1
1
1
1
COM16
8. Display blink position set
(sets the blink position for the SEG area or AD area in COMn.
Display blink position can be set separately for the SEG area and AD area. In this case, select
by command in which COMn the SEG area or AD area is made blink.
The blink disabled state is entered for this setting when power is turned on or when a RESET
signal is input. The display blink cycle is determined by the frequency to be input to the
BLINK pin.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
(1st)
SG AD
LSB
* *
0
0
0
1
: selects either the AD output area or the segment
output area and specifies digit
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(2nd)
G1 G2 G3 G4 G5 G6 G7 G8
LSB
: specifies blink position to COM1 to COM8
MSB
B0 B1 B2 B3 B4 B5 B6 B7
3rd byte
(3rd)
G9 G10 G11 G12 G13 G14 G15 G16
: specifies blink position to COM9 to COM16
The 2nd and 3rd bytes (COM1 to COM16 position specification) are regarded as one data item,
so 300 ns is sufficient for tDOFF time between bytes.
SG: Specifies SEG area
AD: Specifies AD area
Gn: Specifies blinks
22/34
¡ Semiconductor
MSM9200-xx
[SEG and AD display and set data]
SG/AD
Gn
0
0
Does not blink (current state)
0
1
Does not bilnk (current state)
1
0
Specified positions do not blink
1
1
Specified positions blink
SEG and AD display
(The state when power is applied or when RESET is input)
Note: If both SG and AD are set to "1" by command, both the SEG area and the AD area are
specified.
9. DCRAM address shift
(Shifts SEG output left or right.)
DCRAM address shift shifts SEG output 1 digit to the left or right using 1 bit data. AD output
cannot be shifted.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
SG
* * *
1
0
0
1
: selects DCRAM address shift and sets shift
value (left, right)
S: Specifies the direction of shift
[Set data and shift direction of display]
S
Shift direction of display
0
Shift to left
1
Shift to right
23/34
¡ Semiconductor
MSM9200-xx
[DCRAM address shift and COM positions]
When S=0 (shift to left) is performed from the initial state.
Command
No.
HEX K0 K1 K2 K3
COM
Command
position
No.
HEX K0 K1 K2 K3
00
0
0
0
0
COM2
20
0
0
0
0
01
1
0
0
0
COM3
21
1
0
0
0
1
COM
position
3
0E
0
1
1
1
2E
0
1
1
1
0F
1
1
1
1
COM16
2F
1
1
1
1
10
0
0
0
0
30
0
0
0
0
11
1
0
0
0
31
1
0
0
0
2
4
1E
0
1
1
1
3E
0
1
1
1
1F
1
1
1
1
3F
1
1
1
1
COM1
When S=1 (shift to right) is performed from the initial state.
Command
No.
HEX K0 K1 K2 K3
00
0
0
0
0
01
1
0
0
0
COM
Command
position
No.
COM1
1
HEX K0 K1 K2 K3
20
0
0
0
0
21
1
0
0
0
COM
position
3
0E
0
1
1
1
COM14
2E
0
1
1
1
0F
1
1
1
1
COM15
2F
1
1
1
1
10
0
0
0
0
COM16
30
0
0
0
0
11
1
0
0
0
31
1
0
0
0
2
4
1E
0
1
1
1
3E
0
1
1
1
1F
1
1
1
1
3F
1
1
1
1
24/34
¡ Semiconductor
MSM9200-xx
A. DCRAM address reset
(returns display status to initial setting status)
The DCRAM address reset returns the status where a DCRAM address shift is executed to
initial status.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
* * * *
0
1
0
: selects DCRAM address reset
1
Relation between the DCRAM address shifts and the COM outputs
Initial status or the status where display address reset executed (DCRAM address is 00H)
COM output
1
DCRAM address (HEX)
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
When left shift is executed in the initial status
COM output
1
DCRAM address (HEX)
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
3F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E
When right shift is executed in the initial status
COM output
1
DCRAM address (HEX)
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
B. General output port set
(specifies the general output port status)
The general output port is an output for 4-bit static operation.
It is used to control other I/O devices and turn on LED.
When at the "High" level, this output becomes the VDD voltage, and when at the "Low" level,
it becomes the ground potential. Therefore, the fluorescent display tube cannot be driven.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
P1 P2 P3 P4
1
1
0
1
: selects a general output port and specifies
the output status
P1-P4: general output port
[Set data and set state of general output port]
Pn
Display state of general output port
0
Sets to the output to Low
1
Sets to the output to High
(The state when power is applied or when RESET is input.)
25/34
¡ Semiconductor
MSM9200-xx
C. Display duty set
(writes display duty value to duty cycle register)
Display duty adjusts contrast in 16 stages using 4-bit data.
When power is turned on or when the RESET signal is input, the duty cycle register value is
"0". Always execute this instruction before turning the display on, then set a desired duty
value.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
D0 D1 D2 D3
0
0
1
1
: selects display duty set mode and sets duty value
D0 (LSB) to D3 (MSB): display duty data (4 bits: 16 stages)
[Relation between setup data and controlled COM duty]
HEX
*
D3
D2
D1
D0
COM duty
HEX
D3
D2
D1
D0
COM duty
* 0
0
0
0
0
0/16
8
1
0
0
0
8/16
1
0
0
0
1
1/16
9
1
0
0
1
9/16
2
0
0
1
0
2/16
A
1
0
1
0
10/16
3
0
0
1
1
3/16
B
1
0
1
1
11/16
4
0
1
0
0
4/16
C
1
1
0
0
12/16
5
0
1
0
1
5/16
D
1
1
0
1
13/16
6
0
1
1
0
6/16
E
1
1
1
0
14/16
7
0
1
1
1
7/16
F
1
1
1
1
15/16
The state when powered on or when RESET signal inputs.
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¡ Semiconductor
MSM9200-xx
D. Number of digits set
(writes the number of display digits to the display digit register)
The number of digits set can display a maximum of 16 digits using 4-bit data.
When power is turned on or when a RESET signal is input, the number of digit register value
is "0". Always execute this instruction to change the number of digits before turning the
dispaly on.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
K0 K1 K2 K3
1
0
1
1
: selects the number of digit set mode and specifies
the number of digit value
K0 (LSB) to K3 (MSB): number of digit data (4 bits: 16 digits)
[Relation between setup data and controlled COM]
HEX
K3
K2
K1
K0
0
0
0
0
0
1
0
0
0
1
2
0
0
1
3
0
0
1
4
0
1
5
0
1
6
0
7
0
Number of digits
Number of digits
HEX
K3
K2
K1
K0
COM1-16
8
1
0
0
0
COM1-8
COM1-1
9
1
0
0
1
COM1-9
0
COM1-2
A
1
0
1
0
COM1-10
1
COM1-3
B
1
0
1
1
COM1-11
0
0
COM1-4
C
1
1
0
0
COM1-12
0
1
COM1-5
D
1
1
0
1
COM1-13
1
1
0
COM1-6
E
1
1
1
0
COM1-14
1
1
1
COM1-7
F
1
1
1
1
COM1-15
of COM
of COM
E. All display lights ON/OFF set
(turns all dispaly lights ON or OFF)
All display lights ON is used primarily for display testing.
All display lights OFF is primarily used to prevent malfunction when power is turned on.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
L
H
* *
0
1
1
1
: selects all display lights ON or OFF mode and
sets all lights ON or OFF value
[Set data and display state of SEG and AD]
L
H
0
0
All outputs maintain current states
1
0
Sets all outputs to Low
0
1
Sets all outputs to High
1
1
Sets all outputs to High
Display state of SEG and AD
(The state when power is applied or when RESET is input.)
(All lights ON mode has priority.)
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¡ Semiconductor
MSM9200-xx
Initial Setting Flowchart
Apply VFL
All display lights OFF
Status of all outputs by RESET
signal input
General output port set
Number of digits set
Display duty set
Select a RAM to be used
DCRAM
CGRAM
ADRAM
Data write mode
Data write mode
Data write mode
(with address set)
(with address set)
(with address set)
Address is automatically
incremented
Address is automatically
incremented
DCRAM
Character code
NO
DCRAM
Is character code
write ended?
Address is automatically
incremented
ADRAM
Character code
CGRAM
Character code
NO
YES
CGRAM
Is character code
write ended?
YES
YES
NO
ADRAM
Is character code
write ended?
YES
Another RAM to
be set?
Releases all display lights
OFF mode
Display operation mode
End
28/34
¡ Semiconductor
MSM9200-xx
APPLICATION CIRCUIT
Heater transformer
5¥7-dot matrix fluorescent display tube
ANODE
ANODE
GRID
(SEGMENT) (SEGMENT) (DIGIT)
8
R2
VDD
C2
VDD
C3
RESET VDD, AD1-8
VDISP1-3
MCU
Output port
GND
16
SEG1-35
COM1-16
R4
LED
MSM9200-xx
CS
CP
DA
BLINK
P1-4
GND VFL1-2
R3
VFL
VDD
35
OSC0 OSC1
R1
4
NPN Tr
GND
C1
C4
ZD
Notes: 1. The VDD value depends on the power supply voltage of the microcontroller used.
Adjust the values of the constants R1, R2, R4, C1, and C2 to the power supply voltage
used.
2. The VFL value depends on the fluorescent display tube used. Adjust the values of the
constants R3 and ZD to the power supply voltage used.
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¡ Semiconductor
MSM9200-xx
Reference data
The figure below shows the relationship between the VFL voltage and the output current of each
driver.
Take care that the total power consumtion to be used does not exceed the power dissipation.
[VFL Voltage-Output Current of Each Driver]
(mA)
–30
COM1 to COM16
(Condition: VOH=VDISP–1.5 V)
[Output Current] (mA)
–25
–20
–15
AD1 to AD8
(Condition: VOH=VDISP–1.5 V)
–10
SEG1 to SEG35
(Condition: VOH=VDISP–1.5 V)
–5
0
–10
–20
–30
–40
–50
–60 (V)
[VFL Voltage (VDD-n) ]
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¡ Semiconductor
MSM9200-xx
MSM9200-01 ROM Code
00000000B (00H) to 00011111B (1FH) are the CGRAM addresses.
MSB
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
LSB
0000 RAM00 RAM10
0001 RAM01 RAM11
0010 RAM02 RAM12
0011 RAM03 RAM13
0100 RAM04 RAM14
0101 RAM05 RAM15
0110 RAM06 RAM16
0111 RAM07 RAM17
1000 RAM08 RAM18
1001 RAM09 RAM19
1010 RAM0A RAM1A
1011 RAM0B RAM1B
1100 RAM0C RAM1C
1101 RAM0D RAM1D
1101 RAM0E RAM1E
1111 RAM0F RAM1F
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¡ Semiconductor
MSM9200-xx
MSM9200-02 ROM Code
00000000B (00H) to 00011111B (1FH) are the CGRAM addresses.
MSB
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
LSB
0000 RAM00 RAM10
0001 RAM01 RAM11
0010 RAM02 RAM12
0011 RAM03 RAM13
0100 RAM04 RAM14
0101 RAM05 RAM15
0110 RAM06 RAM16
0111 RAM07 RAM17
1000 RAM08 RAM18
1001 RAM09 RAM19
1010 RAM0A RAM1A
1011 RAM0B RAM1B
1100 RAM0C RAM1C
1101 RAM0D RAM1D
1101 RAM0E RAM1E
1111 RAM0F RAM1F
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¡ Semiconductor
MSM9200-xx
Digit Output Timing (for 16-digit display, at a duty of 15/16)
T=8/ fOSC
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
AD1-8
SEG1-35
Frame cycle
t1=1024T
Display timing t2=60T
Blank timing t3=4T
(t1=4.096 ms when fosc=2.0 MHz)
(t2=240 ms when fosc=2.0 MHz)
(t3=16 ms when fosc=2.0 MHz)
VDISP
VFL
VDISP
VFL
33/34
¡ Semiconductor
MSM9200-xx
PACKAGE DIMENSIONS
(Unit : mm)
QFP80-P-1414-0.65-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.85 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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