OKI ML9204-XX

OKI Semiconductor
ML9204-xx
PEDL9204-02
Issue Date: Oct. 12, 2004
Preliminary
5 × 7 Dot Character × 24-Digit × 2-Line Display Controller/Driver with Character RAM (Built-in Key Scan)
GENERAL DESCRIPTION
The ML9204-xx is a 5 × 7 dot matrix type vacuum fluorescent display tube controller driver IC which displays
characters, numerics and symbols of a maximum of 24 digits × 2 lines.
Dot matrix vacuum fluorescent display tube drive signals are generated by serial data sent from a
micro-controller. A display system is easily realized by internal ROM and RAM for character display.
Built-in key scan for 3-channel encoder type rotary switch and 5 × 6 matrix key switch allow the user to receive
each switch input.
The ML9204-xx has low power consumption since it is made by CMOS process technology.
–01 is available as a general-purpose code.
Custom codes are provided on customer’s request.
FEATURES
: 3.3 V±10% or 5.0 V±10%
• Logic power supply (VDD)
• VFD tube drive power supply (VSEG, VCOM ) : 20 to 60 V
• VFD driver output current
(VFD driver output can be connected directly to the VFD tube. No pull-down resistor is required.)
• Segment driver (SEGA1 to A35, SEGB1 to B35)
Only one driver output is high
: –5 mA (VSEG = 60 V)
All the driver outputs are high
: –350 mA (VSEG = 60 V)
• Segment driver (ADA, ADB)
: –15 mA (VSEG = 60 V)
• Grid driver (COM1 to 24)
: –25 mA (VCOM = 60 V)
• Content of display
SEGA1 to SEGA35 and ADA
• CGROM_A
: 5 × 7 dots 240 types (character data)
• CGRAM_A
: 5 × 7 dots 16 types (character data)
• ADRAM_A
: 24 (display digit)× 1 bit (symbol data; can be used for a cursor.)
• DCRAM_A
: 24 (display digit) × 8 bits (register for character data display)
SEGB1 to SEGB35 and ADB
• CGROM_B
: 5 × 7 dots 240 types (character data)
• CGRAM_B
: 5 × 7 dots 16 types (character data)
• ADRAM_B
: 24 (display digit)× 1 bit (symbol data; can be used for a cursor.)
• DCRAM_B
: 24 (display digit) × 8 bits (register for character data display)
• Display control function
• GCRAM
: Simultaneous output of COM1 to 24 can be set in 1 grid.
• Display digits
: 1 to 24 digits (9- to 24-bit arbitrary setting)
• Display duty (brightness adjustment)
: 0/1024 to 960/1024 stages
• All lights ON/OFF
• 5 interfaces with microcontroller:DI/O, CS, CP, RESET, INT
• Built-in key scan circuit for 5 × 6 matrix key switch
• Built-in key scan circuit for 3-channel encoder type rotary switch
• Built-in oscillation circuit
Crystal oscillation or ceramic oscillation: 4.0 MHz (Typ)
• Standby function
Inhibiting the oscillator circuit provides low power consumption.
• Package options:
128-pin plastic QFP (QFP128-P-1420-0.50-K) (ML9204-xxGA)
1/41
PEDL9204-02
OKI Semiconductor
ML9204-xx
BLOCK DIAGRAM
VSEG
VCOM
VDD
D-GND
L-GND
DCRAM_A
24w × 8b
Segment
Driver
CGRAM_A
16w × 35b
RESET
CS
CP
SEGA1
CGROM_A
240w × 35b
ADRAM_B
24w × 1b
8bit Shift
Register
DCRAM_B
24w × 8b
SEGA35
Segment
Driver
ADA
SEGB1
CGROM_B
240w × 35b
Segment
Driver
CGRAM_B
16w × 35b
Command
Decoder
ADRAM_B
24w × 1b
SEGB35
Segment
Driver
ADB
Control
Circuit
Address
Selector
DI/O
Write
Address
Counter
GCRAM
24w × 24b
COM1
Grid
Driver
Read
Address
Counter
COM24
Timing
Generator 2
Digit
Control
Timing
Generator 1
Duty
Control
OSC0
Oscillator
OSC1
5 x 6 Key Scan and Encoder Switch Interface
ROW1
ROW5 COL1
INT
COL6 A1 B1 A2 B2 A3 B3
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PEDL9204-02
OKI Semiconductor
ML9204-xx
104 SEGB31
103 SEGB32
106 SEGB29
105 SEGB30
110 SEGB25
109 SEGB26
108 SEGB27
107 SEGB28
112 SEGB23
111 SEGB24
115 SEGB20
114 SEGB21
113 SEGB22
117 SEGB18
116 SEGB19
119 SEGB16
118 SEGB17
122 SEGB13
121 SEGB14
120 SEGB15
124 SEGB11
123 SEGB12
126 SEGB9
125 SEGB10
128 SEGB7
127 SEGB8
PIN CONFIGURATION (TOP VIEW)
102 SEGB33
101 SEGB34
SEGB6
1
SEGB5
2
SEGB4
SEGB3
3
4
SEGB2
5
98
ADB
VSEG
SEGB1
6
VCOM
7
97
96
D-GND
VDD
COM1
8
9
95
INT
10
94
93
11
92
DI/O
CP
CS
12
13
91
RESET
90
89
B3
88
87
B2
A2
B1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
100 SEGB35
99
14
15
16
86
COM10 17
COM11 18
85
84
COM12 19
83
COM13 20
COM14 21
COM15 22
COM16 23
82
81
COM17 24
80
79
COM18
25
78
COM19
26
77
COM20 27
COM21 28
76
75
COM22
29
COM23
30
74
73
A3
A1
COL6
COL5
COL4
COL3
COL2
COL1
ROW5
ROW4
ROW3
ROW2
ROW1
OSC1
OSC0
COM24 31
VCOM 32
SEGA1 33
72
71
70
D-GND
SEGA2 34
SEGA3 35
SEGA4 36
69
VSEG
ADA
SEGA5 37
66
65
68
67
60
SEGA28
SEGA35
SEGA34
SEGA33
SEGA32 64
59
SEGA27
SEGA29 61
SEGA30 62
SEGA31 63
58
SEGA26
SEGA23 55
SEGA24 56
SEGA25 57
SEGA21 53
SEGA22 54
SEGA19 51
SEGA20 52
SEGA17 49
SEGA18 50
SEGA15 47
SEGA16 48
SEGA14 46
41
SEGA9
SEGA10 42
SEGA11 43
SEGA12 44
SEGA13 45
39
40
SEGA7
SEGA8
SEGA6 38
L-GND
128-Pin Plastic QFP
3/41
PEDL9204-02
OKI Semiconductor
ML9204-xx
PIN DESCRIPTION
Pin
Symbol
33 to 67
SEGA1 to A35
1 to 6
100 to
128
SEGB1 to B35
8 to 31
COM1 to 24
68
ADA
99
ADB
96
VDD
71
L-GND
7,32
VCOM
69,98
VSEG
70,97
D-GND
Type
Connects to
O
VFD tube anode
electrode
VFD tube anode electrode drive output.
Directly connected to fluorescent display tube and a
pull-down resistor is not necessary. IOH < –5 mA
O
VFD tube grid
electrode
VFD tube grid electrode drive output.
Directly connected to fluorescent display tube and a
pull-down resistor is not necessary. IOH < –25 mA
O
VFD tube anode
electrode
VFD tube anode electrode drive output.
Directly connected to fluorescent display tube and a
pull-down resistor is not necessary. IOH < –15 mA
—
Description
Power supply
VDD-L-GND are power supplies for internal logic.
VCOM-D-GND are power supplies for driving VFD tube
grid.
VCOM-D-GND are power supplies for driving VFD tube
anode.
Use the same power supply for L-GND and D-GND.
94
DI/O
I/O
Micro controller
Serial data input-output (positive logic).
Data is input and output to sift register synchronized
with the rise of shift clock.
When Inputting data input from the LSB.
93
CP
l
Micro controller
Shift clock input.
Serial data is shifted on the rising edge of CP.
92
CS
l
Micro controller
Chip select input.
Serial data transfer is disabled when CS pin is “H” level.
Micro controller
Output pin for interrupt signal to micro controller.
When depression or release of key matrix switch is
detected, key scanning starts and when 1 cycle is
completed, this pin becomes high level. Upon receiving
encoder type rotary switch input, this pin becomes high
level. The INT pin remains at high level until the key
scan stop mode is selected..
95
INT
85,86
87,88
89,90
A1,B1
A2,B2
A3,B3
79 to 84
COL1 to 6
O
l
I
Rotary switch
Key matrix
Encoder type rotary switch input pins.
All inputs possess chattering absorption function of
256us period.
Those inputs must be tied to ground when they are
not used.
Input pins for return signal from key matrix with built-in
pull-up resister.
When input is low level, the key matrix switch is
regarded as being pressed.
Dose not have chattering absorption function.
4/41
PEDL9204-02
OKI Semiconductor
74 to 78
91
72
ROW1 to 5
RESET
OSC0
ML9204-xx
O
l
Key matrix
Key matrix scan signal output pins.
Normally low level is output.
Key scanning starts by detecting depression or release
of key matrix switch and continues until selection of key
scan stop mode.
When key scan stop mode is selected, all outputs of
ROW1 to 5 return to low level.
Micro controller
Reset input.
“Low” initializes all the functions.
Initial status is as follows.
• Address of each RAM .............. address “00”H
• Data of each RAM ................... Content is undefined
• Display digit............................. 24 digits
• Brightness adjustment ............. 0/1024
• All lights ON or OFF ................ OFF mode
• ROW1 to 5 .............................. becomes low level
• INT.......................................... becomes low level
l
Crystal or
ceramic
resonator
73
OSC1
O
Pins for self-oscillation.
(Do not apply external clocks to these pins.)
Connect these pins to the crystal and capacitors or to
the ceramic resonator and capacitors.
The target oscillation frequency is 4.0MHz.
(The device has an internal feedback resister.)
VDD
Typical
3.3V
1Mohm
5.0V
0.4Mohm
* For information regarding the oscillator contact the
manufacturer of the oscillator.
* As regards the circuit, refer to the Application Circuit.
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PEDL9204-02
OKI Semiconductor
ML9204-xx
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage (1)
Supply Voltage (2)
Symbol
Condition
Rating
Unit
VDD
—
–0.3 to +6.5
V
VSEG
—
–0.3 to +70
V
VCOM
—
–0.3 to +70
V
–0.3 to VDD+0.3
Input Voltage
VIN
—
Power Dissipation
PD
Ta ≤ 85°C
TSTG
—
–55 to +150
lO1
COM1 to COM24
–50 to +2.0
mA
lO2
ADA, ADB
–30 to +2.0
mA
lO3
SEGA1 to SEGA35,
SEGB1 to SEGB35
–10 to +2.0
mA
IO4
ROW1 to 5 / INT
–2.0 to +2.0
mA
Storage Temperature
Output Current
470
V
*1)
mW
°C
*1) When use two or more COM, be careful of the following things.
The junction temperature which can be found by the following formula does not exceed 120.
Tj = (Px 85°C /W)+Ta
(P is the maximum power consumption of IC.)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (1)
Supply Voltage (2)
Symbol
Condition
Min.
Typ.
Max.
Unit
When the power supply
voltage is 5.0 V (typ.)
4.5
5.0
5.5
V
When the power supply
voltage is 3.3 V (typ.)
3.0
3.3
3.6
V
VSEG
—
20
—
60
V
VCOM
—
20
—
60
V
VDD
Operating Frequency
fOSC
Oscillation
3.5
4.0
4.5
MHz
Frame Frequency
fFR
DIGIT = 1 to 24, oscillation
142
163
183
Hz
Operating Temperature
TOP
—
–40
—
+85
°C
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PEDL9204-02
OKI Semiconductor
ML9204-xx
ELECTRICAL CHARACTERISTICS
DC Characteristics (VDD = 5.0 V±10%)
(VDD = 5.0 V±10%, VSEG and VCOM = 20 to 60 V, Ta = –40 to +85°C, unless otherwise specified)
Parameter
Symbol
Applied pin
Condition
Min.
Max.
Unit
High Level Input Voltage
VIH
*1
VDD = 5.0 V±10%
0.7 VDD
—
V
Low Level Input Voltage
VIL
*1
VDD = 5.0 V±10%
—
0.3 VDD
V
High Level Input Current
IIH
*1
VIH = VDD
–1.0
+1.0
µA
IIL1
*2
VIL = 0.0 V
–1.0
+1.0
µA
IIL2
COL1 to 6
VDD = 5.0 V±10%, VIL = 0.0 V
–450
–100
µA
VOH1
COM1 to 24
VCOM = 60 V, IOH1 = –25 mA
VCOM – 2.0
—
V
VOH2
ADA, ADB
VSEG = 60 V, IOH2 = –15 mA
VSEG – 2.0
—
V
VOH3
SEGA1 to A35
SEGB1 to B35
VSEG = 60 V, IOH3 = –5 mA
VSEG – 2.0
—
V
VOH4
INT, ROW1 to 5
VDD = 5.0 V±10%, IOH4 = –450
µA
VDD – 0.2
—
V
VOL1
*3
—
—
1.0
V
—
0.2
V
—
6.0
mA
—
1.0
mA
—
200
µA
—
1.0
µA
—
20.0
µA
Low Level Input Current
High Level Output
Voltage
Low Level Output
Voltage
VOL2
IDD1
Supply Current (1)
VDD
VDD = 5.0 V±10%, fOSC = 4.0
MHz
VSEG, VCOM
fOSC = 4.0 All output lights ON
MHz,
All output lights OFF
no load
IDISP1
IDISP2
Supply Current (2)
INT, ROW1 to 5 VDD =5.0 V±10%, IOL2 = 450 µA
IDDS
VDD
IDISPS
VSEG, VCOM
In standby mode
*1) CS, CP, DI/O, RESET, COL1 to 6
*2) CS, CP, DI/O, RESET
*3) SEGA1 to A35, SEGB1 to B35, ADA, ADB, COM1 to 24
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PEDL9204-02
OKI Semiconductor
ML9204-xx
DC Characteristics (VDD = 3.3 V±10%)
(VDD = 3.3 V±10%, VSEG and VCOM = 20 to 60 V, Ta = –40 to +85°C, unless otherwise specified)
Parameter
Symbol
Applied pin
Condition
Min.
Max.
Unit
High Level Input Voltage
VIH
*1
VDD = 3.3 V±10%
0.8 VDD
—
V
Low Level Input Voltage
VIL
*1
VDD = 3.3 V±10%
—
0.2
VDD
V
High Level Input Current
IIH
*1
VIH = VDD
–1.0
+1.0
µA
IIL1
*2
VIL = 0.0 V
–1.0
+1.0
µA
IIL3
COL1 to 6
VDD = 3.3 V±10%, VIL = 0.0 V
–120
–25
µA
VOH1
COM1 to 24
VCOM = 60 V, IOH1 = –25 mA
VCOM – 2.0
—
V
VOH2
ADA, ADB
VSEG = 60 V, IOH2 = –15 mA
VSEG – 2.0
—
V
VOH3
SEGA1 to A35
SEGB1 to B35
VSEG = 60 V, IOH3 = –5 mA
VSEG – 2.0
—
V
VOH5
INT, ROW1 to 5
VDD = 3.3 V±10%, IOH5 = –120
µA
VDD – 0.2
—
V
VOL1
*3
—
—
1.0
V
—
0.2
V
—
4.0
mA
—
1.0
mA
—
200
µA
—
1.0
µA
—
20.0
µA
Low Level Input Current
High Level Output
Voltage
Low Level Output
Voltage
VOL2
IDD2
Supply Current (1)
VDD
VDD = 3.3 V±10%, fOSC = 4.0
MHz
VSEG, VCOM
fOSC = 4.0 All output lights ON
MHz,
All output lights OFF
no load
IDISP1
IDISP2
Supply Current (2)
INT, ROW1 to 5 VDD = 3.3 V±10%, IOL3 = 120 µA
IDDS
VDD
IDISPS
VSEG, VCOM
In standby mode
*1) CS, CP, DI/O, RESET, COL1 to 6
*2) CS, CP, DI/O, RESET
*3) SEGA1 to A35, SEGB1 to B35, ADA, ADB, COM1 to 24
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PEDL9204-02
OKI Semiconductor
ML9204-xx
AC Characteristics
(VDD = 5.0 V±10%, or VDD = 3.3 V±10%,VSEG and VCOM = 20 to 60 V, Ta = –40 to +85°C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Max.
Unit
fC
—
—
2.0
MHz
CP Pulse Width
tCW
—
200
—
ns
D/A Setup Time
tDS
—
200
—
ns
D/A Hold Time
tDH
—
200
—
ns
CP Frequency
CS Setup Time
tCSS
—
200
—
ns
CS Hold Time
tCSH
Oscillating state
8
—
µs
CS Wait Time
tCSW
—
200
—
ns
Data Processing Time
tDOFF
Oscillating state
4
—
µs
tWRES
When RESET signal is input from
microcontroller etc. externally
200
—
ns
RESET Pulse Width
RESET Time
tRSON
—
tOSCON
—
D/A Wait Time
tRSOFF
—
200
—
ns
—
2.0
µs
—
2.0
µs
40
60
%
All Output Slew Rate
tR
tF
tR = 20 to 80%
Cl = 100 pF
tF = 80 to 20%
OSC Duty Ratio
duOSC
—
Oscillation Rise Time
tOSCON
—
*1
*1 tOSCON (oscillation rise time) differs with the oscillator pin used.
As regards oscillation rise time, refer to the data of oscillator used.
Key Scan Characteristics
(VDD = 5.0V±10%, or VDD = 3.3V±10%, VSEG and VCOM = 20 to 60 V, Ta = –40 to +85°C unless otherwise specified)
Parameter
Key Scan Time
Key Scan Pulse Width
Symbol
tSCAN
tWSCAN
Condition
fOSC = 3.5 to 4.5 MHz
Min.
Typ.
Max.
Unit
142.2
160
182.8
µs
28.4
32
36.6
µs
Rotary Switch Characteristics
(VDD = 5.0V±10%, or VDD = 3.3V±10%, VSEG and VCOM = 20 to 60 V, Ta = –40 to +85°C unless otherwise specified)
Parameter
Symbol
Phase Input Time
tABW
Phase Input Fixed Time
tABH
Condition
Min.
Typ.
Max.
Unit
fOSC = 3.5 to 4.5 MHz
1.2
—
—
ms
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PEDL9204-02
OKI Semiconductor
ML9204-xx
TIMING DIAGRAMS
Symbol
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VIH
0.7 VDD
0.8 VDD
VIL
0.3 VDD
0.2 VDD
Data Input Timing
tCSS
tCSW
CS
CP
(INPUT)
VIH
VIL
tDH
tDS
DI/O
tCSH
1/fC
tCW tCW
tDOFF
VIH
VIL
VALID VALID
VIH
VIL
VALID VALID
Data Output Timing
CS
tCSS
tCSH
CP
DI/O
TPD
VALID
TPD
VALID
TPD
VALID
TPD
VALID
(OUTPUT)
VALID
–VIH
–VIL
–VIH
–VIL
–VIH
–VIL
Output Timing
All Output
5) Driver
tR
tF
–0.8 (VSEG, VCOM)
–0.2 (VSEG, VCOM)
OSC Timing
duOSC=Bx100/(A+B)
-0.5VDD
OSC1
A
B
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PEDL9204-02
OKI Semiconductor
ML9204-xx
Standby Mode Release Timing
–VIH
CS
200nsec or more
–VIL
–VIH
CP
tRSON
–VIL
–VIH
DI/O
VALID
–VIL
OSC0
0.9Vp-p
Vp-p (stationary state oscillation level)
tOSCON
Reset Timing
* After a VDD injection should surely input a reset signal.
–0.8 VDD
–0.0 V
VDD
tRSON
tWRES
RESET
tRSOFF
DI/O
–VIH
–VIL
–VIH
VALID
–VIL
Key Scan Timing
tSCAN
ROW1
tWSCAN
ROW2
ROW3
ROW4
ROW5
11/41
PEDL9204-02
OKI Semiconductor
ML9204-xx
Rotary Switch Input Timing
A
B
tABW
tABH
tABH
tABW
tABW
Digit Output Timing (24-Digit,960/1024-Duty)
*:T = 1/fOSC
COM1
COM2
COM3
COM4
COM5
Frame cycle t1 = 24576T (fOSC = 4.0 MHz : t1 = 6.144ms)
Display
t2 = 960T (fOSC = 4.0 MHz : t2 = 240µs)
(fOSC = 4.0 MHz : t3 = 16µs)
Blank Timing t3 = 64T
VCOM
D-GND
COM20
COM21
COM22
COM23
COM24
ADA, ADB,
SEGA1~A35,
SEGB1~B35
VSEG
D-GND
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PEDL9204-02
OKI Semiconductor
ML9204-xx
FUNCTIONAL DESCRIPTION
Commands List
Command
1
2
3
DCRAM_A data write
CGRAM_A data write
ADRAM_A data write
LSB
1st byte LSB
2nd byte
MSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7
*
0
*
*
0
*
*
0
*
*
0
*
1
0
1
0
1
1
0
0
0
0
C0 C1 C2 C3 C4 C5 C6 C7
0
0
C0 C5 C10 C15 C20 C25 C30
*
2nd byte
C1 C6 C11 C16 C21 C26 C31
*
3rd byte
C2 C7 C12 C17 C22 C27 C32
*
4th byte
C3 C8 C13 C18 C23 C28 C33
*
5th byte
C4 C9 C14 C19 C24 C29 C34
*
6th byte
C0
*
*
*
*
*
*
*
C0 C1 C2 C3 C4 C5 C6 C7
4
GCRAM data write
*
*
*
*
0
0
1
0
C8 C9 C10 C11 C12 C13 C14 C15
C16 C17 C18 C19 C20 C21 C22 C23
5
Display duty set
D0 D1
6
Number of digits set
K0 K1 K2 K3
7
All lights ON/OFF
L
H
*
9
DCRAM_B data write
*
*
*
A
CGRAM_B data write
0
0
*
0
*
1
0
1
0
0
1
1
0
*
1
1
1
0
*
1
0
0
1
0
0
1
0
D2 D3 D4 D5 D6 D7 D8 D9
C0 C1 C2 C3 C4 C5 C6 C7
1
B
ADRAM_B data write
*
*
*
*
1
1
0
1
C
Key scan stop
*
*
*
*
0
0
1
1
D
Key data output
*
*
*
*
1
0
1
1
F
Standby mode
*
*
*
*
1
1
1
1
0
Test Mode(Note)
0
0
0
0
C0 C5 C10 C15 C20 C25 C30
*
2nd byte
C1 C6 C11 C16 C21 C26 C31
*
3rd byte
C2 C7 C12 C17 C22 C27 C32
*
4th byte
C3 C8 C13 C18 C23 C28 C33
*
5th byte
C4 C9 C14 C19 C24 C29 C34
*
6th byte
C0
*
*
*
*
*
*
Refer to item D of command and
function description.
*
When data is written to RAM (DCRAM, CGRAM,
ADRAM, and GCRAM) continuously, addresses are
internally incremented automatically.
Therefore it is not necessary to specify the 1st byte to write
RAM data for the 2nd and later bytes.
*
Xn
Cn
Dn
Kn
H
L
: Don’t care
: Address specification for each RAM
: Character code specification for each RAM
: Display duty specification
: Number of digits specification
: All lights ON instruction
: All lights OFF instruction
Note: The test mode is used for inspection before shipment.
It is not a user function. The user cannot use this
command. Enter commands 1 to 7, 9 to D, and
F alone in the way described on the next page and the
following pages. (The operation of this device cannot be
guaranteed if other commands are used.
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Positional Relationship Between SEGn and ADn (one digit)
C0
Corresponds to the 2nd byte of the ADRAM_A data write command.
ADA
C0
C1
C2
C3
C4
SEGA1
SEGA2
SEGA3
SEGA4
SEGA5
C5
C6
C7
C8
C9
SEGA6
SEGA7
SEGA8
SEGA9
SEGA10
C10
C11
C12
C13
C14
SEGA11
SEGA12
SEGA13
SEGA14
SEGA15
C15
C16
C17
C18
C19
SEGA16
SEGA17
SEGA18
SEGA19
SEGA20
C20
C21
C22
C23
C24
SEGA21
SEGA22
SEGA23
SEGA24
SEGA25
C25
C26
C27
C28
C29
SEGA26
SEGA27
SEGA28
SEGA29
SEGA30
C30
C31
C32
C33
C34
SEGA31
SEGA32
SEGA33
SEGA34
SEGA35
Corresponds to the 6th byte of the CGRAM_A data write command.
Corresponds to the 5th byte of the CGRAM_A data write command.
Corresponds to the 4th byte of the CGRAM_A data write command.
Corresponds to the 3rd byte of the CGRAM_A data write command.
Corresponds to the 2nd byte of the CGRAM_A data write command.
C0
Corresponds to the 2nd byte of the ADRAM_B data write command.
ADB
C0
C1
C2
C3
C4
SEGB1
SEGB2
SEGB3
SEGB4
SEGB5
C5
C6
C7
C8
C9
SEGB6
SEGB7
SEGB8
SEGB9
SEGB10
C10
C11
C12
C13
C14
SEGB11
SEGB12
SEGB13
SEGB14
SEGB15
C15
C16
C17
C18
C19
SEGB16
SEGB17
SEGB18
SEGB19
SEGB20
C20
C21
C22
C23
C24
SEGB21
SEGB22
SEGB23
SEGB24
SEGB25
C25
C26
C27
C28
C29
SEGB26
SEGB27
SEGB28
SEGB29
SEGB30
C30
C31
C32
C33
C34
SEGB31
SEGB32
SEGB33
SEGB34
SEGB35
Corresponds to the 6th byte of the CGRAM_B data write command.
Corresponds to the 5th byte of the CGRAM_B data write command.
Corresponds to the 4th byte of the CGRAM_B data write command.
Corresponds to the 3rd byte of the CGRAM_B data write command.
Corresponds to the 2nd byte of the CGRAM_B data write command.
COMn
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Data Transfer Method and Command Write Method
Display control command and data are written by an 8-bit serial transfer.
Write timing is shown in the figure below.
Setting the CS pin to “Low” level enables a data transfer.
Data is 8 bits and is sequentially input into the DI/O pin from LSB (LSB first).
As shown in the figure below, data is read by the shift register at the rising edge of the shift clock, which is input
into the CP pin. If 8-bit data is input, internal load signals are automatically generated and data is written to each
register and RAM.
Therefore it is not necessary to input load signals from the outside.
Setting the CS pin to “High” disables data transfer. Data input from the point when the CS pin changes from
“High” to “Low” is recognized in 8-bit units.
CS
tDOFF
tCSH
CP
B0 B1B2 B3 B4 B5 B6 B7
B0 B1B2 B3 B4 B5 B6 B7
B0 B1B2 B3 B4 B5 B6 B7
LSB
LSB
LSB
DA
When data is written
to DCRAM*
1st byte
MSB
Command and address data
2nd byte
MSB
Character code data
3rd byte
MSB
Character code data of the
next address
* When data is written to RAM (DCRAM, ADRAM, CGRAM, GCRAM) continuously, addresses are internally
incremented automatically.
Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd and later bytes.
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Data Outputting and Command Writing
In an operation to read key scan data, when CS goes “Low” after Key Data Output Mode is entered, the DI/O pin
changes modes to OUTPUT and key data is output in synchronization with the rise of Shift Lock.
The waveforms to read key data are shown blow.
The DI/O pin enters the INPUT mode when the CS pin is set to “High” after key data is output.
tCSH
CS
CP
DI/O
B0 B1 B2 B3 B4 B5 B6 B7
B0 B1 B2 B3 B4 B5 B6 B7
LSB
LSB
Keyscan stop
MSB
MSB
Key data output mode
VALID
Data output (42-bit)
Reset Function
Reset is executed when the RESET pin is set to “L”, (when turning power on, for example) and initializes all
functions.
Initial status is as follows.
•
•
•
•
•
•
•
•
•
Address of each RAM ..................... address “00”H
Data of each RAM .......................... All contents are undefined
Display digit ................................... 24 digits
Brightness adjustment..................... 0/1024
All display lights ON or OFF .......... OFF mode
Segment output ............................... All segment outputs go “Low”
AD output....................................... All AD outputs go “Low”
ROW1 to 5...................................... All ROW outputs go “Low”
INT................................................. INT goes “Low.”
Be sure to execute the reset operation when turning power on and set again according to “Setting Flowchart”
after reset.
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Description of Commands and Functions
1,9. DCRAM data write
(Writes the character code of CGROM and CGRAM.)
DCRAM (Data Control RAM) has a 5-bit address to store character code of CGROM and CGRAM.
The character code specified by DCRAM is converted to a 5 × 7 dot matrix character pattern via CGROM or
CGRAM.
(The DCRAM can store 24 characters.)
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
(1st)
*
LSB
*
*
*
1
0
0 0/1
0: Select DCRAM_A
1: Select DCRAM_B
: Selects DCRAM data write mode
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(2nd)
C0 C1 C2 C3 C4 C5 C6 C7
: Specifies character code of CGROM and CGRAM
(Written into DCRAM address 00H)
To specify the character code of CGROM and CGRAM continuously to the next address, specify only character
code as follows.
The addresses of DCRAM are automatically incremented. Specification of an address is unnecessary.
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(3rd)
C0 C1 C2 C3 C4 C5 C6 C7
LSB
: Specifies character code of CGROM and CGRAM
(Written into DCRAM address 01H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(4th)
C0 C1 C2 C3 C4 C5 C6 C7
LSB
: Specifies character code of CGROM and CGRAM
(Written into DCRAM address 02H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(25th)
C0 C1 C2 C3 C4 C5 C6 C7
: Specifies character code of CGROM and CGRAM
(Written into DCRAM address 17H)
A character code setup of CGROM to 24-Digit and CGRAM is completion in the above work.
Furthermore, you have to specify the character codes of a dummy to be DCRAM and 18H-1FH to perform a
character code setup from DCRAM address 00H continuously.
(In order to carry out the increment of the address of DCRAM automatically and to set a DCRAM address to
00H.)
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LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(26th)
C0 C1 C2 C3 C4 C5 C6 C7
8 times enforcement
LSB
: CGROM of a dummy and the character code of CGRAM
are specified.
(It is not written in a DCRAM address.)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(33th)
C0 C1 C2 C3 C4 C5 C6 C7
LSB
MSB
: CGROM of a dummy and the character code of CGRAM
are specified.
(It is not written in a DCRAM address.)
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(34th)
C0 C1 C2 C3 C4 C5 C6 C7
: Character code of CGROM and CGRAM is specified.
(DCRAM address 00H are rewritten.)
C0 (LSB) to C7 (MSB): Character code of CGROM and CGRAM (8 bits: 256 characters)
* : Don’t Care
[COM positions and set DCRAM addresses]
DCRAM address
(HEX)
COM
DCRAM address
(HEX)
COM
DCRAM address
(HEX)
COM
00
COM1
0C
COM13
18
Dummy
01
COM2
0D
COM14
19
Dummy
02
COM3
0E
COM15
1A
Dummy
03
COM4
0F
COM16
1B
Dummy
04
COM5
10
COM17
1C
Dummy
05
COM6
11
COM18
1D
Dummy
06
COM7
12
COM19
1E
Dummy
07
COM8
13
COM20
1F
Dummy
08
COM9
14
COM21
09
COM10
15
COM22
0A
COM11
16
COM23
0B
COM12
17
COM24
Dummy is put in to set up a DCRAM
address from 00H continuously.
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2,A. CGRAM data write
(CGRAM writes character pattern data.)
CGRAM (Character Generator RAM) has a 4-bit address to store 5x 7 dot matrix character patterns.
A character pattern stored in CGRAM can be displayed by specifying the character code (address) by
DCROM.
The address of CGRAM is assigned to 00H to 0FH. (All the other addresses are the CGROM addresses.)
(The CGRAM can store 16 types of character patterns.)
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
(1st)
0
0
0
0
0
1
0: Select CGRAM_A
1: Select CGRAM_B
0 0/1 : Selects CGRAM data write mode
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(2nd)
C0 C5 C10 C15C20 C25 C30
LSB
*
: Specifies 1st column data
(Rewritten into CGRAM address 00H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
3rd byte
(3rd)
C1 C6 C11 C16C21 C26 C31
LSB
*
: Specifies 2nd column data
(Rewritten into CGRAM address 00H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
4th byte
(4th)
C2 C7 C12 C17C22 C27 C32
LSB
*
: Specifies 3rd column data
(Rewritten into CGRAM address 00H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
5th byte
(5th)
C3 C8 C13 C18C23 C28 C33
LSB
*
: Specifies 4th column data
(Rewritten into CGRAM address 00H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(6th)
C4 C9 C14 C19C24 C29 C34
*
: Specifies 5th column data
(Rewritten into CGRAM address 00H)
To specify character pattern data continuously to the next address, specify only character pattern data as follows.
The addresses of CGRAM are automatically incremented. Specification of an address is unnecessary.
The 2nd to 6th byte (character pattern data) are regarded as one data item, so 200 ns is sufficient for tDOFF time
between bytes.
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LSB
ML9204-xx
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(7th)
*
C0 C5 C10 C15C20 C25 C30
LSB
: Specifies 1st column data
(Rewritten into CGRAM address 01H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(11th)
C4 C9 C14 C19C24 C29 C34
LSB
*
: Specifies 5th column data
(Rewritten into CGRAM address 01H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(12th)
C0 C5 C10 C15C20 C25 C30
LSB
*
: Specifies 1st column data
(Rewritten into CGRAM address 02H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(16th)
C4 C9 C14 C19C24 C29 C34
LSB
*
: Specifies 5th column data
(Rewritten into CGRAM address 02H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(77th)
C0 C5 C10C15C20 C25 C30
LSB
*
: Specifies 1st column data
(Rewritten into CGRAM address 0FH)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(81th)
C4 C9 C14C19C24 C29 C34
LSB
*
: Specifies 5th column data
(Rewritten into CGRAM address 0FH)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(82th)
C0 C5 C10 C15C20 C25C30
LSB
*
: Specifies 1st column data
(Rewritten into CGRAM address 00H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(86th)
C4 C9 C14 C19C24 C29C34
*
: Specifies 5th column data
(Rewritten into CGRAM address 00H)
X0 (LSB) to X3 (MSB) : CGRAM addresses (4 bits: 16 characters)
C0 (LSB) to C34 (MSB) : Character pattern data (35 bits: 35 outputs per digit)
* : Don't care
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[CGROM addresses and set CGRAM addresses]
Refer to ROM code tables.
HEX
X0
X1
X2
X3
CGROM address
HEX
X0
X1
X2
X3
CGROM address
00
0
0
0
0
RAM00 (00000000B)
08
0
0
0
1
RAM08 (00001000B)
01
1
0
0
0
RAM01 (00000001B)
09
1
0
0
1
RAM09 (00001001B)
02
0
1
0
0
RAM02 (00000010B)
0A
0
1
0
1
RAM0A (00001010B)
03
1
1
0
0
RAM03 (00000011B)
0B
1
1
0
1
RAM0B (00001011B)
04
0
0
1
0
RAM04 (00000100B)
0C
0
0
1
1
RAM0C (00001100B)
05
1
0
1
0
RAM05 (00000101B)
0D
1
0
1
1
RAM0D (00001101B)
06
0
1
1
0
RAM06 (00000110B)
0E
0
1
1
1
RAM0E (00001110B)
07
1
1
1
0
RAM07 (00000111B)
0F
1
1
1
1
RAM0F (00001111B)
Positional relationship between the output area of CGRAM
C0
C1
C2
C3
C4
SEGn1
SEGn2
SEGn3
SEGn4
SEGn5
C5
C6
C7
C8
C9
C5
C7
C8
SEGn6
SEGn7
SEGn8
SEGn9
SEGn10
SEGn6
SEGn8
SEGn9
C10
C11
C12
C13
C14
C10
C11
C13
C14
SEGn11
SEGn12
SEGn13
SEGn14
SEGn15
SEGn11
SEGn12
SEGn14
SEGn15
C15
C16
C17
C18
C19
C15
C16
C17
C19
SEGn16
SEGn17
SEGn18
SEGn19
SEGn20
SEGn16
SEGn17
SEGn18
SEGn20
C20
C21
C22
C23
C24
C20
C21
C23
C24
SEGn21
SEGn22
SEGn23
SEGn24
SEGn25
SEGn21
SEGn22
SEGn24
SEGn25
C25
C26
C27
C28
C29
C25
C27
C28
SEGn26
SEGn27
SEGn28
SEGn29
SEGn30
SEGn26
SEGn28
SEGn29
C30
C31
C32
C33
C34
SEGn31
SEGn32
SEGn33
SEGn34
SEGn35
Area that corresponds to 2nd byte (1st column)
(Input 1000001*B)
Area that corresponds to 3rd byte (2nd column)
(Input 1100011*B)
Area that corresponds to 4th byte (3rd column)
(Input 1010101*B)
Area that corresponds to 5th byte (4th column)
(Input 1001001*B)
Area that corresponds to 6th byte (5th column)
(Input 1100011*B)
Note: CGROM_A and CGROM_B (Character Generator ROM A, B) have an 8-bit address to generate
5 x 7 dot matrix character patterns.
Each of CGROM_A and CGROM_B can store 240 types of character patterns.
The contents of CGROM_A and CGROM_B can be set separately.
General-purpose code -01 is available (see ROM code tables) and custom codes are provided
on customer's request.
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3,B. ADRAM data write
(ADRAM writes symbol data)
ADRAM (Additional Data RAM) has a 1-bit address to store symbol data.
Symbol data specified by ADRAM is directly output without CGROM and CGRAM.
(The ADRAM can store 1 type of symbol patterns for each digit.)
The terminal to which the contents of ADRAM are output can be used as a cursor.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
(1st)
*
*
*
*
1
1
0 0/1
LSB
0: Select ADRAM_A
1: Select ADRAM_B
: Selects ADRAM data write mode
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(2nd)
C0
*
*
*
*
*
*
*
: Sets symbol data
(Written into ADRAM address 00H)
To specify symbol data continuously to the next address, specify only character data as follows.
The address of ADRAM is automatically incremented. Specification of addresses is unnecessary.
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(3rd)
C0
*
*
*
*
*
*
LSB
*
MSB
: Sets symbol data
(Written into ADRAM address 01H)
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(4th)
C0
*
*
*
*
*
*
LSB
*
: Sets symbol data
(Written into ADRAM address 02H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(25th)
C0
*
*
*
*
*
*
*
: Sets symbol data
(Written into ADRAM address 17H)
A character code setup of 24-Digit is completion in the above work.
Furthermore, you have to specify the character codes of a dummy to be ADRAM and 18H-1FH to perform a
character code setup from ADRAM address 00H continuously.
(In order to carry out the increment of the address of ADRAM automatically and to set a ADRAM address to
00H.)
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LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(26th)
C0
*
*
*
*
*
*
LSB
*
: The sign data of a dummy is specified.
(It is not written in an ADRAM address.)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(33th)
C0
*
*
*
*
*
*
LSB
*
: The sign data of a dummy is specified.
(It is not written in an ADRAM address.)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(34th)
C0
*
*
*
*
*
*
*
: The sign data of a dummy is specified.
(ADRAM address 00H are rewritten.)
C0 : Symbol data (1 bit: 1-symbol data per digit)
* : Don’t care
[COM positions and ADRAM addresses]
ADRAM address
(HEX)
COM
ADRAM address
(HEX)
COM
ADRAM address
(HEX)
COM
00
COM1
0C
COM13
18
Dammy
01
COM2
0D
COM14
19
Dammy
02
COM3
0E
COM15
1A
Dammy
03
COM4
0F
COM16
1B
Dammy
04
COM5
10
COM17
1C
Dammy
05
COM6
11
COM18
1D
Dammy
06
COM7
12
COM19
1E
Dammy
07
COM8
13
COM20
1F
Dammy
08
COM9
14
COM21
09
COM10
15
COM22
0A
COM11
16
COM23
0B
COM12
17
COM24
Dummy is put in to set up a ADRAM
address from 00H continuously.
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4. GCRAM data write
(writes data by the number of COM outputs for digits)
GCRAM (Grid Control RAM) has a 5-bit address to control the number of COM outputs for digits.
GCRAM outputs specified data directly to COMn, allowing COM outputs to be controlled arbitrarily.
It is also possible to supply a large current by connecting a plurality of COMs outside the ML9204.
For example, when COM23 and COM24 are connected, the ML9204 has 23 display digits. In this case, the user
specifies “23” as the number of display digits.
Write grid data at GCRAM addresses 00H and later.
Carry out this mode before putting-out-lights mode release.
Refer to a “setting operation flow chart” about the details of a setup.
Write COM data"0" in the GCRAM address which is not used for incorrect display prevention.
[Command format]
LSB
1st byte
(1st)
B0
*
MSB
B1
*
B2
*
B3
*
B4
0
B5
0
B6
1
B1
C1
B2
C2
B3
C3
B4
C4
B5
C5
B6
C6
LSB
2nd byte
(2nd)
3rd byte
(3rd)
4th byte
(4th)
B0
C0
B7
0
: Selects a GCRAM data write mode.
MSB
B7
C7
LSB
MSB
B0
C8
B1 B2 B3 B4 B5 B6 B7
C9 C10 C11 C12 C13 C14 C15
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
C16 C17 C18 C19 C20 C21 C22 C23
: Specifies COM data.
(Written into GCRAM address 00H)
: Specifies COM data.
(Written into GCRAM address 00H)
: Specifies COM data.
(Written into GCRAM address 00H)
C0 (LSB) to C23 (MSB): Grid control data (24 bits)
*: Don’t Care
Note: To specify additional grid control data, specify the grid control data as shown below. The GCRAM
addresses are automatically incremented.
The second byte to the fourth byte (for grid data) are treated as a single piece of element and the
byte-byte tDOFF can be 200 ns.
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LSB
2nd byte
(5th)
B0
C0
MSB
B1
C1
B2
C2
B3
C3
B4
C4
B5
C5
B6
C6
LSB
B7
C7
MSB
B0 B1 B2 B3 B4 B5 B6 B7
4th byte C16 C17 C18 C19 C20 C21 C22 C23
(7th)
LSB
2nd byte
(71st)
B0
C0
: Specifies COM data.
(Written into GCRAM address 01H)
: Specifies COM data.
(Written into GCRAM address 01H)
MSB
B1
C1
B2
C2
B3
C3
B4
C4
B5
C5
LSB
B6
C6
B7
C7
: Specifies COM data.
(Written into GCRAM address 17H)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
4th byte C16 C17 C18 C19 C20 C21 C22 C23
(73rd)
: Specifies COM data.
(Written into GCRAM address 17H)
With the above operations, COM data of up to 24 digits are set. To set other COM data at GCRAM addresses
00H and later, specify dummy symbol data at GCRAM addresses 18H to 1FH (to automatically increment the
GCRAM address and set the GCRAM address to 00H).
[GCRAM addresses (digit positions) and COM positions]
GCRAM
address
(HEX)
1(00)
2(01)
3(02)
22(15)
23(16)
24(17)
COM1
C0
C1
C2
C21
C22
C23
COM2
C0
C1
C2
C21
C22
C23
COM3
C0
C1
C2
C21
C22
C23
COM4
C0
C1
C2
C21
C22
C23
COM5
C0
C1
C2
C21
C22
C23
•••••
COM20
C0
C1
C2
C21
C22
C23
COM21
C0
C1
C2
C21
C22
C23
COM22
C0
C1
C2
C21
C22
C23
COM23
C0
C1
C2
C21
C22
C23
COM24
C0
C1
C2
C21
C22
C23
25/41
PEDL9204-02
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ML9204-xx
[GCRAM output example]
1. When 4-digit of the 9-digit display requires an output current of 40 mA
<Setup>
Number setup of display beams: 9-digit
GCRAM setup:4-digit of COM4 and COM5
* Write "0" also in the beam which is not used.
GCRAM
address
(HEX)
1(00)
2(01)
3(02)
4(03)
5(04)
6(05)
7(08)
8(07)
9(08)
11(09)
11(0A)
COM1
1
0
0
0
0
0
0
0
0
0
COM2
0
1
0
0
0
0
0
0
0
0
COM3
0
0
1
0
0
0
0
0
0
0
0
COM4
0
0
0
1
0
0
0
0
0
0
0
COM5
0
0
0
1
0
0
0
0
0
0
COM6
0
0
0
0
1
0
0
0
0
COM7
0
0
0
0
0
1
0
0
0
COM8
0
0
0
0
0
0
1
0
COM9
0
0
0
0
0
0
0
COM10
0
0
0
0
0
0
0
……
23(16)
24(17)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
……
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM1
COM2
Strap COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
GRID1
GRID2
GRID3
GRID4
GRID5
GRID6
GRID7
GRID8
GRID9
Dsiplay tube
1 Cycle
* Strapping COM4 and COM5 brings display digits to 9 digits, and a current of 50 mA can be supplied.
26/41
PEDL9204-02
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ML9204-xx
2. When only one digit of the 22-digit display requires an output current of 60 mA
<Setup>
Number setup of display beams:22-digit
GCRAM setup:1-digit of COM1 and COM23 and COM24
* Write "0" also in the beam which is not used.
GCRAM
address
(HEX)
COM1
3(02)
4(03)
5(04)
0
0
0
0
1
0
0
0
1
1(00)
2(01)
1
COM2
COM3
8(07)
6(05)
7(08)
9(08)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
11(09)
……
24(17)
22(15)
23(16)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
……
COM22
0
0
0
0
0
0
0
0
0
0
1
0
0
COM23
1
0
0
0
0
0
0
0
0
0
0
0
0
COM24
1
0
0
0
0
0
0
0
0
0
0
0
0
1 Cycle
COM22
COM23
COM24
Strap
COM1
COM2
COM3
GRID1
GRID2
GRID3
COM22
COM23
COM24
GRID22
Display tube
COM1
COM2
COM3
* Strapping COM1, COM23 and COM24 brings display digits to 22 digits, and a current of 75 mA can be
supplied.
27/41
PEDL9204-02
OKI Semiconductor
ML9204-xx
5. Display duty set
(writes display duty value to duty cycle register)
Display duty adjusts brightness in 1024 stages using 10-bit data.
When power is turned on or when the RESET signal is input, the duty cycle register value is “0”. Always
execute this instruction before turning the display on, then set a desired duty value.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
(1st)
D0 D1
*
*
1
0
LSB
1
0
: Selects display duty set mode and sets duty value (lower 2 bits)
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(2nd)
D2 D3 D4 D5 D6 D7 D8 D9
: sets duty value (upper 8 bits)
D0 (LSB) to D9 (MSB) : Display duty data (10 bits: 1024 stages)
* : Don’t care
[Relation between setup data and controlled COM duty]
HEX
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
COM duty
000
0
0
0
0
0
0
0
0
0
0
0/1024
001
1
0
0
0
0
0
0
0
0
0
1/1024
002
0
1
0
0
0
0
0
0
0
0
2/1024
3BE
0
1
1
1
1
1
0
1
1
1
958/1024
3BF
1
1
1
1
1
1
0
1
1
1
959/1024
3C0
0
0
0
0
0
0
1
1
1
1
960/1024
3C1
1
0
0
0
0
0
1
1
1
1
960/1024
3FF
1
1
1
1
1
1
1
1
1
1
960/1024
The state when power is turned on or when RESET signal is input.
28/41
PEDL9204-02
OKI Semiconductor
ML9204-xx
6. Number of digits set
(writes the number of display digits to the display digit register)
The number of digits set can display 9 to 24 digits using 4-bit data.
When power is turned on or when a RESET signal is input, the number of digit register value is “0”. Always
execute this instruction to change the number of digits before turning the display on.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
K0 K1 K2 K3 0
1
1
0
: selects the number of digit set mode and specifies
the number of digit value
K0 (LSB) to K3 (MSB) : Number of digit data (4 bits: 24 digits)
* : Don’t care
[Relation between setup data and controlled COM]
* When the number of COM is one at 1 digit
HEX
K0
K1
K2
K3
Number of digits of
COM
HEX
K0
K1
K2
K3
Number of digits of
COM
0
0
0
0
0
1-24(COM1 to 24)
0
0
0
0
1
1-16(COM1 to 16)
1
1
0
0
0
1-9(COM1 to 9)
1
1
0
0
1
1-17(COM1 to 17)
2
0
1
0
0
1-10(COM1 to 10)
2
0
1
0
1
1-18(COM1 to 18)
3
1
1
0
0
1-11(COM1 to 11)
3
1
1
0
1
1-19(COM1 to 19)
4
0
0
1
0
1-12(COM1 to 12)
4
0
0
1
1
1-20(COM1 to 20)
5
1
0
1
0
1-13(COM1 to 13)
5
1
0
1
1
1-21(COM1 to 21)
6
0
1
1
0
1-14(COM1 to 14)
6
0
1
1
1
1-22(COM1 to 22)
7
1
1
1
0
1-15(COM1 to 15)
7
1
1
1
1
1-23(COM1 to 23)
The state when power is turned on or when RESET signal is input.
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PEDL9204-02
OKI Semiconductor
ML9204-xx
7. All display lights ON/OFF set
(turns all display lights ON or OFF)
All display lights ON is used primarily for display testing.
All display lights OFF is primarily used for display blink and to prevent malfunction when power is turned on.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
L
H
*
*
1
1
1
0
: Selects all display lights ON or OFF mode
L, H : Display operation data
* : Don’t care
[Set data and display state of SEG and AD]
L
H
0
0
Display state of SEG and AD
Normal display
1
0
Sets all outputs to Low
0
1
Sets all outputs to High
1
1
Sets all outputs to High
* Priority is given to an all-points light command.
30/41
PEDL9204-02
OKI Semiconductor
ML9204-xx
C. Key scan stop
This command stops key scanning and makes ROW1 to ROW5 outputs “Low” and the INT output “Low”.
[Command format]
LSB
B0
*
1st byte
MSB
B1
*
B2
*
B3
*
B4
0
B5
0
B6
1
B7
1
: stops key scanning.
*: Don’t Care
D. Key data output
This command puts the pin in the output mode and causes the pin to output the scanned switch data.
The DI/O pin outputs 42-bit switch data at the rise of a clock.
When the CS pin goes high, the DI/O pin enters the output mode.
“R1, R2, R3 = 0” means turning a control knob clockwise.
“R1, R2, R3 = 1” means turning a control knob counterclockwise.
Contact count bits are Q11(LSB) to Q13(MSB), Q21(LSB) to Q23(MSB), and Q31(LSB) to Q33(MSB).
[Command format]
LSB
B0
*
1st byte
*:
MSB
B1
*
B2
*
B3
*
B4
1
B5
0
B6
1
B7
1
: outputs key data.
Don’t Care
[COL input and ROW output key-switch matrix]
ROW1
COL1
ROW3
ROW2
ROW5
ROW4
S11
S21
S31
S41
S51
S12
S22
S32
S42
S52
S13
S23
S33
S43
S53
S14
S24
S34
S44
S54
S15
S25
S35
S45
S55
S16
S26
S36
S46
S56
COL2
COL3
COL4
COL5
COL6
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ML9204-xx
[Output Data Format]
Output data: 42 bits
5 × 6 push switch data: 30 bits
Encoder switch data: 12 bits
Bit
1
2
3
4
5
6
7
8
9
10
11
12
Output Data
S11
S12
S13
S14
S15
S16
S21
S22
S23
S24
S25
S26
Bit
13
14
15
16
17
18
19
20
21
22
23
24
Output Data
S31
S32
S33
S34
S35
S36
S41
S42
S43
S44
S45
S46
Bit
25
26
27
28
29
30
31
32
33
34
35
36
Output Data
S51
S52
S53
S54
S55
S56
R1
Q11
Q12
Q13
R2
Q21
Bit
37
38
39
40
41
42
Output Data
Q22
Q23
R3
Q31
Q32
Q33
Sij: i = ROW1 to 5; j = COL1 to 6
Sij = 1: switch ON
Sij = 0: switch OFF
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PEDL9204-02
OKI Semiconductor
ML9204-xx
Keyscan
Keyscanning is started only when depression or release of any key is detected in order to minimize noise caused
by scanning signal. Then, keyscanning is continued until the keyscan stop mode is sent from a microcomputer.
The INT pin goes to the high level at the completion of 1-cycle scanning after the keyscan start, so the (high
level) signal sent from the INT pin can be used as an interrupt signal.
[Keyscan Timing and Cycles]
ROW1
ROW2
ROW3
ROW4
ROW5
1 keyscan cycle
INT
keyscan stop
Depress/Release
Keyscanning cannot be stopped by selecting the keyscan stop mode only once if:
- keyscanning is started after depression or release of any key is detected, and then
- a key is depressed or released again before the keyscan stop mode is selected.
To stop keyscanning, it is required to select the keyscan stop mode once again.
Depress
INT
CS
Depress
Keyscan
Release
Keyscan
KS
KS
KS
KS: Keyscan stop mode
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PEDL9204-02
OKI Semiconductor
ML9204-xx
The rotary encoder switch function
As Figure 1 shows, the rotary encoder switch circuit is consisted of Phase detection, Interrupt generation,
Up/down counter, Direction latch and Parallel-in serial-out shift register.
A
B
Phase Detection
UP
DOWN
Interrupt
Generation
UP/DOWN Counter
Q3 Q2 Q1
for INT
Direction Latch
R1
P-in/S-out Shift Register
Output data
The Rotary Encoder Switch Circuit
1.
Phase detection
1-1. Clockwise rotation
The input A and B have a chattering absorption circuit of 256 µs period. When signal A and B input as shown
below, the phase detection circuit outputs UP signal after the chattering absorption period. At this time, the
output INT also goes to high level, so this signal can be used as an interrupt. The INT stays High level until the
keyscan stop mode is selected.
A
B
chattering absorption time
UP (internal)
INT
The Input and Output Timing in the Case of Clockwise Rotation
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PEDL9204-02
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ML9204-xx
1-2. Counterclockwise rotation
When signal A and B input as shown below, the phase detection circuit outputs Down signal after the chattering
absorption period. At this time, the output INT also goes to High level. The INT stays High level until the
keyscan stop mode is selected.
A
chattering absorption time
B
DOWN (internal)
INT
The Input and Output Timing in the Case of Counterclockwise Rotation
2. UP/DOWN COUNTER
When the UP/DOWN COUNTER is input UP, it counts up and when it is input DOWN, it counts down.
But if the UP/DOWN COUNTER is incremented beyond “111”, it stays “111”.
A
B
Q1, Q2, Q3
100
010
110
001
101
011
111
111
Counter Overflow
3. Direction latch
When the Direction latch is input DOWN the output R1 goes “1”. But if the UP pulse is input and the count
value changes to a positive value, the output R1 goes to “0”.
A
B
R1
Q1, Q2, Q3
100
100
010
000
100
010
Direction Latch
35/41
PEDL9204-02
OKI Semiconductor
ML9204-xx
F. Standby mode set
(Display all switched off and an oscillation stopped)
Standby mode realizes low power consumption of VDD, VSEG, and VCOM by all switching off a display,
stopping an oscillation of an external (COM is fixed to Low) oscillation child, and stopping internal operation
completely. All display lights OFF is primarily used for display blink and to prevent malfunction when power is
turned on.
* If a RESET signal is inputted during standby mode execution, standby mode is canceled, and keep in mind it
that all states will be initialized.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
*
*
*
*
1
1
1
1
1
: Standby mode is specified.
* : Don’t care
[Release standby mode]
Release in standby mode is performed in falling of CS. (An oscillation child's oscillation is started)
Data input will become possible if an oscillation is stabilized. (Please return brought-down CS high-level before
data input)
When you display after standby mode release since it is all putting out lights although the setting state is held,
please cancel all putting-out-lights modes (in usual mode).
* Please do not input a shift clock into CP until an oscillation is stabilized. (Data will be given)
tRSON (oscillation standup time) changes with oscillation children who use it. Please make reference an
oscillation child's data to be used.
CS
Data input
Set it as 200nsec.
tRSON
CP
* May not place the section.
DA
B0 B1B2 B3 B4 B5 B6 B7
Standby state
Standby release,
Standby section
OSC0
Usually, a state of operation
(all putting-out-lights states)
0.9Vp-p
Oscillation stop state
Oscillation unstable state
(oscillation standup time)
LSB
1st byte
MSB
Vp-p
Oscillation stable state
Oscillation start
36/41
PEDL9204-02
OKI Semiconductor
ML9204-xx
SETTING FLOWCHART
(Power applying included)
Apply VDD
RESET execution
Apply VSEG/VCOM
Status of all outputs by RESET
All display lights OFF
Number of digits setting
Display duty setting
Select a RAM to be used
DCRAM_A or B
CGRAM_A or B
ADRAM_A or B
GCRAM
Data write mode
Data write mode
Data write mode
Data write mode
(with address setting)
Address is automatically
incremented
Address is automatically
incremented
CGRAM_A or B
Character code
DCRAM_A or B
Character code
NO
DCRAM
Is character code
write ended?
YES
Address is automatically
incremented
NO
ADRAM_A or B
Character code
CGRAM
Is character code
write ended?
NO
ADRAM
Is character code
write ended?
YES
YES
Address is automatically
incremented
GCRAM code
NO
YES
GCRAM
write ended?
YES
Another RAM to
be set?
NO
Releases all display lights
OFF mode
End of setting
Display operation mode
37/41
PEDL9204-02
OKI Semiconductor
ML9204-xx
POWER-OFF FLOWCHART
Display operation mode
Turn off VSEG/VCOM
Turn off VDD
APPLICATION CIRCUIT
5 x 7 dot matrix fluorescent display
ANODE
ANODE
ANODE
GRID
(SEGMENT) (SEGMENT) (SEGMENT) (DIGIT)
2
VDD
VDD
35
VDD
MCU
24
COM1-24
*1
R
VSEG
VSEG / VCOM
CS
CP
DI/O
Output port
35
ADA,ADB SEGB1-B35 SEGA1-A35
ML9204-xx
INT
VCOM
RESET
GND
OSC0 OSC1 L-GND D-GND A1-3 B1-3 ROW1-5 COL1-6
ZD
*2
*3
5x6Key matrix
and rotary switch
Crystal oscillation or
Ceramic oscillation
*1 The VSEG and VCOM voltages depend on the fluorescent display tube used. Adjust the value of the
constants R and ZD to the VSEG and VCOM voltages used.
*2 The wiring trace between the OSC0 pin and the resonator should be kept as short as possible, and
the GND traces should be provided along both sides of the wiring trace.
*3 Adjust the capacitance of the capacitor depending on the type of the oscillator used. (Refer to the
data of oscillator used.)
38/41
PEDL9204-02
OKI Semiconductor
ML9204-xx
PACKAGE DIMENSIONS
(Unit: mm)
QFP128-P-1420-0.50-K
Mirror finish
5
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
1.19 TYP.
4/Nov. 28, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
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REVISION HISTORY
Page
Previous Current
Edition
Edition
Document No.
Date
Description
PEDL9204-01
Jan. 8, 2003
–
–
Preliminary edition 1
PEDL9204-02
Oct. 12, 2004
4
4
Pin description added
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PEDL9204-02
OKI Semiconductor
ML9204-xx
NOTICE
1. The information contained herein can change without notice owing to product and/or technical
improvements. Before using the product, please make sure that the information being referred to is
up-to-date.
2.
The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product,
please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the
specified maximum ratings or operation outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained
herein. No responsibility is assumed by us for any infringement of a third party’s right which may result
from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any
system or application that requires special or enhanced quality and reliability characteristics nor in any
system or application where the failure of such system or application may result in the loss or damage of
property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices,
aerospace equipment, nuclear power control, medical equipment, and life-support systems.
7.
Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2004 Oki Electric Industry Co., Ltd.
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