TI CSD17556Q5B

CSD17556Q5B
www.ti.com
SLPS392 – MARCH 2013
30V N-Channel NexFET™ Power MOSFETs
Check for Samples: CSD17556Q5B
PRODUCT SUMMARY
FEATURES
1
•
•
•
•
•
•
•
•
2
TA = 25°C unless otherwise stated
Extremely Low Resistance
Ultralow Qg and Qgd
Low Thermal Resistance
Avalanche Rated
Pb Free Terminal Plating
RoHS Compliant
Halogen Free
SON 5-mm × 6-mm Plastic Package
•
•
Point-of-Load Synchronous Buck in
Networking, Telecom, and Computing Systems
Synchronous Rectification
Active ORing and Hotswap Applications
30
V
Qg
Gate Charge Total (4.5V)
30
nC
Qgd
Gate Charge Gate to Drain
RDS(on)
Drain to Source On Resistance
VGS(th)
Threshold Voltage
The NexFET™ power MOSFET has been designed
to minimize losses in synchronous rectification and
other power conversion applications.
Top View
1
8
D
S
2
7
D
S
3
6
D
G
4
5
D
7.5
nC
VGS = 4.5V
1.5
mΩ
VGS = 10V
1.2
mΩ
1.4
V
Device
Package
Media
Qty
Ship
CSD17556Q5B
SON 5-mm × 6-mm
Plastic Package
13-Inch
Reel
2500
Tape and
Reel
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise stated
VALUE
UNIT
VDS
Drain to Source Voltage
30
V
VGS
Gate to Source Voltage
±20
V
Continuous Drain Current (Package limited),
TC = 25°C
100
Continuous Drain Current (Silicon limited),
TC = 25°C
215
DESCRIPTION
S
UNIT
Drain to Source Voltage
ORDERING INFORMATION
APPLICATIONS
•
TYPICAL VALUE
VDS
ID
A
Continuous Drain Current(1)
34
IDM
Pulsed Drain Current, TA = 25°C(1)(2)
214
A
PD
Power Dissipation(1)
3.1
W
TJ,
TSTG
Operating Junction and Storage
Temperature Range
–55 to 150
°C
EAS
Avalanche Energy, single pulse
ID = 100A, L = 0.1mH, RG = 25Ω
500
mJ
A
(1) Typical RθJA = 42°C/W on 1-inch2 (6.45-cm2), 2-oz. (0.071mm thick) Cu pad on a 0.06-inch (1.52-mm) thick FR4 PCB.
(2) Pulse duration ≤300μs, duty cycle ≤2%
D
P0093-01
SPACE
RDS(on) vs VGS
SPACE
GATE CHARGE
10
TC = 25°C Id = 30A
TC = 125ºC Id = 30A
5
VGS - Gate-to-Source Voltage (V)
RDS(on) - On-State Resistance (mΩ)
6
4
3
2
1
0
0
2
4
6
8
10
VGS - Gate-to- Source Voltage (V)
12
G001
ID = 30A
VDS =15V
8
6
4
2
0
0
10
20
30
40
50
Qg - Gate Charge (nC)
60
70
G001
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NexFET is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
CSD17556Q5B
SLPS392 – MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Static Characteristics
BVDSS
Drain to Source Voltage
VGS = 0V, IDS = 250μA
IDSS
Drain to Source Leakage Current
VGS = 0V, VDS = 24V
IGSS
Gate to Source Leakage Current
VDS = 0V, VGS = 20V
VGS(th)
Gate to Source Threshold Voltage
VDS = VGS, IDS = 250μA
RDS(on)
Drain to Source On Resistance
gfs
Transconductance
30
1.15
V
1
μA
100
nA
1.4
1.65
V
1.5
1.8
mΩ
VGS = 10V, IDS = 40A
1.2
1.4
mΩ
VDS = 15V, IDS = 40A
197
VGS = 4.5V, IDS = 40A
S
Dynamic Characteristics
Ciss
Input Capacitance
VGS = 0V, VDS = 15V,
f = 1MHz
5400
7020
pF
Coss
Output Capacitance
1770
2310
pF
Crss
Reverse Transfer Capacitance
68
88
pF
RG
Series Gate Resistance
0.7
1.4
Ω
Qg
Gate Charge Total (4.5V)
30
39
nC
Qgd
Gate Charge Gate to Drain
7.5
nC
Qgs
Gate Charge Gate to Source
11
nC
Qg(th)
Gate Charge at Vth
6.1
nC
Qoss
Output Charge
48
nC
td(on)
Turn On Delay Time
14
ns
tr
Rise Time
26
ns
td(off)
Turn Off Delay Time
27
ns
tf
Fall Time
12
ns
VDS = 15V, IDS = 40A
VDS = 15V, VGS = 0V
VDS = 15V, VGS = 4.5V,
IDS = 40A,RG = 2Ω
Diode Characteristics
VSD
Diode Forward Voltage
Qrr
Reverse Recovery Charge
trr
Reverse Recovery Time
ISD = 40A, VGS = 0V
0.8
VDD= 15V, IF = 40A, di/dt = 300A/μs
1
V
68
nC
36
ns
THERMAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
MAX
UNIT
RθJC
Thermal Resistance Junction to Case (1)
PARAMETER
1.3
°C/W
RθJA
Thermal Resistance Junction to Ambient (1) (2)
50
°C/W
(1)
(2)
2
MIN
TYP
RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm ×
3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.
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GATE
SLPS392 – MARCH 2013
GATE
Source
N-Chan 5x6 QFN TTA MIN Rev3
N-Chan 5x6 QFN TTA MAX Rev3
Max RθJA = 50°C/W
when mounted on
1 inch2 (6.45 cm2) of 2oz. (0.071-mm thick)
Cu.
Source
Max RθJA = 125°C/W
when mounted on a
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
DRAIN
DRAIN
M0137-02
M0137-01
TYPICAL MOSFET CHARACTERISTICS
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
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SLPS392 – MARCH 2013
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TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
200
180
180
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
TEXT ADDED FOR SPACING
200
160
140
120
100
80
60
VGS =10V
VGS =6V
VGS =4.5V
40
20
0
0
0.1
0.2
0.3
0.4
VDS - Drain-to-Source Voltage (V)
160
140
120
100
80
60
TC = 125°C
TC = 25°C
TC = −55°C
40
20
0
0.5
VDS = 5V
0
1
G001
Figure 2. Saturation Characteristics
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
8
C − Capacitance (pF)
VGS - Gate-to-Source Voltage (V)
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
6
4
10000
1000
100
2
0
10
20
30
40
50
Qg - Gate Charge (nC)
60
10
70
0
10
20
VDS - Drain-to-Source Voltage (V)
G001
Figure 4. Gate Charge
30
G001
Figure 5. Capacitance
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
2
6
RDS(on) - On-State Resistance (mΩ)
ID = 250uA
VGS(th) - Threshold Voltage (V)
G001
100000
ID = 30A
VDS =15V
0
5
Figure 3. Transfer Characteristics
10
1.8
1.6
1.4
1.2
1
0.8
0.6
−75
−25
25
75
125
TC - Case Temperature (ºC)
Figure 6. Threshold Voltage vs. Temperature
4
2
3
4
VGS - Gate-to-Source Voltage (V)
175
TC = 25°C Id = 30A
TC = 125ºC Id = 30A
5
4
3
2
1
0
0
G001
2
4
6
8
10
VGS - Gate-to- Source Voltage (V)
12
G001
Figure 7. On-State Resistance vs. Gate-to-Source Voltage
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SLPS392 – MARCH 2013
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
100
VGS = 4.5V
VGS = 10V
2
ID =30A
ISD − Source-to-Drain Current (A)
Normalized On-State Resistance
2.2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
−75
−25
25
75
125
TC - Case Temperature (ºC)
175
TC = 25°C
TC = 125°C
10
1
0.1
0.01
0.001
0.0001
0
0.2
0.4
0.6
0.8
VSD − Source-to-Drain Voltage (V)
G001
Figure 8. Normalized On-State Resistance vs. Temperature
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
300
1ms
10ms
1000
100ms
1s
DC
IAV - Peak Avalanche Current (A)
IDS - Drain-to-Source Current (A)
G001
Figure 9. Typical Diode Forward Voltage
10000
100
10
1
0.1
1
Single Pulse
Typical RthetaJA =100ºC/W(min Cu)
0.01
0.01
0.1
1
10
VDS - Drain-to-Source Voltage (V)
50
TC = 25ºC
TC = 125ºC
100
10
0.01
0.1
TAV - Time in Avalanche (mS)
G001
Figure 10. Maximum Safe Operating Area
1
G001
Figure 11. Single Pulse Unclamped Inductive Switching
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
IDS - Drain- to- Source Current (A)
300.0
Silicon limited
Package limited
250.0
200.0
150.0
100.0
50.0
0.0
−50
−25
0
25
50
75
100 125
TC - Case Temperature (ºC)
150
175
G001
Figure 12. Maximum Drain Current vs. Temperature
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CSD17556Q5B
SLPS392 – MARCH 2013
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MECHANICAL DATA
Q5B Package Dimensions
DIM
MILLIMETERS
MIN
NOM
MAX
A
0.95
1.00
1.05
b
0.36
0.41
0.46
c
0.15
0.20
0.25
c1
0.15
0.20
0.25
c2
0.20
0.25
0.30
D1
4.90
5.00
5.10
D2
4.12
4.22
4.32
d
0.20
0.25
0.30
E
4.90
5.00
5.10
E1
5.90
6.00
6.10
E2
3.48
3.58
3.68
e
L
0.46
0.56
0.66
θ
0°
-
-
K
6
1.27 TYP
1.40 TYP
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SLPS392 – MARCH 2013
Recommended PCB Pattern
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
Recommended Stencil Pattern
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SLPS392 – MARCH 2013
www.ti.com
K0
4.00 ±0.10 (See Note 1)
0.30 ±0.05
2.00 ±0.05
+0.10
–0.00
12.00 ±0.30
Ø 1.50
1.75 ±0.10
Q5B Tape and Reel Information
5.50 ±0.05
B0
R 0.30 MAX
A0
8.00 ±0.10
Ø 1.50 MIN
A0 = 6.50 ±0.10
B0 = 5.30 ±0.10
K0 = 1.40 ±0.10
R 0.30 TYP
M0138-01
Notes:
1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm (unless otherwise specified)
5. A0 and B0 measured on a plane 0.3mm above the bottom of the pocket
8
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PACKAGE OPTION ADDENDUM
www.ti.com
22-Mar-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
CSD17556Q5B
ACTIVE
Package Type Package Pins Package Qty
Drawing
VSON
DNK
8
2500
Eco Plan
Lead/Ball Finish
(2)
Pb-Free (RoHS
Exempt)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
CU SN
Level-1-260C-UNLIM
(4)
-55 to 150
CSD17556
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CSD17556Q5B
Package Package Pins
Type Drawing
VSON
DNK
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.8
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
5.3
1.4
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CSD17556Q5B
VSON
DNK
8
2500
335.0
335.0
32.0
Pack Materials-Page 2
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