TI CSD17571Q2

CSD17571Q2
www.ti.com
SLPS393 – OCTOBER 2013
30V N-Channel NexFET™ Power MOSFETs
Check for Samples: CSD17571Q2
FEATURES
1
•
•
•
•
•
•
•
2
PRODUCT SUMMARY
Low Qg and Qgd
Low Thermal Resistance
Avalanche Rated
Pb-Free Terminal Plating
RoHS Compliant
Halogen Free
SON 2-mm × 2-mm Plastic Package
VDS
Drain to Source Voltage
30
V
Qg
Gate Charge Total (4.5 V)
2.4
nC
Qgd
Gate Charge Gate to Drain
RDS(on)
Drain to Source On Resistance
VGS(th)
Threshold Voltage
nC
24
mΩ
VGS = 10 V
20
mΩ
1.6
V
ORDERING INFORMATION
Device
Package
Media
CSD17571Q2
SON 2-mm × 2-mm
Plastic Package
7-Inch
Reel
APPLICATIONS
•
•
•
0.6
VGS = 4.5 V
Optimized for Load Switch Applications
Storage, Tablets, and Handheld Devices
Optimized for Control FET Applications
Qty
Ship
3000
Tape and
Reel
ABSOLUTE MAXIMUM RATINGS
TA = 25°C
VALUE
UNIT
DESCRIPTION
VDS
Drain to Source Voltage
30
V
This 30V, 20mΩ, Son2x2 NexFET™ power MOSFET
has been designed to minimize losses in power
conversion and load management applications, while
offering excellent thermal performance for the size of
the package.
VGS
Gate to Source Voltage
±20
V
Continuous Drain Current (Package Limit)
22
A
Continuous Drain Current(1)
7.6
A
IDM
Pulsed Drain Current, TA = 25°C(2)
39
A
PD
Power Dissipation(1)
2.5
W
TJ,
TSTG
Operating Junction and Storage
Temperature Range
–55 to 150
°C
EAS
Avalanche Energy, single pulse
ID = 12 A, L = 0.1 mH, RG = 25 Ω
7.2
mJ
Top View
D
1
6
D
5
D
4
S
ID
D
D
2
G
3
S
(1) RθJA = 50 on 1in² Cu (2 oz.) on .060" thick FR4 PCB
(2) Pulse duration 10 μs, duty cycle ≤2%
P0108-01
RDS(on) vs VGS
GATE CHARGE
10
TC = 25°C, I D = 5A
TC = 125°C, I D = 5A
46
VGS - Gate-to-Source Voltage (V)
RDS(on) - On-State Resistance (mΩ)
50
42
38
34
30
26
22
18
14
10
0
2
4
6
8
10
12
14
16
VGS - Gate-to- Source Voltage (V)
18
20
G001
ID = 5A
VDS =15V
9
8
7
6
5
4
3
2
1
0
0
0.5
1
1.5
2 2.5 3 3.5 4
Qg - Gate Charge (nC)
4.5
5
5.5
G001
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NexFET is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
CSD17571Q2
SLPS393 – OCTOBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
TA = 25°C, unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
Static Characteristics
BVDSS
Drain to Source Voltage
VGS = 0 V, ID = 250 μA
IDSS
Drain to Source Leakage Current
VGS = 0 V, VDS = 24 V
IGSS
Gate to Source Leakage Current
VDS = 0 V, VGS = 20 V
VGS(th)
Gate to Source Threshold Voltage
VDS = VGS, IDS = 250 μA
RDS(on)
Drain to Source On Resistance
gfs
Transconductance
30
1.3
V
1
μA
100
nA
1.6
2.0
V
VGS = 4.5 V, IDS = 5 A
24
29
mΩ
VGS = 10 V, IDS = 5 A
20
24
mΩ
VDS = 15 V, IDS = 5 A
43
S
Dynamic Characteristics
CISS
Input Capacitance
360
468
pF
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
101
131
pF
9
12
Rg
pF
Series Gate Resistance
3.8
7.6
Ω
Qg
Gate Charge Total (4.5V)
2.4
3.1
nC
Qgd
Gate Charge – Gate to Drain
0.6
nC
Qgs
Gate Charge Gate to Source
0.9
nC
Qg(th)
Gate Charge at Vth
0.6
nC
QOSS
Output Charge
3.4
nC
td(on)
Turn On Delay Time
5.3
ns
tr
Rise Time
19
ns
td(off)
Turn Off Delay Time
8.0
ns
tf
Fall Time
2.6
ns
VGS = 0 V, VDS = 15 V, f = 1 MHz
VDS = 15 V, IDS = 5 A
VDS = 15 V, VGS = 0 V
VDS = 15 V, VGS = 4.5 V, IDS = 5 A
RG = 2 Ω
Diode Characteristics
VSD
Diode Forward Voltage
Qrr
Reverse Recovery Charge
trr
Reverse Recovery Time
IDS = 5 A, VGS = 0 V
0.8
VDD = 15 V, IF = 5 A, di/dt = 300 A/μs
1
V
2.3
nC
11
ns
THERMAL CHARACTERISTICS
TA = 25°C unless otherwise specified
PARAMETER
RθJC
Thermal Resistance Junction to Case
RθJA
Thermal Resistance Junction to Ambient (1) (2)
(1)
(2)
2
MIN
(1)
2
TYP
MAX
UNIT
6.2
°C/W
65
°C/W
2
RθJC is determined with the device mounted on a 1-inch (6.45-cm ), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm ×
3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.
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CSD17571Q2
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SLPS393 – OCTOBER 2013
GATE
GATE
Source
Source
N-Chan
N-Chan
Max RθJA = 65 when
mounted on 1 inch2
(6.45 cm2) of 2-oz.
(0.071-mm thick) Cu.
Max RθJA = 235 when
mounted on minimum
pad area of 2-oz.
(0.071-mm thick) Cu.
DRAIN
DRAIN
M0164-02
M0164-01
TYPICAL MOSFET CHARACTERISTICS
TA = 25°C unless otherwise specified
Figure 1. Transient Thermal Impedance
TEXT ADDED FOR SPACING
30
45
27
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
TEXT ADDED FOR SPACING
50
40
35
30
25
20
15
VGS = 10V
VGS = 6V
VGS = 4.5V
10
5
0
0
0.2
0.4 0.6 0.8
1
1.2 1.4 1.6
VDS - Drain-to-Source Voltage (V)
1.8
2
VDS = 5V
24
21
18
15
12
9
TC = 125°C
TC = 25°C
TC = −55°C
6
3
0
0
G001
Figure 2. Saturation Characteristics
0.5
1
1.5
2
2.5
3
VGS - Gate-to-Source Voltage (V)
3.5
Product Folder Links: CSD17571Q2
G001
Figure 3. Transfer Characteristics
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CSD17571Q2
SLPS393 – OCTOBER 2013
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TYPICAL MOSFET CHARACTERISTICS (continued)
TA = 25°C unless otherwise specified
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1000
ID = 5A
VDS =15V
9
8
C − Capacitance (pF)
VGS - Gate-to-Source Voltage (V)
10
7
6
5
4
3
100
10
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
2
1
0
0
0.5
1
1.5
2 2.5 3 3.5 4
Qg - Gate Charge (nC)
4.5
5
1
5.5
0
3
6
G001
Figure 4. Gate Charge
TEXT ADDED FOR SPACING
G001
TEXT ADDED FOR SPACING
ID = 250uA
1.9
RDS(on) - On-State Resistance (mΩ)
VGS(th) - Threshold Voltage (V)
30
50
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
−75
−25
25
75
125
TC - Case Temperature (ºC)
TC = 25°C, I D = 5A
TC = 125°C, I D = 5A
46
42
38
34
30
26
22
18
14
10
175
0
2
G001
Figure 6. Threshold Voltage vs. Temperature
TEXT ADDED FOR SPACING
18
20
G001
TEXT ADDED FOR SPACING
VGS = 4.5V
VGS = 10V
ID = 5A
1.3
1.2
1.1
1
0.9
0.8
0.7
−75
6
8
10
12
14
16
VGS - Gate-to- Source Voltage (V)
100
ISD − Source-to-Drain Current (A)
1.4
4
Figure 7. On-State Resistance vs. Gate-to-Source Voltage
1.5
Normalized On-State Resistance
27
Figure 5. Capacitance
2
−25
25
75
125
TC - Case Temperature (ºC)
175
TC = 25°C
TC = 125°C
10
1
0.1
0.01
0.001
0.0001
0
0.2
0.4
0.6
0.8
VSD − Source-to-Drain Voltage (V)
G001
Figure 8. Normalized On-State Resistance vs. Temperature
4
9
12
15
18
21
24
VDS - Drain-to-Source Voltage (V)
1
G001
Figure 9. Typical Diode Forward Voltage
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CSD17571Q2
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SLPS393 – OCTOBER 2013
TYPICAL MOSFET CHARACTERISTICS (continued)
TA = 25°C unless otherwise specified
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
100
1ms
10ms
100ms
1s
DC
IAV - Peak Avalanche Current (A)
IDS - Drain-to-Source Current (A)
1000
100
10
1
0.1
Single Pulse
Typical RthetaJA =190ºC/W(min Cu)
0.01
0.01
0.1
1
10
VDS - Drain-to-Source Voltage (V)
50
TC = 25ºC
TC = 125ºC
10
1
0.1
0.01
0.1
TAV - Time in Avalanche (mS)
G001
Figure 10. Maximum Safe Operating Area
1
G001
Figure 11. Single Pulse Unclamped Inductive Switching
TEXT ADDED FOR SPACING
IDS - Drain- to- Source Current (A)
30.0
27.0
24.0
21.0
18.0
15.0
12.0
9.0
6.0
3.0
0.0
−50
−25
0
25
50
75
100 125
TA - AmbientTemperature (ºC)
150
175
G001
Figure 12. Maximum Drain Current vs. Temperature
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CSD17571Q2
SLPS393 – OCTOBER 2013
www.ti.com
MECHANICAL DATA
Q2 Package Dimensions
D2
D
K3
K1
K
K2
4
1
2
3
4
5
6
3
2
1
K4
E
E1
E2
5
E3
6
L
Pin 1 Dot
Top View
Pin 1 ID
e
b
D1
A
A1
C
Bottom View
Front View
M0165-01
DIM
MILLIMETERS
MIN
NOM
MAX
MIN
NOM
MAX
A
0.700
0.750
0.800
0.028
0.030
0.032
A1
0.000
0.050
0.000
b
0.250
0.350
0.010
0.300
C
0.203 TYP
D
2.000 TYP
D1
0.900
0.950
D2
0.300 TYP
E
2.000 TYP
E1
0.900
1.000
0.002
0.012
0.080 TYP
1.000
0.036
0.038
0.080 TYP
1.100
0.036
0.040
0.280 TYP
0.0112 TYP
0.470 TYP
0.0188 TYP
e
0.650 BSC
0.026 TYP
K
0.280 TYP
0.0112 TYP
K1
0.350 TYP
0.014 TYP
K2
0.200 TYP
0.008 TYP
K3
0.200 TYP
0.008 TYP
0.470 TYP
0.200
0.25
0.040
0.012 TYP
E3
L
0.014
0.008 TYP
E2
K4
6
INCHES
0.044
0.0188 TYP
0.300
0.008
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0.010
0.012
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: CSD17571Q2
CSD17571Q2
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SLPS393 – OCTOBER 2013
Recommended PCB Pattern
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
Recommended Stencil Pattern
Note:
All dimensions are in mm, unless otherwise specified.
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CSD17571Q2
SLPS393 – OCTOBER 2013
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Q2 Tape and Reel Information
4.00 ±0.10
Ø 1.50 ±0.10
4.00 ±0.10
Ø 1.00 ±0.25
1.00 ±0.05
2.30 ±0.05
10° Max
3.50 ±0.05
8.00
+0.30
–0.10
1.75 ±0.10
2.00 ±0.05
0.254 ±0.02
2.30 ±0.05
10° Max
M0168-01
Notes: 1. Measured from centerline of sprocket hole to centerline of pocket
2. Cumulative tolerance of 10 sprocket holes is ±0.20
3. Other material available
4. Typical SR of form tape Max 109 OHM/SQ
5. All dimensions are in mm, unless otherwise specified.
8
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Jan-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
CSD17571Q2
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SON
DQK
6
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-55 to 150
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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25-Jan-2014
Addendum-Page 2
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