PRELIMINARY SPECIFICATION PE84244 Military Operating Temperature Range Product Description SPDT MOSFET RF Switch The PE84244 MOSFET RF Switch is designed to cover a broad range of applications from DC to 3.0 GHz. This switch integrates on-board CMOS control logic with a low voltage CMOS compatible control input. Using a +3-volt nominal power supply voltage, a 1 dB compression point of +27 dBm can be achieved. The PE84244 also exhibits excellent isolation of 28 dB at 2.0 GHz and is offered in a small 8-lead MSOP package. Features • Single +3.0-volt Power Supply • Low Insertion loss: 0.70 dB up to 2.0 GHz • High isolation of 39 dB at 1.0 GHz, 28 dB at 2.0 GHz, typical • Typical 1 dB compression of +27 dBm • Single-pin CMOS logic control The PE4244 MOSFET RF Switch is manufactured in Peregrine’s patented Ultra Thin Silicon (UTSi) CMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Schematic Diagram • Packaged in 8-lead MSOP Figure 2. Package Type RFCommon RF1 RF2 8-lead MSOP CTRL Table 1. Electrical Specifications -55 °C to +125 °C, VDD = 3 V (ZS = ZL = 50 Ω) Parameter Conditions 1 Operation Frequency Minimum Typical DC Units 3000 MHz 0.95 dB Insertion Loss 2000 MHz Isolation – RFCommon to RF1/RF2 2000 MHz 25 28 dB Isolation – RF1 to RF2 2000 MHz 24 27 dB Return Loss 2000 MHz 18 25 dB ‘ON’ Switching Time CTRL to 0.1 dB final value, 2 GHz 200 ns ‘OFF’ Switching Time CTRL to 25 dB isolation, 2 GHz 90 ns 15 mVpp Video Feedthrough 0.7 Maximum 2 Input 1 dB Compression 2000 MHz 25 27 dBm Input IP3 2000 MHz, 14dBm 40 42 dBm Notes: 1. Device linearity will begin to degrade below 10 MHz. 2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to High or High to Low in a 50 Ω test set-up, measured with 1ns risetime pulses and 500 MHz bandwidth. PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2003 Page 1 of 7 PE84244 Preliminary Specification Figure 3. Pin Configuration VDD 1 CTRL 2 GND RFCommon Table 4. DC Electrical Specifications 8 RF1 Parameter Min Typ Max Units VDD Power Supply Voltage 2.7 3.0 3.3 V 250 500 nA 7 GND IDD Power Supply Current VDD = 3V, VCNTL = 3V 3 6 GND Control Voltage High 4 5 RF2 PE84244 0.7xVDD V Control Voltage Low 0.3xVDD V Table 5. Control Logic Truth Table Table 2. Pin Descriptions Pin No. Pin Name 1 VDD Control Voltage Description Nominal 3 V supply connection. A bypass capacitor (100 pF) to the ground plane should be placed as close as possible to the pin 2 CTRL CMOS logic level: High = RFCommon to RF1 signal path Low = RFCommon to RF2 signal path 3 GND Ground connection. Traces should be physically short and connected to ground plane for best performance. 4 RF Common 5 RF2 RF2 port (Note 1) 6 GND Ground Connection. Traces should be physically short and connected to ground plane for best performance. 7 GND Ground Connection. Traces should be physically short and connected to ground plane for best performance. 8 RF1 RF1 port (Note 1) Common RF port for switch (Note 1) Signal Path CTRL = CMOS High RFCommon to RF1 CTRL = CMOS Low RFCommon to RF2 Electrostatic Discharge (ESD) Precautions When handling this UTSi device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified. Latch-Up Avoidance Unlike conventional CMOS devices, UTSi CMOS devices are immune to latch-up. Note 1: All RF pins must be DC blocked with an external series capacitor or held at 0VDC. Table 3. Absolute Maximum Ratings Symbol Parameter/Conditions Min Max Units VDD Power supply voltage -0.3 4.0 V VI Voltage on any input -0.3 VDD+ 0.3 V TST Storage temperature range -65 150 °C TOP Operating temperature range -55 125 °C 30 dBm 1500 V PIN Input power (50Ω) VESD ESD voltage (Human Body Model) Copyright Peregrine Semiconductor Corp. 2003 Page 2 of 7 File No. 70/0129~00A | UTSi CMOS RFIC SOLUTIONS PE84244 Preliminary Specification Typical Performance Data -55 °C to +125 °C (Unless Otherwise Noted) Figure 4. Insertion Loss – RFC to RF1 Figure 5. Input 1 dB Compression Point & IIP3 0.0 60 -55°C -55°C IIP3 -0.3 25°C Power (dBm) Insertion Loss (dB) 50 -0.6 25°C 125°C -0.9 40 125°C 30 -1.2 1dB Compression -1.5 20 0 500 1000 1500 2000 2500 3000 0 500 1000 Frequency Hz) Frequency (M (MHz) 1500 2000 2500 3000 Frequency (MHz) (M Hz) Frequency Figure 7. Isolation – RFC to RF1 Figure 6. Insertion Loss – RFC to RF2 0.0 0 -55°C -20 Isolation (dB) Insertion Loss (dB) -0.3 -0.6 25°C 125°C -0.9 -1.2 125°C -40 -55°C -60 25°C -80 -1.5 -100 0 500 1000 1500 2000 2500 3000 PEREGRINE SEMICONDUCTOR CORP. | 0 500 1000 1500 2000 2500 3000 Frequency (M Hz) Frequency (MHz) Hz) Frequency (M (MHz) http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2003 Page 3 of 7 PE84244 Preliminary Specification Typical Performance Data -55 °C to +125 °C (Unless Otherwise Noted) Figure 9. Isolation – RF1 to RF2, RF2 to RF1 0 0 -20 -20 125°C Isolation (dB) Isolation (dB) Figure 8. Isolation – RFC to RF2 -40 -55°C -60 RF2 -40 RF1 -60 25°C -80 -80 -100 -100 0 500 1000 1500 2000 2500 3000 0 500 1000 1500 2000 2500 3000 Frequency (M Hz) Frequency (MHz) Frequency (M Hz) Frequency (MHz) Figure 10. Return Loss – RFC to RF1, RF2 Figure 11. Return Loss – RF1, RF2 0 0 -5 -10 Return Loss (dB) Return Loss (dB) -10 -15 -20 RF2 RF1 -25 -20 RF1 RF2 -30 -30 -35 0 500 1000 1500 2000 Frequency (M Hz) Copyright Peregrine Semiconductor Corp. 2003 Page 4 of 7 2500 3000 -40 0 500 1000 1500 2000 2500 3000 Frequency Hz) Frequency(M (MHz) File No. 70/0129~00A | UTSi CMOS RFIC SOLUTIONS PE84244 Preliminary Specification Evaluation Kit Information Figure 12. Evaluation Board Layouts Evaluation Kit The SPDT Switch Evaluation Kit board was designed to ease customer evaluation of the PE84244 SPDT switch. The RF common port is connected through a 50Ω transmission line to the top left SMA connector, J1. Port 1 and Port 2 are connected through 50Ω transmission lines to the top two SMA connectors on the right side of the board, J3 and J4. A through transmission line connects SMA connectors J6 and J8. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. The board is constructed of a two metal layer FR4 material with a total thickness of 0.031”. The bottom layer provides ground for the RF transmission lines. The transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 0.030”, trace gaps of 0.007”, dielectric thickness of 0.028”, metal thickness of 0.0014” and εr of 4.4. J2 provides a means for controlling DC and digital inputs to the device. Starting from the lower left pin, the second pin to the right (J2-3) is connected to the device CNTL input. The fourth pin to the right (J2-7) is connected to the device VDD input. A decoupling capacitor (100 pF) is provided on both CNTL and VDD traces. It is the responsibility of the customer to determine proper supply decoupling for their design application. Removing these components from the evaluation board has not been shown to degrade RF performance. Figure 13. Evaluation Board Schematic J2-7 100 pF VDD RF1 CNTL GND GND GND RFC RF2 J3 Optional J2-3 100 pF Optional J1 J4 J6 PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com J8 Copyright Peregrine Semiconductor Corp. 2003 Page 5 of 7 PE84244 Preliminary Specification Figure 14. Package Drawing 8-lead MSOP TOP VIEW 0.65BSC .525BSC 8 7 6 5 2.45±0.10 2X 3.00±0.10 0.51±0.13 -B- 0.51±0.13 2 1 3 4 2.95±0.10 .25 A B C -C0.86±0.08 2.95±0.10 1.10 MAX -A0.10 A 0.33+0.07 -0.08 0.08 A B C 3.00±0.10 4.90±0.15 0.10±0.05 3.00±0.10 FRONT VIEW SIDE VIEW Table 6. Ordering Information Order Code Part Marking Description Package Shipping Method 84244-01 84244 PE84244-08MSOP-50A 8-lead MSOP 50 units / Tube 84244-02 84244 PE84244-08MSOP-2000C 8-lead MSOP 2000 units / T&R 84244-00 PE84244-EK PE84244-08MSOP-EK Evaluation Kit 1 / Box Copyright Peregrine Semiconductor Corp. 2003 Page 6 of 7 File No. 70/0129~00A | UTSi CMOS RFIC SOLUTIONS